RTEMS  5.1
mpc5xx.h
1 /*
2  *
3  * MPC5xx Internal I/O Definitions
4  */
5 
6 /*
7  * MPC5xx port sponsored by Defence Research and Development Canada - Suffield
8  * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
9  *
10  * Derived from c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h:
11  *
12  * Submitted By: *
13  * *
14  * W. Eric Norum *
15  * Saskatchewan Accelerator Laboratory *
16  * University of Saskatchewan *
17  * 107 North Road *
18  * Saskatoon, Saskatchewan, CANADA *
19  * S7N 5C6 *
20  * *
21  * eric@skatter.usask.ca *
22  * *
23  * Modified for use with the MPC860 (original code was for MC68360) *
24  * by *
25  * Jay Monkman *
26  * Frasca International, Inc. *
27  * 906 E. Airport Rd. *
28  * Urbana, IL, 61801 *
29  * *
30  * jmonkman@frasca.com *
31  * *
32  * Modified further for use with the MPC821 by: *
33  * Andrew Bray <andy@chaos.org.uk> *
34  * *
35  * With some corrections/additions by: *
36  * Darlene A. Stewart and *
37  * Charles-Antoine Gauthier *
38  * Institute for Information Technology *
39  * National Research Council of Canada *
40  * Ottawa, ON K1A 0R6 *
41  * *
42  * Darlene.Stewart@iit.nrc.ca *
43  * charles.gauthier@iit.nrc.ca *
44  * *
45  * Corrections/additions: *
46  * Copyright (c) 1999, National Research Council of Canada *
47  *
48  * MPC5xx port sponsored by Defence Research and Development Canada - Suffield
49  * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
50  *
51  * The license and distribution terms for this file may be
52  * found in the file LICENSE in this distribution or at
53  * http://www.rtems.org/license/LICENSE.
54  */
55 
56 #ifndef _MPC5XX_H
57 #define _MPC5XX_H
58 
59 #include <libcpu/spr.h>
60 
61 
62 #ifndef ASM
63 
64 #ifdef __cplusplus
65 extern "C" {
66 #endif
67 
68 /*
69  * Macros for accessing Special Purpose Registers (SPRs)
70  */
71 
72 #define _eieio __asm__ volatile ("eieio\n"::)
73 #define _sync __asm__ volatile ("sync\n"::)
74 #define _isync __asm__ volatile ("isync\n"::)
75 
76 /*
77  * Core Registers (SPRs)
78  */
79 #define DER 149 /* Debug Enable Register */
80 #define IMMR 638 /* Internal Memory Map Register */
81 #define IMMR_FLEN (1<<11) /* Internal flash ROM enabled */
82 
83 /*
84  * Interrupt Control Registers (SPRs)
85  */
86 #define EIE 80 /* External Interrupt Enable Register */
87 #define EID 81 /* External Interrupt Disable Register */
88 #define NRI 82 /* Non-Recoverable Interrupt Register */
89 
90 #define ECR 148 /* Exception Cause Register */
91 
92 /*
93  * Bus Control Registers (SPRs)
94  */
95 #define LCTRL1 156 /* L-Bus Support Control Register 1 */
96 #define LCTRL2 157 /* L-Bus Support Control Register 2 */
97 #define ICTRL 158 /* I-Bus Support Control Register */
98 
99 /*
100  * Burst Buffer Control Registers (SPRs)
101  */
102 #define BBCMCR 560 /* Burst Buffer Configuration Register */
103 #define BBCMCR_BE (1<<13) /* Burst enable */
104 #define BBCMCR_ETRE (1<<12) /* Exception table relocation enable */
105 
106 #define MI_RBA0 784 /* Region 0 Address Register */
107 #define MI_RBA1 785 /* Region 1 Address Register */
108 #define MI_RBA2 786 /* Region 2 Address Register */
109 #define MI_RBA3 787 /* Region 3 Address Register */
110 
111 #define MI_RA0 816 /* Region 0 Attribute Register */
112 #define MI_RA1 817 /* Region 1 Attribute Register */
113 #define MI_RA2 818 /* Region 2 Attribute Register */
114 #define MI_RA3 819 /* Region 3 Attribute Register */
115 #define MI_GRA 528 /* Region Global Attribute Register */
116 #define MI_RA_PP (3 << 10) /* Protection bits: */
117 #define MI_RA_PP_SUPV (1 << 10) /* Supervisor */
118 #define MI_RA_PP_USER (2 << 10) /* User */
119 #define MI_RA_G (1 << 6) /* Guarded region */
120 
121 
122 /*
123  * L-Bus to U-Bus Interface (L2U) Registers (SPRs)
124  */
125 #define L2U_MCR 568 /* L2U Module Configuration Register */
126 
127 #define L2U_RBA0 792 /* L2U Region 0 Address Register */
128 #define L2U_RBA1 793 /* L2U Region 1 Address Register */
129 #define L2U_RBA2 794 /* L2U Region 2 Address Register */
130 #define L2U_RBA3 795 /* L2U Region 3 Address Register */
131 
132 #define L2U_RA0 824 /* L2U Region 0 Attribute Register */
133 #define L2U_RA1 825 /* L2U Region 1 Attribute Register */
134 #define L2U_RA2 826 /* L2U Region 2 Attribute Register */
135 #define L2U_RA3 827 /* L2U Region 3 Attribute Register */
136 #define L2U_GRA 536 /* L2U Global Region Attribute Register */
137 #define L2U_RA_PP (3 << 10) /* Protection bits: */
138 #define L2U_RA_PP_SUPV (1 << 10) /* Supervisor */
139 #define L2U_RA_PP_USER (2 << 10) /* User */
140 #define L2U_RA_G (1 << 6) /* Guarded region */
141 
142 
143 /*
144  *************************************************************************
145  * REGISTER SUBBLOCKS *
146  *************************************************************************
147  */
148 
149 /*
150  *************************************************************************
151  * System Protection Control Register (SYPCR) *
152  *************************************************************************
153  */
154 #define USIU_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */
155 #define USIU_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */
156 #define USIU_SYPCR_BME (1<<7) /* Bus monitor enable */
157 #define USIU_SYPCR_SWF (1<<3) /* Software watchdog freeze */
158 #define USIU_SYPCR_SWE (1<<2) /* Software watchdog enable */
159 #define USIU_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */
160 #define USIU_SYPCR_SWP (1<<0) /* Software watchdog prescale */
161 
162 #define USIU_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */
163 #define USIU_SYPCR_BME (1<<7) /* Bus monitor enable */
164 #define USIU_SYPCR_SWF (1<<3) /* Software watchdog freeze */
165 #define USIU_SYPCR_SWE (1<<2) /* Software watchdog enable */
166 #define USIU_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */
167 #define USIU_SYPCR_SWP (1<<0) /* Software watchdog prescale */
168 
169 /*
170  *************************************************************************
171  * Software Service Register (SWSR) *
172  *************************************************************************
173  */
174 #define TICKLE_WATCHDOG() \
175 do { \
176  usiu.swsr = 0x556C; \
177  usiu.swsr = 0xAA39; \
178 } while (0) \
179 
180 /*
181  *************************************************************************
182  * Memory Control Registers *
183  *************************************************************************
184  */
185 #define USIU_MEMC_BR_BA(x) (((uint32_t)x)&0xffff8000)
186  /* Base address */
187 #define USIU_MEMC_BR_AT(x) ((x)<<12) /* Address type */
188 #define USIU_MEMC_BR_PS8 (1<<10) /* 8 bit port */
189 #define USIU_MEMC_BR_PS16 (2<<10) /* 16 bit port */
190 #define USIU_MEMC_BR_PS32 (0<<10) /* 32 bit port */
191 #define USIU_MEMC_BR_WP (1<<8) /* Write protect */
192 #define USIU_MEMC_BR_WEBS (1<<5) /* Write enable/byte select */
193 #define USIU_MEMC_BR_TBDIP (1<<4) /* Toggle-Burst data in progress*/
194 #define USIU_MEMC_BR_LBDIP (1<<3) /* Late-burst data in progress */
195 #define USIU_MEMC_BR_SETA (1<<2) /* External transfer acknowledge */
196 #define USIU_MEMC_BR_BI (1<<1) /* Burst inhibit */
197 #define USIU_MEMC_BR_V (1<<0) /* Base/Option register are valid */
198 
199 #define USIU_MEMC_OR_32K 0xffff8000 /* Address range */
200 #define USIU_MEMC_OR_64K 0xffff0000
201 #define USIU_MEMC_OR_128K 0xfffe0000
202 #define USIU_MEMC_OR_256K 0xfffc0000
203 #define USIU_MEMC_OR_512K 0xfff80000
204 #define USIU_MEMC_OR_1M 0xfff00000
205 #define USIU_MEMC_OR_2M 0xffe00000
206 #define USIU_MEMC_OR_4M 0xffc00000
207 #define USIU_MEMC_OR_8M 0xff800000
208 #define USIU_MEMC_OR_16M 0xff000000
209 #define USIU_MEMC_OR_32M 0xfe000000
210 #define USIU_MEMC_OR_64M 0xfc000000
211 #define USIU_MEMC_OR_128 0xf8000000
212 #define USIU_MEMC_OR_256M 0xf0000000
213 #define USIU_MEMC_OR_512M 0xe0000000
214 #define USIU_MEMC_OR_1G 0xc0000000
215 #define USIU_MEMC_OR_2G 0x80000000
216 #define USIU_MEMC_OR_4G 0x00000000
217 #define USIU_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */
218 #define USIU_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */
219 #define USIU_MEMC_OR_ACS_NORM (0<<9) /* *CS asserted with addr lines */
220 #define USIU_MEMC_OR_ACS_QRTR (2<<9) /* *CS asserted 1/4 after addr */
221 #define USIU_MEMC_OR_ACS_HALF (3<<9) /* *CS asserted 1/2 after addr */
222 #define USIU_MEMC_OR_ETHR (1<<8) /* Extended hold time on reads */
223 #define USIU_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */
224 #define USIU_MEMC_OR_BSCY(x) ((x)<<1) /* Burst beat length in clocks */
225 #define USIU_MEMC_OR_TRLX (1<<0) /* Relaxed timing in GPCM */
226 
227 /*
228  *************************************************************************
229  * Clocks and Reset Controlmer *
230  *************************************************************************
231  */
232 
233 #define USIU_SCCR_DBCT (1<<31) /* Disable backup clock for timers */
234 #define USIU_SCCR_COM(x) ((x)<<29) /* Clock output mode */
235 #define USIU_SCCR_RTDIV (1<<24) /* RTC, PIT divide by 256, not 4 */
236 #define USIU_PRQEN (1<<21) /* MSR[POW] controls frequency */
237 #define USIU_SCCR_EBDF(x) ((x)<<17) /* External bus division factor */
238 #define USIU_LME (1<<16) /* Enable limp mode */
239 #define USIU_ENGDIV(x) ((x)<<9) /* Set engineering clock divisor */
240 
241 #define USIU_PLPRCR_MF(x) (((x)-1)<<20) /* PLL mult. factor (true) */
242 #define USIU_PLPRCR_SPLS (1<<16) /* System PLL locked */
243 #define USIU_PLPRCR_TEXPS (1<<14) /* Assert TEXP always */
244 
245 /*
246  *************************************************************************
247  * Programmable Interval Timer *
248  *************************************************************************
249  */
250 #define USIU_PISCR_PIRQ(x) (1<<(15-x)) /* PIT interrupt level */
251 #define USIU_PISCR_PS (1<<7) /* PIT Interrupt state */
252 #define USIU_PISCR_PIE (1<<2) /* PIT interrupt enable */
253 #define USIU_PISCR_PITF (1<<1) /* Stop timer when freeze asserted */
254 #define USIU_PISCR_PTE (1<<0) /* PIT enable */
255 
256 /*
257  *************************************************************************
258  * Time Base *
259  *************************************************************************
260  */
261 #define USIU_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */
262 #define USIU_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */
263 #define USIU_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */
264 #define USIU_TBSCR_REFAE (1<<3) /* Enable ints for REFA */
265 #define USIU_TBSCR_REFBE (1<<2) /* Enable ints for REFB */
266 #define USIU_TBSCR_TBF (1<<1) /* TB stops on FREEZE */
267 #define USIU_TBSCR_TBE (1<<0) /* enable TB and decrementer */
268 
269 /*
270  *************************************************************************
271  * SIU Interrupt Mask *
272  *************************************************************************
273  */
274 #define USIU_SIMASK_IRM0 (1<<31)
275 #define USIU_SIMASK_LVM0 (1<<30)
276 #define USIU_SIMASK_IRM1 (1<<29)
277 #define USIU_SIMASK_LVM1 (1<<28)
278 #define USIU_SIMASK_IRM2 (1<<27)
279 #define USIU_SIMASK_LVM2 (1<<26)
280 #define USIU_SIMASK_IRM3 (1<<25)
281 #define USIU_SIMASK_LVM3 (1<<24)
282 #define USIU_SIMASK_IRM4 (1<<23)
283 #define USIU_SIMASK_LVM4 (1<<22)
284 #define USIU_SIMASK_IRM5 (1<<21)
285 #define USIU_SIMASK_LVM5 (1<<20)
286 #define USIU_SIMASK_IRM6 (1<<19)
287 #define USIU_SIMASK_LVM6 (1<<18)
288 #define USIU_SIMASK_IRM7 (1<<17)
289 #define USIU_SIMASK_LVM7 (1<<16)
290 
291 /*
292  *************************************************************************
293  * SIU Module Control *
294  *************************************************************************
295  */
296 #define USIU_SIUMCR_EARB (1<<31)
297 #define USIU_SIUMCR_EARP0 (0<<28)
298 #define USIU_SIUMCR_EARP1 (1<<28)
299 #define USIU_SIUMCR_EARP2 (2<<28)
300 #define USIU_SIUMCR_EARP3 (3<<28)
301 #define USIU_SIUMCR_EARP4 (4<<28)
302 #define USIU_SIUMCR_EARP5 (5<<28)
303 #define USIU_SIUMCR_EARP6 (6<<28)
304 #define USIU_SIUMCR_EARP7 (7<<28)
305 #define USIU_SIUMCR_DSHW (1<<23)
306 #define USIU_SIUMCR_DBGC0 (0<<21)
307 #define USIU_SIUMCR_DBGC1 (1<<21)
308 #define USIU_SIUMCR_DBGC2 (2<<21)
309 #define USIU_SIUMCR_DBGC3 (3<<21)
310 #define USIU_SIUMCR_DBPC (1<<20)
311 #define USIU_SIUMCR_ATWC (1<<19)
312 #define USIU_SIUMCR_GPC0 (0<<17)
313 #define USIU_SIUMCR_GPC1 (1<<17)
314 #define USIU_SIUMCR_GPC2 (2<<17)
315 #define USIU_SIUMCR_GPC3 (3<<17)
316 #define USIU_SIUMCR_DLK (1<<16)
317 #define USIU_SIUMCR_SC0 (0<<13)
318 #define USIU_SIUMCR_SC1 (1<<13)
319 #define USIU_SIUMCR_SC2 (2<<13)
320 #define USIU_SIUMCR_SC3 (3<<13)
321 #define USIU_SIUMCR_RCTX (1<<12)
322 #define USIU_SIUMCR_MLRC0 (0<<10)
323 #define USIU_SIUMCR_MLRC1 (1<<10)
324 #define USIU_SIUMCR_MLRC2 (2<<10)
325 #define USIU_SIUMCR_MLRC3 (3<<10)
326 #define USIU_SIUMCR_MTSC (1<<7)
327 
328 /*
329  * Value to write to a key register to unlock the corresponding SIU register
330  */
331 #define USIU_UNLOCK_KEY 0x55CCAA33
332 
333 /*
334  *************************************************************************
335  * UIMB Module Control *
336  *************************************************************************
337  */
338 #define UIMB_UMCR_STOP (1<<31)
339 #define UIMB_UMCR_IRQMUX(x) ((x)<<29)
340 #define UIMB_UMCR_HSPEED (1<<28)
341 
342 /*
343  *************************************************************************
344  * QSMCM Serial Communications Interface (SCI) *
345  *************************************************************************
346  */
347 
348 
349 #define QSMCM_ILDSCI(x) ((x)<<8) /* SCI interrupt level */
350 
351 #define QSMCM_SCI_BAUD(x) ((x)&0x1FFF) /* Baud rate field */
352 
353 #define QSMCM_SCI_LOOPS (1<<14) /* Loopback test mode */
354 #define QSMCM_SCI_WOMS (1<<13) /* Wire-or mode select */
355 #define QSMCM_SCI_ILT (1<<12) /* Idle-line detect type */
356 #define QSMCM_SCI_PT (1<<11) /* Parity type */
357 #define QSMCM_SCI_PE (1<<10) /* Parity enable */
358 #define QSMCM_SCI_M (1<<9) /* 11-bit mode */
359 #define QSMCM_SCI_WAKE (1<<8) /* Wakeup mode */
360 
361 #define QSMCM_SCI_TIE (1<<7) /* Transmitter interrupt enable */
362 #define QSMCM_SCI_TCIE (1<<6) /* Transmit complete intr. enable */
363 #define QSMCM_SCI_RIE (1<<5) /* Receiver interrupt enable */
364 #define QSMCM_SCI_ILIE (1<<4) /* Idle line interrupt enable */
365 #define QSMCM_SCI_TE (1<<3) /* Transmitter enable */
366 #define QSMCM_SCI_RE (1<<2) /* Receiver enable */
367 #define QSMCM_SCI_RWU (1<<1) /* Receiver wake-up enable */
368 #define QSMCM_SCI_SBK (1<<0) /* Send break */
369 
370 #define QSMCM_SCI_TDRE (1<<8) /* Transmit data register empty */
371 #define QSMCM_SCI_TC (1<<7) /* Transmit complete */
372 #define QSMCM_SCI_RDRF (1<<6) /* Receive data register full */
373 #define QSMCM_SCI_RAF (1<<5) /* Receiver active flag */
374 #define QSMCM_SCI_IDLE (1<<4) /* Idle line detected */
375 #define QSMCM_SCI_OR (1<<3) /* Receiver overrun error */
376 #define QSMCM_SCI_NF (1<<2) /* Receiver noise error flag */
377 #define QSMCM_SCI_FE (1<<1) /* Receiver framing error */
378 #define QSMCM_SCI_PF (1<<0) /* Receiver parity error */
379 
380 /*
381  *************************************************************************
382  * Unified System Interface Unit *
383  *************************************************************************
384  */
385 
386 /*
387  * Memory controller registers
388  */
389 typedef struct m5xxMEMCRegisters_ {
390  uint32_t _br;
391  uint32_t _or; /* Used to be called 'or'; reserved ANSI C++ keyword */
392 } m5xxMEMCRegisters_t;
393 
394 /*
395  * USIU itself
396  */
397 typedef struct usiu_ {
398  /*
399  * SIU Block
400  */
401  uint32_t siumcr;
402  uint32_t sypcr;
403  uint32_t _pad70;
404  uint16_t _pad0;
405  uint16_t swsr;
406  uint32_t sipend;
407  uint32_t simask;
408  uint32_t siel;
409  uint32_t sivec;
410  uint32_t tesr;
411  uint32_t sgpiodt1;
412  uint32_t sgpiodt2;
413  uint32_t sgpiocr;
414  uint32_t emcr;
415  uint8_t _pad71[0x03C-0x034];
416  uint32_t pdmcr;
417  uint8_t _pad2[0x100-0x40];
418 
419  /*
420  * MEMC Block
421  */
422  m5xxMEMCRegisters_t memc[4];
423  uint8_t _pad7[0x140-0x120];
424  uint32_t dmbr;
425  uint32_t dmor;
426  uint8_t _pad8[0x178-0x148];
427  uint16_t mstat;
428  uint8_t _pad9[0x200-0x17A];
429 
430  /*
431  * System integration timers
432  */
433  uint16_t tbscr;
434  uint16_t _pad10;
435  uint32_t tbreff0;
436  uint32_t tbreff1;
437  uint8_t _pad11[0x220-0x20c];
438  uint16_t rtcsc;
439  uint16_t _pad12;
440  uint32_t rtc;
441  uint32_t rtsec;
442  uint32_t rtcal;
443  uint32_t _pad13[4];
444  uint16_t piscr;
445  uint16_t _pad14;
446  uint16_t pitc;
447  uint16_t _pad_14_1;
448  uint16_t pitr;
449  uint16_t _pad_14_2;
450  uint8_t _pad15[0x280-0x24c];
451 
452  /*
453  * Clocks and Reset
454  */
455  uint32_t sccr;
456  uint32_t plprcr;
457  uint16_t rsr;
458  uint16_t _pad72;
459  uint16_t colir;
460  uint16_t _pad73;
461  uint16_t vsrmcr;
462  uint8_t _pad16[0x300-0x292];
463 
464  /*
465  * System integration timers keys
466  */
467  uint32_t tbscrk;
468  uint32_t tbreff0k;
469  uint32_t tbreff1k;
470  uint32_t tbk;
471  uint32_t _pad17[4];
472  uint32_t rtcsk;
473  uint32_t rtck;
474  uint32_t rtseck;
475  uint32_t rtcalk;
476  uint32_t _pad18[4];
477  uint32_t piscrk;
478  uint32_t pitck;
479  uint8_t _pad19[0x380-0x348];
480 
481  /*
482  * Clocks and Reset Keys
483  */
484  uint32_t sccrk;
485  uint32_t plprck;
486  uint32_t rsrk;
487  uint8_t _pad20[0x400-0x38c];
488 } usiu_t;
489 
490 extern volatile usiu_t usiu; /* defined in linkcmds */
491 
492 /*
493  *************************************************************************
494  * Inter-Module Bus and Devices *
495  *************************************************************************
496  */
497 
498 /*
499  * Dual-Port TPU RAM (DPTRAM)
500  */
501 typedef struct m5xxDPTRAMRegisters_ {
502  uint8_t pad[0x4000]; /* define later */
503 } m5xxDPTRAMRegisters_t;
504 
505 /*
506  * Time Processor Unit (TPU)
507  */
508 typedef struct m5xxTPU3Registers_ {
509  uint8_t pad[0x400]; /* define later */
510 } m5xxTPU3Registers_t;
511 
512 /*
513  * Queued A/D Converter (QADC)
514  */
515 typedef struct m5xxQADC64Registers_ {
516  uint8_t pad[0x400]; /* define later */
517 } m5xxQADC64Registers_t;
518 
519 /*
520  * Serial Communications Interface (SCI)
521  */
522 typedef struct m5xxSCIRegisters_ {
523  uint16_t sccr0;
524  uint16_t sccr1;
525  uint16_t scsr;
526  uint16_t scdr;
527 } m5xxSCIRegisters_t;
528 
529 /*
530  * Serial Peripheral Interface (SPI)
531  */
532 typedef struct m5xxSPIRegisters_ {
533  uint16_t spcr0;
534  uint16_t spcr1;
535  uint16_t spcr2;
536  uint8_t spcr3;
537  uint8_t spsr;
538 } m5xxSPIRegisters_t;
539 
540 /*
541  * Queued Serial Multi-Channel Module (QSMCM)
542  */
543 typedef struct m5xxQSMCMRegisters_ {
544  uint16_t qsmcmmcr;
545  uint16_t qtest;
546  uint16_t qdsci_il;
547  uint16_t qspi_il;
548 
549  m5xxSCIRegisters_t sci1;
550 
551  uint8_t _pad10[0x14-0x10];
552 
553  uint16_t portqs;
554  uint16_t pqspar;
555  m5xxSPIRegisters_t spi;
556 
557  m5xxSCIRegisters_t sci2;
558 
559  uint16_t qsci1cr;
560  uint16_t qsci1sr;
561  uint16_t sctq[0x10];
562  uint16_t scrq[0x10];
563 
564  uint8_t _pad6C[0x140-0x06C];
565 
566  uint16_t recram[0x20];
567  uint16_t tranram[0x20];
568  uint16_t comdram[0x20];
569 } m5xxQSMCMRegisters_t;
570 
571 /*
572  * Modular Input/Output System (MIOS)
573  */
574 typedef struct m5xxMIOS1Registers_ {
575  uint8_t pad[0x1000]; /* define later */
576 } m5xxMIOS1Registers_t;
577 
578 /*
579  * Can 2.0B Controller (TouCAN)
580  */
581 typedef struct m5xxTouCANRegisters_ {
582  uint8_t pad[0x400]; /* define later */
583 } m5xxTouCANRegisters_t;
584 
585 /*
586  * U-Bus to IMB3 Bus Interface Module (UIMB)
587  */
588 typedef struct m5xxUIMBRegisters_ {
589  uint32_t umcr;
590  uint32_t utstcreg;
591  uint32_t uipend;
592 } m5xxUIMBRegisters_t;
593 
594 /*
595  * IMB itself
596  */
597 typedef struct imb_ {
598  m5xxDPTRAMRegisters_t dptram;
599  m5xxTPU3Registers_t tpu[2];
600  m5xxQADC64Registers_t qadc[2];
601  m5xxQSMCMRegisters_t qsmcm;
602  uint8_t _pad5200[0x6000-0x5200];
603  m5xxMIOS1Registers_t mios;
604  m5xxTouCANRegisters_t toucan[2];
605  uint8_t _pad7800[0x7F80-0x7800];
606  m5xxUIMBRegisters_t uimb;
607 } imb_t;
608 
609 extern volatile imb_t imb; /* defined in linkcmds */
610 
611 
612 /*
613  * Methods shared across libcpu and the BSP.
614  */
615 void clockOn(void* unused);
616 void clockOff(void* unused);
617 int clockIsOn(void* unused);
618 rtems_isr Clock_isr(rtems_vector_number vector);
619 
620 #ifdef __cplusplus
621 }
622 #endif
623 
624 #endif /* ASM */
625 
626 #endif /* _MPC5XX_H */
m5xxQSMCMRegisters_
Definition: mpc5xx.h:543
m5xxSCIRegisters_
Definition: mpc5xx.h:522
m5xxSPIRegisters_
Definition: mpc5xx.h:532
m5xxMIOS1Registers_
Definition: mpc5xx.h:574
m5xxMEMCRegisters_
Definition: mpc5xx.h:389
m5xxUIMBRegisters_
Definition: mpc5xx.h:588
rtems_vector_number
ISR_Vector_number rtems_vector_number
Control block type used to manage the vectors.
Definition: intr.h:47
rtems_isr
ISR_Handler rtems_isr
Return type for interrupt handler.
Definition: intr.h:52
m5xxQADC64Registers_
Definition: mpc5xx.h:515
m5xxDPTRAMRegisters_
Definition: mpc5xx.h:501
m5xxTPU3Registers_
Definition: mpc5xx.h:508
Clock_isr
rtems_isr Clock_isr(rtems_vector_number vector)
Clock_isr.
Definition: clockimpl.h:134
usiu_
Definition: mpc5xx.h:397
imb_
Definition: mpc5xx.h:597
m5xxTouCANRegisters_
Definition: mpc5xx.h:581
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