RTEMS  5.1
mpc5200.h
1 /*===============================================================*\
2 | Project: RTEMS generic MPC5200 BSP |
3 +-----------------------------------------------------------------+
4 | Partially based on the code references which are named below. |
5 | Adaptions, modifications, enhancements and any recent parts of |
6 | the code are: |
7 | Copyright (c) 2005 |
8 | Embedded Brains GmbH |
9 | Obere Lagerstr. 30 |
10 | D-82178 Puchheim |
11 | Germany |
12 | rtems@embedded-brains.de |
13 +-----------------------------------------------------------------+
14 | The license and distribution terms for this file may be |
15 | found in the file LICENSE in this distribution or at |
16 | |
17 | http://www.rtems.org/license/LICENSE. |
18 | |
19 +-----------------------------------------------------------------+
20 | this file contains definitions for the mpc5200 hw registers |
21 \*===============================================================*/
22 
23 #ifndef __MPC5200_h__
24 #define __MPC5200_h__
25 
26 /* Additional Harpo Core SPR definitions (603le only) */
27 #define CSRR0 58 /* Critical Interrupt SRR0 */
28 #define CSRR1 59 /* Critical Interrupt SRR1 */
29 #define DABR2 1000 /* Data Address Breakpoint #2 */
30 #define DBCR 1001 /* Data Address Breakpoint Control */
31 #define IBCR 1002 /* Instruction Breakpoint Control */
32 #define IABR2 1018 /* Instruction Breakpoint #2 */
33 
34 /*
35  * Initial post-reset location of MGT5100 module base address register (MBAR)
36  */
37 #define MBAR_RESET 0x80000000
38 
39 /*
40  * Location and size of onchip SRAM (relative to MBAR)
41  */
42 #define ONCHIP_SRAM_OFFSET 0x8000
43 #define ONCHIP_SRAM_SIZE 0x4000
44 
45 #ifndef ASM
46 #include <rtems.h>
47 
48 #include <bsp/utility.h>
49 
50 #ifdef __cplusplus
51 extern "C" {
52 #endif
53 
54 #define MPC5200_CAN_NO 2
55 #define MPC5200_PSC_NO 6
56  /* XXX: there are only 6 PSCs, but PSC6 has an extra register gap
57  * from PSC5, therefore we instantiate seven(!) PSC register sets
58  */
59 #define MPC5200_PSC_REG_SETS 7
60 
61 #define MPC5200_GPT_NO 8
62 #define MPC5200_SLT_NO 2
63 
64 /*
65  * Bit fields for FEC interrupts, ievent and imask above.
66  */
67 #define FEC_INTR_HBERR 0x80000000 /* heartbeat error */
68 #define FEC_INTR_BABR 0x40000000 /* babbling receive error */
69 #define FEC_INTR_BABT 0x20000000 /* babbling transmit error */
70 #define FEC_INTR_GRA 0x10000000 /* graceful stop complete */
71 #define FEC_INTR_TFINT 0x08000000 /* transmit frame interrupt */
72 /* 0x04000000 reserved */
73 /* 0x02000000 reserved */
74 /* 0x01000000 reserved */
75 #define FEC_INTR_MII 0x00800000 /* MII interrupt */
76 /* 0x00400000 reserved */
77 #define FEC_INTR_LATE_COL 0x00200000 /* late collision */
78 #define FEC_INTR_COL_RETRY 0x00100000 /* collision retry limit */
79 #define FEC_INTR_XFIFO_UN 0x00080000 /* transmit FIFO error */
80 #define FEC_INTR_XFIFO_ERR 0x00040000 /* transmit FIFO error */
81 #define FEC_INTR_RFIFO_ERR 0x00020000 /* receive FIFO error */
82 /* 0x00010000 reserved */
83 /* 0x0000ffff reserved */
84 #define FEC_INTR_HBEEN FEC_INTR_HBERR
85 #define FEC_INTR_BREN FEC_INTR_BABR
86 #define FEC_INTR_BTEN FEC_INTR_BABT
87 #define FEC_INTR_GRAEN FEC_INTR_GRA
88 #define FEC_INTR_TFINTEN FEC_INTR_TFINT
89 #define FEC_INTR_MIIEN FEC_INTR_MII
90 #define FEC_INTR_LCEN FEC_INTR_LATE_COL
91 #define FEC_INTR_CRLEN FEC_INTR_COL_RETRY
92 #define FEC_INTR_XFUNEN FEC_INTR_XFIFO_UN
93 #define FEC_INTR_XFERREN FEC_INTR_XFIFO_ERR
94 #define FEC_INTR_RFERREN FEC_INTR_RFIFO_ERR
95 #define FEC_INTR_CLEAR_ALL 0xffffffff /* clear all interrupt events */
96 #define FEC_INTR_MASK_ALL 0x00000000 /* mask all interrupt events */
97 
98 /*
99  * Bit fields for FEC ethernet control, ecntrl above.
100  */
101 #define FEC_ECNTRL_TAG 0xf0000000 /* TBUS tag bits */
102 /* 0x08000000 reserved */
103 #define FEC_ECNTRL_TESTMD 0x04000000 /* test mode */
104 /* 0x03fffff8 reserved */
105 #define FEC_ECNTRL_OE 0x00000004 /* FEC output enable */
106 #define FEC_ECNTRL_EN 0x00000002 /* ethernet enable */
107 #define FEC_ECNTRL_RESET 0x00000001 /* ethernet controller reset */
108 
109 /*
110  * Bit fields for FEC receive control, r_cntrl above.
111  */
112 /* 0xf1000000 reserved */
113 #define FEC_RCNTRL_MAX_FL 0x07ff0000 /* maximum frame length */
114 #define FEC_RCNTRL_MAX_FL_SHIFT 16
115 /* 0x0000ffc0 reserved */
116 #define FEC_RCNTRL_FCE 0x00000020 /* flow control enable */
117 #define FEC_RCNTRL_BC_REJ 0x00000010 /* broadcast frame reject */
118 #define FEC_RCNTRL_PROM 0x00000008 /* promiscuous mode */
119 #define FEC_RCNTRL_MII_MODE 0x00000004 /* select 18-wire (MII) mode */
120 #define FEC_RCNTRL_DRT 0x00000002 /* disable receive on transmit */
121 #define FEC_RCNTRL_LOOP 0x00000001 /* internal loopback */
122 
123 /*
124  * Bit fields for FEC transmit control, x_cntrl above.
125  */
126 /* 0xffffffe0 reserved */
127 #define FEC_XCNTRL_RFC_PAUS 0x00000010 /* FDX flow control pause rx */
128 #define FEC_XCNTRL_TFC_PAUS 0x00000008 /* assert a PAUSE frame */
129 #define FEC_XCNTRL_FDEN 0x00000004 /* full duplex enable */
130 #define FEC_XCNTRL_HBC 0x00000002 /* heartbeat control */
131 #define FEC_XCNTRL_GTS 0x00000001 /* graceful transmit stop */
132 
133 /*
134  * Bit fields for FEC transmit status, x_status above.
135  */
136 /* 0xfc000000 reserved */
137 #define FEC_XSTAT_DEF 0x02000000 /* defer */
138 #define FEC_XSTAT_HB 0x01000000 /* heartbeat error */
139 #define FEC_XSTAT_LC 0x00800000 /* late collision */
140 #define FEC_XSTAT_RL 0x00400000 /* retry limit */
141 #define FEC_XSTAT_RC 0x003c0000 /* retry count */
142 #define FEC_XSTAT_UN 0x00020000 /* underrun */
143 #define FEX_XSTAT_CSL 0x00010000 /* carrier sense lost */
144 /* 0x0000ffff reserved */
145 
146 /*
147  * Bit fields for FEC transmit FIFO watermark, x_wmrk above.
148  */
149 #define FEC_XWMRK_64 0x00000000 /* 64 bytes written to TxFIFO */
150 #define FEC_XWMRK_128 0x00000001 /* 128 bytes written to TxFIFO */
151 #define FEC_XWMRK_192 0x00000002 /* 192 bytes written to TxFIFO */
152 #define FEC_XWMRK_256 0x00000003 /* 256 bytes written to TxFIFO */
153 #define FEC_XWMRK_320 0x00000004 /* 320 bytes written to TxFIFO */
154 #define FEC_XWMRK_384 0x00000005 /* 384 bytes written to TxFIFO */
155 #define FEC_XWMRK_448 0x00000006 /* 448 bytes written to TxFIFO */
156 #define FEC_XWMRK_512 0x00000007 /* 512 bytes written to TxFIFO */
157 #define FEC_XWMRK_576 0x00000008 /* 576 bytes written to TxFIFO */
158 #define FEC_XWMRK_640 0x00000009 /* 640 bytes written to TxFIFO */
159 #define FEC_XWMRK_704 0x0000000a /* 704 bytes written to TxFIFO */
160 #define FEC_XWMRK_768 0x0000000b /* 768 bytes written to TxFIFO */
161 #define FEC_XWMRK_832 0x0000000c /* 832 bytes written to TxFIFO */
162 #define FEC_XWMRK_896 0x0000000d /* 896 bytes written to TxFIFO */
163 #define FEC_XWMRK_960 0x0000000e /* 960 bytes written to TxFIFO */
164 #define FEC_XWMRK_1024 0x0000000f /* 1024 bytes written to TxFIFO */
165 
166 /*
167  * Bit fields for FEC transmit finite state machine.
168  */
169 /* 0xfc000000 reserved */
170 #define FEC_FSM_CRC 0x02000000 /* append CRC (typical use) */
171 #define FEC_FSM_ENFSM 0x01000000 /* enable CRC FSM (typical use) */
172 /* 0x00ffffff reserved */
173 
174 /*
175  * Bit fields for FEC FIFOs, rfifo_status, rfifo_cntrl, tfifo_status
176  * and tfifo_cntrl.
177  */
178 #define FEC_FIFO_STAT_IP 0x80000000 /* illegal pointer, sticky */
179 /* 0x70000000 reserved */
180 #define FEC_FIFO_STAT_FRAME 0x0f000000 /* frame indicator */
181 #define FEC_FIFO_STAT_FAE 0x00800000 /* frame accept error */
182 #define FEC_FIFO_STAT_RXW 0x00400000 /* receive wait condition */
183 #define FEC_FIFO_STAT_UF 0x00200000 /* underflow */
184 #define FEC_FIFO_STAT_OF 0x00100000 /* overflow */
185 #define FEC_FIFO_STAT_FR 0x00080000 /* frame ready, read-only */
186 #define FEC_FIFO_STAT_FULL 0x00040000 /* full alarm, read-only */
187 #define FEC_FIFO_STAT_ALARM 0x00020000 /* fifo alarm */
188 #define FEC_FIFO_STAT_EMPTY 0x00010000 /* empty, read-only */
189 /* 0x0000ffff reserved */
190 #define FEC_FIFO_STAT_ERROR ( FEC_FIFO_STAT_IP \
191  | FEC_FIFO_STAT_FAE \
192  | FEC_FIFO_STAT_RXW \
193  | FEC_FIFO_STAT_UF \
194  | FEC_FIFO_STAT_OF \
195  )
196 
197 /* 0x80000000 reserved */
198 #define FEC_FIFO_CNTRL_WCTL 0x40000000 /* write control */
199 #define FEC_FIFO_CNTRL_WFR 0x20000000 /* write frame */
200 /* 0x10000000 reserved */
201 #define FEC_FIFO_CNTRL_FRAME 0x08000000 /* frame mode enable */
202 #define FEC_FIFO_CNTRL_GR 0x07000000 /* last transfer granularity */
203 #define FEC_FIFO_CNTRL_GR_SHIFT 24
204 #define FEC_FIFO_CNTRL_IP_MASK 0x00800000 /* illegal pointer mask */
205 #define FEC_FIFO_CNTRL_FAE_MASK 0x00400000 /* frame accept mask */
206 #define FEC_FIFO_CNTRL_RXW_MASK 0x00200000 /* receive wait mask */
207 #define FEC_FIFO_CNTRL_UF_MASK 0x00100000 /* underflow mask */
208 #define FEC_FIFO_CNTRL_OF_MASK 0x00080000 /* overflow mask */
209 /* 0x0007ffff reserved */
210 
211 #define SDMA_TCR_EN BSP_BBIT16(0)
212 #define SDMA_TCR_VAL BSP_BBIT16(1)
213 #define SDMA_TCR_ALW_INIT BSP_BBIT16(2)
214 #define SDMA_TCR_IN(val) BSP_BFLD16(val, 3, 7)
215 #define SDMA_TCR_AUTO_START BSP_BBIT16(8)
216 #define SDMA_TCR_HIGH_EN BSP_BBIT16(9)
217 #define SDMA_TCR_HOLD BSP_BBIT16(10)
218 #define SDMA_TCR_AS(val) BSP_BFLD16(val, 12, 15)
219 
220 #define SDMA_IPR_HOLD BSP_BBIT8(0)
221 #define SDMA_IPR_PRIOR(val) BSP_BFLD8(val, 5, 7)
222 
223 #define SDMA_REQMUX_SET_31(reg, val) BSP_BFLD32SET(reg, val, 0, 1)
224 #define SDMA_REQMUX_SET_30(reg, val) BSP_BFLD32SET(reg, val, 2, 3)
225 #define SDMA_REQMUX_SET_29(reg, val) BSP_BFLD32SET(reg, val, 4, 5)
226 #define SDMA_REQMUX_SET_28(reg, val) BSP_BFLD32SET(reg, val, 6, 7)
227 #define SDMA_REQMUX_SET_27(reg, val) BSP_BFLD32SET(reg, val, 8, 9)
228 #define SDMA_REQMUX_SET_26(reg, val) BSP_BFLD32SET(reg, val, 10, 11)
229 #define SDMA_REQMUX_SET_25(reg, val) BSP_BFLD32SET(reg, val, 12, 13)
230 #define SDMA_REQMUX_SET_24(reg, val) BSP_BFLD32SET(reg, val, 14, 15)
231 #define SDMA_REQMUX_SET_23(reg, val) BSP_BFLD32SET(reg, val, 16, 17)
232 #define SDMA_REQMUX_SET_22(reg, val) BSP_BFLD32SET(reg, val, 18, 19)
233 #define SDMA_REQMUX_SET_21(reg, val) BSP_BFLD32SET(reg, val, 20, 21)
234 #define SDMA_REQMUX_SET_20(reg, val) BSP_BFLD32SET(reg, val, 22, 23)
235 #define SDMA_REQMUX_SET_19(reg, val) BSP_BFLD32SET(reg, val, 24, 25)
236 #define SDMA_REQMUX_SET_18(reg, val) BSP_BFLD32SET(reg, val, 26, 27)
237 #define SDMA_REQMUX_SET_17(reg, val) BSP_BFLD32SET(reg, val, 28, 29)
238 #define SDMA_REQMUX_SET_16(reg, val) BSP_BFLD32SET(reg, val, 30, 31)
239 
240 /* SDMA / BestComm */
241 typedef struct {
242  uint32_t taskBar;
243  uint32_t currentPointer;
244  uint32_t endPointer;
245  uint32_t variablePointer;
246  uint8_t IntVect1;
247  uint8_t IntVect2;
248  uint16_t PtdCntrl;
249  uint32_t IntPend;
250  uint32_t IntMask;
251  uint16_t tcr [16];
252  uint8_t ipr [32];
253  uint32_t cReqSelect;
254  uint32_t task_size0;
255  uint32_t task_size1;
256  uint32_t reserved_0;
257  uint32_t reserved_1;
258  uint32_t Value1;
259  uint32_t Value2;
260  uint32_t Control;
261  uint32_t Status;
262 } mpc5200_sdma;
263 
264 typedef struct {
265 #define CSC_CFG_WAITP(val) BSP_BFLD32(val, 0, 7)
266 #define CSC_CFG_WAITX(val) BSP_BFLD32(val, 8, 15)
267 #define CSC_CFG_MX BSP_BBIT32(16)
268 #define CSC_CFG_AA BSP_BBIT32(18)
269 #define CSC_CFG_CE BSP_BBIT32(19)
270 #define CSC_CFG_AS(val) BSP_BFLD32(val, 20, 21)
271 #define CSC_CFG_DS(val) BSP_BFLD32(val, 22, 23)
272 #define CSC_CFG_BANK(val) BSP_BFLD32(val, 24, 25)
273 #define CSC_CFG_WTYP(val) BSP_BFLD32(val, 26, 27)
274 #define CSC_CFG_WS BSP_BBIT32(28)
275 #define CSC_CFG_RS BSP_BBIT32(29)
276 #define CSC_CFG_WO BSP_BBIT32(30)
277 #define CSC_CFG_RO BSP_BBIT32(31)
278  uint32_t config_0;
279  uint32_t config_1;
280  uint32_t config_2;
281  uint32_t config_3;
282  uint32_t config_4;
283  uint32_t config_5;
284 
285 #define CSC_CTRL_ME BSP_BBIT32(7)
286  uint32_t control;
287 
288 #define CSC_STAT_WOERR BSP_BBIT32(2)
289 #define CSC_STAT_ROERR BSP_BBIT32(3)
290 #define CSC_STAT_GET_CSXERR(reg) BSP_BFLD32GET(reg, 5, 7)
291  uint32_t status;
292 
293  uint32_t config_6;
294  uint32_t config_7;
295 
296 #define CSC_BST_CTRL_CW7 BSP_BBIT32(0)
297 #define CSC_BST_CTRL_SLB7 BSP_BBIT32(1)
298 #define CSC_BST_CTRL_BRE7 BSP_BBIT32(3)
299 #define CSC_BST_CTRL_CW6 BSP_BBIT32(4)
300 #define CSC_BST_CTRL_SLB6 BSP_BBIT32(5)
301 #define CSC_BST_CTRL_BRE6 BSP_BBIT32(7)
302 #define CSC_BST_CTRL_CW5 BSP_BBIT32(8)
303 #define CSC_BST_CTRL_SLB5 BSP_BBIT32(9)
304 #define CSC_BST_CTRL_BRE5 BSP_BBIT32(11)
305 #define CSC_BST_CTRL_CW4 BSP_BBIT32(12)
306 #define CSC_BST_CTRL_SLB4 BSP_BBIT32(13)
307 #define CSC_BST_CTRL_BRE4 BSP_BBIT32(15)
308 #define CSC_BST_CTRL_CW3 BSP_BBIT32(16)
309 #define CSC_BST_CTRL_SLB3 BSP_BBIT32(17)
310 #define CSC_BST_CTRL_BRE3 BSP_BBIT32(19)
311 #define CSC_BST_CTRL_CW2 BSP_BBIT32(20)
312 #define CSC_BST_CTRL_SLB2 BSP_BBIT32(21)
313 #define CSC_BST_CTRL_BRE2 BSP_BBIT32(23)
314 #define CSC_BST_CTRL_CW1 BSP_BBIT32(24)
315 #define CSC_BST_CTRL_SLB1 BSP_BBIT32(25)
316 #define CSC_BST_CTRL_BRE1 BSP_BBIT32(27)
317 #define CSC_BST_CTRL_CW0 BSP_BBIT32(28)
318 #define CSC_BST_CTRL_SLB0 BSP_BBIT32(29)
319 #define CSC_BST_CTRL_BRE0 BSP_BBIT32(31)
320  uint32_t burst_control;
321 
322 #define CSC_DCYC_CTRL_DC7(val) BSP_BFLD32(val, 2, 3)
323 #define CSC_DCYC_CTRL_SET_DC7(reg, val) BSP_BFLD32SET(reg, val, 2, 3)
324 #define CSC_DCYC_CTRL_DC6(val) BSP_BFLD32(val, 6, 7)
325 #define CSC_DCYC_CTRL_SET_DC6(reg, val) BSP_BFLD32SET(reg, val, 6, 7)
326 #define CSC_DCYC_CTRL_DC5(val) BSP_BFLD32(val, 10, 11)
327 #define CSC_DCYC_CTRL_SET_DC5(reg, val) BSP_BFLD32SET(reg, val, 10, 11)
328 #define CSC_DCYC_CTRL_DC4(val) BSP_BFLD32(val, 14, 15)
329 #define CSC_DCYC_CTRL_SET_DC4(reg, val) BSP_BFLD32SET(reg, val, 14, 15)
330 #define CSC_DCYC_CTRL_DC3(val) BSP_BFLD32(val, 18, 19)
331 #define CSC_DCYC_CTRL_SET_DC3(reg, val) BSP_BFLD32SET(reg, val, 18, 19)
332 #define CSC_DCYC_CTRL_DC2(val) BSP_BFLD32(val, 22, 23)
333 #define CSC_DCYC_CTRL_SET_DC2(reg, val) BSP_BFLD32SET(reg, val, 22, 23)
334 #define CSC_DCYC_CTRL_DC1(val) BSP_BFLD32(val, 26, 27)
335 #define CSC_DCYC_CTRL_SET_DC1(reg, val) BSP_BFLD32SET(reg, val, 26, 27)
336 #define CSC_DCYC_CTRL_DC0(val) BSP_BFLD32(val, 30, 31)
337 #define CSC_DCYC_CTRL_SET_DC0(reg, val) BSP_BFLD32SET(reg, val, 30, 31)
338  uint32_t deadcycle_control;
339 
340  uint8_t reserved [208];
341 } mpc5200_csc;
342 
343 typedef struct {
344  uint32_t memory_address_base;
345  uint32_t cs0_start_address;
346  uint32_t cs0_stop_address;
347  uint32_t cs1_start_address;
348  uint32_t cs1_stop_address;
349  uint32_t cs2_start_address;
350  uint32_t cs2_stop_address;
351  uint32_t cs3_start_address;
352  uint32_t cs3_stop_address;
353  uint32_t cs4_start_address;
354  uint32_t cs4_stop_address;
355  uint32_t cs5_start_address;
356  uint32_t cs5_stop_address;
357  uint32_t sdram_chip_select_0;
358  uint32_t sdram_chip_select_1;
359  uint8_t reserved_0 [16];
360  uint32_t boot_start_address;
361  uint32_t boot_stop_address;
362 
363 #define MM_IPBI_CTRL_CS7ENA BSP_BBIT16(4)
364 #define MM_IPBI_CTRL_CS6ENA BSP_BBIT16(5)
365 #define MM_IPBI_CTRL_BOOTENA BSP_BBIT16(6)
366 #define MM_IPBI_CTRL_CS5ENA BSP_BBIT16(10)
367 #define MM_IPBI_CTRL_CS4ENA BSP_BBIT16(11)
368 #define MM_IPBI_CTRL_CS3ENA BSP_BBIT16(12)
369 #define MM_IPBI_CTRL_CS2ENA BSP_BBIT16(13)
370 #define MM_IPBI_CTRL_CS1ENA BSP_BBIT16(14)
371 #define MM_IPBI_CTRL_CS0ENA BSP_BBIT16(15)
372  uint16_t ipbi_control;
373 
374  uint16_t wait_state_enable;
375  uint32_t cs6_start_address;
376  uint32_t cs6_stop_address;
377  uint32_t cs7_start_address;
378  uint32_t cs7_stop_address;
379  uint8_t reserved_1 [152];
380 } mpc5200_mm;
381 
382 /*
383 *************************************************************************
384 * MPC5x00 internal register memory map *
385 *************************************************************************
386 */
387 typedef struct mpc5200_ {
388  /*
389  * memory map registers (MBAR + 0)
390  */
391  volatile mpc5200_mm mm;
392 
393  /*
394  * SDRAM memory controller registers (MBAR + 0x100)
395  */
396  volatile uint8_t mc[0x100];
397 
398  /*
399  * clock distribution module registers (MBAR + 0x200)
400  */
401  volatile uint8_t cdm[0x100];
402 
403  /*
404  * chip selct controller registers(MBAR + 0x300)
405  */
406  volatile mpc5200_csc csc;
407 
408  /*
409  * SmartComm timer registers (MBAR + 0x400)
410  */
411  volatile uint8_t sct[0x100];
412 
413  /*
414  * interrupt controller registers (MBAR + 0x500)
415  */
416  volatile uint32_t per_mask; /* + 0x00 */
417  volatile uint32_t per_pri_1; /* + 0x04 */
418  volatile uint32_t per_pri_2; /* + 0x08 */
419  volatile uint32_t per_pri_3; /* + 0x0C */
420 
421 #define ICTL_EET_ECLR0 BSP_BBIT32(4)
422 #define ICTL_EET_ECLR1 BSP_BBIT32(5)
423 #define ICTL_EET_ECLR2 BSP_BBIT32(6)
424 #define ICTL_EET_ECLR3 BSP_BBIT32(7)
425 #define ICTL_EET_ETYPE0(val) BSP_BFLD32(val, 8, 9)
426 #define ICTL_EET_ETYPE1(val) BSP_BFLD32(val, 10, 11)
427 #define ICTL_EET_ETYPE2(val) BSP_BFLD32(val, 12, 13)
428 #define ICTL_EET_ETYPE3(val) BSP_BFLD32(val, 14, 15)
429 #define ICTL_EET_SET_ETYPE0(reg, val) BSP_BFLD32SET(reg, val, 8, 9)
430 #define ICTL_EET_SET_ETYPE1(reg, val) BSP_BFLD32SET(reg, val, 10, 11)
431 #define ICTL_EET_SET_ETYPE2(reg, val) BSP_BFLD32SET(reg, val, 12, 13)
432 #define ICTL_EET_SET_ETYPE3(reg, val) BSP_BFLD32SET(reg, val, 14, 15)
433 #define ICTL_EET_MEE BSP_BBIT32(19)
434 #define ICTL_EET_EENA0 BSP_BBIT32(20)
435 #define ICTL_EET_EENA1 BSP_BBIT32(21)
436 #define ICTL_EET_EENA2 BSP_BBIT32(22)
437 #define ICTL_EET_EENA3 BSP_BBIT32(23)
438 #define ICTL_EET_CEB BSP_BBIT32(31)
439 
440  volatile uint32_t ext_en_type; /* + 0x10 */
441  volatile uint32_t crit_pri_main_mask;/* + 0x14 */
442  volatile uint32_t main_pri_1; /* + 0x18 */
443  volatile uint32_t main_pri_2; /* + 0x1C */
444  volatile uint32_t res1; /* + 0x20 */
445  volatile uint32_t pmce; /* + 0x24 */
446  volatile uint32_t csa; /* + 0x28 */
447  volatile uint32_t msa; /* + 0x2C */
448  volatile uint32_t psa; /* + 0x30 */
449  volatile uint32_t res2; /* + 0x34 */
450  volatile uint32_t psa_be; /* + 0x38 */
451  volatile uint8_t res3[0xC4]; /* + 0x3C */
452 
453  /*
454  * general pupose timer registers (MBAR + 0x600/+ 0x610/+ 0x620/+ 0x630/+ 0x640/+ 0x650/+ 0x660/+ 0x670)
455  */
456  struct mpc5200_gpt {
457  volatile uint32_t emsel; /* + 0x00 */
458  volatile uint32_t count_in; /* + 0x04 */
459  volatile uint32_t pwm_conf; /* + 0x08 */
460  volatile uint32_t status; /* + 0x0C */
461  } gpt[MPC5200_GPT_NO];
462 
463 #define GPT_STATUS_RESET 0x0000000F
464 #define GPT_STATUS_TEXP (1 << 3)
465 #define GPT_STATUS_PIN (1 << 8)
466 #define GPT_EMSEL_GPIO_DIR (2 << 4)
467 #define GPT_EMSEL_GPIO_OUT (1 << 4)
468 #define GPT_EMSEL_GPIO_OUT_HIGH (3 << 4)
469 #define GPT_EMSEL_TIMER_MS_GPIO (4 << 0)
470 #define GPT_EMSEL_GPIO_IN (0 << 0)
471 #define GPT_EMSEL_CE (1 << 12)
472 #define GPT_EMSEL_ST_CONT (1 << 10)
473 #define GPT_EMSEL_INTEN (1 << 8)
474 #define GPT_EMSEL_WDEN (1 << 15)
475 
476 #define GPT0 0
477 #define GPT1 1
478 #define GPT2 2
479 #define GPT3 3
480 #define GPT4 4
481 #define GPT5 5
482 #define GPT6 6
483 #define GPT7 7
484 
485  volatile uint8_t gpt_res[0x80];
486 
487  /*
488  * slice time registers (MBAR + 0x700/+ 0x710)
489  */
490  struct mpc5200_slt {
491  volatile uint32_t tcr; /* + 0x00 */
492  volatile uint32_t cntrl; /* + 0x04 */
493  volatile uint32_t cvr; /* + 0x08 */
494  volatile uint32_t tsr; /* + 0x0C */
495  } slt[MPC5200_SLT_NO];
496 
497  volatile uint8_t slt_res[0xE0];
498 
499  /*
500  * real time clock registers (MBAR + 0x800)
501  */
502  volatile uint8_t rtc[0x100];
503 
504 
505  /*
506  * MSCAN registers (MBAR + 0x900 /+ 0x980)
507  */
508  struct mpc5200_mscan {
509  volatile uint8_t ctl0; /* + 0x0 */
510  volatile uint8_t ctl1; /* + 0x1 */
511  volatile uint8_t res1; /* + 0x2 */
512  volatile uint8_t res2; /* + 0x3 */
513  volatile uint8_t btr0; /* + 0x4 */
514  volatile uint8_t btr1; /* + 0x5 */
515  volatile uint8_t res3; /* + 0x6 */
516  volatile uint8_t res4; /* + 0x7 */
517  volatile uint8_t rflg; /* + 0x8 */
518  volatile uint8_t rier; /* + 0x9 */
519  volatile uint8_t res5; /* + 0xA */
520  volatile uint8_t res6; /* + 0xB */
521  volatile uint8_t tflg; /* + 0xC */
522  volatile uint8_t tier; /* + 0xD */
523  volatile uint8_t res7; /* + 0xE */
524  volatile uint8_t res8; /* + 0xF */
525  volatile uint8_t tarq; /* + 0x10 */
526  volatile uint8_t taak; /* + 0x11 */
527  volatile uint8_t res9; /* + 0x12 */
528  volatile uint8_t res10; /* + 0x13 */
529  volatile uint8_t bsel; /* + 0x14 */
530  volatile uint8_t idac; /* + 0x15 */
531  volatile uint8_t res11; /* + 0x16 */
532  volatile uint8_t res12; /* + 0x17 */
533  volatile uint8_t res13; /* + 0x18 */
534  volatile uint8_t res14; /* + 0x19 */
535  volatile uint8_t res15; /* + 0x1A */
536  volatile uint8_t res16; /* + 0x1B */
537  volatile uint8_t rxerr; /* + 0x1C */
538  volatile uint8_t txerr; /* + 0x1D */
539  volatile uint8_t res17; /* + 0x1E */
540  volatile uint8_t res18; /* + 0x1F */
541  volatile uint8_t idar0; /* + 0x20 */
542  volatile uint8_t idar1; /* + 0x21 */
543  volatile uint8_t res19; /* + 0x22 */
544  volatile uint8_t res20; /* + 0x23 */
545  volatile uint8_t idar2; /* + 0x24 */
546  volatile uint8_t idar3; /* + 0x25 */
547  volatile uint8_t res21; /* + 0x26 */
548  volatile uint8_t res22; /* + 0x27 */
549  volatile uint8_t idmr0; /* + 0x28 */
550  volatile uint8_t idmr1; /* + 0x29 */
551  volatile uint8_t res23; /* + 0x2A */
552  volatile uint8_t res24; /* + 0x2B */
553  volatile uint8_t idmr2; /* + 0x2C */
554  volatile uint8_t idmr3; /* + 0x2D */
555  volatile uint8_t res25; /* + 0x2E */
556  volatile uint8_t res26; /* + 0x2F */
557  volatile uint8_t idar4; /* + 0x30 */
558  volatile uint8_t idar5; /* + 0x31 */
559  volatile uint8_t res27; /* + 0x32 */
560  volatile uint8_t res28; /* + 0x33 */
561  volatile uint8_t idar6; /* + 0x34 */
562  volatile uint8_t idar7; /* + 0x35 */
563  volatile uint8_t res29; /* + 0x36 */
564  volatile uint8_t res30; /* + 0x37 */
565  volatile uint8_t idmr4; /* + 0x38 */
566  volatile uint8_t idmr5; /* + 0x39 */
567  volatile uint8_t res31; /* + 0x3A */
568  volatile uint8_t res32; /* + 0x3B */
569  volatile uint8_t idmr6; /* + 0x3C */
570  volatile uint8_t idmr7; /* + 0x3D */
571  volatile uint8_t res33; /* + 0x3E */
572  volatile uint8_t res34; /* + 0x3F */
573  volatile uint8_t rxidr0; /* + 0x40 */
574  volatile uint8_t rxidr1; /* + 0x41 */
575  volatile uint8_t res35; /* + 0x42 */
576  volatile uint8_t res36; /* + 0x43 */
577  volatile uint8_t rxidr2; /* + 0x44 */
578  volatile uint8_t rxidr3; /* + 0x45 */
579  volatile uint8_t res37; /* + 0x46 */
580  volatile uint8_t res38; /* + 0x47 */
581  volatile uint8_t rxdsr0; /* + 0x48 */
582  volatile uint8_t rxdsr1; /* + 0x49 */
583  volatile uint8_t res39; /* + 0x4A */
584  volatile uint8_t res40; /* + 0x4B */
585  volatile uint8_t rxdsr2; /* + 0x4C */
586  volatile uint8_t rxdsr3; /* + 0x4D */
587  volatile uint8_t res41; /* + 0x4E */
588  volatile uint8_t res42; /* + 0x4F */
589  volatile uint8_t rxdsr4; /* + 0x50 */
590  volatile uint8_t rxdsr5; /* + 0x51 */
591  volatile uint8_t res43; /* + 0x52 */
592  volatile uint8_t res44; /* + 0x53 */
593  volatile uint8_t rxdsr6; /* + 0x54 */
594  volatile uint8_t rxdsr7; /* + 0x55 */
595  volatile uint8_t res45; /* + 0x56 */
596  volatile uint8_t res46; /* + 0x57 */
597  volatile uint8_t rxdlr; /* + 0x58 */
598  volatile uint8_t res47; /* + 0x59 */
599  volatile uint8_t res48; /* + 0x5A */
600  volatile uint8_t res49; /* + 0x5B */
601  volatile uint8_t rxtimh; /* + 0x5C */
602  volatile uint8_t rxtiml; /* + 0x5D */
603  volatile uint8_t res50; /* + 0x5E */
604  volatile uint8_t res51; /* + 0x5F */
605  volatile uint8_t txidr0; /* + 0x60 */
606  volatile uint8_t txidr1; /* + 0x61 */
607  volatile uint8_t res52; /* + 0x62 */
608  volatile uint8_t res53; /* + 0x63 */
609  volatile uint8_t txidr2; /* + 0x64 */
610  volatile uint8_t txidr3; /* + 0x65 */
611  volatile uint8_t res54; /* + 0x66 */
612  volatile uint8_t res55; /* + 0x67 */
613  volatile uint8_t txdsr0; /* + 0x68 */
614  volatile uint8_t txdsr1; /* + 0x69 */
615  volatile uint8_t res56; /* + 0x6A */
616  volatile uint8_t res57; /* + 0x6B */
617  volatile uint8_t txdsr2; /* + 0x6C */
618  volatile uint8_t txdsr3; /* + 0x6D */
619  volatile uint8_t res58; /* + 0x6E */
620  volatile uint8_t res59; /* + 0x6F */
621  volatile uint8_t txdsr4; /* + 0x70 */
622  volatile uint8_t txdsr5; /* + 0x71 */
623  volatile uint8_t res60; /* + 0x72 */
624  volatile uint8_t res61; /* + 0x73 */
625  volatile uint8_t txdsr6; /* + 0x74 */
626  volatile uint8_t txdsr7; /* + 0x75 */
627  volatile uint8_t res62; /* + 0x76 */
628  volatile uint8_t res63; /* + 0x77 */
629  volatile uint8_t txdlr; /* + 0x78 */
630  volatile uint8_t txtbpr; /* + 0x79 */
631  volatile uint8_t res64; /* + 0x7A */
632  volatile uint8_t res65; /* + 0x7B */
633  volatile uint8_t txtimh; /* + 0x7C */
634  volatile uint8_t txtiml; /* + 0x7D */
635  volatile uint8_t res66; /* + 0x7E */
636  volatile uint8_t res67; /* + 0x7F */
637  } mscan[MPC5200_CAN_NO];
638 
639  volatile uint8_t res[0x100];
640 
641  /*
642  * GPIO standard registers (MBAR + 0xB00)
643  */
644  volatile uint32_t gpiopcr; /* + 0x00 */
645  #define GPIO_PCR_CHIP_SELECT_1 0x80000000
646  #define GPIO_PCR_CHIP_ALTS 0x30000000
647  #define GPIO_PCR_CHIP_ALTS_NONE 0x00000000
648  #define GPIO_PCR_CHIP_ALTS_CAN 0x10000000
649  #define GPIO_PCR_CHIP_ALTS_SPI 0x20000000
650  #define GPIO_PCR_CHIP_ALTS_BOTH 0x30000000
651  #define GPIO_PCR_CHIP_SELECT_7 0x08000000
652  #define GPIO_PCR_CHIP_SELECT_6 0x04000000
653  #define GPIO_PCR_CHIP_SELECT_ATA 0x03000000
654  #define GPIO_PCR_CHIP_SELECT_IR_USB_CLK 0x00800000
655  #define GPIO_PCR_IRDA 0x00700000
656  #define GPIO_PCR_ETHERNET 0x000F0000
657  #define GPIO_PCR_PCI_DIS 0x00008000
658  #define GPIO_PCR_USB_SE 0x00004000
659  #define GPIO_PCR_USB_GPIO 0x00003000
660  #define GPIO_PCR_PSC3 0x00000F00
661  #define GPIO_PCR_PSC2 0x00000070
662  #define GPIO_PCR_PSC1 0x00000007
663 
664  #define GPIO_S_PIN_IR_USB_CLK BSP_BBIT32(2)
665  #define GPIO_S_PIN_IRDA_TX BSP_BBIT32(3)
666  #define GPIO_S_PIN_ETH_11 BSP_BBIT32(4)
667  #define GPIO_S_PIN_ETH_10 BSP_BBIT32(5)
668  #define GPIO_S_PIN_ETH_9 BSP_BBIT32(6)
669  #define GPIO_S_PIN_ETH_8 BSP_BBIT32(7)
670  #define GPIO_S_PIN_USB1_8 BSP_BBIT32(12)
671  #define GPIO_S_PIN_USB1_7 BSP_BBIT32(13)
672  #define GPIO_S_PIN_USB1_6 BSP_BBIT32(14)
673  #define GPIO_S_PIN_USB1_0 BSP_BBIT32(15)
674  #define GPIO_S_PIN_PSC3_7 BSP_BBIT32(18)
675  #define GPIO_S_PIN_PSC3_6 BSP_BBIT32(19)
676  #define GPIO_S_PIN_PSC3_3 BSP_BBIT32(20)
677  #define GPIO_S_PIN_PSC3_2 BSP_BBIT32(21)
678  #define GPIO_S_PIN_PSC3_1 BSP_BBIT32(22)
679  #define GPIO_S_PIN_PSC3_0 BSP_BBIT32(23)
680  #define GPIO_S_PIN_PSC2_3 BSP_BBIT32(24)
681  #define GPIO_S_PIN_PSC2_2 BSP_BBIT32(25)
682  #define GPIO_S_PIN_PSC2_1 BSP_BBIT32(26)
683  #define GPIO_S_PIN_PSC2_0 BSP_BBIT32(27)
684  #define GPIO_S_PIN_PSC1_3 BSP_BBIT32(28)
685  #define GPIO_S_PIN_PSC1_2 BSP_BBIT32(29)
686  #define GPIO_S_PIN_PSC1_1 BSP_BBIT32(30)
687  #define GPIO_S_PIN_PSC1_0 BSP_BBIT32(31)
688 
689  volatile uint32_t gpiosen; /* + 0x04 */
690  volatile uint32_t gpiosod; /* + 0x08 */
691  volatile uint32_t gpiosdd; /* + 0x0C */
692  volatile uint32_t gpiosdo; /* + 0x10 */
693  volatile uint32_t gpiosdi; /* + 0x14 */
694 
695  #define GPIO_O_PIN_ETH_7 BSP_BBIT32(0)
696  #define GPIO_O_PIN_ETH_6 BSP_BBIT32(1)
697  #define GPIO_O_PIN_ETH_5 BSP_BBIT32(2)
698  #define GPIO_O_PIN_ETH_4 BSP_BBIT32(3)
699  #define GPIO_O_PIN_ETH_3 BSP_BBIT32(4)
700  #define GPIO_O_PIN_ETH_2 BSP_BBIT32(5)
701  #define GPIO_O_PIN_ETH_1 BSP_BBIT32(6)
702  #define GPIO_O_PIN_ETH_0 BSP_BBIT32(7)
703  #define GPIO_O_PIN_I2C_3 BSP_BBIT32(13)
704  #define GPIO_O_PIN_I2C_0 BSP_BBIT32(14)
705  #define GPIO_O_PIN_I2C_1 BSP_BBIT32(15)
706 
707  volatile uint32_t gpiooe; /* + 0x18 */
708  volatile uint32_t gpioodo; /* + 0x1C */
709 
710  #define GPIO_I_PIN_ETH_16 BSP_BBIT32(0)
711  #define GPIO_I_PIN_ETH_15 BSP_BBIT32(1)
712  #define GPIO_I_PIN_ETH_14 BSP_BBIT32(2)
713  #define GPIO_I_PIN_ETH_13 BSP_BBIT32(3)
714  #define GPIO_I_PIN_USB1_9 BSP_BBIT32(4)
715  #define GPIO_I_PIN_PSC3_8 BSP_BBIT32(5)
716  #define GPIO_I_PIN_PSC3_5 BSP_BBIT32(6)
717  #define GPIO_I_PIN_PSC3_4 BSP_BBIT32(7)
718 
719  volatile uint32_t gpiosie; /* + 0x20 */
720  #define GPIO_SIE_SINT_7_ETH_16_PIN 0x80000000
721  #define GPIO_SIE_SINT_6_ETH_15_PIN 0x40000000
722  #define GPIO_SIE_SINT_5_ETH_14_PIN 0x20000000
723  #define GPIO_SIE_SINT_4_ETH_13_PIN 0x10000000
724  #define GPIO_SIE_SINT_3_USB1_9_PIN 0x08000000
725  #define GPIO_SIE_SINT_2_PSC3_8_PIN 0x04000000
726  #define GPIO_SIE_SINT_1_PSC3_5_PIN 0x02000000
727  #define GPIO_SIE_SINT_0_PSC3_4_PIN 0x01000000
728 
729  volatile uint32_t gpiosiod; /* + 0x24 */
730 
731  volatile uint32_t gpiosidd; /* + 0x28 */
732  #define GPIO_SIDD_SINT_7_ETH_16_PIN 0x80000000
733  #define GPIO_SIDD_SINT_6_ETH_15_PIN 0x40000000
734  #define GPIO_SIDD_SINT_5_ETH_14_PIN 0x20000000
735  #define GPIO_SIDD_SINT_4_ETH_13_PIN 0x10000000
736  #define GPIO_SIDD_SINT_3_USB1_9_PIN 0x08000000
737  #define GPIO_SIDD_SINT_2_PSC3_8_PIN 0x04000000
738  #define GPIO_SIDD_SINT_1_PSC3_5_PIN 0x02000000
739  #define GPIO_SIDD_SINT_0_PSC3_4_PIN 0x01000000
740 
741  volatile uint32_t gpiosido; /* + 0x2C */
742 
743  volatile uint32_t gpiosiie; /* + 0x30 */
744  #define GPIO_SIIE_SINT_7_ETH_16_PIN 0x80000000
745  #define GPIO_SIIE_SINT_6_ETH_15_PIN 0x40000000
746  #define GPIO_SIIE_SINT_5_ETH_14_PIN 0x20000000
747  #define GPIO_SIIE_SINT_4_ETH_13_PIN 0x10000000
748  #define GPIO_SIIE_SINT_3_USB1_9_PIN 0x08000000
749  #define GPIO_SIIE_SINT_2_PSC3_8_PIN 0x04000000
750  #define GPIO_SIIE_SINT_1_PSC3_5_PIN 0x02000000
751  #define GPIO_SIIE_SINT_0_PSC3_4_PIN 0x01000000
752 
753  volatile uint32_t gpiosiit; /* + 0x34 */
754  #define GPIO_SIIT_SET_ETH_16_PIN(reg, val) BSP_BFLD32SET(reg, val, 0, 1)
755  #define GPIO_SIIT_SET_ETH_15_PIN(reg, val) BSP_BFLD32SET(reg, val, 2, 3)
756  #define GPIO_SIIT_SET_ETH_14_PIN(reg, val) BSP_BFLD32SET(reg, val, 4, 5)
757  #define GPIO_SIIT_SET_ETH_13_PIN(reg, val) BSP_BFLD32SET(reg, val, 6, 7)
758  #define GPIO_SIIT_SET_USB1_9_PIN(reg, val) BSP_BFLD32SET(reg, val, 8, 9)
759  #define GPIO_SIIT_SET_PSC3_8_PIN(reg, val) BSP_BFLD32SET(reg, val, 10, 11)
760  #define GPIO_SIIT_SET_PSC3_5_PIN(reg, val) BSP_BFLD32SET(reg, val, 12, 13)
761  #define GPIO_SIIT_SET_PSC3_4_PIN(reg, val) BSP_BFLD32SET(reg, val, 14, 15)
762 
763  #define GPIO_SIIT_SINT_7_ETH_16_PIN_MASK 0xc0000000
764  #define GPIO_SIIT_SINT_6_ETH_15_PIN_MASK 0x30000000
765  #define GPIO_SIIT_SINT_5_ETH_14_PIN_MASK 0x0c000000
766  #define GPIO_SIIT_SINT_4_ETH_13_PIN_MASK 0x03000000
767  #define GPIO_SIIT_SINT_3_USB1_9_PIN_MASK 0x00c00000
768  #define GPIO_SIIT_SINT_2_PSC3_8_PIN_MASK 0x00300000
769  #define GPIO_SIIT_SINT_1_PSC3_5_PIN_MASK 0x000c0000
770  #define GPIO_SIIT_SINT_0_PSC3_4_PIN_MASK 0x00030000
771 
772  #define GPIO_SIIT_ON_ANY_TRANSITION 0x00000000
773  #define GPIO_SIIT_ON_RISING_EDGE 0x00000001
774  #define GPIO_SIIT_ON_FALLING_EDGE 0x00000002
775  #define GPIO_SIIT_ON_PULSE 0x00000003
776 
777  #define GPIO_SIIT_SINT_7_ETH_16_PIN_SHIFT 16
778  #define GPIO_SIIT_SINT_6_ETH_15_PIN_SHIFT 18
779  #define GPIO_SIIT_SINT_5_ETH_14_PIN_SHIFT 20
780  #define GPIO_SIIT_SINT_4_ETH_13_PIN_SHIFT 22
781  #define GPIO_SIIT_SINT_3_USB1_9_PIN_SHIFT 24
782  #define GPIO_SIIT_SINT_2_PSC3_8_PIN_SHIFT 26
783  #define GPIO_SIIT_SINT_1_PSC3_5_PIN_SHIFT 28
784  #define GPIO_SIIT_SINT_0_PSC3_4_PIN_SHIFT 30
785 
786  volatile uint32_t gpiosime; /* + 0x38 */
787  #define GPIO_SIME_MASTER_ENABLE 0x10000000
788 
789  volatile uint32_t gpiosist; /* + 0x3C */
790  #define GPIO_SIST_SINT_7_ETH_16_PIN_STATUS 0x80000000
791  #define GPIO_SIST_SINT_6_ETH_15_PIN_STATUS 0x40000000
792  #define GPIO_SIST_SINT_5_ETH_14_PIN_STATUS 0x20000000
793  #define GPIO_SIST_SINT_4_ETH_13_PIN_STATUS 0x10000000
794  #define GPIO_SIST_SINT_3_USB1_9_PIN_STATUS 0x08000000
795  #define GPIO_SIST_SINT_2_PSC3_8_PIN_STATUS 0x04000000
796  #define GPIO_SIST_SINT_1_PSC3_5_PIN_STATUS 0x02000000
797  #define GPIO_SIST_SINT_0_PSC3_4_PIN_STATUS 0x01000000
798  #define GPIO_SIST_SINT_7_ETH_16_PIN_VALUE 0x00800000
799  #define GPIO_SIST_SINT_6_ETH_15_PIN_VALUE 0x00400000
800  #define GPIO_SIST_SINT_5_ETH_14_PIN_VALUE 0x00200000
801  #define GPIO_SIST_SINT_4_ETH_13_PIN_VALUE 0x00100000
802  #define GPIO_SIST_SINT_3_USB1_9_PIN_VALUE 0x00080000
803  #define GPIO_SIST_SINT_2_PSC3_8_PIN_VALUE 0x00040000
804  #define GPIO_SIST_SINT_1_PSC3_5_PIN_VALUE 0x00020000
805  #define GPIO_SIST_SINT_0_PSC3_4_PIN_VALUE 0x00010000
806 
807  #define GPIO_SIST_SINT_CLEAR_ALL 0xff000000
808 
809  volatile uint8_t res4[0xC0];
810 
811  /*
812  * GPIO wakeup registers (MBAR + 0xC00)
813  */
814 
815  #define GPIO_W_PIN_GPIO_WKUP_7 BSP_BBIT32(0)
816  #define GPIO_W_PIN_GPIO_WKUP_6 BSP_BBIT32(1)
817  #define GPIO_W_PIN_PSC6_1 BSP_BBIT32(2)
818  #define GPIO_W_PIN_PSC6_0 BSP_BBIT32(3)
819  #define GPIO_W_PIN_ETH_17 BSP_BBIT32(4)
820  #define GPIO_W_PIN_PSC3_9 BSP_BBIT32(5)
821  #define GPIO_W_PIN_PSC2_4 BSP_BBIT32(6)
822  #define GPIO_W_PIN_PSC1_4 BSP_BBIT32(7)
823 
824  volatile uint32_t gpiowe; /* + 0x00 */
825  volatile uint32_t gpiowod; /* + 0x04 */
826  volatile uint32_t gpiowdd; /* + 0x08 */
827  volatile uint32_t gpiowdo; /* + 0x0C */
828  volatile uint32_t gpiowue; /* + 0x10 */
829  volatile uint32_t gpiowsie; /* + 0x14 */
830  volatile uint32_t gpiowt; /* + 0x18 */
831  volatile uint32_t gpiowme; /* + 0x1C */
832  volatile uint32_t gpiowi; /* + 0x20 */
833  volatile uint32_t gpiows; /* + 0x24 */
834  volatile uint8_t gpiow_res[0xD8];
835 
836  /*
837  * PPC PCI registers (MBAR + 0xD00)
838  */
839  volatile uint8_t ppci[0x100];
840 
841  /*
842  * consumer infrared registers (MBAR + 0xE00)
843  */
844  volatile uint8_t ir[0x100];
845 
846  /*
847  * serial peripheral interface registers (MBAR + 0xF00)
848  */
849  volatile uint8_t spi[0x100];
850 
851  /*
852  * universal serial bus registers (MBAR + 0x1000)
853  */
854  volatile uint8_t usb[0x200];
855 
856  /*
857  * SmartComm DMA registers (MBAR + 0x1200)
858  */
859  volatile mpc5200_sdma sdma;
860 
861  volatile uint32_t EU00; /* + 0x80 sdMac macer reg */
862  volatile uint32_t EU01; /* + 0x84 sdMac macemr reg */
863  volatile uint32_t EU02; /* + 0x88 unused */
864  volatile uint32_t EU03; /* + 0x8c unused */
865  volatile uint32_t EU04; /* + 0x90 unused */
866  volatile uint32_t EU05; /* + 0x94 unused */
867  volatile uint32_t EU06; /* + 0x98 unused */
868  volatile uint32_t EU07; /* + 0x9c unused */
869  volatile uint32_t EU10; /* + 0xa0 unused */
870  volatile uint32_t EU11; /* + 0xa4 unused */
871  volatile uint32_t EU12; /* + 0xa8 unused */
872  volatile uint32_t EU13; /* + 0xac unused */
873  volatile uint32_t EU14; /* + 0xb0 unused */
874  volatile uint32_t EU15; /* + 0xb4 unused */
875  volatile uint32_t EU16; /* + 0xb8 unused */
876  volatile uint32_t EU17; /* + 0xbc unused */
877  volatile uint32_t EU20; /* + 0xc0 unused */
878  volatile uint32_t EU21; /* + 0xc4 unused */
879  volatile uint32_t EU22; /* + 0xc8 unused */
880  volatile uint32_t EU23; /* + 0xcc unused */
881  volatile uint32_t EU24; /* + 0xd0 unused */
882  volatile uint32_t EU25; /* + 0xd4 unused */
883  volatile uint32_t EU26; /* + 0xd8 unused */
884  volatile uint32_t EU27; /* + 0xdc unused */
885  volatile uint32_t EU30; /* + 0xe0 unused */
886  volatile uint32_t EU31; /* + 0xe4 unused */
887  volatile uint32_t EU32; /* + 0xe8 unused */
888  volatile uint32_t EU33; /* + 0xec unused */
889  volatile uint32_t EU34; /* + 0xf0 unused */
890  volatile uint32_t EU35; /* + 0xf4 unused */
891  volatile uint32_t EU36; /* + 0xf8 unused */
892  volatile uint32_t EU37; /* + 0xfc unused */
893 #if 0
894  volatile uint32_t res8[0x340];
895 #else
896  volatile uint8_t res_1300[0xc00];
897 
898  volatile uint32_t reserved0; /* MBAR_XLB_ARB + 0x0000 reserved */
899  volatile uint32_t reserved1; /* MBAR_XLB_ARB + 0x0004 reserved */
900  volatile uint32_t reserved2; /* MBAR_XLB_ARB + 0x0008 reserved */
901  volatile uint32_t reserved3; /* MBAR_XLB_ARB + 0x000c reserved */
902  volatile uint32_t reserved4; /* MBAR_XLB_ARB + 0x0010 reserved */
903  volatile uint32_t reserved5; /* MBAR_XLB_ARB + 0x0014 reserved */
904  volatile uint32_t reserved6; /* MBAR_XLB_ARB + 0x0018 reserved */
905  volatile uint32_t reserved7; /* MBAR_XLB_ARB + 0x001c reserved */
906  volatile uint32_t reserved8; /* MBAR_XLB_ARB + 0x0020 reserved */
907  volatile uint32_t reserved9; /* MBAR_XLB_ARB + 0x0024 reserved */
908  volatile uint32_t reserved10; /* MBAR_XLB_ARB + 0x0028 reserved */
909  volatile uint32_t reserved11; /* MBAR_XLB_ARB + 0x002c reserved */
910  volatile uint32_t reserved12; /* MBAR_XLB_ARB + 0x0030 reserved */
911  volatile uint32_t reserved13; /* MBAR_XLB_ARB + 0x0034 reserved */
912  volatile uint32_t reserved14; /* MBAR_XLB_ARB + 0x0038 reserved */
913  volatile uint32_t reserved15; /* MBAR_XLB_ARB + 0x003c reserved */
914 
915 #define XLB_CFG_PLDIS BSP_BBIT32(0)
916 #define XLB_CFG_BSDIS BSP_BBIT32(15)
917 #define XLB_CFG_SE BSP_BBIT32(16)
918 #define XLB_CFG_USE_WWF BSP_BBIT32(17)
919 #define XLB_CFG_TBEN BSP_BBIT32(18)
920 #define XLB_CFG_WS BSP_BBIT32(20)
921 #define XLB_CFG_SP(val) BSP_BFLD32(val, 21, 23)
922 #define XLB_CFG_SET_SP(reg, val) BSP_BFLD32SET(reg, val, 21, 23)
923 #define XLB_CFG_PM(val) BSP_BFLD32(val, 25, 26)
924 #define XLB_CFG_SET_PM(reg, val) BSP_BFLD32SET(reg, val, 25, 26)
925 #define XLB_CFG_BA BSP_BBIT32(28)
926 #define XLB_CFG_DT BSP_BBIT32(29)
927 #define XLB_CFG_AT BSP_BBIT32(30)
928 
929  volatile uint32_t config; /* MBAR_XLB_ARB + 0x0040 */
930  volatile uint32_t version; /* MBAR_XLB_ARB + 0x0044 */
931 
932 #define XLB_ST_SEA BSP_BBIT32(23)
933 #define XLB_ST_MM BSP_BBIT32(24)
934 #define XLB_ST_TTA BSP_BBIT32(25)
935 #define XLB_ST_TTR BSP_BBIT32(26)
936 #define XLB_ST_ECW BSP_BBIT32(27)
937 #define XLB_ST_TTM BSP_BBIT32(28)
938 #define XLB_ST_BA BSP_BBIT32(29)
939 #define XLB_ST_DT BSP_BBIT32(30)
940 #define XLB_ST_AT BSP_BBIT32(31)
941  /* read only = 0x0001 */
942  volatile uint32_t xlb_status; /* MBAR_XLB_ARB + 0x0048 */
943  volatile uint32_t int_enable; /* MBAR_XLB_ARB + 0x004c */
944  volatile uint32_t add_capture; /* MBAR_XLB_ARB + 0x0050 read only */
945  volatile uint32_t bus_sig_capture; /* MBAR_XLB_ARB + 0x0054 read only */
946  volatile uint32_t add_time_out; /* MBAR_XLB_ARB + 0x0058 */
947  volatile uint32_t data_time_out; /* MBAR_XLB_ARB + 0x005c */
948  volatile uint32_t bus_time_out; /* MBAR_XLB_ARB + 0x0060 */
949  volatile uint32_t priority_enable; /* MBAR_XLB_ARB + 0x0064 */
950  volatile uint32_t priority; /* MBAR_XLB_ARB + 0x0068 */
951  volatile uint32_t arb_base_addr2; /* MBAR_XLB_ARB + 0x006c */
952  volatile uint32_t snoop_window; /* MBAR_XLB_ARB + 0x0070 */
953 
954  volatile uint32_t reserved16; /* MBAR_XLB_ARB + 0x0074 reserved */
955  volatile uint32_t reserved17; /* MBAR_XLB_ARB + 0x0078 reserved */
956  volatile uint32_t reserved18; /* MBAR_XLB_ARB + 0x007c reserved */
957 
958  volatile uint32_t control; /* MBAR_XLB_ARB + 0x0080 */
959  volatile uint32_t init_total_count; /* MBAR_XLB_ARB + 0x0084 */
960  volatile uint32_t int_total_count; /* MBAR_XLB_ARB + 0x0088 */
961 
962  volatile uint32_t reserved19; /* MBAR_XLB_ARB + 0x008c reserved */
963 
964  volatile uint32_t lower_address; /* MBAR_XLB_ARB + 0x0090 */
965  volatile uint32_t higher_address; /* MBAR_XLB_ARB + 0x0094 */
966  volatile uint32_t int_window_count; /* MBAR_XLB_ARB + 0x0098 */
967  volatile uint32_t window_ter_count; /* MBAR_XLB_ARB + 0x009c */
968  volatile uint8_t res_0x1fa0[0x60];
969 
970 
971 #endif
972  /*
973  * programmable serial controller 1 (MBAR + 0x2000)
974  */
975 
976  struct mpc5200_psc {
977  volatile uint8_t mr; /* + 0x00 */
978  volatile uint8_t res1[3];
979  volatile uint16_t sr_csr; /* + 0x04 */
980  volatile uint16_t res2[1];
981  volatile uint16_t cr; /* + 0x08 */
982  volatile uint16_t res3[1];
983  volatile uint32_t rb_tb; /* + 0x0c */
984  volatile uint16_t ipcr_acr; /* + 0x10 */
985  volatile uint16_t res4[1];
986  volatile uint16_t isr_imr; /* + 0x14 */
987 #define ISR_TX_RDY (1 << 8)
988 #define ISR_RX_RDY_FULL (1 << 9)
989 #define ISR_RB (1 << 15)
990 #define ISR_FE (1 << 14)
991 #define ISR_PE (1 << 13)
992 #define ISR_OE (1 << 12)
993 #define ISR_ERROR (ISR_FE | ISR_PE | ISR_OE)
994 
995 #define IMR_TX_RDY (1 << 8)
996 #define IMR_RX_RDY_FULL (1 << 9)
997  volatile uint16_t res5[1];
998  volatile uint8_t ctur; /* + 0x18 */
999  volatile uint8_t res6[3];
1000  volatile uint8_t ctlr; /* + 0x1C */
1001  volatile uint8_t res7[0x13];
1002  volatile uint8_t ivr; /* + 0x30 */
1003  volatile uint8_t res8[3];
1004  volatile uint8_t ip; /* + 0x34 */
1005  volatile uint8_t res9[3];
1006  volatile uint8_t op1; /* + 0x38 */
1007  volatile uint8_t res10[3];
1008  volatile uint8_t op0; /* + 0x3C */
1009  volatile uint8_t res11[3];
1010  volatile uint8_t sicr; /* + 0x40 */
1011  volatile uint8_t res12[0x17];
1012  volatile uint16_t rfnum; /* + 0x58 */
1013  volatile uint16_t res13[1];
1014  volatile uint16_t tfnum; /* + 0x5C */
1015  volatile uint16_t res14[1];
1016  volatile uint16_t rfdata; /* + 0x60 */
1017  volatile uint16_t res15[1];
1018  volatile uint16_t rfstat; /* + 0x64 */
1019  volatile uint16_t res16[1];
1020  volatile uint8_t rfcntl; /* + 0x68 */
1021  volatile uint8_t res17[5];
1022  volatile uint16_t rfalarm; /* + 0x6E */
1023  volatile uint8_t res18[2];
1024  volatile uint16_t rfrptr; /* + 0x72 */
1025  volatile uint16_t res19[1];
1026  volatile uint16_t rfwptr; /* + 0x76 */
1027  volatile uint16_t res20[1];
1028  volatile uint16_t rflrfptr; /* + 0x7A */
1029  volatile uint16_t rflwfptr; /* + 0x7C */
1030  volatile uint16_t res21[1];
1031  volatile uint16_t tfdata; /* + 0x80 */
1032  volatile uint16_t res22[1];
1033  volatile uint16_t tfstat; /* + 0x84 */
1034  volatile uint16_t res23[1];
1035  volatile uint8_t tfcntl; /* + 0x88 */
1036  volatile uint8_t res24[5];
1037  volatile uint16_t tfalarm; /* + 0x8E */
1038  volatile uint8_t res25[2];
1039  volatile uint16_t tfrptr; /* + 0x92 */
1040  volatile uint16_t res26[1];
1041  volatile uint16_t tfwptr; /* + 0x96 */
1042  volatile uint16_t res27[1];
1043  volatile uint16_t tflrfptr; /* + 0x96 */
1044  volatile uint16_t tflwfptr; /* + 0x9C */
1045  volatile uint16_t res28[1]; /* end at offset 0x9F */
1046  volatile uint8_t res29[0x160];
1047  } psc[MPC5200_PSC_REG_SETS];
1048  /* XXX: there are only 6 PSCs, but PSC6 has an extra register gap
1049  * from PSC5, therefore we instantiate seven(!) PSC register sets
1050  */
1051 
1052 #define TX_FIFO_SIZE 256
1053 #define RX_FIFO_SIZE 512
1054 
1055 
1056  volatile uint8_t irda[0x200];
1057 
1058  /*
1059  * ethernet registers (MBAR + 0x3000)
1060  */
1061 
1062  /* Control and status Registers (offset 000-1FF) */
1063 
1064  volatile uint32_t fec_id; /* + 0x000 */
1065  volatile uint32_t ievent; /* + 0x004 */
1066  volatile uint32_t imask; /* + 0x008 */
1067 
1068  volatile uint32_t res9[1]; /* + 0x00C */
1069  volatile uint32_t r_des_active; /* + 0x010 */
1070  volatile uint32_t x_des_active; /* + 0x014 */
1071  volatile uint32_t r_des_active_cl; /* + 0x018 */
1072  volatile uint32_t x_des_active_cl; /* + 0x01C */
1073  volatile uint32_t ivent_set; /* + 0x020 */
1074  volatile uint32_t ecntrl; /* + 0x024 */
1075 
1076  volatile uint32_t res10[6]; /* + 0x028-03C */
1077  volatile uint32_t mii_data; /* + 0x040 */
1078  volatile uint32_t mii_speed; /* + 0x044 */
1079  volatile uint32_t mii_status; /* + 0x048 */
1080 
1081  volatile uint32_t res11[5]; /* + 0x04C-05C */
1082  volatile uint32_t mib_data; /* + 0x060 */
1083  volatile uint32_t mib_control; /* + 0x064 */
1084 
1085  volatile uint32_t res12[6]; /* + 0x068-7C */
1086  volatile uint32_t r_activate; /* + 0x080 */
1087  volatile uint32_t r_cntrl; /* + 0x084 */
1088  volatile uint32_t r_hash; /* + 0x088 */
1089  volatile uint32_t r_data; /* + 0x08C */
1090  volatile uint32_t ar_done; /* + 0x090 */
1091  volatile uint32_t r_test; /* + 0x094 */
1092  volatile uint32_t r_mib; /* + 0x098 */
1093  volatile uint32_t r_da_low; /* + 0x09C */
1094  volatile uint32_t r_da_high; /* + 0x0A0 */
1095 
1096  volatile uint32_t res13[7]; /* + 0x0A4-0BC */
1097  volatile uint32_t x_activate; /* + 0x0C0 */
1098  volatile uint32_t x_cntrl; /* + 0x0C4 */
1099  volatile uint32_t backoff; /* + 0x0C8 */
1100  volatile uint32_t x_data; /* + 0x0CC */
1101  volatile uint32_t x_status; /* + 0x0D0 */
1102  volatile uint32_t x_mib; /* + 0x0D4 */
1103  volatile uint32_t x_test; /* + 0x0D8 */
1104  volatile uint32_t fdxfc_da1; /* + 0x0DC */
1105  volatile uint32_t fdxfc_da2; /* + 0x0E0 */
1106  volatile uint32_t paddr1; /* + 0x0E4 */
1107  volatile uint32_t paddr2; /* + 0x0E8 */
1108  volatile uint32_t op_pause; /* + 0x0EC */
1109 
1110  volatile uint32_t res14[4]; /* + 0x0F0-0FC */
1111  volatile uint32_t instr_reg; /* + 0x100 */
1112  volatile uint32_t context_reg; /* + 0x104 */
1113  volatile uint32_t test_cntrl; /* + 0x108 */
1114  volatile uint32_t acc_reg; /* + 0x10C */
1115  volatile uint32_t ones; /* + 0x110 */
1116  volatile uint32_t zeros; /* + 0x114 */
1117  volatile uint32_t iaddr1; /* + 0x118 */
1118  volatile uint32_t iaddr2; /* + 0x11C */
1119  volatile uint32_t gaddr1; /* + 0x120 */
1120  volatile uint32_t gaddr2; /* + 0x124 */
1121  volatile uint32_t random; /* + 0x128 */
1122  volatile uint32_t rand1; /* + 0x12C */
1123  volatile uint32_t tmp; /* + 0x130 */
1124 
1125  volatile uint32_t res15[3]; /* + 0x134-13C */
1126  volatile uint32_t fifo_id; /* + 0x140 */
1127  volatile uint32_t x_wmrk; /* + 0x144 */
1128  volatile uint32_t fcntrl; /* + 0x148 */
1129  volatile uint32_t r_bound; /* + 0x14C */
1130  volatile uint32_t r_fstart; /* + 0x150 */
1131  volatile uint32_t r_count; /* + 0x154 */
1132  volatile uint32_t r_lag; /* + 0x158 */
1133  volatile uint32_t r_read; /* + 0x15C */
1134  volatile uint32_t r_write; /* + 0x160 */
1135  volatile uint32_t x_count; /* + 0x164 */
1136  volatile uint32_t x_lag; /* + 0x168 */
1137  volatile uint32_t x_retry; /* + 0x16C */
1138  volatile uint32_t x_write; /* + 0x170 */
1139  volatile uint32_t x_read; /* + 0x174 */
1140 
1141  volatile uint32_t res16[2]; /* + 0x178-17C */
1142  volatile uint32_t fm_cntrl; /* + 0x180 */
1143  volatile uint32_t rfifo_data; /* + 0x184 */
1144  volatile uint32_t rfifo_status; /* + 0x188 */
1145  volatile uint32_t rfifo_cntrl; /* + 0x18C */
1146  volatile uint32_t rfifo_lrf_ptr; /* + 0x190 */
1147  volatile uint32_t rfifo_lwf_ptr; /* + 0x194 */
1148  volatile uint32_t rfifo_alarm; /* + 0x198 */
1149  volatile uint32_t rfifo_rdptr; /* + 0x19C */
1150  volatile uint32_t rfifo_wrptr; /* + 0x1A0 */
1151  volatile uint32_t tfifo_data; /* + 0x1A4 */
1152  volatile uint32_t tfifo_status; /* + 0x1A8 */
1153  volatile uint32_t tfifo_cntrl; /* + 0x1AC */
1154  volatile uint32_t tfifo_lrf_ptr; /* + 0x1B0 */
1155  volatile uint32_t tfifo_lwf_ptr; /* + 0x1B4 */
1156  volatile uint32_t tfifo_alarm; /* + 0x1B8 */
1157  volatile uint32_t tfifo_rdptr; /* + 0x1BC */
1158  volatile uint32_t tfifo_wrptr; /* + 0x1C0 */
1159 
1160  volatile uint32_t reset_cntrl; /* + 0x1C4 */
1161  volatile uint32_t xmit_fsm; /* + 0x1C8 */
1162 
1163  volatile uint32_t res17[3]; /* + 0x1CC-1D4 */
1164  volatile uint32_t rdes_data0; /* + 0x1D8 */
1165  volatile uint32_t rdes_data1; /* + 0x1DC */
1166  volatile uint32_t r_length; /* + 0x1E0 */
1167  volatile uint32_t x_length; /* + 0x1E4 */
1168  volatile uint32_t x_addr; /* + 0x1E8 */
1169  volatile uint32_t cdes_data; /* + 0x1EC */
1170  volatile uint32_t status; /* + 0x1F0 */
1171  volatile uint32_t dma_control; /* + 0x1F4 */
1172  volatile uint32_t des_cmnd; /* + 0x1F8 */
1173  volatile uint32_t data; /* + 0x1FC */
1174 
1175  volatile uint8_t RES[0x600];
1176 
1177 
1178 #if 0
1179  /* MIB COUNTERS (Offset 200-2FF) */
1180 
1181  volatile uint32_t rmon_t_drop; /* + 0x200 */
1182  volatile uint32_t rmon_t_packets; /* + 0x204 */
1183  volatile uint32_t rmon_t_bc_pkt; /* + 0x208 */
1184  volatile uint32_t rmon_t_mc_pkt; /* + 0x20C */
1185  volatile uint32_t rmon_t_crc_align; /* + 0x210 */
1186  volatile uint32_t rmon_t_undersize; /* + 0x214 */
1187  volatile uint32_t rmon_t_oversize; /* + 0x218 */
1188  volatile uint32_t rmon_t_frag; /* + 0x21C */
1189  volatile uint32_t rmon_t_jab; /* + 0x220 */
1190  volatile uint32_t rmon_t_col; /* + 0x224 */
1191  volatile uint32_t rmon_t_p64; /* + 0x228 */
1192  volatile uint32_t rmon_t_p65to127; /* + 0x22C */
1193  volatile uint32_t rmon_t_p128to255; /* + 0x230 */
1194  volatile uint32_t rmon_t_p256to511; /* + 0x234 */
1195  volatile uint32_t rmon_t_p512to1023; /* + 0x238 */
1196  volatile uint32_t rmon_t_p1024to2047; /* + 0x23C */
1197  volatile uint32_t rmon_t_p_gte2048; /* + 0x240 */
1198  volatile uint32_t rmon_t_octets; /* + 0x244 */
1199  volatile uint32_t ieee_t_drop; /* + 0x248 */
1200  volatile uint32_t ieee_t_frame_ok; /* + 0x24C */
1201  volatile uint32_t ieee_t_1col; /* + 0x250 */
1202  volatile uint32_t ieee_t_mcol; /* + 0x254 */
1203  volatile uint32_t ieee_t_def; /* + 0x258 */
1204  volatile uint32_t ieee_t_lcol; /* + 0x25C */
1205  volatile uint32_t ieee_t_excol; /* + 0x260 */
1206  volatile uint32_t ieee_t_macerr; /* + 0x264 */
1207  volatile uint32_t ieee_t_cserr; /* + 0x268 */
1208  volatile uint32_t ieee_t_sqe; /* + 0x26C */
1209  volatile uint32_t t_fdxfc; /* + 0x270 */
1210  volatile uint32_t ieee_t_octets_ok; /* + 0x274 */
1211 
1212  volatile uint32_t res18[2]; /* + 0x278-27C */
1213  volatile uint32_t rmon_r_drop; /* + 0x280 */
1214  volatile uint32_t rmon_r_packets; /* + 0x284 */
1215  volatile uint32_t rmon_r_bc_pkt; /* + 0x288 */
1216  volatile uint32_t rmon_r_mc_pkt; /* + 0x28C */
1217  volatile uint32_t rmon_r_crc_align; /* + 0x290 */
1218  volatile uint32_t rmon_r_undersize; /* + 0x294 */
1219  volatile uint32_t rmon_r_oversize; /* + 0x298 */
1220  volatile uint32_t rmon_r_frag; /* + 0x29C */
1221  volatile uint32_t rmon_r_jab; /* + 0x2A0 */
1222 
1223  volatile uint32_t rmon_r_resvd_0; /* + 0x2A4 */
1224 
1225  volatile uint32_t rmon_r_p64; /* + 0x2A8 */
1226  volatile uint32_t rmon_r_p65to127; /* + 0x2AC */
1227  volatile uint32_t rmon_r_p128to255; /* + 0x2B0 */
1228  volatile uint32_t rmon_r_p256to511; /* + 0x2B4 */
1229  volatile uint32_t rmon_r_p512to1023; /* + 0x2B8 */
1230  volatile uint32_t rmon_r_p1024to2047; /* + 0x2BC */
1231  volatile uint32_t rmon_r_p_gte2048; /* + 0x2C0 */
1232  volatile uint32_t rmon_r_octets; /* + 0x2C4 */
1233  volatile uint32_t ieee_r_drop; /* + 0x2C8 */
1234  volatile uint32_t ieee_r_frame_ok; /* + 0x2CC */
1235  volatile uint32_t ieee_r_crc; /* + 0x2D0 */
1236  volatile uint32_t ieee_r_align; /* + 0x2D4 */
1237  volatile uint32_t r_macerr; /* + 0x2D8 */
1238  volatile uint32_t r_fdxfc; /* + 0x2DC */
1239  volatile uint32_t ieee_r_octets_ok; /* + 0x2E0 */
1240 
1241  volatile uint32_t res19[6]; /* + 0x2E4-2FC */
1242 
1243  volatile uint32_t res20[64]; /* + 0x300-3FF */
1244 
1245  volatile uint32_t res21[256]; /* + 0x400-800 */
1246 #endif
1247 
1248  /*
1249  * SmartComm DMA PCI registers (MBAR + 0x3800)
1250  */
1251  volatile uint8_t pci[0x200];
1252 
1253  /*
1254  * advanced technology attachment registers (MBAR + 0x3A00)
1255  */
1256 
1257  /* ATA host registers (offset 0x00-0x28) */
1258  volatile uint32_t ata_hcfg; /* + 0x00 */
1259  volatile uint32_t ata_hsr; /* + 0x04 */
1260  volatile uint32_t ata_pio1; /* + 0x08 */
1261  volatile uint32_t ata_pio2; /* + 0x0C */
1262  volatile uint32_t ata_dma1; /* + 0x10 */
1263  volatile uint32_t ata_dma2; /* + 0x14 */
1264  volatile uint32_t ata_udma1; /* + 0x18 */
1265  volatile uint32_t ata_udma2; /* + 0x1C */
1266  volatile uint32_t ata_udma3; /* + 0x20 */
1267  volatile uint32_t ata_udma4; /* + 0x24 */
1268  volatile uint32_t ata_udma5; /* + 0x28 */
1269  volatile uint32_t ata_res1[4]; /* + 0x2C-0x3C */
1270 
1271  /* ATA FIFO registers (offset 0x3C-0x50) */
1272  volatile uint32_t ata_rtfdwr; /* + 0x3C */
1273 
1274 #define ATA_RTFSR_ERR BSP_BBIT32(9)
1275 #define ATA_RTFSR_UF BSP_BBIT32(10)
1276 #define ATA_RTFSR_OF BSP_BBIT32(11)
1277 #define ATA_RTFSR_FULL BSP_BBIT32(12)
1278 #define ATA_RTFSR_HI BSP_BBIT32(13)
1279 #define ATA_RTFSR_LO BSP_BBIT32(14)
1280 #define ATA_RTFSR_EMPTY BSP_BBIT32(15)
1281 
1282  volatile uint32_t ata_rtfsr; /* + 0x40 */
1283 
1284 #define ATA_RTFCR_WFR BSP_BBIT32(2)
1285 #define ATA_RTFCR_GR(val) BSP_BFLD32(val, 5, 7)
1286 
1287  volatile uint32_t ata_rtfcr; /* + 0x44 */
1288  volatile uint32_t ata_rtfar; /* + 0x48 */
1289  volatile uint32_t ata_rtfrpr; /* + 0x4C */
1290  volatile uint32_t ata_rtfwpr; /* + 0x50 */
1291  volatile uint32_t ata_res2[2]; /* + 0x54-0x5C */
1292 
1293  /* ATA drive registers (offset 0x5C-0x80) */
1294  volatile uint32_t ata_dctr_dasr; /* + 0x5C */
1295  volatile uint32_t ata_ddr; /* + 0x60 */
1296  volatile uint32_t ata_dfr_der; /* + 0x64 */
1297  volatile uint32_t ata_dscr; /* + 0x68 */
1298  volatile uint32_t ata_dsnr; /* + 0x6C */
1299  volatile uint32_t ata_dclr; /* + 0x70 */
1300  volatile uint32_t ata_dchr; /* + 0x74 */
1301  volatile uint32_t ata_ddhr; /* + 0x78 */
1302  volatile uint32_t ata_dcr_dsr; /* + 0x7C */
1303  volatile uint32_t ata_res3[0xA0]; /* + 0x80-0x200 */
1304 
1305  /*
1306  * inter-integrated circuit registers (MBAR + 0x3D00)
1307  */
1308  struct mpc5200_i2c_regs_s {
1309  volatile uint8_t madr; /* i2c address reg. + 0x00 */
1310  volatile uint8_t res_1[3];
1311  volatile uint8_t mfdr; /* i2c freq. divider reg. + 0x04 */
1312  volatile uint8_t res_5[3];
1313  volatile uint8_t mcr; /* i2c control reg. + 0x08 */
1314  volatile uint8_t res_9[3];
1315 
1316 #define MPC5200_I2C_MCR_MEN (1 << (7-0))
1317 #define MPC5200_I2C_MCR_MIEN (1 << (7-1))
1318 #define MPC5200_I2C_MCR_MSTA (1 << (7-2))
1319 #define MPC5200_I2C_MCR_MTX (1 << (7-3))
1320 #define MPC5200_I2C_MCR_TXAK (1 << (7-4))
1321 #define MPC5200_I2C_MCR_RSTA (1 << (7-5))
1322 
1323  volatile uint8_t msr; /* i2c status reg. + 0x0C */
1324  volatile uint8_t res_d[3];
1325 #define MPC5200_I2C_MSR_CF (1 << (7-0))
1326 #define MPC5200_I2C_MSR_MAAS (1 << (7-1))
1327 #define MPC5200_I2C_MSR_BB (1 << (7-2))
1328 #define MPC5200_I2C_MSR_MAL (1 << (7-3))
1329 #define MPC5200_I2C_MSR_SRW (1 << (7-5))
1330 #define MPC5200_I2C_MSR_MIF (1 << (7-6))
1331 #define MPC5200_I2C_MSR_RXAK (1 << (7-7))
1332  volatile uint8_t mdr; /* i2c data I/O reg. + 0x10 */
1333  volatile uint8_t res_11[3];
1334  volatile uint8_t res_14[12]; /* reserved + 0x14 */
1335  volatile uint8_t icr; /* i2c irq ctrl reg. + 0x20 */
1336 #define MPC5200_I2C_ICR_BNBE2 (1 << (7-0))
1337 #define MPC5200_I2C_ICR_TE2 (1 << (7-1))
1338 #define MPC5200_I2C_ICR_RE2 (1 << (7-2))
1339 #define MPC5200_I2C_ICR_IE2 (1 << (7-3))
1340 #define MPC5200_I2C_ICR_MASK2 (MPC5200_I2C_ICR_BNBE2|MPC5200_I2C_ICR_TE2\
1341  |MPC5200_I2C_ICR_RE2|MPC5200_I2C_ICR_IE2)
1342 #define MPC5200_I2C_ICR_BNBE1 (1 << (7-4))
1343 #define MPC5200_I2C_ICR_TE1 (1 << (7-5))
1344 #define MPC5200_I2C_ICR_RE1 (1 << (7-6))
1345 #define MPC5200_I2C_ICR_IE1 (1 << (7-7))
1346 #define MPC5200_I2C_ICR_MASK1 (MPC5200_I2C_ICR_BNBE1|MPC5200_I2C_ICR_TE1\
1347  |MPC5200_I2C_ICR_RE1|MPC5200_I2C_ICR_IE1)
1348  volatile uint8_t res_21[3];
1349  volatile uint32_t res_24[7]; /* reserved + 0x24 */
1350  } i2c_regs[2];
1351  volatile uint8_t res_3d80[0x280];
1352 
1353  /*
1354  * on-chip static RAM memory locations (MBAR + 0x4000)
1355  */
1356  volatile uint8_t sram_res0x4000[0x4000];
1357  volatile uint8_t sram[0x4000];
1358 
1359 } mpc5200_t;
1360 
1361 extern volatile mpc5200_t mpc5200;
1362 
1363 #ifdef __cplusplus
1364 }
1365 #endif
1366 
1367 #endif /*ASM*/
1368 
1369 #endif /* __MPC5200_h__ */
mpc5200_::mpc5200_mscan
Definition: mpc5200.h:508
mpc5200_csc
Definition: mpc5200.h:264
mpc5200_sdma
Definition: mpc5200.h:241
config_s
Definition: deflate.c:115
mpc5200_::mpc5200_i2c_regs_s
Definition: mpc5200.h:1308
mpc5200_::mpc5200_psc
Definition: mpc5200.h:976
mpc5200_mm
Definition: mpc5200.h:343
mpc5200_
Definition: mpc5200.h:387
utility.h
Utility macros.
control
Definition: intercom.c:74
mpc5200_::mpc5200_slt
Definition: mpc5200.h:490
mpc5200_::mpc5200_gpt
Definition: mpc5200.h:456
mscan
struct mpc5200_mscan mscan
MSCAN registers.
Definition: mscan-base.h:242
i2c_regs
Definition: i2c.h:52
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