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#define | MAILBOX_ADDRESS(address) (0xFFFC & (address)) |
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#define | CAN_CLK_FREQ_HZ MCAN_PROG_CLK_FREQ_HZ |
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#define | MCAN0_TSEG1 (MCAN0_PROP_SEG + MCAN0_PHASE_SEG1) |
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#define | MCAN0_TSEG2 (MCAN0_PHASE_SEG2) |
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#define | MCAN0_BRP |
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#define | MCAN0_SJW (MCAN0_SYNC_JUMP - 1) |
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#define | MCAN0_FTSEG1 (MCAN0_FAST_PROP_SEG + MCAN0_FAST_PHASE_SEG1) |
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#define | MCAN0_FTSEG2 (MCAN0_FAST_PHASE_SEG2) |
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#define | MCAN0_FBRP |
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#define | MCAN0_FSJW (MCAN0_FAST_SYNC_JUMP - 1) |
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#define | MCAN0_STD_FLTS_WRDS (MCAN0_NMBR_STD_FLTS) |
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#define | MCAN0_EXT_FLTS_WRDS (MCAN0_NMBR_EXT_FLTS * 2) |
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#define | MCAN0_RX_FIFO0_WRDS |
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#define | MCAN0_RX_FIFO1_WRDS |
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#define | MCAN0_RX_DED_BUFS_WRDS |
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#define | MCAN0_TX_EVT_FIFO_WRDS (MCAN0_NMBR_TX_EVT_FIFO_ELMTS * 2) |
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#define | MCAN0_TX_DED_BUF_WRDS |
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#define | MCAN0_TX_FIFO_Q_WRDS |
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#define | MCAN1_TSEG1 (MCAN1_PROP_SEG + MCAN1_PHASE_SEG1) |
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#define | MCAN1_TSEG2 (MCAN1_PHASE_SEG2) |
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#define | MCAN1_BRP |
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#define | MCAN1_SJW (MCAN1_SYNC_JUMP - 1) |
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#define | MCAN1_FTSEG1 (MCAN1_FAST_PROP_SEG + MCAN1_FAST_PHASE_SEG1) |
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#define | MCAN1_FTSEG2 (MCAN1_FAST_PHASE_SEG2) |
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#define | MCAN1_FBRP |
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#define | MCAN1_FSJW (MCAN1_FAST_SYNC_JUMP - 1) |
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#define | MCAN1_STD_FLTS_WRDS (MCAN1_NMBR_STD_FLTS) |
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#define | MCAN1_EXT_FLTS_WRDS (MCAN1_NMBR_EXT_FLTS * 2) |
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#define | MCAN1_RX_FIFO0_WRDS |
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#define | MCAN1_RX_FIFO1_WRDS |
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#define | MCAN1_RX_DED_BUFS_WRDS |
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#define | MCAN1_TX_EVT_FIFO_WRDS (MCAN1_NMBR_TX_EVT_FIFO_ELMTS * 2) |
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#define | MCAN1_TX_DED_BUF_WRDS |
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#define | MCAN1_TX_FIFO_Q_WRDS |
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#define | CAN_11_BIT_ID_MASK (0x7FF) |
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#define | CAN_29_BIT_ID_MASK (0x1FFFFFFF) |
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#define | ELMT_SIZE_MASK (0x1F) |
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#define | BUFFER_XTD_MASK (0x40000000) |
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#define | BUFFER_EXT_ID_MASK (0x1FFFFFFF) |
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#define | BUFFER_STD_ID_MASK (0x1FFC0000) |
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#define | BUFFER_DLC_MASK (0x000F0000) |
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#define | BUFFER_RXTS_MASK (0x0000FFFF) |
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#define | STD_FILT_SFT_MASK (3U << 30) |
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#define | STD_FILT_SFT_RANGE (0U << 30) |
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#define | STD_FILT_SFT_DUAL (1U << 30) |
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#define | STD_FILT_SFT_CLASSIC (2U << 30) |
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#define | STD_FILT_SFEC_MASK (7U << 27) |
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#define | STD_FILT_SFEC_DISABLE (0U << 27) |
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#define | STD_FILT_SFEC_FIFO0 (1U << 27) |
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#define | STD_FILT_SFEC_FIFO1 (2U << 27) |
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#define | STD_FILT_SFEC_REJECT (3U << 27) |
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#define | STD_FILT_SFEC_PRIORITY (4U << 27) |
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#define | STD_FILT_SFEC_PRIORITY_FIFO0 (5U << 27) |
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#define | STD_FILT_SFEC_PRIORITY_FIFO1 (6U << 27) |
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#define | STD_FILT_SFEC_BUFFER (7U << 27) |
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#define | STD_FILT_SFID1_MASK (0x03FFU << 16) |
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#define | STD_FILT_SFID2_MASK (0x3FFU << 0) |
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#define | STD_FILT_SFID2_RX_BUFFER (0U << 9) |
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#define | STD_FILT_SFID2_DEBUG_A (1U << 9) |
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#define | STD_FILT_SFID2_DEBUG_B (2U << 9) |
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#define | STD_FILT_SFID2_DEBUG_C (3U << 9) |
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#define | STD_FILT_SFID2_BUFFER(nmbr) (nmbr & 0x3F) |
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#define | EXT_FILT_EFEC_MASK (7U << 29) |
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#define | EXT_FILT_EFEC_DISABLE (0U << 29) |
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#define | EXT_FILT_EFEC_FIFO0 (1U << 29) |
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#define | EXT_FILT_EFEC_FIFO1 (2U << 29) |
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#define | EXT_FILT_EFEC_REJECT (3U << 29) |
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#define | EXT_FILT_EFEC_PRIORITY (4U << 29) |
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#define | EXT_FILT_EFEC_PRIORITY_FIFO0 (5U << 29) |
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#define | EXT_FILT_EFEC_PRIORITY_FIFO1 (6U << 29) |
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#define | EXT_FILT_EFEC_BUFFER (7U << 29) |
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#define | EXT_FILT_EFID1_MASK (0x1FFFFFFF) |
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#define | EXT_FILT_EFT_MASK (3U << 30) |
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#define | EXT_FILT_EFT_RANGE (0U << 30) |
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#define | EXT_FILT_EFT_DUAL (1U << 30) |
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#define | EXT_FILT_EFT_CLASSIC (2U << 30) |
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#define | EXT_FILT_EFT_RANGE_NO_XIDAM (3U << 30) |
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#define | EXT_FILT_EFID2_MASK (0x1FFFFFFF) |
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#define | EXT_FILT_EFID2_RX_BUFFER (0U << 9) |
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#define | EXT_FILT_EFID2_DEBUG_A (1U << 9) |
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#define | EXT_FILT_EFID2_DEBUG_B (2U << 9) |
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#define | EXT_FILT_EFID2_DEBUG_C (3U << 9) |
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#define | EXT_FILT_EFID2_BUFFER(nmbr) (nmbr & 0x3F) |
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