RTEMS
5.1
bsps
powerpc
gen5200
nvram
m93cxx.h
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/*===============================================================*\
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| Project: RTEMS generic MPC5200 BSP |
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+-----------------------------------------------------------------+
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| Partially based on the code references which are named below. |
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| Adaptions, modifications, enhancements and any recent parts of |
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| the code are: |
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| Copyright (c) 2005 |
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| Embedded Brains GmbH |
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| Obere Lagerstr. 30 |
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| D-82178 Puchheim |
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| Germany |
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| rtems@embedded-brains.de |
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+-----------------------------------------------------------------+
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| The license and distribution terms for this file may be |
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| found in the file LICENSE in this distribution or at |
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| |
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| http://www.rtems.org/license/LICENSE. |
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| |
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+-----------------------------------------------------------------+
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| this file contains definitions for the M93Cxx EEPROM devices |
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\*===============================================================*/
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/***********************************************************************/
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/* */
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/* Module: m93cxx.h */
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/* Date: 07/17/2003 */
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/* Purpose: RTEMS M93C64-based header file */
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/* */
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/*---------------------------------------------------------------------*/
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/* */
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/* Description: M93C46 is a serial microwire EEPROM which contains */
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/* 1Kbit (128 bytes/64 words) of non-volatile memory. */
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/* The device can be configured for byte- or word- */
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/* access. The driver provides a file-like interface */
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/* to this memory. */
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/* */
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/* MPC5x00 PIN settings: */
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/* */
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/* PSC3_6 (output) -> MC93C46 serial data in (D) */
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/* PSC3_7 (input) -> MC93C46 serial data out (Q) */
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/* PSC3_8 (output) -> MC93C46 chip select input (S) */
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/* PSC3_9 (output) -> MC93C46 serial clock (C) */
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/* */
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/*---------------------------------------------------------------------*/
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/* */
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/* Code */
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/* References: none */
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/* Module: */
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/* Project: */
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/* Version */
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/* Date: */
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/* Author: */
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/* Copyright: */
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/* */
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/*---------------------------------------------------------------------*/
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/* */
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/* Partially based on the code references which are named above. */
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/* Adaptions, modifications, enhancements and any recent parts of */
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/* the code are under the right of */
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/* */
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/* IPR Engineering, Dachauer Straße 38, D-80335 München */
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/* Copyright(C) 2003 */
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/* */
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/*---------------------------------------------------------------------*/
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/* */
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/* IPR Engineering makes no representation or warranties with */
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/* respect to the performance of this computer program, and */
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/* specifically disclaims any responsibility for any damages, */
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/* special or consequential, connected with the use of this program. */
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/* */
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/*---------------------------------------------------------------------*/
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/* */
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/* Version history: 1.0 */
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/* */
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/***********************************************************************/
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#ifndef __M93CXX_H__
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#define __M93CXX_H__
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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static
void
m93cxx_enable_write(
void
);
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static
void
m93cxx_disable_write(
void
);
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static
void
m93cxx_write_byte(uint32_t, uint8_t);
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static
uint8_t m93cxx_read_byte(uint32_t);
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void
wait_usec(
unsigned
long
);
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#define M93CXX_MODE_WORD
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/*#define M93C46_MODE_BYTE*/
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#define M93C46
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#define M93C46_NVRAM_SIZE 128
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#define GPIO_PSC3_6 (1 << 12)
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#define GPIO_PSC3_7 (1 << 13)
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#define GPIO_PSC3_8 (1 << 26)
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#define GPIO_PSC3_9 (1 << 26)
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#define START_BIT 0x1
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#define EWDS_OPCODE 0x0
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#define WRAL_OPCODE 0x1
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#define ERAL_OPCODE 0x2
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#define EWEN_OPCODE 0x3
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#define WRITE_OPCODE 0x4
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#define READ_OPCODE 0x8
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#define ERASE_OPCODE 0xC
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#define WAIT(i) wait_usec(i)
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#define ENABLE_CHIP_SELECT mpc5200.gpiosido |= GPIO_PSC3_8
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#define DISABLE_CHIP_SELECT mpc5200.gpiosido &= ~GPIO_PSC3_8
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#define SET_DATA_BIT_HIGH mpc5200.gpiosdo |= GPIO_PSC3_6
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#define SET_DATA_BIT_LOW mpc5200.gpiosdo &= ~GPIO_PSC3_6
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#ifdef M93CXX_MODE_BYTE
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#define GET_DATA_BYTE_SHIFT(val) ((val) |= ((mpc5200.gpiosdi & GPIO_PSC3_7) >> 13)); \
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((val) <<= 1)
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#define SET_DATA_BYTE_SHIFT(val) (((val) & 0x80) ? (mpc5200.gpiosdo |= GPIO_PSC3_6) : (mpc5200.gpiosdo &= ~GPIO_PSC3_6)); \
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((val) <<= 1)
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#else
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#define GET_DATA_WORD_SHIFT(val) ((val) |= ((mpc5200.gpiosdi & GPIO_PSC3_7) >> 13)); \
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((val) <<= 1)
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#define SET_DATA_WORD_SHIFT(val) (((val) & 0x8000) ? (mpc5200.gpiosdo |= GPIO_PSC3_6) : (mpc5200.gpiosdo &= ~GPIO_PSC3_6)); \
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((val) <<= 1)
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#endif
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#define MASK_HEAD_SHIFT(head) ((((head) & 0x80000000) >> 31) ? (mpc5200.gpiosdo |= GPIO_PSC3_6) : (mpc5200.gpiosdo &= ~GPIO_PSC3_6)); \
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((head) <<= 1)
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#define DO_CLOCK_CYCLE mpc5200.gpiowdo |= GPIO_PSC3_9; \
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WAIT(1000); \
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mpc5200.gpiowdo &= ~GPIO_PSC3_9
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#define CHECK_WRITE_BUSY while(!(mpc5200.gpiosdi & GPIO_PSC3_7))
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#ifdef M93CXX_MODE_BYTE
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#ifdef M93C46
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#define M93C46_EWDS ((START_BIT << 31) | (EWDS_OPCODE << 27))
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#define M93C46_WRAL ((START_BIT << 31) | (WRAL_OPCODE << 27))
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#define M93C46_ERAL ((START_BIT << 31) | (ERAL_OPCODE << 27))
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#define M93C46_EWEN ((START_BIT << 31) | (EWEN_OPCODE << 27))
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#define M93C46_READ(addr) ((START_BIT << 31) | (READ_OPCODE << 27) | ((addr) << 22))
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#define M93C46_WRITE(addr) ((START_BIT << 31) | (WRITE_OPCODE << 27) | ((addr) << 22))
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#define M93C46_ERASE(addr) ((START_BIT << 31) | (ERASE_OPCODE << 27) | ((addr) << 22))
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#define M93C46_CLOCK_CYCLES 10
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#endif
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#else
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#ifdef M93C46
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#define M93C46_EWDS ((START_BIT << 31) | (EWDS_OPCODE << 27))
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#define M93C46_WRAL ((START_BIT << 31) | (WRAL_OPCODE << 27))
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#define M93C46_ERAL ((START_BIT << 31) | (ERAL_OPCODE << 27))
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#define M93C46_EWEN ((START_BIT << 31) | (EWEN_OPCODE << 27))
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#define M93C46_READ(addr) ((START_BIT << 31) | (READ_OPCODE << 27) | ((addr) << 23))
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#define M93C46_WRITE(addr) ((START_BIT << 31) | (WRITE_OPCODE << 27) | ((addr) << 23))
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#define M93C46_ERASE(addr) ((START_BIT << 31) | (ERASE_OPCODE << 27) | ((addr) << 23))
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#define M93C46_CLOCK_CYCLES 9
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#endif
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
/* __M93CXX_H__ */
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