RTEMS  5.1
iosh7045.h
1 /*
2  * This include file contains information pertaining to the Hitachi SH
3  * processor.
4  *
5  * NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
6  *
7  * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
8  * Bernd Becker (becker@faw.uni-ulm.de)
9  *
10  * Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
11  * contained no copyright notice.
12  *
13  * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
18  *
19  *
20  * COPYRIGHT (c) 1998.
21  * On-Line Applications Research Corporation (OAR).
22  *
23  * The license and distribution terms for this file may be
24  * found in the file LICENSE in this distribution or at
25  * http://www.rtems.org/license/LICENSE.
26  *
27  * Modified to reflect on-chip registers for sh7045 processor, based on
28  * "Register.h" distributed with Hitachi's EVB7045F tutorials, and which
29  * contained no copyright notice:
30  * John M. Mills (jmills@tga.com)
31  * TGA Technologies, Inc.
32  * 100 Pinnacle Way, Suite 140
33  * Norcross, GA 30071 U.S.A.
34  * August, 1999
35  *
36  * This modified file may be copied and distributed in accordance
37  * the above-referenced license. It is provided for critique and
38  * developmental purposes without any warranty nor representation
39  * by the authors or by TGA Technologies.
40  */
41 
42 #ifndef __IOSH7045_H
43 #define __IOSH7045_H
44 
45 /*
46  * After each line is explained whether the access is char short or long.
47  * The functions read/writeb, w, l, 8, 16, 32 can be found
48  * in exec/score/cpu/sh/sh_io.h
49  *
50  * 8 bit == char ( readb, writeb, read8, write8)
51  * 16 bit == short ( readw, writew, read16, write16 )
52  * 32 bit == long ( readl, writel, read32, write32 )
53  * JMM: Addresses noted "[char, ]short,word" are per Hitachi _SuperH_RISC_
54  * ENGINE_..Hardware_Manual; alignment access-restrictions may apply
55  */
56 
57 #define REG_BASE 0xFFFF8000
58 
59 /* SCI0 Registers */
60 #define SCI_SMR0 (REG_BASE + 0x01a0) /*char: Serial mode ch 0 */
61 #define SCI_BRR0 (REG_BASE + 0x01a1) /*char: Bit rate ch 0 */
62 #define SCI_SCR0 (REG_BASE + 0x01a2) /*char: Serial control ch 0 */
63 #define SCI_TDR0 (REG_BASE + 0x01a3) /*char: Transmit data ch 0 */
64 #define SCI_SSR0 (REG_BASE + 0x01a4) /*char: Serial status ch 0 */
65 #define SCI_RDR0 (REG_BASE + 0x01a5) /*char: Receive data ch 0 */
66 
67 #define SCI0_SMR SCI_SMR0
68 
69 /* SCI1 Registers */
70 #define SCI_SMR1 (REG_BASE + 0x01b0) /* char: Serial mode ch 1 */
71 #define SCI_BRR1 (REG_BASE + 0x01b1) /* char: Bit rate ch 1 */
72 #define SCI_SCR1 (REG_BASE + 0x01b2) /* char: Serial control ch 1 */
73 #define SCI_TDR1 (REG_BASE + 0x01b3) /* char: Transmit data ch 1 */
74 #define SCI_SSR1 (REG_BASE + 0x01b4) /* char: Serial status ch 1 */
75 #define SCI_RDR1 (REG_BASE + 0x01b5) /* char: Receive data ch 1 */
76 
77 #define SCI1_SMR SCI_SMR1
78 
79 /* ADI */
80 /* High Speed A/D (Excluding A-Mask Part)*/
81 #define ADDRA (REG_BASE + 0x03F0) /* short */
82 #define ADDRB (REG_BASE + 0x03F2) /* short */
83 #define ADDRC (REG_BASE + 0x03F4) /* short */
84 #define ADDRD (REG_BASE + 0x03F6) /* short */
85 #define ADDRE (REG_BASE + 0x03F8) /* short */
86 #define ADDRF (REG_BASE + 0x03FA) /* short */
87 #define ADDRG (REG_BASE + 0x03FC) /* short */
88 #define ADDRH (REG_BASE + 0x03FE) /* short */
89 #define ADCSR (REG_BASE + 0x03E0) /* char */
90 #define ADCR (REG_BASE + 0x03E1) /* char */
91 
92 /* Mid-Speed A/D (A-Mask part)*/
93 #define ADDRA0 (REG_BASE + 0x0400) /* char, short */
94 #define ADDRA0H (REG_BASE + 0x0400) /* char, short */
95 #define ADDRA0L (REG_BASE + 0x0401) /* char */
96 #define ADDRB0 (REG_BASE + 0x0402) /* char, short */
97 #define ADDRB0H (REG_BASE + 0x0402) /* char, short */
98 #define ADDRB0L (REG_BASE + 0x0403) /* char */
99 #define ADDRC0 (REG_BASE + 0x0404) /* char, short */
100 #define ADDRC0H (REG_BASE + 0x0404) /* char, short */
101 #define ADDRC0L (REG_BASE + 0x0405) /* char */
102 #define ADDRD0 (REG_BASE + 0x0406) /* char, short */
103 #define ADDRD0H (REG_BASE + 0x0406) /* char, short */
104 #define ADDRD0L (REG_BASE + 0x0407) /* char */
105 #define ADCSR0 (REG_BASE + 0x0410) /* char */
106 #define ADCR0 (REG_BASE + 0x0412) /* char */
107 #define ADDRA1 (REG_BASE + 0x0408) /* char, short */
108 #define ADDRA1H (REG_BASE + 0x0408) /* char, short */
109 #define ADDRA1L (REG_BASE + 0x0409) /* char */
110 #define ADDRB1 (REG_BASE + 0x040A) /* char, short */
111 #define ADDRB1H (REG_BASE + 0x040A) /* char, short */
112 #define ADDRB1L (REG_BASE + 0x040B) /* char */
113 #define ADDRC1 (REG_BASE + 0x040C) /* char, short */
114 #define ADDRC1H (REG_BASE + 0x040C) /* char, short */
115 #define ADDRC1L (REG_BASE + 0x040D) /* char */
116 #define ADDRD1 (REG_BASE + 0x040E) /* char, short */
117 #define ADDRD1H (REG_BASE + 0x040E) /* char, short */
118 #define ADDRD1L (REG_BASE + 0x040F) /* char */
119 #define ADCSR1 (REG_BASE + 0x0411) /* char */
120 #define ADCR1 (REG_BASE + 0x0413) /* char */
121 
122 /*MTU SHARED*/
123 #define MTU_TSTR (REG_BASE + 0x0240) /* char, short, word */
124 #define MTU_TSYR (REG_BASE + 0x0241) /* char, short, word */
125 #define MTU_ICSR (REG_BASE + 0x03C0) /* input lev. CSR */
126 #define MTU_OCSR (REG_BASE + 0x03C0) /* output lev. CSR */
127 
128 /*MTU CHANNEL 0*/
129 #define MTU_TCR0 (REG_BASE + 0x0260) /* char, short, word */
130 #define MTU_TMDR0 (REG_BASE + 0x0261) /* char, short, word */
131 #define MTU_TIORH0 (REG_BASE + 0x0262) /* char, short, word */
132 #define MTU_TIORL0 (REG_BASE + 0x0263) /* char, short, word */
133 #define MTU_TIER0 (REG_BASE + 0x0264) /* char, short, word */
134 #define MTU_TSR0 (REG_BASE + 0x0265) /* char, short, word */
135 #define MTU_TCNT0 (REG_BASE + 0x0266) /* short, word */
136 #define MTU_GR0A (REG_BASE + 0x0268) /* short, word */
137 #define MTU_GR0B (REG_BASE + 0x026A) /* short, word */
138 #define MTU_GR0C (REG_BASE + 0x026C) /* short, word */
139 #define MTU_GR0D (REG_BASE + 0x026E) /* short, word */
140 
141 /*MTU CHANNEL 1*/
142 #define MTU_TCR1 (REG_BASE + 0x0280) /* char, short, word */
143 #define MTU_TMDR1 (REG_BASE + 0x0281) /* char, short, word */
144 #define MTU_TIOR1 (REG_BASE + 0x0282) /* char, short, word */
145 #define MTU_TIER1 (REG_BASE + 0x0284) /* char, short, word */
146 #define MTU_TSR1 (REG_BASE + 0x0285) /* char, short, word */
147 #define MTU_TCNT1 (REG_BASE + 0x0286) /* short, word */
148 #define MTU_GR1A (REG_BASE + 0x0288) /* short, word */
149 #define MTU_GR1B (REG_BASE + 0x028A) /* short, word */
150 
151 /*MTU CHANNEL 2*/
152 #define MTU_TCR2 (REG_BASE + 0x02A0) /* char, short, word */
153 #define MTU_TMDR2 (REG_BASE + 0x02A1) /* char, short, word */
154 #define MTU_TIOR2 (REG_BASE + 0x02A2) /* char, short, word */
155 #define MTU_TIER2 (REG_BASE + 0x02A4) /* char, short, word */
156 #define MTU_TSR2 (REG_BASE + 0x02A5) /* char, short, word */
157 #define MTU_TCNT2 (REG_BASE + 0x02A6) /* short, word */
158 #define MTU_GR2A (REG_BASE + 0x02A8) /* short, word */
159 #define MTU_GR2B (REG_BASE + 0x02AA) /* short, word */
160 
161 /*MTU CHANNELS 3-4 SHARED*/
162 #define MTU_TOER (REG_BASE + 0x020A) /* char, short, word */
163 #define MTU_TOCR (REG_BASE + 0x020B) /* char, short, word */
164 #define MTU_TGCR (REG_BASE + 0x020D) /* char, short, word */
165 #define MTU_TCDR (REG_BASE + 0x0214) /* short, word */
166 #define MTU_TDDR (REG_BASE + 0x0216) /* short, word */
167 #define MTU_TCNTS (REG_BASE + 0x0220) /* short, word */
168 #define MTU_TCBR (REG_BASE + 0x0222) /* short, word */
169 
170 /*MTU CHANNEL 3*/
171 #define MTU_TCR3 (REG_BASE + 0x0200) /* char, short, word */
172 #define MTU_TMDR3 (REG_BASE + 0x0202) /* char, short, word */
173 #define MTU_TIORH3 (REG_BASE + 0x0204) /* char, short, word */
174 #define MTU_TIORL3 (REG_BASE + 0x0205) /* char, short, word */
175 #define MTU_TIER3 (REG_BASE + 0x0208) /* char, short, word */
176 #define MTU_TSR3 (REG_BASE + 0x022C) /* char, short, word */
177 #define MTU_TCNT3 (REG_BASE + 0x0210) /* short, word */
178 #define MTU_GR3A (REG_BASE + 0x0218) /* short, word */
179 #define MTU_GR3B (REG_BASE + 0x021A) /* short, word */
180 #define MTU_GR3C (REG_BASE + 0x0224) /* short, word */
181 #define MTU_GR3D (REG_BASE + 0x0226) /* short, word */
182 
183 /*MTU CHANNEL 4*/
184 #define MTU_TCR4 (REG_BASE + 0x0201) /* char, short, word */
185 #define MTU_TMDR4 (REG_BASE + 0x0203) /* char, short, word */
186 #define MTU_TIOR4 (REG_BASE + 0x0206) /* char, short, word */
187 #define MTU_TIORH4 (REG_BASE + 0x0206) /* char, short, word */
188 #define MTU_TIORL4 (REG_BASE + 0x0207) /* char, short, word */
189 #define MTU_TIER4 (REG_BASE + 0x0209) /* char, short, word */
190 #define MTU_TSR4 (REG_BASE + 0x022D) /* char, short, word */
191 #define MTU_TCNT4 (REG_BASE + 0x0212) /* short, word */
192 #define MTU_GR4A (REG_BASE + 0x021C) /* short, word */
193 #define MTU_GR4B (REG_BASE + 0x021E) /* short, word */
194 #define MTU_GR4C (REG_BASE + 0x0228) /* short, word */
195 #define MTU_GR4D (REG_BASE + 0x022A) /* short, word */
196 
197 /*DMAC CHANNELS 0-3 SHARED*/
198 #define DMAOR (REG_BASE + 0x06B0) /* short */
199 
200 /*DMAC CHANNEL 0*/
201 #define DMA_SAR0 (REG_BASE + 0x06C0) /* short, word */
202 #define DMA_DAR0 (REG_BASE + 0x06C4) /* short, word */
203 #define DMA_DMATCR0 (REG_BASE + 0x06C8) /* short, word */
204 #define DMA_CHCR0 (REG_BASE + 0x06CC) /* short, word */
205 
206 /*DMAC CHANNEL 1*/
207 #define DMA_SAR1 (REG_BASE + 0x06D0) /* short, word */
208 #define DMA_DAR1 (REG_BASE + 0x06D4) /* short, word */
209 #define DMA_DMATCR1 (REG_BASE + 0x06D8) /* short, wordt */
210 #define DMA_CHCR1 (REG_BASE + 0x06DC) /* short, word */
211 
212 /*DMAC CHANNEL 3*/
213 #define DMA_SAR3 (REG_BASE + 0x06E0) /* short, word */
214 #define DMA_DAR3 (REG_BASE + 0x06E4) /* short, word */
215 #define DMA_DMATCR3 (REG_BASE + 0x06E8) /* short, word */
216 #define DMA_CHCR3 (REG_BASE + 0x06EC) /* short, word */
217 
218 /*DMAC CHANNEL 4*/
219 #define DMA_SAR4 (REG_BASE + 0x06F0) /* short, word */
220 #define DMA_DAR4 (REG_BASE + 0x06F4) /* short, word */
221 #define DMA_DMATCR4 (REG_BASE + 0x06F8) /* short, word */
222 #define DMA_CHCR4 (REG_BASE + 0x06FC) /* short, word */
223 
224 /*Data Transfer Controller*/
225 #define DTC_DTEA (REG_BASE + 0x0700) /* char, short, word */
226 #define DTC_DTEB (REG_BASE + 0x0701) /* char, short(?), word(?) */
227 #define DTC_DTEC (REG_BASE + 0x0702) /* char, short(?), word(?) */
228 #define DTC_DTED (REG_BASE + 0x0703) /* char, short(?), word(?) */
229 #define DTC_DTEE (REG_BASE + 0x0704) /* char, short(?), word(?) */
230 #define DTC_DTCSR (REG_BASE + 0x0706) /* char, short, word */
231 #define DTC_DTBR (REG_BASE + 0x0708) /* short, word */
232 
233 /*Cache Memory*/
234 #define CAC_CCR (REG_BASE + 0x0740) /* char, short, word */
235 
236 /*INTC*/
237 #define INTC_IPRA (REG_BASE + 0x0348) /* char, short, word */
238 #define INTC_IPRB (REG_BASE + 0x034A) /* char, short, word */
239 #define INTC_IPRC (REG_BASE + 0x034C) /* char, short, word */
240 #define INTC_IPRD (REG_BASE + 0x034E) /* char, short, word */
241 #define INTC_IPRE (REG_BASE + 0x0350) /* char, short, word */
242 #define INTC_IPRF (REG_BASE + 0x0352) /* char, short, word */
243 #define INTC_IPRG (REG_BASE + 0x0354) /* char, short, word */
244 #define INTC_IPRH (REG_BASE + 0x0356) /* char, short, word */
245 #define INTC_ICR (REG_BASE + 0x0358) /* char, short, word */
246 #define INTC_ISR (REG_BASE + 0x035A) /* char, short, word */
247 
248 /*Flash (F-ZTAT)*/
249 #define FL_FLMCR1 (REG_BASE + 0x0580) /* Fl.Mem.Contr.Reg 1: char */
250 #define FL_FLMCR2 (REG_BASE + 0x0581) /* Fl.Mem.Contr.Reg 2: char */
251 #define FL_EBR1 (REG_BASE + 0x0582) /* Fl.Mem.Erase Blk.1: char */
252 #define FL_EBR2 (REG_BASE + 0x0584) /* Fl.Mem.Erase Blk.2: char */
253 #define FL_RAMER (REG_BASE + 0x0628) /* Ram Emul.Reg.- char,short,word */
254 
255 /*UBC*/
256 #define UBC_BARH (REG_BASE + 0x0600) /* char, short, word */
257 #define UBC_BARL (REG_BASE + 0x0602) /* char, short, word */
258 #define UBC_BAMRH (REG_BASE + 0x0604) /* char, short, word */
259 #define UBC_BAMRL (REG_BASE + 0x0606) /* char, short, word */
260 #define UBC_BBR (REG_BASE + 0x0608) /* char, short, word */
261 /*BSC*/
262 #define BSC_BCR1 (REG_BASE + 0x0620) /* short */
263 #define BSC_BCR2 (REG_BASE + 0x0622) /* short */
264 #define BSC_WCR1 (REG_BASE + 0x0624) /* short */
265 #define BSC_WCR2 (REG_BASE + 0x0626) /* short */
266 #define BSC_DCR (REG_BASE + 0x062A) /* short */
267 #define BSC_RTCSR (REG_BASE + 0x062C) /* short */
268 #define BSC_RTCNT (REG_BASE + 0x062E) /* short */
269 #define BSC_RTCOR (REG_BASE + 0x0630) /* short */
270 
271 /*WDT*/
272 #define WDT_R_TCSR (REG_BASE + 0x0610) /* rd: char */
273 #define WDT_R_TCNT (REG_BASE + 0x0611) /* rd: char */
274 #define WDT_R_RSTCSR (REG_BASE + 0x0613) /* rd: char */
275 #define WDT_W_TCSR (REG_BASE + 0x0610) /* wrt: short */
276 #define WDT_W_TCNT (REG_BASE + 0x0610) /* wrt: short */
277 #define WDT_W_RSTCSR (REG_BASE + 0x0612) /* wrt: short */
278 
279 /*POWER DOWN STATE*/
280 #define PDT_SBYCR (REG_BASE + 0x0614) /* char */
281 
282 /* Port I/O Control Registers */
283 #define IO_PADRH (REG_BASE + 0x0380) /* Port A Data Register */
284 #define IO_PADRL (REG_BASE + 0x0382) /* Port A Data Register */
285 #define IO_PBDR (REG_BASE + 0x0390) /* Port B Data Register */
286 #define IO_PCDR (REG_BASE + 0x0392) /* Port C Data Register */
287 #define IO_PDDRH (REG_BASE + 0x03A0) /* Port D Data Register */
288 #define IO_PDDRL (REG_BASE + 0x03A2) /* Port D Data Register */
289 #define IO_PEDR (REG_BASE + 0x03B0) /* Port E Data Register */
290 #define IO_PFDR (REG_BASE + 0x03B2) /* Port F Data Register */
291 
292 /*Pin Function Control Register*/
293 #define PFC_PAIORH (REG_BASE + 0x0384) /* Port A I/O Reg. H */
294 #define PFC_PAIORL (REG_BASE + 0x0386) /* Port A I/O Reg. L */
295 #define PFC_PACRH (REG_BASE + 0x0388) /* Port A Ctr. Reg. H */
296 #define PFC_PACRL1 (REG_BASE + 0x038C) /* Port A Ctr. Reg. L1 */
297 #define PFC_PACRL2 (REG_BASE + 0x038E) /* Port A Ctr. Reg. L2 */
298 #define PFC_PBIOR (REG_BASE + 0x0394) /* Port B I/O Register */
299 #define PFC_PBCR1 (REG_BASE + 0x0398) /* Port B Ctr. Reg. R1 */
300 #define PFC_PBCR2 (REG_BASE + 0x039A) /* Port B Ctr. Reg. R2 */
301 #define PFC_PCIOR (REG_BASE + 0x0396) /* Port C I/O Register */
302 #define PFC_PCCR (REG_BASE + 0x039C) /* Port C Ctr. Reg. */
303 #define PFC_PDIORH (REG_BASE + 0x03A4) /* Port D I/O Reg. H */
304 #define PFC_PDIORL (REG_BASE + 0x03A6) /* Port D I/O Reg. L */
305 #define PFC_PDCRH1 (REG_BASE + 0x03A8) /* Port D Ctr. Reg. H1 */
306 #define PFC_PDCRH2 (REG_BASE + 0x03AA) /* Port D Ctr. Reg. H2 */
307 #define PFC_PDCRL (REG_BASE + 0x03AC) /* Port D Ctr. Reg. L */
308 #define PFC_PEIOR (REG_BASE + 0x03B4) /* Port E I/O Register */
309 #define PFC_PECR1 (REG_BASE + 0x03B8) /* Port E Ctr. Reg. 1 */
310 #define PFC_PECR2 (REG_BASE + 0x03BA) /* Port E Ctr. Reg. 2 */
311 #define PFC_IFCR (REG_BASE + 0x03C8) /* short */
312 
313 /*Compare/Match Timer*/
314 #define CMT_CMSTR (REG_BASE + 0x3D0) /* Start Reg. char, short, word */
315 #define CMT_CMCSR0 (REG_BASE + 0x3D2) /* C0 SCR short, word */
316 #define CMT_CMCNT0 (REG_BASE + 0x3D4) /* C0 Counter char, short, word */
317 #define CMT_CMCOR0 (REG_BASE + 0x3D6) /* C0 Const.Reg. char, short, word */
318 #define CMT_CMCSR1 (REG_BASE + 0x3D8) /* C1 SCR short, word */
319 #define CMT_CMCNT1 (REG_BASE + 0x3DA) /* C1 Counter char, short, word */
320 #define CMT_CMCOR1 (REG_BASE + 0x3DC) /* C1 Const.Reg. char, short, word */
321 
322 #endif
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