RTEMS  5.1
gtintrreg.h
1 /* $NetBSD: gtintrreg.h,v 1.3 2005/02/27 00:27:21 perry Exp $ */
2 
3 /*
4  * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  * notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  * notice, this list of conditions and the following disclaimer in the
14  * documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  * must display the following acknowledgement:
17  * This product includes software developed for the NetBSD Project by
18  * Allegro Networks, Inc., and Wasabi Systems, Inc.
19  * 4. The name of Allegro Networks, Inc. may not be used to endorse
20  * or promote products derived from this software without specific prior
21  * written permission.
22  * 5. The name of Wasabi Systems, Inc. may not be used to endorse
23  * or promote products derived from this software without specific prior
24  * written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
27  * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
28  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
29  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30  * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37  * POSSIBILITY OF SUCH DAMAGE.
38  */
39 
40 /*
41  * gt64260intr.h: defines for GT-64260 system controller interrupts
42  *
43  * creation Sun Jan 7 18:05:59 PST 2001 cliff
44  *
45  * NOTE:
46  * Galileo GT-64260 manual bit defines assume Little Endian
47  * ordering of bits within bytes, i.e.
48  * bit #0 --> 0x01
49  * vs. Motorola Big Endian bit numbering where
50  * bit #0 --> 0x80
51  * Consequently we define bits in Little Endian format and plan
52  * to swizzle bytes during programmed I/O by using lwbrx/swbrx
53  * to load/store GT-64260 registers.
54  */
55 
56 
57 #ifndef _DISCOVERY_GT64260INTR_H
58 #define _DISCOVERY_GT64260INTR_H
59 
60 #define BIT(n) (1<<(n))
61 
62 
63 /*
64  * GT-64260 Interrupt Controller Register Map
65  */
66 #define ICR_260_MIC_LO 0xc18 /* main interrupt cause low */
67 #define ICR_260_MIC_HI 0xc68 /* main interrupt cause high */
68 #define ICR_260_CIM_LO 0xc1c /* CPU interrupt mask low */
69 #define ICR_260_CIM_HI 0xc6c /* CPU interrupt mask high */
70 #define ICR_260_CSC 0xc70 /* CPU select cause */
71 #define ICR_260_P0IM_LO 0xc24 /* PCI_0 interrupt mask low */
72 #define ICR_260_P0IM_HI 0xc64 /* PCI_0 interrupt mask high */
73 #define ICR_260_P0SC 0xc74 /* PCI_0 select cause */
74 #define ICR_260_P1IM_LO 0xca4 /* PCI_1 interrupt mask low */
75 #define ICR_260_P1IM_HI 0xce4 /* PCI_1 interrupt mask high */
76 #define ICR_260_P1SC 0xcf4 /* PCI_1 select cause */
77 #define ICR_260_CI0M 0xe60 /* CPU int[0] mask */
78 #define ICR_260_CI1M 0xe64 /* CPU int[1] mask */
79 #define ICR_260_CI2M 0xe68 /* CPU int[2] mask */
80 #define ICR_260_CI3M 0xe6c /* CPU int[3] mask */
81 
82 /*
83  * MV64360 Interrupt Controller Register Map
84  */
85 #define ICR_360_MIC_LO 0x004 /* main interrupt cause low */
86 #define ICR_360_MIC_HI 0x00c /* main interrupt cause high */
87 #define ICR_360_C0IM_LO 0x014 /* CPU 0 interrupt mask low */
88 #define ICR_360_C0IM_HI 0x01c /* CPU 0 interrupt mask high */
89 #define ICR_360_C0SC 0x024 /* CPU 0 select cause */
90 #define ICR_360_C1IM_LO 0x034 /* CPU 1 interrupt mask low */
91 #define ICR_360_C1IM_HI 0x03c /* CPU 1 interrupt mask high */
92 #define ICR_360_C1SC 0x044 /* CPU 1 select cause */
93 #define ICR_360_I0M_LO 0x014 /* Int 0 mask low */
94 #define ICR_360_I0M_HI 0x01c /* Int 0 mask high */
95 #define ICR_360_I0SC 0x024 /* Int 0 select cause */
96 #define ICR_360_I1M_LO 0x034 /* Int 1 mask low */
97 #define ICR_360_I1M_HI 0x03c /* Int 1 mask high */
98 #define ICR_360_C1SC 0x044 /* Int 1 select cause */
99 
100 
101 /*
102  * IRQs:
103  * we define IRQs based on bit number in the
104  * ICU_LEN dimensioned hardware portion of the imask_t bit vector
105  * which consists of 64 bits of Main Cause and Mask register pairs
106  * (ICR_MIC_LO, ICR_MIC_HI and ICR_CIM_LO, ICR_CIM_HI)
107  * as well as 32 bits in GPP registers (see intr.h):
108  *
109  * IRQs:
110  * 31.............................0 63.............................32
111  * | | |
112  * imask_t index: | | |
113  * | | | |
114  * ^--------- IM_PIC_LO ----------^ ^------ IM_PIC_HI ------------^
115  * | | |
116  * Bitmasks: | | |
117  * | | | |
118  * ^--------- IML_* --------------^ ^------ IMH_* ----------------^
119  * | | |
120  * Registers: | | |
121  * | | | |
122  * ^--------- ICR_MIC_LO ---------^ ^------ ICR_MIC_HI -----------^
123  * ^--------- ICR_CIM_LO ---------^ ^------ ICR_CIM_HI -----------^
124  *
125  * IRQs:
126  * 95............................64 127............................96
127  * | | |
128  * imask_t index: | | |
129  * | | | |
130  * ^-------- IMASK_GPP ----------^ ^----- IMASK_SOFTINT --------^
131  * | | |
132  * Bitmasks: | | |
133  * | | | |
134  * ^--------- GPP_* --------------^ ^------ SIBIT(irq) -----------^
135  * | | |
136  * Registers: | | |
137  * | | | |
138  * ^--- GT_GPP_Interrupt_Cause ---^ ^------- (none) -----------^
139  * ^--- GT_GPP_Interrupt_Mask ---^
140  *
141  *
142  * Note that GPP interrupts are summarized in the Main Cause Register.
143  *
144  * Some IRQs are "resvered" undefined due to gaps in HW register utilization.
145  */
146 #define IRQ_DEV 1 /* device interface interrupt */
147 #define IRQ_DMA 2 /* DMA addres error interrupt */
148 #define IRQ_CPU 3 /* CPU interface interrupt */
149 #define IRQ_IDMA0_1 4 /* IDMA ch. 0..1 complete interrupt */
150 #define IRQ_IDMA2_3 5 /* IDMA ch. 2..3 complete interrupt */
151 #define IRQ_IDMA4_5 6 /* IDMA ch. 4..5 complete interrupt */
152 #define IRQ_IDMA6_7 7 /* IDMA ch. 6..7 complete interrupt */
153 #define IRQ_TIME0_1 8 /* Timer 0..1 interrupt */
154 #define IRQ_TIME2_3 9 /* Timer 2..3 interrupt */
155 #define IRQ_TIME4_5 10 /* Timer 4..5 interrupt */
156 #define IRQ_TIME6_7 11 /* Timer 6..7 interrupt */
157 #define IRQ_PCI0_0 12 /* PCI 0 interrupt 0 summary */
158 #define IRQ_PCI0_1 13 /* PCI 0 interrupt 1 summary */
159 #define IRQ_PCI0_2 14 /* PCI 0 interrupt 2 summary */
160 #define IRQ_PCI0_3 15 /* PCI 0 interrupt 3 summary */
161 #define IRQ_PCI1_0 16 /* PCI 1 interrupt 0 summary */
162 #define IRQ_ECC 17 /* ECC error interrupt */
163 #define IRQ_PCI1_1 18 /* PCI 1 interrupt 1 summary */
164 #define IRQ_PCI1_2 19 /* PCI 1 interrupt 2 summary */
165 #define IRQ_PCI1_3 20 /* PCI 1 interrupt 3 summary */
166 #define IRQ_PCI0OUT_LO 21 /* PCI 0 outbound interrupt summary */
167 #define IRQ_PCI0OUT_HI 22 /* PCI 0 outbound interrupt summary */
168 #define IRQ_PCI1OUT_LO 23 /* PCI 1 outbound interrupt summary */
169 #define IRQ_PCI1OUT_HI 24 /* PCI 1 outbound interrupt summary */
170 #define IRQ_PCI0IN_LO 26 /* PCI 0 inbound interrupt summary */
171 #define IRQ_PCI0IN_HI 27 /* PCI 0 inbound interrupt summary */
172 #define IRQ_PCI1IN_LO 28 /* PCI 1 inbound interrupt summary */
173 #define IRQ_PCI1IN_HI 29 /* PCI 1 inbound interrupt summary */
174 #define IRQ_ETH0 (32+0) /* Ethernet controller 0 interrupt */
175 #define IRQ_ETH1 (32+1) /* Ethernet controller 1 interrupt */
176 #define IRQ_ETH2 (32+2) /* Ethernet controller 2 interrupt */
177 #define IRQ_SDMA (32+4) /* SDMA interrupt */
178 #define IRQ_I2C (32+5) /* I2C interrupt */
179 #define IRQ_BRG (32+7) /* Baud Rate Generator interrupt */
180 #define IRQ_MPSC0 (32+8) /* MPSC 0 interrupt */
181 #define IRQ_MPSC1 (32+10) /* MPSC 1 interrupt */
182 #define IRQ_COMM (32+11) /* Comm unit interrupt */
183 #define IRQ_GPP7_0 (32+24) /* GPP[7..0] interrupt */
184 #define IRQ_GPP15_8 (32+25) /* GPP[15..8] interrupt */
185 #define IRQ_GPP23_16 (32+26) /* GPP[23..16] interrupt */
186 #define IRQ_GPP31_24 (32+27) /* GPP[31..24] interrupt */
187 
188 /*
189  * low word interrupt mask register bits
190  */
191 #define IML_SUM BIT(0)
192 #define IML_DEV BIT(IRQ_DEV)
193 #define IML_DMA BIT(IRQ_DMA)
194 #define IML_CPU BIT(IRQ_CPU)
195 #define IML_IDMA0_1 BIT(IRQ_IDMA0_1)
196 #define IML_IDMA2_3 BIT(IRQ_IDMA2_3)
197 #define IML_IDMA4_5 BIT(IRQ_IDMA4_5)
198 #define IML_IDMA6_7 BIT(IRQ_IDMA6_7)
199 #define IML_TIME0_1 BIT(IRQ_TIME0_1)
200 #define IML_TIME2_3 BIT(IRQ_TIME2_3)
201 #define IML_TIME4_5 BIT(IRQ_TIME4_5)
202 #define IML_TIME6_7 BIT(IRQ_TIME6_7)
203 #define IML_PCI0_0 BIT(IRQ_PCI0_0)
204 #define IML_PCI0_1 BIT(IRQ_PCI0_1)
205 #define IML_PCI0_2 BIT(IRQ_PCI0_2)
206 #define IML_PCI0_3 BIT(IRQ_PCI0_3)
207 #define IML_PCI1_0 BIT(IRQ_PCI1_0)
208 #define IML_ECC BIT(IRQ_ECC)
209 #define IML_PCI1_1 BIT(IRQ_PCI1_1)
210 #define IML_PCI1_2 BIT(IRQ_PCI1_2)
211 #define IML_PCI1_3 BIT(IRQ_PCI1_3)
212 #define IML_PCI0OUT_LO BIT(IRQ_PCI0OUT_LO)
213 #define IML_PCI0OUT_HI BIT(IRQ_PCI0OUT_HI)
214 #define IML_PCI1OUT_LO BIT(IRQ_PCI1OUT_LO)
215 #define IML_PCI1OUT_HI BIT(IRQ_PCI1OUT_HI)
216 #define IML_PCI0IN_LO BIT(IRQ_PCI0IN_LO)
217 #define IML_PCI0IN_HI BIT(IRQ_PCI0IN_HI)
218 #define IML_PCI1IN_LO BIT(IRQ_PCI1IN_LO)
219 #define IML_PCI1IN_HI BIT(IRQ_PCI1IN_HI)
220 #define IML_RES (BIT(25)|BIT(30)|BIT(31))
221 
222 /*
223  * high word interrupt mask register bits
224  */
225 #define IMH_ETH0 BIT(IRQ_ETH0-32)
226 #define IMH_ETH1 BIT(IRQ_ETH1-32)
227 #define IMH_ETH2 BIT(IRQ_ETH2-32)
228 #define IMH_SDMA BIT(IRQ_SDMA-32)
229 #define IMH_I2C BIT(IRQ_I2C-32)
230 #define IMH_BRG BIT(IRQ_BRG-32)
231 #define IMH_MPSC0 BIT(IRQ_MPSC0-32)
232 #define IMH_MPSC1 BIT(IRQ_MPSC1-32)
233 #define IMH_COMM BIT(IRQ_COMM-32)
234 #define IMH_GPP7_0 BIT(IRQ_GPP7_0-32)
235 #define IMH_GPP15_8 BIT(IRQ_GPP15_8-32)
236 #define IMH_GPP23_16 BIT(IRQ_GPP23_16-32)
237 #define IMH_GPP31_24 BIT(IRQ_GPP31_24-32)
238 #define IMH_GPP_SUM (IMH_GPP7_0|IMH_GPP15_8|IMH_GPP23_16|IMH_GPP31_24)
239 #define IMH_RES (BIT(3) |BIT(6) |BIT(9) |BIT(12)|BIT(13)|BIT(14) \
240  |BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20) \
241  |BIT(21)|BIT(22)|BIT(23)|BIT(28)|BIT(29)|BIT(30) \
242  |BIT(31))
243 
244 /*
245  * ICR_CSC "Select Cause" register bits
246  */
247 #define CSC_SEL BIT(30) /* HI/LO select */
248 #define CSC_STAT BIT(31) /* ? "irq active" : "irq none" */
249 #define CSC_CAUSE ~(CSC_SEL|CSC_STAT)
250 
251 
252 /*
253  * CPU Int[n] Mask bit(s)
254  */
255 #define CPUINT_SEL 0x80000000 /* HI/LO select */
256 
257 #endif /* _DISCOVERY_GT64260INTR_H */
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