RTEMS  5.1
Data Structures | Macros
AHB Bus Matrix
Board Support Packages » ARM » Atmel/Microchip SAM E70, S70, V70 and V71 » Contributed Code » SAMV71

Data Structures

struct  MatrixPr
 MatrixPr hardware registers. More...
 
struct  Matrix
 Matrix hardware registers. More...
 

Macros

#define MATRIXPR_NUMBER   9
 Matrix hardware registers.
 
#define MATRIX_MCFG_ULBT_Pos   0
 
#define MATRIX_MCFG_ULBT_Msk   (0x7u << MATRIX_MCFG_ULBT_Pos)
 (MATRIX_MCFG[12]) Undefined Length Burst Type
 
#define MATRIX_MCFG_ULBT(value)   ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))
 
#define MATRIX_MCFG_ULBT_UNLTD_LENGTH   (0x0u << 0)
 (MATRIX_MCFG[12]) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
 
#define MATRIX_MCFG_ULBT_SINGLE_ACCESS   (0x1u << 0)
 (MATRIX_MCFG[12]) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
 
#define MATRIX_MCFG_ULBT_4BEAT_BURST   (0x2u << 0)
 (MATRIX_MCFG[12]) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
 
#define MATRIX_MCFG_ULBT_8BEAT_BURST   (0x3u << 0)
 (MATRIX_MCFG[12]) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
 
#define MATRIX_MCFG_ULBT_16BEAT_BURST   (0x4u << 0)
 (MATRIX_MCFG[12]) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
 
#define MATRIX_MCFG_ULBT_32BEAT_BURST   (0x5u << 0)
 (MATRIX_MCFG[12]) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
 
#define MATRIX_MCFG_ULBT_64BEAT_BURST   (0x6u << 0)
 (MATRIX_MCFG[12]) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
 
#define MATRIX_MCFG_ULBT_128BEAT_BURST   (0x7u << 0)
 (MATRIX_MCFG[12]) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
 
#define MATRIX_SCFG_SLOT_CYCLE_Pos   0
 
#define MATRIX_SCFG_SLOT_CYCLE_Msk   (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos)
 (MATRIX_SCFG[9]) Maximum Bus Grant Duration for Masters
 
#define MATRIX_SCFG_SLOT_CYCLE(value)   ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
 
#define MATRIX_SCFG_DEFMSTR_TYPE_Pos   16
 
#define MATRIX_SCFG_DEFMSTR_TYPE_Msk   (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos)
 (MATRIX_SCFG[9]) Default Master Type
 
#define MATRIX_SCFG_DEFMSTR_TYPE(value)   ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
 
#define MATRIX_SCFG_DEFMSTR_TYPE_NONE   (0x0u << 16)
 (MATRIX_SCFG[9]) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
 
#define MATRIX_SCFG_DEFMSTR_TYPE_LAST   (0x1u << 16)
 (MATRIX_SCFG[9]) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
 
#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED   (0x2u << 16)
 (MATRIX_SCFG[9]) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
 
#define MATRIX_SCFG_FIXED_DEFMSTR_Pos   18
 
#define MATRIX_SCFG_FIXED_DEFMSTR_Msk   (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos)
 (MATRIX_SCFG[9]) Fixed Default Master
 
#define MATRIX_SCFG_FIXED_DEFMSTR(value)   ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
 
#define MATRIX_PRAS_M0PR_Pos   0
 
#define MATRIX_PRAS_M0PR_Msk   (0x3u << MATRIX_PRAS_M0PR_Pos)
 (MATRIX_PRAS) Master 0 Priority
 
#define MATRIX_PRAS_M0PR(value)   ((MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos)))
 
#define MATRIX_PRAS_M1PR_Pos   4
 
#define MATRIX_PRAS_M1PR_Msk   (0x3u << MATRIX_PRAS_M1PR_Pos)
 (MATRIX_PRAS) Master 1 Priority
 
#define MATRIX_PRAS_M1PR(value)   ((MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos)))
 
#define MATRIX_PRAS_M2PR_Pos   8
 
#define MATRIX_PRAS_M2PR_Msk   (0x3u << MATRIX_PRAS_M2PR_Pos)
 (MATRIX_PRAS) Master 2 Priority
 
#define MATRIX_PRAS_M2PR(value)   ((MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos)))
 
#define MATRIX_PRAS_M3PR_Pos   12
 
#define MATRIX_PRAS_M3PR_Msk   (0x3u << MATRIX_PRAS_M3PR_Pos)
 (MATRIX_PRAS) Master 3 Priority
 
#define MATRIX_PRAS_M3PR(value)   ((MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos)))
 
#define MATRIX_PRAS_M4PR_Pos   16
 
#define MATRIX_PRAS_M4PR_Msk   (0x3u << MATRIX_PRAS_M4PR_Pos)
 (MATRIX_PRAS) Master 4 Priority
 
#define MATRIX_PRAS_M4PR(value)   ((MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos)))
 
#define MATRIX_PRAS_M5PR_Pos   20
 
#define MATRIX_PRAS_M5PR_Msk   (0x3u << MATRIX_PRAS_M5PR_Pos)
 (MATRIX_PRAS) Master 5 Priority
 
#define MATRIX_PRAS_M5PR(value)   ((MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos)))
 
#define MATRIX_PRAS_M6PR_Pos   24
 
#define MATRIX_PRAS_M6PR_Msk   (0x3u << MATRIX_PRAS_M6PR_Pos)
 (MATRIX_PRAS) Master 6 Priority
 
#define MATRIX_PRAS_M6PR(value)   ((MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos)))
 
#define MATRIX_PRAS_M7PR_Pos   28
 
#define MATRIX_PRAS_M7PR_Msk   (0x3u << MATRIX_PRAS_M7PR_Pos)
 (MATRIX_PRAS) Master 7 Priority
 
#define MATRIX_PRAS_M7PR(value)   ((MATRIX_PRAS_M7PR_Msk & ((value) << MATRIX_PRAS_M7PR_Pos)))
 
#define MATRIX_PRBS_M8PR_Pos   0
 
#define MATRIX_PRBS_M8PR_Msk   (0x3u << MATRIX_PRBS_M8PR_Pos)
 (MATRIX_PRBS) Master 8 Priority
 
#define MATRIX_PRBS_M8PR(value)   ((MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos)))
 
#define MATRIX_PRBS_M9PR_Pos   4
 
#define MATRIX_PRBS_M9PR_Msk   (0x3u << MATRIX_PRBS_M9PR_Pos)
 (MATRIX_PRBS) Master 9 Priority
 
#define MATRIX_PRBS_M9PR(value)   ((MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos)))
 
#define MATRIX_PRBS_M10PR_Pos   8
 
#define MATRIX_PRBS_M10PR_Msk   (0x3u << MATRIX_PRBS_M10PR_Pos)
 (MATRIX_PRBS) Master 10 Priority
 
#define MATRIX_PRBS_M10PR(value)   ((MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos)))
 
#define MATRIX_PRBS_M11PR_Pos   12
 
#define MATRIX_PRBS_M11PR_Msk   (0x3u << MATRIX_PRBS_M11PR_Pos)
 (MATRIX_PRBS) Master 11 Priority
 
#define MATRIX_PRBS_M11PR(value)   ((MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos)))
 
#define MATRIX_MRCR_RCB0   (0x1u << 0)
 (MATRIX_MRCR) Remap Command Bit for Master 0
 
#define MATRIX_MRCR_RCB1   (0x1u << 1)
 (MATRIX_MRCR) Remap Command Bit for Master 1
 
#define MATRIX_MRCR_RCB2   (0x1u << 2)
 (MATRIX_MRCR) Remap Command Bit for Master 2
 
#define MATRIX_MRCR_RCB3   (0x1u << 3)
 (MATRIX_MRCR) Remap Command Bit for Master 3
 
#define MATRIX_MRCR_RCB4   (0x1u << 4)
 (MATRIX_MRCR) Remap Command Bit for Master 4
 
#define MATRIX_MRCR_RCB5   (0x1u << 5)
 (MATRIX_MRCR) Remap Command Bit for Master 5
 
#define MATRIX_MRCR_RCB6   (0x1u << 6)
 (MATRIX_MRCR) Remap Command Bit for Master 6
 
#define MATRIX_MRCR_RCB7   (0x1u << 7)
 (MATRIX_MRCR) Remap Command Bit for Master 7
 
#define MATRIX_MRCR_RCB8   (0x1u << 8)
 (MATRIX_MRCR) Remap Command Bit for Master 8
 
#define MATRIX_MRCR_RCB9   (0x1u << 9)
 (MATRIX_MRCR) Remap Command Bit for Master 9
 
#define MATRIX_MRCR_RCB10   (0x1u << 10)
 (MATRIX_MRCR) Remap Command Bit for Master 10
 
#define MATRIX_MRCR_RCB11   (0x1u << 11)
 (MATRIX_MRCR) Remap Command Bit for Master 11
 
#define CCFG_CAN0_CAN0DMABA_Pos   16
 
#define CCFG_CAN0_CAN0DMABA_Msk   (0xffffu << CCFG_CAN0_CAN0DMABA_Pos)
 (CCFG_CAN0) CAN0 DMA Base Address
 
#define CCFG_CAN0_CAN0DMABA(value)   ((CCFG_CAN0_CAN0DMABA_Msk & ((value) << CCFG_CAN0_CAN0DMABA_Pos)))
 
#define CCFG_SYSIO_SYSIO4   (0x1u << 4)
 (CCFG_SYSIO) PB4 or TDI Assignment
 
#define CCFG_SYSIO_SYSIO5   (0x1u << 5)
 (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment
 
#define CCFG_SYSIO_SYSIO6   (0x1u << 6)
 (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment
 
#define CCFG_SYSIO_SYSIO7   (0x1u << 7)
 (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment
 
#define CCFG_SYSIO_SYSIO12   (0x1u << 12)
 (CCFG_SYSIO) PB12 or ERASE Assignment
 
#define CCFG_SYSIO_CAN1DMABA_Pos   16
 
#define CCFG_SYSIO_CAN1DMABA_Msk   (0xffffu << CCFG_SYSIO_CAN1DMABA_Pos)
 (CCFG_SYSIO) CAN1 DMA Base Address
 
#define CCFG_SYSIO_CAN1DMABA(value)   ((CCFG_SYSIO_CAN1DMABA_Msk & ((value) << CCFG_SYSIO_CAN1DMABA_Pos)))
 
#define CCFG_SMCNFCS_SMC_NFCS0   (0x1u << 0)
 (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment
 
#define CCFG_SMCNFCS_SMC_NFCS1   (0x1u << 1)
 (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment
 
#define CCFG_SMCNFCS_SMC_NFCS2   (0x1u << 2)
 (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment
 
#define CCFG_SMCNFCS_SMC_NFCS3   (0x1u << 3)
 (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment
 
#define CCFG_SMCNFCS_SDRAMEN   (0x1u << 4)
 (CCFG_SMCNFCS) SDRAM Enable
 
#define MATRIX_WPMR_WPEN   (0x1u << 0)
 (MATRIX_WPMR) Write Protection Enable
 
#define MATRIX_WPMR_WPKEY_Pos   8
 
#define MATRIX_WPMR_WPKEY_Msk   (0xffffffu << MATRIX_WPMR_WPKEY_Pos)
 (MATRIX_WPMR) Write Protection Key
 
#define MATRIX_WPMR_WPKEY(value)   ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
 
#define MATRIX_WPMR_WPKEY_PASSWD   (0x4D4154u << 8)
 (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
 
#define MATRIX_WPSR_WPVS   (0x1u << 0)
 (MATRIX_WPSR) Write Protection Violation Status
 
#define MATRIX_WPSR_WPVSRC_Pos   8
 
#define MATRIX_WPSR_WPVSRC_Msk   (0xffffu << MATRIX_WPSR_WPVSRC_Pos)
 (MATRIX_WPSR) Write Protection Violation Source
 
#define MATRIX_VERSION_VERSION_Pos   0
 
#define MATRIX_VERSION_VERSION_Msk   (0xfffu << MATRIX_VERSION_VERSION_Pos)
 (MATRIX_VERSION) Version of the Hardware Module
 
#define MATRIX_VERSION_MFN_Pos   16
 
#define MATRIX_VERSION_MFN_Msk   (0x7u << MATRIX_VERSION_MFN_Pos)
 (MATRIX_VERSION) Metal Fix Number
 

Detailed Description

SOFTWARE API DEFINITION FOR AHB Bus Matrix

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