RTEMS  5.1
Modules | Macros

Modules

 CMSIS Definitions
 
 Peripheral Base Address Definitions
 
 Peripheral Ids Definitions
 
 Peripheral Pio Definitions
 
 Peripheral Software API
 
 Registers Access Definitions
 

Macros

#define IFLASH_SIZE   (0x80000u)
 
#define IFLASH_PAGE_SIZE   (512u)
 
#define IFLASH_LOCK_REGION_SIZE   (8192u)
 
#define IFLASH_NB_OF_PAGES   (1024u)
 
#define IFLASH_NB_OF_LOCK_BITS   (32u)
 
#define IRAM_SIZE   (0x40000u)
 
#define QSPIMEM_ADDR   (0x80000000u)
 
#define AXIMX_ADDR   (0xA0000000u)
 
#define ITCM_ADDR   (0x00000000u)
 
#define IFLASH_ADDR   (0x00400000u)
 
#define IROM_ADDR   (0x00800000u)
 
#define DTCM_ADDR   (0x20000000u)
 
#define IRAM_ADDR   (0x20400000u)
 
#define EBI_CS0_ADDR   (0x60000000u)
 
#define EBI_CS1_ADDR   (0x61000000u)
 
#define EBI_CS2_ADDR   (0x62000000u)
 
#define EBI_CS3_ADDR   (0x63000000u)
 
#define SDRAM_CS_ADDR   (0x70000000u)
 
#define CHIP_JTAGID   (0x05B3D03FUL)
 
#define CHIP_CIDR   (0xA12D0A00UL)
 
#define CHIP_EXID   (0x00000002UL)
 
#define CHIP_FREQ_SLCK_RC_MIN   (20000UL)
 
#define CHIP_FREQ_SLCK_RC   (32000UL)
 
#define CHIP_FREQ_SLCK_RC_MAX   (44000UL)
 
#define CHIP_FREQ_MAINCK_RC_4MHZ   (4000000UL)
 
#define CHIP_FREQ_MAINCK_RC_8MHZ   (8000000UL)
 
#define CHIP_FREQ_MAINCK_RC_12MHZ   (12000000UL)
 
#define CHIP_FREQ_CPU_MAX   (120000000UL)
 
#define CHIP_FREQ_XTAL_32K   (32768UL)
 
#define CHIP_FREQ_XTAL_12M   (12000000UL)
 
#define CHIP_FREQ_FWS_0   (20000000UL)
 Maximum operating frequency when FWS is 0.
 
#define CHIP_FREQ_FWS_1   (40000000UL)
 Maximum operating frequency when FWS is 1.
 
#define CHIP_FREQ_FWS_2   (60000000UL)
 Maximum operating frequency when FWS is 2.
 
#define CHIP_FREQ_FWS_3   (80000000UL)
 Maximum operating frequency when FWS is 3.
 
#define CHIP_FREQ_FWS_4   (100000000UL)
 Maximum operating frequency when FWS is 4.
 
#define CHIP_FREQ_FWS_5   (123000000UL)
 Maximum operating frequency when FWS is 5.
 

Detailed Description

This file defines all structures and symbols for SAMV71Q19:

Macro Definition Documentation

◆ AXIMX_ADDR

#define AXIMX_ADDR   (0xA0000000u)

AXI Bus Matrix base address

◆ DTCM_ADDR

#define DTCM_ADDR   (0x20000000u)

Data Tightly Coupled Memory base address

◆ EBI_CS0_ADDR

#define EBI_CS0_ADDR   (0x60000000u)

EBI Chip Select 0 base address

◆ EBI_CS1_ADDR

#define EBI_CS1_ADDR   (0x61000000u)

EBI Chip Select 1 base address

◆ EBI_CS2_ADDR

#define EBI_CS2_ADDR   (0x62000000u)

EBI Chip Select 2 base address

◆ EBI_CS3_ADDR

#define EBI_CS3_ADDR   (0x63000000u)

EBI Chip Select 3 base address

◆ IFLASH_ADDR

#define IFLASH_ADDR   (0x00400000u)

Internal Flash base address

◆ IRAM_ADDR

#define IRAM_ADDR   (0x20400000u)

Internal RAM base address

◆ IROM_ADDR

#define IROM_ADDR   (0x00800000u)

Internal ROM base address

◆ ITCM_ADDR

#define ITCM_ADDR   (0x00000000u)

Instruction Tightly Coupled Memory base address

◆ QSPIMEM_ADDR

#define QSPIMEM_ADDR   (0x80000000u)

QSPI Memory base address

◆ SDRAM_CS_ADDR

#define SDRAM_CS_ADDR   (0x70000000u)

SDRAM Chip Select base address