Static Memory Controller

Data Structures
struct	SmcCs_number
	SmcCs_number hardware registers. More...
struct	Smc

Macros
#define	SMCCS_NUMBER_NUMBER   4
	Smc hardware registers.
#define	SMC_SETUP_NWE_SETUP_Pos   0
#define	SMC_SETUP_NWE_SETUP_Msk   (0x3fu << SMC_SETUP_NWE_SETUP_Pos)
	(SMC_SETUP) NWE Setup Length
#define	SMC_SETUP_NWE_SETUP(value)   ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
#define	SMC_SETUP_NCS_WR_SETUP_Pos   8
#define	SMC_SETUP_NCS_WR_SETUP_Msk   (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos)
	(SMC_SETUP) NCS Setup Length in WRITE Access
#define	SMC_SETUP_NCS_WR_SETUP(value)   ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
#define	SMC_SETUP_NRD_SETUP_Pos   16
#define	SMC_SETUP_NRD_SETUP_Msk   (0x3fu << SMC_SETUP_NRD_SETUP_Pos)
	(SMC_SETUP) NRD Setup Length
#define	SMC_SETUP_NRD_SETUP(value)   ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
#define	SMC_SETUP_NCS_RD_SETUP_Pos   24
#define	SMC_SETUP_NCS_RD_SETUP_Msk   (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos)
	(SMC_SETUP) NCS Setup Length in READ Access
#define	SMC_SETUP_NCS_RD_SETUP(value)   ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
#define	SMC_PULSE_NWE_PULSE_Pos   0
#define	SMC_PULSE_NWE_PULSE_Msk   (0x7fu << SMC_PULSE_NWE_PULSE_Pos)
	(SMC_PULSE) NWE Pulse Length
#define	SMC_PULSE_NWE_PULSE(value)   ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
#define	SMC_PULSE_NCS_WR_PULSE_Pos   8
#define	SMC_PULSE_NCS_WR_PULSE_Msk   (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos)
	(SMC_PULSE) NCS Pulse Length in WRITE Access
#define	SMC_PULSE_NCS_WR_PULSE(value)   ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
#define	SMC_PULSE_NRD_PULSE_Pos   16
#define	SMC_PULSE_NRD_PULSE_Msk   (0x7fu << SMC_PULSE_NRD_PULSE_Pos)
	(SMC_PULSE) NRD Pulse Length
#define	SMC_PULSE_NRD_PULSE(value)   ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
#define	SMC_PULSE_NCS_RD_PULSE_Pos   24
#define	SMC_PULSE_NCS_RD_PULSE_Msk   (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos)
	(SMC_PULSE) NCS Pulse Length in READ Access
#define	SMC_PULSE_NCS_RD_PULSE(value)   ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
#define	SMC_CYCLE_NWE_CYCLE_Pos   0
#define	SMC_CYCLE_NWE_CYCLE_Msk   (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos)
	(SMC_CYCLE) Total Write Cycle Length
#define	SMC_CYCLE_NWE_CYCLE(value)   ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
#define	SMC_CYCLE_NRD_CYCLE_Pos   16
#define	SMC_CYCLE_NRD_CYCLE_Msk   (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos)
	(SMC_CYCLE) Total Read Cycle Length
#define	SMC_CYCLE_NRD_CYCLE(value)   ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
#define	SMC_MODE_READ_MODE   (0x1u << 0)
	(SMC_MODE) Read Mode
#define	SMC_MODE_WRITE_MODE   (0x1u << 1)
	(SMC_MODE) Write Mode
#define	SMC_MODE_EXNW_MODE_Pos   4
#define	SMC_MODE_EXNW_MODE_Msk   (0x3u << SMC_MODE_EXNW_MODE_Pos)
	(SMC_MODE) NWAIT Mode
#define	SMC_MODE_EXNW_MODE(value)   ((SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos)))
#define	SMC_MODE_EXNW_MODE_DISABLED   (0x0u << 4)
	(SMC_MODE) Disabled
#define	SMC_MODE_EXNW_MODE_FROZEN   (0x2u << 4)
	(SMC_MODE) Frozen Mode
#define	SMC_MODE_EXNW_MODE_READY   (0x3u << 4)
	(SMC_MODE) Ready Mode
#define	SMC_MODE_BAT   (0x1u << 8)
	(SMC_MODE) Byte Access Type
#define	SMC_MODE_BAT_BYTE_SELECT   (0x0u << 8)
	(SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1.
#define	SMC_MODE_BAT_BYTE_WRITE   (0x1u << 8)
	(SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD.
#define	SMC_MODE_DBW   (0x1u << 12)
	(SMC_MODE) Data Bus Width
#define	SMC_MODE_DBW_8_BIT   (0x0u << 12)
	(SMC_MODE) 8-bit Data Bus
#define	SMC_MODE_DBW_16_BIT   (0x1u << 12)
	(SMC_MODE) 16-bit Data Bus
#define	SMC_MODE_TDF_CYCLES_Pos   16
#define	SMC_MODE_TDF_CYCLES_Msk   (0xfu << SMC_MODE_TDF_CYCLES_Pos)
	(SMC_MODE) Data Float Time
#define	SMC_MODE_TDF_CYCLES(value)   ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
#define	SMC_MODE_TDF_MODE   (0x1u << 20)
	(SMC_MODE) TDF Optimization
#define	SMC_MODE_PMEN   (0x1u << 24)
	(SMC_MODE) Page Mode Enabled
#define	SMC_MODE_PS_Pos   28
#define	SMC_MODE_PS_Msk   (0x3u << SMC_MODE_PS_Pos)
	(SMC_MODE) Page Size
#define	SMC_MODE_PS(value)   ((SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos)))
#define	SMC_MODE_PS_4_BYTE   (0x0u << 28)
	(SMC_MODE) 4-byte page
#define	SMC_MODE_PS_8_BYTE   (0x1u << 28)
	(SMC_MODE) 8-byte page
#define	SMC_MODE_PS_16_BYTE   (0x2u << 28)
	(SMC_MODE) 16-byte page
#define	SMC_MODE_PS_32_BYTE   (0x3u << 28)
	(SMC_MODE) 32-byte page
#define	SMC_OCMS_SMSE   (0x1u << 0)
	(SMC_OCMS) Static Memory Controller Scrambling Enable
#define	SMC_KEY1_KEY1_Pos   0
#define	SMC_KEY1_KEY1_Msk   (0xffffffffu << SMC_KEY1_KEY1_Pos)
	(SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1
#define	SMC_KEY1_KEY1(value)   ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
#define	SMC_KEY2_KEY2_Pos   0
#define	SMC_KEY2_KEY2_Msk   (0xffffffffu << SMC_KEY2_KEY2_Pos)
	(SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2
#define	SMC_KEY2_KEY2(value)   ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
#define	SMC_WPMR_WPEN   (0x1u << 0)
	(SMC_WPMR) Write Protect Enable
#define	SMC_WPMR_WPKEY_Pos   8
#define	SMC_WPMR_WPKEY_Msk   (0xffffffu << SMC_WPMR_WPKEY_Pos)
	(SMC_WPMR) Write Protection Key
#define	SMC_WPMR_WPKEY(value)   ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos)))
#define	SMC_WPMR_WPKEY_PASSWD   (0x534D43u << 8)
	(SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
#define	SMC_WPSR_WPVS   (0x1u << 0)
	(SMC_WPSR) Write Protection Violation Status
#define	SMC_WPSR_WPVSRC_Pos   8
#define	SMC_WPSR_WPVSRC_Msk   (0xffffu << SMC_WPSR_WPVSRC_Pos)
	(SMC_WPSR) Write Protection Violation Source

Detailed Description

SOFTWARE API DEFINITION FOR Static Memory Controller