RTEMS  5.1
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greth.h
1 /*
2  * Cobham Gaisler ethernet MAC driver
3  * adapted from Opencores driver by Marko Isomaki
4  *
5  * The license and distribution terms for this file may be
6  * found in found in the file LICENSE in this distribution or at
7  * http://www.rtems.org/license/LICENSE.
8  */
9 
10 #ifndef __GRETH_H__
11 #define __GRETH_H__
12 
13 #ifdef __cplusplus
14 extern "C" {
15 #endif
16 
17 /* Ethernet configuration registers */
18 
19 typedef struct _greth_regs {
20  volatile uint32_t ctrl; /* Ctrl Register */
21  volatile uint32_t status; /* Status Register */
22  volatile uint32_t mac_addr_msb; /* Bit 47-32 of MAC address */
23  volatile uint32_t mac_addr_lsb; /* Bit 31-0 of MAC address */
24  volatile uint32_t mdio_ctrl; /* MDIO control and status */
25  volatile uint32_t txdesc; /* Transmit descriptor pointer */
26  volatile uint32_t rxdesc; /* Receive descriptor pointer */
27  volatile uint32_t edcl; /* EDCL IP register */
28  volatile uint32_t ht_msb; /* Multicast MSB hash */
29  volatile uint32_t ht_lsb; /* Multicast LSB hash */
30 } greth_regs;
31 
32 #define GRETH_TOTAL_BD 128
33 #define GRETH_MAXBUF_LEN 1520
34 
35 /* Tx BD */
36 #define GRETH_TXD_ENABLE 0x0800 /* Tx BD Enable */
37 #define GRETH_TXD_WRAP 0x1000 /* Tx BD Wrap (last BD) */
38 #define GRETH_TXD_IRQ 0x2000 /* Tx BD IRQ Enable */
39 #define GRETH_TXD_MORE 0x20000 /* Tx BD More (more descs for packet) */
40 #define GRETH_TXD_IPCS 0x40000 /* Tx BD insert ip chksum */
41 #define GRETH_TXD_TCPCS 0x80000 /* Tx BD insert tcp chksum */
42 #define GRETH_TXD_UDPCS 0x100000 /* Tx BD insert udp chksum */
43 
44 #define GRETH_TXD_UNDERRUN 0x4000 /* Tx BD Underrun Status */
45 #define GRETH_TXD_RETLIM 0x8000 /* Tx BD Retransmission Limit Status */
46 #define GRETH_TXD_LATECOL 0x10000 /* Tx BD Late Collision */
47 
48 #define GRETH_TXD_STATS (GRETH_TXD_UNDERRUN | \
49  GRETH_TXD_RETLIM | \
50  GRETH_TXD_LATECOL)
51 
52 #define GRETH_TXD_CS (GRETH_TXD_IPCS | \
53  GRETH_TXD_TCPCS | \
54  GRETH_TXD_UDPCS)
55 
56 /* Rx BD */
57 #define GRETH_RXD_ENABLE 0x0800 /* Rx BD Enable */
58 #define GRETH_RXD_WRAP 0x1000 /* Rx BD Wrap (last BD) */
59 #define GRETH_RXD_IRQ 0x2000 /* Rx BD IRQ Enable */
60 
61 #define GRETH_RXD_DRIBBLE 0x4000 /* Rx BD Dribble Nibble Status */
62 #define GRETH_RXD_TOOLONG 0x8000 /* Rx BD Too Long Status */
63 #define GRETH_RXD_CRCERR 0x10000 /* Rx BD CRC Error Status */
64 #define GRETH_RXD_OVERRUN 0x20000 /* Rx BD Overrun Status */
65 #define GRETH_RXD_LENERR 0x40000 /* Rx BD Length Error */
66 #define GRETH_RXD_ID 0x40000 /* Rx BD IP Detected */
67 #define GRETH_RXD_IR 0x40000 /* Rx BD IP Chksum Error */
68 #define GRETH_RXD_UD 0x40000 /* Rx BD UDP Detected*/
69 #define GRETH_RXD_UR 0x40000 /* Rx BD UDP Chksum Error */
70 #define GRETH_RXD_TD 0x40000 /* Rx BD TCP Detected */
71 #define GRETH_RXD_TR 0x40000 /* Rx BD TCP Chksum Error */
72 
73 
74 #define GRETH_RXD_STATS (GRETH_RXD_OVERRUN | \
75  GRETH_RXD_DRIBBLE | \
76  GRETH_RXD_TOOLONG | \
77  GRETH_RXD_CRCERR)
78 
79 /* CTRL Register */
80 #define GRETH_CTRL_TXEN 0x00000001 /* Transmit Enable */
81 #define GRETH_CTRL_RXEN 0x00000002 /* Receive Enable */
82 #define GRETH_CTRL_TXIRQ 0x00000004 /* Transmit Enable */
83 #define GRETH_CTRL_RXIRQ 0x00000008 /* Receive Enable */
84 #define GRETH_CTRL_FULLD 0x00000010 /* Full Duplex */
85 #define GRETH_CTRL_PRO 0x00000020 /* Promiscuous (receive all) */
86 #define GRETH_CTRL_RST 0x00000040 /* Reset MAC */
87 #define GRETH_CTRL_SP 0x00000080 /* 100MBit speed mode */
88 #define GRETH_CTRL_GB 0x00000100 /* 1GBit speed mode */
89 #define GRETH_CTRL_MCE 0x00000800 /* Multicast Enable */
90 #define GRETH_CTRL_DD 0x00001000 /* Disable EDCL Duplex Detection */
91 #define GRETH_CTRL_ED 0x00004000 /* EDCL Disable */
92 #define GRETH_CTRL_MC 0x02000000 /* Multicast available */
93 #define GRETH_CTRL_ME 0x04000000 /* MDIO interrupts enabled */
94 #define GRETH_CTRL_GA 0x08000000 /* Gigabit MAC available */
95 
96 /* Status Register */
97 #define GRETH_STATUS_RXERR 0x00000001 /* Receive Error */
98 #define GRETH_STATUS_TXERR 0x00000002 /* Transmit Error IRQ */
99 #define GRETH_STATUS_RXIRQ 0x00000004 /* Receive Frame IRQ */
100 #define GRETH_STATUS_TXIRQ 0x00000008 /* Transmit Error IRQ */
101 #define GRETH_STATUS_RXAHBERR 0x00000010 /* Receiver AHB Error */
102 #define GRETH_STATUS_TXAHBERR 0x00000020 /* Transmitter AHB Error */
103 
104 /* MDIO Control */
105 #define GRETH_MDIO_WRITE 0x00000001 /* MDIO Write */
106 #define GRETH_MDIO_READ 0x00000002 /* MDIO Read */
107 #define GRETH_MDIO_LINKFAIL 0x00000004 /* MDIO Link failed */
108 #define GRETH_MDIO_BUSY 0x00000008 /* MDIO Link Busy */
109 #define GRETH_MDIO_REGADR 0x000007C0 /* Register Address */
110 #define GRETH_MDIO_PHYADR 0x0000F800 /* PHY address */
111 #define GRETH_MDIO_DATA 0xFFFF0000 /* MDIO DATA */
112 
113 
114 /* MII registers */
115 #define GRETH_MII_EXTADV_1000FD 0x00000200
116 #define GRETH_MII_EXTADV_1000HD 0x00000100
117 #define GRETH_MII_EXTPRT_1000FD 0x00000800
118 #define GRETH_MII_EXTPRT_1000HD 0x00000400
119 
120 #define GRETH_MII_100T4 0x00000200
121 #define GRETH_MII_100TXFD 0x00000100
122 #define GRETH_MII_100TXHD 0x00000080
123 #define GRETH_MII_10FD 0x00000040
124 #define GRETH_MII_10HD 0x00000020
125 
126 
127 /* Attach routine */
128 
129 void greth_register_drv(void);
130 
131 /* PHY data */
133 {
134  int vendor;
135  int device;
136  int rev;
137 
138  int adv;
139  int part;
140 
141  int extadv;
142  int extpart;
143 };
144 
145 /* Limit speed modes advertised during auto-negotiation */
146 #define GRETH_ADV_10_HD 0x0001
147 #define GRETH_ADV_10_FD 0x0002
148 #define GRETH_ADV_100_HD 0x0004
149 #define GRETH_ADV_100_FD 0x0008
150 #define GRETH_ADV_1000_HD 0x0010
151 #define GRETH_ADV_1000_FD 0x0020
152 #define GRETH_ADV_ALL 0x003f
153 /*
154 #ifdef CPU_U32_FIX
155 void ipalign(struct mbuf *m);
156 #endif
157 
158 */
159 #ifdef __cplusplus
160 }
161 #endif
162 
163 #endif
164 
Definition: greth.h:132
Definition: rtemscompat1.h:15
Definition: greth.h:19