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#define | BSP_INTERRUPT_VECTOR_MIN 0 |
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#define | AU1X00_IRQ_SW0 (MIPS_INTERRUPT_BASE + 0) |
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#define | AU1X00_IRQ_SW1 (MIPS_INTERRUPT_BASE + 1) |
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#define | AU1X00_IRQ_IC0_REQ0 (MIPS_INTERRUPT_BASE + 2) |
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#define | AU1X00_IRQ_IC0_REQ1 (MIPS_INTERRUPT_BASE + 3) |
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#define | AU1X00_IRQ_IC1_REQ0 (MIPS_INTERRUPT_BASE + 4) |
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#define | AU1X00_IRQ_IC1_REQ1 (MIPS_INTERRUPT_BASE + 5) |
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#define | AU1X00_IRQ_PERF (MIPS_INTERRUPT_BASE + 6) |
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#define | AU1X00_IRQ_CNT (MIPS_INTERRUPT_BASE + 7) |
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#define | AU1X00_IRQ_IC0_BASE (MIPS_INTERRUPT_BASE + 8) |
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#define | AU1X00_IRQ_UART0 (MIPS_INTERRUPT_BASE + 8) |
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#define | AU1X00_IRQ_INTA (MIPS_INTERRUPT_BASE + 9) |
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#define | AU1X00_IRQ_INTB (MIPS_INTERRUPT_BASE + 10) |
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#define | AU1X00_IRQ_UART3 (MIPS_INTERRUPT_BASE + 11) |
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#define | AU1X00_IRQ_INTC (MIPS_INTERRUPT_BASE + 12) |
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#define | AU1X00_IRQ_INTD (MIPS_INTERRUPT_BASE + 13) |
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#define | AU1X00_IRQ_DMA0 (MIPS_INTERRUPT_BASE + 14) |
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#define | AU1X00_IRQ_DMA1 (MIPS_INTERRUPT_BASE + 15) |
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#define | AU1X00_IRQ_DMA2 (MIPS_INTERRUPT_BASE + 16) |
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#define | AU1X00_IRQ_DMA3 (MIPS_INTERRUPT_BASE + 17) |
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#define | AU1X00_IRQ_DMA4 (MIPS_INTERRUPT_BASE + 18) |
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#define | AU1X00_IRQ_DMA5 (MIPS_INTERRUPT_BASE + 19) |
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#define | AU1X00_IRQ_DMA6 (MIPS_INTERRUPT_BASE + 20) |
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#define | AU1X00_IRQ_DMA7 (MIPS_INTERRUPT_BASE + 21) |
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#define | AU1X00_IRQ_TOY_TICK (MIPS_INTERRUPT_BASE + 22) |
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#define | AU1X00_IRQ_TOY_MATCH0 (MIPS_INTERRUPT_BASE + 23) |
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#define | AU1X00_IRQ_TOY_MATCH1 (MIPS_INTERRUPT_BASE + 24) |
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#define | AU1X00_IRQ_TOY_MATCH2 (MIPS_INTERRUPT_BASE + 25) |
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#define | AU1X00_IRQ_RTC_TICK (MIPS_INTERRUPT_BASE + 26) |
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#define | AU1X00_IRQ_RTC_MATCH0 (MIPS_INTERRUPT_BASE + 27) |
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#define | AU1X00_IRQ_RTC_MATCH1 (MIPS_INTERRUPT_BASE + 28) |
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#define | AU1X00_IRQ_RTC_MATCH2 (MIPS_INTERRUPT_BASE + 29) |
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#define | AU1X00_IRQ_PCI_ERR (MIPS_INTERRUPT_BASE + 30) |
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#define | AU1X00_IRQ_RSV0 (MIPS_INTERRUPT_BASE + 31) |
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#define | AU1X00_IRQ_USB_DEV (MIPS_INTERRUPT_BASE + 32) |
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#define | AU1X00_IRQ_USB_SUSPEND (MIPS_INTERRUPT_BASE + 33) |
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#define | AU1X00_IRQ_USB_HOST (MIPS_INTERRUPT_BASE + 34) |
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#define | AU1X00_IRQ_AC97_ACSYNC (MIPS_INTERRUPT_BASE + 35) |
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#define | AU1X00_IRQ_MAC0 (MIPS_INTERRUPT_BASE + 36) |
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#define | AU1X00_IRQ_MAC1 (MIPS_INTERRUPT_BASE + 37) |
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#define | AU1X00_IRQ_RSV1 (MIPS_INTERRUPT_BASE + 38) |
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#define | AU1X00_IRQ_AC97_CMD (MIPS_INTERRUPT_BASE + 39) |
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#define | AU1X00_IRQ_IC1_BASE (MIPS_INTERRUPT_BASE + 40) |
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#define | AU1X00_IRQ_GPIO0 (MIPS_INTERRUPT_BASE + 40) |
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#define | AU1X00_IRQ_GPIO1 (MIPS_INTERRUPT_BASE + 41) |
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#define | AU1X00_IRQ_GPIO2 (MIPS_INTERRUPT_BASE + 42) |
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#define | AU1X00_IRQ_GPIO3 (MIPS_INTERRUPT_BASE + 43) |
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#define | AU1X00_IRQ_GPIO4 (MIPS_INTERRUPT_BASE + 44) |
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#define | AU1X00_IRQ_GPIO5 (MIPS_INTERRUPT_BASE + 45) |
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#define | AU1X00_IRQ_GPIO6 (MIPS_INTERRUPT_BASE + 46) |
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#define | AU1X00_IRQ_GPIO7 (MIPS_INTERRUPT_BASE + 47) |
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#define | AU1X00_IRQ_GPIO8 (MIPS_INTERRUPT_BASE + 48) |
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#define | AU1X00_IRQ_GPIO9 (MIPS_INTERRUPT_BASE + 49) |
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#define | AU1X00_IRQ_GPIO10 (MIPS_INTERRUPT_BASE + 50) |
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#define | AU1X00_IRQ_GPIO11 (MIPS_INTERRUPT_BASE + 51) |
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#define | AU1X00_IRQ_GPIO12 (MIPS_INTERRUPT_BASE + 52) |
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#define | AU1X00_IRQ_GPIO13 (MIPS_INTERRUPT_BASE + 53) |
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#define | AU1X00_IRQ_GPIO14 (MIPS_INTERRUPT_BASE + 54) |
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#define | AU1X00_IRQ_GPIO15 (MIPS_INTERRUPT_BASE + 55) |
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#define | AU1X00_IRQ_GPIO200 (MIPS_INTERRUPT_BASE + 56) |
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#define | AU1X00_IRQ_GPIO201 (MIPS_INTERRUPT_BASE + 57) |
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#define | AU1X00_IRQ_GPIO202 (MIPS_INTERRUPT_BASE + 58) |
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#define | AU1X00_IRQ_GPIO203 (MIPS_INTERRUPT_BASE + 59) |
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#define | AU1X00_IRQ_GPIO20 (MIPS_INTERRUPT_BASE + 60) |
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#define | AU1X00_IRQ_GPIO204 (MIPS_INTERRUPT_BASE + 61) |
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#define | AU1X00_IRQ_GPIO205 (MIPS_INTERRUPT_BASE + 62) |
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#define | AU1X00_IRQ_GPIO23 (MIPS_INTERRUPT_BASE + 63) |
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#define | AU1X00_IRQ_GPIO24 (MIPS_INTERRUPT_BASE + 64) |
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#define | AU1X00_IRQ_GPIO25 (MIPS_INTERRUPT_BASE + 65) |
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#define | AU1X00_IRQ_GPIO26 (MIPS_INTERRUPT_BASE + 66) |
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#define | AU1X00_IRQ_GPIO27 (MIPS_INTERRUPT_BASE + 67) |
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#define | AU1X00_IRQ_GPIO28 (MIPS_INTERRUPT_BASE + 68) |
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#define | AU1X00_IRQ_GPIO206 (MIPS_INTERRUPT_BASE + 69) |
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#define | AU1X00_IRQ_GPIO207 (MIPS_INTERRUPT_BASE + 70) |
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#define | AU1X00_IRQ_GPIO208_215 (MIPS_INTERRUPT_BASE + 71) |
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#define | AU1X00_MAXIMUM_VECTORS (MIPS_INTERRUPT_BASE + 72) |
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#define | BSP_INTERRUPT_VECTOR_MAX AU1X00_MAXIMUM_VECTORS |
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1.8.15