alt_interrupt_common.h File Reference

#include "hwlib.h"
#include <stdbool.h>
#include <stddef.h>

Go to the source code of this file.

Macros
#define	ALT_INT_ICCIAR_CPUID_GET(icciar)   ((icciar >> 10) & 0x7)
#define	ALT_INT_ICCIAR_ACKINTID_GET(icciar)   (icciar & 0x3FF)

Typedefs
typedef enum ALT_INT_INTERRUPT_e	ALT_INT_INTERRUPT_t
typedef uint32_t	alt_int_cpu_target_t
typedef enum ALT_INT_TRIGGER_e	ALT_INT_TRIGGER_t
typedef enum ALT_INT_SGI_TARGET_e	ALT_INT_SGI_TARGET_t
typedef void(*	alt_int_callback_t) (uint32_t icciar, void *context)

Enumerations
enum	ALT_INT_INTERRUPT_e {   ALT_INT_INTERRUPT_SGI0 = 0, ALT_INT_INTERRUPT_SGI1 = 1, ALT_INT_INTERRUPT_SGI2 = 2, ALT_INT_INTERRUPT_SGI3 = 3,   ALT_INT_INTERRUPT_SGI4 = 4, ALT_INT_INTERRUPT_SGI5 = 5, ALT_INT_INTERRUPT_SGI6 = 6, ALT_INT_INTERRUPT_SGI7 = 7,   ALT_INT_INTERRUPT_SGI8 = 8, ALT_INT_INTERRUPT_SGI9 = 9, ALT_INT_INTERRUPT_SGI10 = 10, ALT_INT_INTERRUPT_SGI11 = 11,   ALT_INT_INTERRUPT_SGI12 = 12, ALT_INT_INTERRUPT_SGI13 = 13, ALT_INT_INTERRUPT_SGI14 = 14, ALT_INT_INTERRUPT_SGI15 = 15,   ALT_INT_INTERRUPT_PPI_TIMER_GLOBAL = 27, ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE = 29, ALT_INT_INTERRUPT_PPI_TIMER_WATCHDOG = 30, ALT_INT_INTERRUPT_CPU0_PARITYFAIL = 32,   ALT_INT_INTERRUPT_CPU0_PARITYFAIL_BTAC = 33, ALT_INT_INTERRUPT_CPU0_PARITYFAIL_GHB = 34, ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_TAG = 35, ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_DATA = 36,   ALT_INT_INTERRUPT_CPU0_PARITYFAIL_TLB = 37, ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_OUTER = 38, ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_TAG = 39, ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_DATA = 40,   ALT_INT_INTERRUPT_CPU0_DEFLAGS0 = 41, ALT_INT_INTERRUPT_CPU0_DEFLAGS1 = 42, ALT_INT_INTERRUPT_CPU0_DEFLAGS2 = 43, ALT_INT_INTERRUPT_CPU0_DEFLAGS3 = 44,   ALT_INT_INTERRUPT_CPU0_DEFLAGS4 = 45, ALT_INT_INTERRUPT_CPU0_DEFLAGS5 = 46, ALT_INT_INTERRUPT_CPU0_DEFLAGS6 = 47, ALT_INT_INTERRUPT_CPU1_PARITYFAIL = 48,   ALT_INT_INTERRUPT_CPU1_PARITYFAIL_BTAC = 49, ALT_INT_INTERRUPT_CPU1_PARITYFAIL_GHB = 50, ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_TAG = 51, ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_DATA = 52,   ALT_INT_INTERRUPT_CPU1_PARITYFAIL_TLB = 53, ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_OUTER = 54, ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_TAG = 55, ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_DATA = 56,   ALT_INT_INTERRUPT_CPU1_DEFLAGS0 = 57, ALT_INT_INTERRUPT_CPU1_DEFLAGS1 = 58, ALT_INT_INTERRUPT_CPU1_DEFLAGS2 = 59, ALT_INT_INTERRUPT_CPU1_DEFLAGS3 = 60,   ALT_INT_INTERRUPT_CPU1_DEFLAGS4 = 61, ALT_INT_INTERRUPT_CPU1_DEFLAGS5 = 62, ALT_INT_INTERRUPT_CPU1_DEFLAGS6 = 63, ALT_INT_INTERRUPT_SCU_PARITYFAIL0 = 64,   ALT_INT_INTERRUPT_SCU_PARITYFAIL1 = 65, ALT_INT_INTERRUPT_SCU_EV_ABORT = 66, ALT_INT_INTERRUPT_L2_ECC_BYTE_WR_IRQ = 67, ALT_INT_INTERRUPT_L2_ECC_CORRECTED_IRQ = 68,   ALT_INT_INTERRUPT_L2_ECC_UNCORRECTED_IRQ = 69, ALT_INT_INTERRUPT_L2_COMBINED_IRQ = 70, ALT_INT_INTERRUPT_DDR_ECC_ERROR_IRQ = 71, ALT_INT_INTERRUPT_F2S_FPGA_IRQ0 = 72,   ALT_INT_INTERRUPT_F2S_FPGA_IRQ1 = 73, ALT_INT_INTERRUPT_F2S_FPGA_IRQ2 = 74, ALT_INT_INTERRUPT_F2S_FPGA_IRQ3 = 75, ALT_INT_INTERRUPT_F2S_FPGA_IRQ4 = 76,   ALT_INT_INTERRUPT_F2S_FPGA_IRQ5 = 77, ALT_INT_INTERRUPT_F2S_FPGA_IRQ6 = 78, ALT_INT_INTERRUPT_F2S_FPGA_IRQ7 = 79, ALT_INT_INTERRUPT_F2S_FPGA_IRQ8 = 80,   ALT_INT_INTERRUPT_F2S_FPGA_IRQ9 = 81, ALT_INT_INTERRUPT_F2S_FPGA_IRQ10 = 82, ALT_INT_INTERRUPT_F2S_FPGA_IRQ11 = 83, ALT_INT_INTERRUPT_F2S_FPGA_IRQ12 = 84,   ALT_INT_INTERRUPT_F2S_FPGA_IRQ13 = 85, ALT_INT_INTERRUPT_F2S_FPGA_IRQ14 = 86, ALT_INT_INTERRUPT_F2S_FPGA_IRQ15 = 87, ALT_INT_INTERRUPT_F2S_FPGA_IRQ16 = 88,   ALT_INT_INTERRUPT_F2S_FPGA_IRQ17 = 89, ALT_INT_INTERRUPT_F2S_FPGA_IRQ18 = 90, ALT_INT_INTERRUPT_F2S_FPGA_IRQ19 = 91, ALT_INT_INTERRUPT_F2S_FPGA_IRQ20 = 92,   ALT_INT_INTERRUPT_F2S_FPGA_IRQ21 = 93, ALT_INT_INTERRUPT_F2S_FPGA_IRQ22 = 94, ALT_INT_INTERRUPT_F2S_FPGA_IRQ23 = 95, ALT_INT_INTERRUPT_F2S_FPGA_IRQ24 = 96,   ALT_INT_INTERRUPT_F2S_FPGA_IRQ25 = 97, ALT_INT_INTERRUPT_F2S_FPGA_IRQ26 = 98, ALT_INT_INTERRUPT_F2S_FPGA_IRQ27 = 99, ALT_INT_INTERRUPT_F2S_FPGA_IRQ28 = 100,   ALT_INT_INTERRUPT_F2S_FPGA_IRQ29 = 101, ALT_INT_INTERRUPT_F2S_FPGA_IRQ30 = 102, ALT_INT_INTERRUPT_F2S_FPGA_IRQ31 = 103, ALT_INT_INTERRUPT_F2S_FPGA_IRQ32 = 104,   ALT_INT_INTERRUPT_F2S_FPGA_IRQ33 = 105, ALT_INT_INTERRUPT_F2S_FPGA_IRQ34 = 106, ALT_INT_INTERRUPT_F2S_FPGA_IRQ35 = 107, ALT_INT_INTERRUPT_F2S_FPGA_IRQ36 = 108,   ALT_INT_INTERRUPT_F2S_FPGA_IRQ37 = 109, ALT_INT_INTERRUPT_F2S_FPGA_IRQ38 = 110, ALT_INT_INTERRUPT_F2S_FPGA_IRQ39 = 111, ALT_INT_INTERRUPT_F2S_FPGA_IRQ40 = 112,   ALT_INT_INTERRUPT_F2S_FPGA_IRQ41 = 113, ALT_INT_INTERRUPT_F2S_FPGA_IRQ42 = 114, ALT_INT_INTERRUPT_F2S_FPGA_IRQ43 = 115, ALT_INT_INTERRUPT_F2S_FPGA_IRQ44 = 116,   ALT_INT_INTERRUPT_F2S_FPGA_IRQ45 = 117, ALT_INT_INTERRUPT_F2S_FPGA_IRQ46 = 118, ALT_INT_INTERRUPT_F2S_FPGA_IRQ47 = 119, ALT_INT_INTERRUPT_F2S_FPGA_IRQ48 = 120,   ALT_INT_INTERRUPT_F2S_FPGA_IRQ49 = 121, ALT_INT_INTERRUPT_F2S_FPGA_IRQ50 = 122, ALT_INT_INTERRUPT_F2S_FPGA_IRQ51 = 123, ALT_INT_INTERRUPT_F2S_FPGA_IRQ52 = 124,   ALT_INT_INTERRUPT_F2S_FPGA_IRQ53 = 125, ALT_INT_INTERRUPT_F2S_FPGA_IRQ54 = 126, ALT_INT_INTERRUPT_F2S_FPGA_IRQ55 = 127, ALT_INT_INTERRUPT_F2S_FPGA_IRQ56 = 128,   ALT_INT_INTERRUPT_F2S_FPGA_IRQ57 = 129, ALT_INT_INTERRUPT_F2S_FPGA_IRQ58 = 130, ALT_INT_INTERRUPT_F2S_FPGA_IRQ59 = 131, ALT_INT_INTERRUPT_F2S_FPGA_IRQ60 = 132,   ALT_INT_INTERRUPT_F2S_FPGA_IRQ61 = 133, ALT_INT_INTERRUPT_F2S_FPGA_IRQ62 = 134, ALT_INT_INTERRUPT_F2S_FPGA_IRQ63 = 135, ALT_INT_INTERRUPT_DMA_IRQ0 = 136,   ALT_INT_INTERRUPT_DMA_IRQ1 = 137, ALT_INT_INTERRUPT_DMA_IRQ2 = 138, ALT_INT_INTERRUPT_DMA_IRQ3 = 139, ALT_INT_INTERRUPT_DMA_IRQ4 = 140,   ALT_INT_INTERRUPT_DMA_IRQ5 = 141, ALT_INT_INTERRUPT_DMA_IRQ6 = 142, ALT_INT_INTERRUPT_DMA_IRQ7 = 143, ALT_INT_INTERRUPT_DMA_IRQ_ABORT = 144,   ALT_INT_INTERRUPT_DMA_ECC_CORRECTED_IRQ = 145, ALT_INT_INTERRUPT_DMA_ECC_UNCORRECTED_IRQ = 146, ALT_INT_INTERRUPT_EMAC0_IRQ = 147, ALT_INT_INTERRUPT_EMAC0_TX_ECC_CORRECTED_IRQ = 148,   ALT_INT_INTERRUPT_EMAC0_TX_ECC_UNCORRECTED_IRQ = 149, ALT_INT_INTERRUPT_EMAC0_RX_ECC_CORRECTED_IRQ = 150, ALT_INT_INTERRUPT_EMAC0_RX_ECC_UNCORRECTED_IRQ = 151, ALT_INT_INTERRUPT_EMAC1_IRQ = 152,   ALT_INT_INTERRUPT_EMAC1_TX_ECC_CORRECTED_IRQ = 153, ALT_INT_INTERRUPT_EMAC1_TX_ECC_UNCORRECTED_IRQ = 154, ALT_INT_INTERRUPT_EMAC1_RX_ECC_CORRECTED_IRQ = 155, ALT_INT_INTERRUPT_EMAC1_RX_ECC_UNCORRECTED_IRQ = 156,   ALT_INT_INTERRUPT_USB0_IRQ = 157, ALT_INT_INTERRUPT_USB0_ECC_CORRECTED = 158, ALT_INT_INTERRUPT_USB0_ECC_UNCORRECTED = 159, ALT_INT_INTERRUPT_USB1_IRQ = 160,   ALT_INT_INTERRUPT_USB1_ECC_CORRECTED = 161, ALT_INT_INTERRUPT_USB1_ECC_UNCORRECTED = 162, ALT_INT_INTERRUPT_CAN0_STS_IRQ = 163, ALT_INT_INTERRUPT_CAN0_MO_IRQ = 164,   ALT_INT_INTERRUPT_CAN0_ECC_CORRECTED_IRQ = 165, ALT_INT_INTERRUPT_CAN0_ECC_UNCORRECTED_IRQ = 166, ALT_INT_INTERRUPT_CAN1_STS_IRQ = 167, ALT_INT_INTERRUPT_CAN1_MO_IRQ = 168,   ALT_INT_INTERRUPT_CAN1_ECC_CORRECTED_IRQ = 169, ALT_INT_INTERRUPT_CAN1_ECC_UNCORRECTED_IRQ = 170, ALT_INT_INTERRUPT_SDMMC_IRQ = 171, ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_CORRECTED = 172,   ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_UNCORRECTED = 173, ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_CORRECTED = 174, ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_UNCORRECTED = 175, ALT_INT_INTERRUPT_NAND_IRQ = 176,   ALT_INT_INTERRUPT_NANDR_ECC_CORRECTED_IRQ = 177, ALT_INT_INTERRUPT_NANDR_ECC_UNCORRECTED_IRQ = 178, ALT_INT_INTERRUPT_NANDW_ECC_CORRECTED_IRQ = 179, ALT_INT_INTERRUPT_NANDW_ECC_UNCORRECTED_IRQ = 180,   ALT_INT_INTERRUPT_NANDE_ECC_CORRECTED_IRQ = 181, ALT_INT_INTERRUPT_NANDE_ECC_UNCORRECTED_IRQ = 182, ALT_INT_INTERRUPT_QSPI_IRQ = 183, ALT_INT_INTERRUPT_QSPI_ECC_CORRECTED_IRQ = 184,   ALT_INT_INTERRUPT_QSPI_ECC_UNCORRECTED_IRQ = 185, ALT_INT_INTERRUPT_SPI0_IRQ = 186, ALT_INT_INTERRUPT_SPI1_IRQ = 187, ALT_INT_INTERRUPT_SPI2_IRQ = 188,   ALT_INT_INTERRUPT_SPI3_IRQ = 189, ALT_INT_INTERRUPT_I2C0_IRQ = 190, ALT_INT_INTERRUPT_I2C1_IRQ = 191, ALT_INT_INTERRUPT_I2C2_IRQ = 192,   ALT_INT_INTERRUPT_I2C3_IRQ = 193, ALT_INT_INTERRUPT_UART0 = 194, ALT_INT_INTERRUPT_UART1 = 195, ALT_INT_INTERRUPT_GPIO0 = 196,   ALT_INT_INTERRUPT_GPIO1 = 197, ALT_INT_INTERRUPT_GPIO2 = 198, ALT_INT_INTERRUPT_TIMER_L4SP_0_IRQ = 199, ALT_INT_INTERRUPT_TIMER_L4SP_1_IRQ = 200,   ALT_INT_INTERRUPT_TIMER_OSC1_0_IRQ = 201, ALT_INT_INTERRUPT_TIMER_OSC1_1_IRQ = 202, ALT_INT_INTERRUPT_WDOG0_IRQ = 203, ALT_INT_INTERRUPT_WDOG1_IRQ = 204,   ALT_INT_INTERRUPT_CLKMGR_IRQ = 205, ALT_INT_INTERRUPT_MPUWAKEUP_IRQ = 206, ALT_INT_INTERRUPT_FPGA_MAN_IRQ = 207, ALT_INT_INTERRUPT_NCTIIRQ0 = 208,   ALT_INT_INTERRUPT_NCTIIRQ1 = 209, ALT_INT_INTERRUPT_RAM_ECC_CORRECTED_IRQ = 210, ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ = 211 }
enum	ALT_INT_TRIGGER_e {   ALT_INT_TRIGGER_EDGE, ALT_INT_TRIGGER_LEVEL, ALT_INT_TRIGGER_SOFTWARE, ALT_INT_TRIGGER_AUTODETECT,   ALT_INT_TRIGGER_NA }
enum	ALT_INT_SGI_TARGET_e { ALT_INT_SGI_TARGET_LIST, ALT_INT_SGI_TARGET_ALL_EXCL_SENDER, ALT_INT_SGI_TARGET_SENDER_ONLY }