16 #ifndef _RTEMS_SCORE_CPUIMPL_H 17 #define _RTEMS_SCORE_CPUIMPL_H 32 #define SPARC_MINIMUM_STACK_FRAME_SIZE 0x60 39 #define ISF_PSR_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x00 41 #define ISF_PC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x04 43 #define ISF_NPC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x08 45 #define ISF_G1_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x0c 47 #define ISF_G2_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x10 49 #define ISF_G3_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x14 51 #define ISF_G4_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x18 53 #define ISF_G5_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x1c 55 #define ISF_G7_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x24 57 #define ISF_I0_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x28 59 #define ISF_I1_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x2c 61 #define ISF_I2_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x30 63 #define ISF_I3_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x34 65 #define ISF_I4_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x38 67 #define ISF_I5_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x3c 69 #define ISF_I6_FP_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x40 71 #define ISF_I7_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x44 73 #define ISF_Y_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x48 75 #define ISF_TPC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x4c 78 #define CPU_INTERRUPT_FRAME_SIZE SPARC_MINIMUM_STACK_FRAME_SIZE + 0x50 80 #define SPARC_FP_CONTEXT_OFFSET_F0_F1 0 81 #define SPARC_FP_CONTEXT_OFFSET_F2_F3 8 82 #define SPARC_FP_CONTEXT_OFFSET_F4_F5 16 83 #define SPARC_FP_CONTEXT_OFFSET_F6_F7 24 84 #define SPARC_FP_CONTEXT_OFFSET_F8_F9 32 85 #define SPARC_FP_CONTEXT_OFFSET_F10_F11 40 86 #define SPARC_FP_CONTEXT_OFFSET_F12_F13 48 87 #define SPARC_FP_CONTEXT_OFFSET_F14_F15 56 88 #define SPARC_FP_CONTEXT_OFFSET_F16_F17 64 89 #define SPARC_FP_CONTEXT_OFFSET_F18_F19 72 90 #define SPARC_FP_CONTEXT_OFFSET_F20_F21 80 91 #define SPARC_FP_CONTEXT_OFFSET_F22_F23 88 92 #define SPARC_FP_CONTEXT_OFFSET_F24_F25 96 93 #define SPARC_FP_CONTEXT_OFFSET_F26_F27 104 94 #define SPARC_FP_CONTEXT_OFFSET_F28_F29 112 95 #define SPARC_FP_CONTEXT_OFFSET_F30_F31 120 96 #define SPARC_FP_CONTEXT_OFFSET_FSR 128 98 #if ( SPARC_HAS_FPU == 1 ) 99 #define CPU_PER_CPU_CONTROL_SIZE 8 101 #define CPU_PER_CPU_CONTROL_SIZE 0 104 #if ( SPARC_HAS_FPU == 1 ) 109 #define SPARC_PER_CPU_FSR_OFFSET 0 111 #if defined(SPARC_USE_LAZY_FP_SWITCH) 116 #define SPARC_PER_CPU_FP_OWNER_OFFSET 4 127 #if ( SPARC_HAS_FPU == 1 ) 137 #if defined(SPARC_USE_LAZY_FP_SWITCH) 144 uint32_t reserved_for_alignment_of_interrupt_frame;
155 #define _CPU_Get_current_per_CPU_control() _SPARC_Per_CPU_current 157 #define _CPU_Get_thread_executing() ( _SPARC_Per_CPU_current->executing ) 159 void _CPU_Context_volatile_clobber( uintptr_t pattern );
161 void _CPU_Context_validate( uintptr_t pattern );
165 __asm__
volatile (
"unimp 0" );
170 __asm__
volatile (
"nop" );
register struct Per_CPU_Control * _SPARC_Per_CPU_current
The pointer to the current per-CPU control is available via register g6.
SPARC CPU Department Source.
#define RTEMS_INLINE_ROUTINE
Gives a hint to the compiler in a function declaration to inline this function.