RTEMS
cpuimpl.h
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1 
7 /*
8  * Copyright (c) 1989, 2007 On-Line Applications Research Corporation (OAR)
9  * Copyright (c) 2013, 2016 embedded brains GmbH
10  *
11  * The license and distribution terms for this file may be
12  * found in the file LICENSE in this distribution or at
13  * http://www.rtems.org/license/LICENSE.
14  */
15 
16 #ifndef _RTEMS_SCORE_CPUIMPL_H
17 #define _RTEMS_SCORE_CPUIMPL_H
18 
19 #include <rtems/score/cpu.h>
20 
32 #define SPARC_MINIMUM_STACK_FRAME_SIZE 0x60
33 
34 /*
35  * Offsets of fields with CPU_Interrupt_frame for assembly routines.
36  */
37 
39 #define ISF_PSR_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x00
40 
41 #define ISF_PC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x04
42 
43 #define ISF_NPC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x08
44 
45 #define ISF_G1_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x0c
46 
47 #define ISF_G2_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x10
48 
49 #define ISF_G3_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x14
50 
51 #define ISF_G4_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x18
52 
53 #define ISF_G5_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x1c
54 
55 #define ISF_G7_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x24
56 
57 #define ISF_I0_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x28
58 
59 #define ISF_I1_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x2c
60 
61 #define ISF_I2_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x30
62 
63 #define ISF_I3_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x34
64 
65 #define ISF_I4_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x38
66 
67 #define ISF_I5_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x3c
68 
69 #define ISF_I6_FP_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x40
70 
71 #define ISF_I7_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x44
72 
73 #define ISF_Y_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x48
74 
75 #define ISF_TPC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x4c
76 
78 #define CPU_INTERRUPT_FRAME_SIZE SPARC_MINIMUM_STACK_FRAME_SIZE + 0x50
79 
80 #define SPARC_FP_CONTEXT_OFFSET_F0_F1 0
81 #define SPARC_FP_CONTEXT_OFFSET_F2_F3 8
82 #define SPARC_FP_CONTEXT_OFFSET_F4_F5 16
83 #define SPARC_FP_CONTEXT_OFFSET_F6_F7 24
84 #define SPARC_FP_CONTEXT_OFFSET_F8_F9 32
85 #define SPARC_FP_CONTEXT_OFFSET_F10_F11 40
86 #define SPARC_FP_CONTEXT_OFFSET_F12_F13 48
87 #define SPARC_FP_CONTEXT_OFFSET_F14_F15 56
88 #define SPARC_FP_CONTEXT_OFFSET_F16_F17 64
89 #define SPARC_FP_CONTEXT_OFFSET_F18_F19 72
90 #define SPARC_FP_CONTEXT_OFFSET_F20_F21 80
91 #define SPARC_FP_CONTEXT_OFFSET_F22_F23 88
92 #define SPARC_FP_CONTEXT_OFFSET_F24_F25 96
93 #define SPARC_FP_CONTEXT_OFFSET_F26_F27 104
94 #define SPARC_FP_CONTEXT_OFFSET_F28_F29 112
95 #define SPARC_FP_CONTEXT_OFFSET_F30_F31 120
96 #define SPARC_FP_CONTEXT_OFFSET_FSR 128
97 
98 #if ( SPARC_HAS_FPU == 1 )
99  #define CPU_PER_CPU_CONTROL_SIZE 8
100 #else
101  #define CPU_PER_CPU_CONTROL_SIZE 0
102 #endif
103 
104 #if ( SPARC_HAS_FPU == 1 )
105 
109  #define SPARC_PER_CPU_FSR_OFFSET 0
110 
111  #if defined(SPARC_USE_LAZY_FP_SWITCH)
112 
116  #define SPARC_PER_CPU_FP_OWNER_OFFSET 4
117  #endif
118 #endif
119 
120 #ifndef ASM
121 
122 #ifdef __cplusplus
123 extern "C" {
124 #endif
125 
126 typedef struct {
127 #if ( SPARC_HAS_FPU == 1 )
128 
135  uint32_t fsr;
136 
137 #if defined(SPARC_USE_LAZY_FP_SWITCH)
138 
141  struct _Thread_Control *fp_owner;
142 #else
143  /* See Per_CPU_Control::Interrupt_frame */
144  uint32_t reserved_for_alignment_of_interrupt_frame;
145 #endif
146 #endif
148 
153 register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__( "g6" );
154 
155 #define _CPU_Get_current_per_CPU_control() _SPARC_Per_CPU_current
156 
157 #define _CPU_Get_thread_executing() ( _SPARC_Per_CPU_current->executing )
158 
159 void _CPU_Context_volatile_clobber( uintptr_t pattern );
160 
161 void _CPU_Context_validate( uintptr_t pattern );
162 
163 RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
164 {
165  __asm__ volatile ( "unimp 0" );
166 }
167 
168 RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
169 {
170  __asm__ volatile ( "nop" );
171 }
172 
173 #ifdef __cplusplus
174 }
175 #endif
176 
177 #endif /* ASM */
178 
181 #endif /* _RTEMS_SCORE_CPUIMPL_H */
register struct Per_CPU_Control * _SPARC_Per_CPU_current
The pointer to the current per-CPU control is available via register g6.
Definition: cpuimpl.h:153
Per CPU Core Structure.
Definition: percpu.h:347
SPARC CPU Department Source.
#define RTEMS_INLINE_ROUTINE
Gives a hint to the compiler in a function declaration to inline this function.
Definition: basedefs.h:683