RTEMS 7.0-rc1
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regs-edma.h
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1
7/*
8 * Copyright (C) 2011 embedded brains GmbH & Co. KG
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32/*********************************************************************
33 *
34 * Copyright:
35 * Freescale Semiconductor, INC. All Rights Reserved.
36 * You are hereby granted a copyright license to use, modify, and
37 * distribute the SOFTWARE so long as this entire notice is
38 * retained without alteration in any modified and/or redistributed
39 * versions, and that such modified versions are clearly identified
40 * as such. No licenses are granted by implication, estoppel or
41 * otherwise under any patents or trademarks of Freescale
42 * Semiconductor, Inc. This software is provided on an "AS IS"
43 * basis and without warranty.
44 *
45 * To the maximum extent permitted by applicable law, Freescale
46 * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
47 * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
48 * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
49 * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
50 * AND ANY ACCOMPANYING WRITTEN MATERIALS.
51 *
52 * To the maximum extent permitted by applicable law, IN NO EVENT
53 * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
54 * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
55 * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
56 * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
57 *
58 * Freescale Semiconductor assumes no responsibility for the
59 * maintenance and support of this software
60 *
61 ********************************************************************/
62
63#ifndef LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H
64#define LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H
65
66#include <stdint.h>
67
68#include <bspopts.h>
69
70#ifdef __cplusplus
71extern "C" {
72#endif
73
74/****************************************************************************/
75/* MODULE : eDMA */
76/****************************************************************************/
77 struct EDMA_tag {
78 union EDMA_CR_tag {
79 uint32_t R;
80 struct {
81#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567
82 uint32_t:14;
83 uint32_t CX:1;
84 uint32_t ECX:1;
85#else
86 uint32_t:16;
87#endif
88 uint32_t GRP3PRI:2;
89 uint32_t GRP2PRI:2;
90 uint32_t GRP1PRI:2;
91 uint32_t GRP0PRI:2;
92#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567
93 uint32_t EMLM:1;
94 uint32_t CLM:1;
95 uint32_t HALT:1;
96 uint32_t HOE:1;
97#else
98 uint32_t:4;
99#endif
100 uint32_t ERGA:1;
101 uint32_t ERCA:1;
102 uint32_t EDBG:1;
103 uint32_t EBW:1;
104 } B;
105 } CR; /* Control Register */
106
107 union {
108 uint32_t R;
109 struct {
110 uint32_t VLD:1;
111#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567
112 uint32_t:14;
113 uint32_t ECX:1;
114#else
115 uint32_t:15;
116#endif
117 uint32_t GPE:1;
118 uint32_t CPE:1;
119 uint32_t ERRCHN:6;
120 uint32_t SAE:1;
121 uint32_t SOE:1;
122 uint32_t DAE:1;
123 uint32_t DOE:1;
124 uint32_t NCE:1;
125 uint32_t SGE:1;
126 uint32_t SBE:1;
127 uint32_t DBE:1;
128 } B;
129 } ESR; /* Error Status Register */
130
131 union {
132 uint32_t R;
133 struct {
134 uint32_t ERQ63:1;
135 uint32_t ERQ62:1;
136 uint32_t ERQ61:1;
137 uint32_t ERQ60:1;
138 uint32_t ERQ59:1;
139 uint32_t ERQ58:1;
140 uint32_t ERQ57:1;
141 uint32_t ERQ56:1;
142 uint32_t ERQ55:1;
143 uint32_t ERQ54:1;
144 uint32_t ERQ53:1;
145 uint32_t ERQ52:1;
146 uint32_t ERQ51:1;
147 uint32_t ERQ50:1;
148 uint32_t ERQ49:1;
149 uint32_t ERQ48:1;
150 uint32_t ERQ47:1;
151 uint32_t ERQ46:1;
152 uint32_t ERQ45:1;
153 uint32_t ERQ44:1;
154 uint32_t ERQ43:1;
155 uint32_t ERQ42:1;
156 uint32_t ERQ41:1;
157 uint32_t ERQ40:1;
158 uint32_t ERQ39:1;
159 uint32_t ERQ38:1;
160 uint32_t ERQ37:1;
161 uint32_t ERQ36:1;
162 uint32_t ERQ35:1;
163 uint32_t ERQ34:1;
164 uint32_t ERQ33:1;
165 uint32_t ERQ32:1;
166 } B;
167 } ERQRH; /* DMA Enable Request Register High */
168
169 union {
170 uint32_t R;
171 struct {
172 uint32_t ERQ31:1;
173 uint32_t ERQ30:1;
174 uint32_t ERQ29:1;
175 uint32_t ERQ28:1;
176 uint32_t ERQ27:1;
177 uint32_t ERQ26:1;
178 uint32_t ERQ25:1;
179 uint32_t ERQ24:1;
180 uint32_t ERQ23:1;
181 uint32_t ERQ22:1;
182 uint32_t ERQ21:1;
183 uint32_t ERQ20:1;
184 uint32_t ERQ19:1;
185 uint32_t ERQ18:1;
186 uint32_t ERQ17:1;
187 uint32_t ERQ16:1;
188 uint32_t ERQ15:1;
189 uint32_t ERQ14:1;
190 uint32_t ERQ13:1;
191 uint32_t ERQ12:1;
192 uint32_t ERQ11:1;
193 uint32_t ERQ10:1;
194 uint32_t ERQ09:1;
195 uint32_t ERQ08:1;
196 uint32_t ERQ07:1;
197 uint32_t ERQ06:1;
198 uint32_t ERQ05:1;
199 uint32_t ERQ04:1;
200 uint32_t ERQ03:1;
201 uint32_t ERQ02:1;
202 uint32_t ERQ01:1;
203 uint32_t ERQ00:1;
204 } B;
205 } ERQRL; /* DMA Enable Request Register Low */
206
207 union {
208 uint32_t R;
209 struct {
210 uint32_t EEI63:1;
211 uint32_t EEI62:1;
212 uint32_t EEI61:1;
213 uint32_t EEI60:1;
214 uint32_t EEI59:1;
215 uint32_t EEI58:1;
216 uint32_t EEI57:1;
217 uint32_t EEI56:1;
218 uint32_t EEI55:1;
219 uint32_t EEI54:1;
220 uint32_t EEI53:1;
221 uint32_t EEI52:1;
222 uint32_t EEI51:1;
223 uint32_t EEI50:1;
224 uint32_t EEI49:1;
225 uint32_t EEI48:1;
226 uint32_t EEI47:1;
227 uint32_t EEI46:1;
228 uint32_t EEI45:1;
229 uint32_t EEI44:1;
230 uint32_t EEI43:1;
231 uint32_t EEI42:1;
232 uint32_t EEI41:1;
233 uint32_t EEI40:1;
234 uint32_t EEI39:1;
235 uint32_t EEI38:1;
236 uint32_t EEI37:1;
237 uint32_t EEI36:1;
238 uint32_t EEI35:1;
239 uint32_t EEI34:1;
240 uint32_t EEI33:1;
241 uint32_t EEI32:1;
242 } B;
243 } EEIRH; /* DMA Enable Error Interrupt Register High */
244
245 union {
246 uint32_t R;
247 struct {
248 uint32_t EEI31:1;
249 uint32_t EEI30:1;
250 uint32_t EEI29:1;
251 uint32_t EEI28:1;
252 uint32_t EEI27:1;
253 uint32_t EEI26:1;
254 uint32_t EEI25:1;
255 uint32_t EEI24:1;
256 uint32_t EEI23:1;
257 uint32_t EEI22:1;
258 uint32_t EEI21:1;
259 uint32_t EEI20:1;
260 uint32_t EEI19:1;
261 uint32_t EEI18:1;
262 uint32_t EEI17:1;
263 uint32_t EEI16:1;
264 uint32_t EEI15:1;
265 uint32_t EEI14:1;
266 uint32_t EEI13:1;
267 uint32_t EEI12:1;
268 uint32_t EEI11:1;
269 uint32_t EEI10:1;
270 uint32_t EEI09:1;
271 uint32_t EEI08:1;
272 uint32_t EEI07:1;
273 uint32_t EEI06:1;
274 uint32_t EEI05:1;
275 uint32_t EEI04:1;
276 uint32_t EEI03:1;
277 uint32_t EEI02:1;
278 uint32_t EEI01:1;
279 uint32_t EEI00:1;
280 } B;
281 } EEIRL; /* DMA Enable Error Interrupt Register Low */
282
283 union { /* DMA Set Enable Request Register */
284 uint8_t R;
285 struct {
286 uint8_t NOP:1;
287 uint8_t SERQ:7;
288 } B;
289 } SERQR;
290
291 union { /* DMA Clear Enable Request Register */
292 uint8_t R;
293 struct {
294 uint8_t NOP:1;
295 uint8_t CERQ:7;
296 } B;
297 } CERQR;
298
299 union { /* DMA Set Enable Error Interrupt Register */
300 uint8_t R;
301 struct {
302 uint8_t NOP:1;
303 uint8_t SEEI:7;
304 } B;
305 } SEEIR;
306
307 union { /* DMA Clear Enable Error Interrupt Register */
308 uint8_t R;
309 struct {
310 uint8_t NOP:1;
311 uint8_t CEEI:7;
312 } B;
313 } CEEIR;
314
315 union { /* DMA Clear Interrupt Request Register */
316 uint8_t R;
317 struct {
318 uint8_t NOP:1;
319 uint8_t CINT:7;
320 } B;
321 } CIRQR;
322
323 union { /* DMA Clear error Register */
324 uint8_t R;
325 struct {
326 uint8_t NOP:1;
327 uint8_t CERR:7;
328 } B;
329 } CER;
330
331 union { /* Set Start Bit Register */
332 uint8_t R;
333 struct {
334 uint8_t NOP:1;
335 uint8_t SSB:7;
336 } B;
337 } SSBR;
338
339 union { /* Clear Done Status Bit Register */
340 uint8_t R;
341 struct {
342 uint8_t NOP:1;
343 uint8_t CDSB:7;
344 } B;
345 } CDSBR;
346
347 union {
348 uint32_t R;
349 struct {
350 uint32_t INT63:1;
351 uint32_t INT62:1;
352 uint32_t INT61:1;
353 uint32_t INT60:1;
354 uint32_t INT59:1;
355 uint32_t INT58:1;
356 uint32_t INT57:1;
357 uint32_t INT56:1;
358 uint32_t INT55:1;
359 uint32_t INT54:1;
360 uint32_t INT53:1;
361 uint32_t INT52:1;
362 uint32_t INT51:1;
363 uint32_t INT50:1;
364 uint32_t INT49:1;
365 uint32_t INT48:1;
366 uint32_t INT47:1;
367 uint32_t INT46:1;
368 uint32_t INT45:1;
369 uint32_t INT44:1;
370 uint32_t INT43:1;
371 uint32_t INT42:1;
372 uint32_t INT41:1;
373 uint32_t INT40:1;
374 uint32_t INT39:1;
375 uint32_t INT38:1;
376 uint32_t INT37:1;
377 uint32_t INT36:1;
378 uint32_t INT35:1;
379 uint32_t INT34:1;
380 uint32_t INT33:1;
381 uint32_t INT32:1;
382 } B;
383 } IRQRH; /* DMA Interrupt Request High */
384
385 union {
386 uint32_t R;
387 struct {
388 uint32_t INT31:1;
389 uint32_t INT30:1;
390 uint32_t INT29:1;
391 uint32_t INT28:1;
392 uint32_t INT27:1;
393 uint32_t INT26:1;
394 uint32_t INT25:1;
395 uint32_t INT24:1;
396 uint32_t INT23:1;
397 uint32_t INT22:1;
398 uint32_t INT21:1;
399 uint32_t INT20:1;
400 uint32_t INT19:1;
401 uint32_t INT18:1;
402 uint32_t INT17:1;
403 uint32_t INT16:1;
404 uint32_t INT15:1;
405 uint32_t INT14:1;
406 uint32_t INT13:1;
407 uint32_t INT12:1;
408 uint32_t INT11:1;
409 uint32_t INT10:1;
410 uint32_t INT09:1;
411 uint32_t INT08:1;
412 uint32_t INT07:1;
413 uint32_t INT06:1;
414 uint32_t INT05:1;
415 uint32_t INT04:1;
416 uint32_t INT03:1;
417 uint32_t INT02:1;
418 uint32_t INT01:1;
419 uint32_t INT00:1;
420 } B;
421 } IRQRL; /* DMA Interrupt Request Low */
422
423 union {
424 uint32_t R;
425 struct {
426 uint32_t ERR63:1;
427 uint32_t ERR62:1;
428 uint32_t ERR61:1;
429 uint32_t ERR60:1;
430 uint32_t ERR59:1;
431 uint32_t ERR58:1;
432 uint32_t ERR57:1;
433 uint32_t ERR56:1;
434 uint32_t ERR55:1;
435 uint32_t ERR54:1;
436 uint32_t ERR53:1;
437 uint32_t ERR52:1;
438 uint32_t ERR51:1;
439 uint32_t ERR50:1;
440 uint32_t ERR49:1;
441 uint32_t ERR48:1;
442 uint32_t ERR47:1;
443 uint32_t ERR46:1;
444 uint32_t ERR45:1;
445 uint32_t ERR44:1;
446 uint32_t ERR43:1;
447 uint32_t ERR42:1;
448 uint32_t ERR41:1;
449 uint32_t ERR40:1;
450 uint32_t ERR39:1;
451 uint32_t ERR38:1;
452 uint32_t ERR37:1;
453 uint32_t ERR36:1;
454 uint32_t ERR35:1;
455 uint32_t ERR34:1;
456 uint32_t ERR33:1;
457 uint32_t ERR32:1;
458 } B;
459 } ERH; /* DMA Error High */
460
461 union {
462 uint32_t R;
463 struct {
464 uint32_t ERR31:1;
465 uint32_t ERR30:1;
466 uint32_t ERR29:1;
467 uint32_t ERR28:1;
468 uint32_t ERR27:1;
469 uint32_t ERR26:1;
470 uint32_t ERR25:1;
471 uint32_t ERR24:1;
472 uint32_t ERR23:1;
473 uint32_t ERR22:1;
474 uint32_t ERR21:1;
475 uint32_t ERR20:1;
476 uint32_t ERR19:1;
477 uint32_t ERR18:1;
478 uint32_t ERR17:1;
479 uint32_t ERR16:1;
480 uint32_t ERR15:1;
481 uint32_t ERR14:1;
482 uint32_t ERR13:1;
483 uint32_t ERR12:1;
484 uint32_t ERR11:1;
485 uint32_t ERR10:1;
486 uint32_t ERR09:1;
487 uint32_t ERR08:1;
488 uint32_t ERR07:1;
489 uint32_t ERR06:1;
490 uint32_t ERR05:1;
491 uint32_t ERR04:1;
492 uint32_t ERR03:1;
493 uint32_t ERR02:1;
494 uint32_t ERR01:1;
495 uint32_t ERR00:1;
496 } B;
497 } ERL; /* DMA Error Low */
498
499#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567
500 union { /* hardware request status high */
501 uint32_t R;
502 struct {
503 uint32_t HRS63:1;
504 uint32_t HRS62:1;
505 uint32_t HRS61:1;
506 uint32_t HRS60:1;
507 uint32_t HRS59:1;
508 uint32_t HRS58:1;
509 uint32_t HRS57:1;
510 uint32_t HRS56:1;
511 uint32_t HRS55:1;
512 uint32_t HRS54:1;
513 uint32_t HRS53:1;
514 uint32_t HRS52:1;
515 uint32_t HRS51:1;
516 uint32_t HRS50:1;
517 uint32_t HRS49:1;
518 uint32_t HRS48:1;
519 uint32_t HRS47:1;
520 uint32_t HRS46:1;
521 uint32_t HRS45:1;
522 uint32_t HRS44:1;
523 uint32_t HRS43:1;
524 uint32_t HRS42:1;
525 uint32_t HRS41:1;
526 uint32_t HRS40:1;
527 uint32_t HRS39:1;
528 uint32_t HRS38:1;
529 uint32_t HRS37:1;
530 uint32_t HRS36:1;
531 uint32_t HRS35:1;
532 uint32_t HRS34:1;
533 uint32_t HRS33:1;
534 uint32_t HRS32:1;
535 } B;
536 } HRSH;
537
538 union { /* hardware request status low */
539 uint32_t R;
540 struct {
541 uint32_t HRS31:1;
542 uint32_t HRS30:1;
543 uint32_t HRS29:1;
544 uint32_t HRS28:1;
545 uint32_t HRS27:1;
546 uint32_t HRS26:1;
547 uint32_t HRS25:1;
548 uint32_t HRS24:1;
549 uint32_t HRS23:1;
550 uint32_t HRS22:1;
551 uint32_t HRS21:1;
552 uint32_t HRS20:1;
553 uint32_t HRS19:1;
554 uint32_t HRS18:1;
555 uint32_t HRS17:1;
556 uint32_t HRS16:1;
557 uint32_t HRS15:1;
558 uint32_t HRS14:1;
559 uint32_t HRS13:1;
560 uint32_t HRS12:1;
561 uint32_t HRS11:1;
562 uint32_t HRS10:1;
563 uint32_t HRS09:1;
564 uint32_t HRS08:1;
565 uint32_t HRS07:1;
566 uint32_t HRS06:1;
567 uint32_t HRS05:1;
568 uint32_t HRS04:1;
569 uint32_t HRS03:1;
570 uint32_t HRS02:1;
571 uint32_t HRS01:1;
572 uint32_t HRS00:1;
573 } B;
574 } HRSL;
575
576 uint32_t eDMA_reserved0038[50]; /* 0x0038-0x00FF */
577#else
578 uint32_t edma_reserved1[52];
579#endif
580
581 union {
582 uint8_t R;
583 struct {
584 uint8_t ECP:1;
585#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567
586 uint8_t DPA:1;
587#else
588 uint8_t:1;
589#endif
590 uint8_t GRPPRI:2;
591 uint8_t CHPRI:4;
592 } B;
593 } CPR[64];
594
595 uint32_t edma_reserved2[944];
596
597/****************************************************************************/
598/* DMA2 Transfer Control Descriptor */
599/****************************************************************************/
600 struct tcd_t {
601 uint32_t SADDR; /* source address */
602
603 /* Source and destination fields */
604 union tcd_SDF_tag {
605 uint32_t R;
606 struct {
607 uint16_t SMOD:5; /* source address modulo */
608 uint16_t SSIZE:3; /* source transfer size */
609 uint16_t DMOD:5; /* destination address modulo */
610 uint16_t DSIZE:3; /* destination transfer size */
611 int16_t SOFF; /* signed source address offset */
612 } B;
613 } SDF;
614
615 uint32_t NBYTES; /* inner (minor) byte count */
616
617 int32_t SLAST; /* last destination address adjustment, or
618 scatter/gather address (if e_sg = 1) */
619
620 uint32_t DADDR; /* destination address */
621
622 /* CITER and destination fields */
623 union tcd_CDF_tag {
624 uint32_t R;
625 struct {
626 uint16_t CITERE_LINK:1;
627 uint16_t CITER:15;
628 int16_t DOFF; /* signed destination address offset */
629 } B;
630 struct {
631 uint16_t CITERE_LINK:1;
632 uint16_t CITERLINKCH:6;
633 uint16_t CITER:9;
634 int16_t DOFF;
635 } B_ALT;
636 struct {
637 uint16_t CITER;
638 int16_t DOFF;
639 } B_NOLINK;
640 } CDF;
641
642 int32_t DLAST_SGA;
643
644 /* BITER and misc fields */
645 union tcd_BMF_tag {
646 uint32_t R;
647 struct {
648 uint32_t BITERE_LINK:1; /* beginning ("major") iteration count */
649 uint32_t BITER:15;
650 uint32_t BWC:2; /* bandwidth control */
651 uint32_t MAJORLINKCH:6; /* enable channel-to-channel link */
652 uint32_t DONE:1; /* channel done */
653 uint32_t ACTIVE:1; /* channel active */
654 uint32_t MAJORE_LINK:1; /* enable channel-to-channel link */
655 uint32_t E_SG:1; /* enable scatter/gather descriptor */
656 uint32_t D_REQ:1; /* disable ipd_req when done */
657 uint32_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */
658 uint32_t INT_MAJ:1; /* interrupt on major loop completion */
659 uint32_t START:1; /* explicit channel start */
660 } B;
661 struct {
662 uint32_t BITERE_LINK:1;
663 uint32_t BITERLINKCH:6;
664 uint32_t BITER:9;
665 uint32_t BWC:2;
666 uint32_t MAJORLINKCH:6;
667 uint32_t DONE:1;
668 uint32_t ACTIVE:1;
669 uint32_t MAJORE_LINK:1;
670 uint32_t E_SG:1;
671 uint32_t D_REQ:1;
672 uint32_t INT_HALF:1;
673 uint32_t INT_MAJ:1;
674 uint32_t START:1;
675 } B_ALT;
676 struct {
677 uint16_t BITER;
678 uint16_t BWC:2;
679 uint16_t MAJORLINKCH:6;
680 uint16_t DONE:1;
681 uint16_t ACTIVE:1;
682 uint16_t MAJORE_LINK:1;
683 uint16_t E_SG:1;
684 uint16_t D_REQ:1;
685 uint16_t INT_HALF:1;
686 uint16_t INT_MAJ:1;
687 uint16_t START:1;
688 } B_NOLINK;
689 } BMF;
690 } TCD[64]; /* transfer_control_descriptor */
691 };
692
693#ifndef __cplusplus
694 static const struct tcd_t EDMA_TCD_DEFAULT = {
695 .SADDR = 0,
696 .SDF = { .R = 0 },
697 .NBYTES = 0,
698 .SLAST = 0,
699 .DADDR = 0,
700 .CDF = { .R = 0 },
701 .DLAST_SGA = 0,
702 .BMF = { .R = 0 }
703 };
704#endif /* __cplusplus */
705
706#define EDMA_TCD_BITER_MASK 0x7fff
707
708#define EDMA_TCD_BITER_SIZE (EDMA_TCD_BITER_MASK + 1)
709
710#define EDMA_TCD_BITER_LINKED_MASK 0x1ff
711
712#define EDMA_TCD_BITER_LINKED_SIZE (EDMA_TCD_BITER_LINKED_MASK + 1)
713
714#define EDMA_TCD_LINK_AND_BITER(link, biter) \
715 (((link) << 9) + ((biter) & EDMA_TCD_BITER_LINKED_MASK))
716
717#ifdef __cplusplus
718}
719#endif /* __cplusplus */
720
721#endif /* LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H */
EDMA_tag::tcd_t
Definition: regs-edma.h:600
EDMA_tag
Definition: regs-edma.h:77
EDMA_tag::EDMA_CR_tag
Definition: regs-edma.h:78
EDMA_tag::tcd_t::tcd_BMF_tag
Definition: regs-edma.h:645
EDMA_tag::tcd_t::tcd_CDF_tag
Definition: regs-edma.h:623
EDMA_tag::tcd_t::tcd_SDF_tag
Definition: regs-edma.h:604
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