cpu.h

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/* SPDX-License-Identifier: BSD-2-Clause */
 
/*
 *  This include file contains information pertaining to the XXX
 *  processor.
 *
 *  @note This file is part of a porting template that is intended
 *  to be used as the starting point when porting RTEMS to a new
 *  CPU family.  The following needs to be done when using this as
 *  the starting point for a new port:
 *
 *  + Anywhere there is an XXX, it should be replaced
 *    with information about the CPU family being ported to.
 *
 *  + At the end of each comment section, there is a heading which
 *    says "Port Specific Information:".  When porting to RTEMS,
 *    add CPU family specific information in this section
 */
 
/*
 *  COPYRIGHT (c) 1989-2008.
 *  On-Line Applications Research Corporation (OAR).
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef _RTEMS_SCORE_CPU_H
#define _RTEMS_SCORE_CPU_H
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <rtems/score/basedefs.h>
#include <rtems/score/no_cpu.h>
 
/* conditional compilation parameters */
 
#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
 
#define CPU_ISR_PASSES_FRAME_POINTER FALSE
 
#if ( NO_CPU_HAS_FPU == 1 )
#define CPU_HARDWARE_FP     TRUE
#else
#define CPU_HARDWARE_FP     FALSE
#endif
#define CPU_SOFTWARE_FP     FALSE
 
#define CPU_ALL_TASKS_ARE_FP     TRUE
 
#define CPU_IDLE_TASK_IS_FP      FALSE
 
#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
 
#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
 
#define CPU_STACK_GROWS_UP               TRUE
 
#define CPU_CACHE_LINE_BYTES 32
 
#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
 
#define CPU_MODES_INTERRUPT_MASK   0x00000001
 
#define CPU_MAXIMUM_PROCESSORS 32
 
#define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE
 
/*
 *  Processor defined structures required for cpukit/score.
 *
 *  Port Specific Information:
 *
 *  XXX document implementation including references if appropriate
 */
 
/* may need to put some structures here.  */
 
typedef struct {
    uint32_t   some_integer_register;
    uint32_t   some_system_register;
 
    uint32_t   stack_pointer;
 
#ifdef RTEMS_SMP
    volatile bool is_executing;
#endif
} Context_Control;
 
#define _CPU_Context_Get_SP( _context ) \
  (uintptr_t)(_context)->stack_pointer
 
typedef struct {
    double      some_float_register;
} Context_Control_fp;
 
typedef struct {
    uint32_t   special_interrupt_register;
} CPU_Interrupt_frame;
 
extern Context_Control_fp _CPU_Null_fp_context;
 
/*
 *  Nothing prevents the porter from declaring more CPU specific variables.
 *
 *  Port Specific Information:
 *
 *  XXX document implementation including references if appropriate
 */
 
/* XXX: if needed, put more variables here */
 
#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
 
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
 
#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
 
#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
 
#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
 
#define CPU_STACK_MINIMUM_SIZE          (1024*4)
 
#define CPU_SIZEOF_POINTER         4
 
#define CPU_ALIGNMENT              8
 
#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
 
#define CPU_STACK_ALIGNMENT        CPU_HEAP_ALIGNMENT
 
#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
 
/*
 *  ISR handler macros
 */
 
#define _CPU_ISR_Disable( _isr_cookie ) \
  { \
    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
  }
 
#define _CPU_ISR_Enable( _isr_cookie )  \
  { \
  }
 
#define _CPU_ISR_Flash( _isr_cookie ) \
  { \
  }
 
static inline bool _CPU_ISR_Is_enabled( uint32_t level )
{
  return false;
}
 
#define _CPU_ISR_Set_level( new_level ) \
  { \
  }
 
uint32_t   _CPU_ISR_Get_level( void );
 
/* end of ISR handler macros */
 
/* Context handler macros */
 
#define _CPU_Context_Destroy( _the_thread, _the_context ) \
  { \
  }
 
#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
                                 _isr, _entry_point, _is_fp, _tls_area ) \
  { \
  }
 
#define _CPU_Context_Restart_self( _the_context ) \
   _CPU_Context_restore( (_the_context) );
 
#define _CPU_Context_Initialize_fp( _destination ) \
  { \
   *(*(_destination)) = _CPU_Null_fp_context; \
  }
 
/* end of Context handler macros */
 
/* Bitfield handler macros */
 
#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
 
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
  { \
    (_output) = 0;   /* do something to prevent warnings */ \
  }
#endif
 
/* end of Bitfield handler macros */
 
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
 
#define _CPU_Priority_Mask( _bit_number ) \
  ( 1 << (_bit_number) )
 
#endif
 
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
 
#define _CPU_Priority_bits_index( _priority ) \
  (_priority)
 
#endif
 
/* end of Priority handler macros */
 
/* functions */
 
void _CPU_Initialize(void);
 
typedef void ( *CPU_ISR_raw_handler )( void );
 
void _CPU_ISR_install_raw_handler(
  uint32_t             vector,
  CPU_ISR_raw_handler  new_handler,
  CPU_ISR_raw_handler *old_handler
);
 
typedef void ( *CPU_ISR_handler )( uint32_t );
 
void _CPU_ISR_install_vector(
  uint32_t         vector,
  CPU_ISR_handler  new_handler,
  CPU_ISR_handler *old_handler
);
 
RTEMS_NO_RETURN void *_CPU_Thread_Idle_body( uintptr_t ignored );
 
void _CPU_Context_switch(
  Context_Control  *executing,
  Context_Control  *heir
);
 
RTEMS_NO_RETURN void _CPU_Context_switch_no_return(
  Context_Control *executing,
  Context_Control *heir
);
 
RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context );
 
void _CPU_Context_save_fp(
  Context_Control_fp **fp_context_ptr
);
 
void _CPU_Context_restore_fp(
  Context_Control_fp **fp_context_ptr
);
 
typedef struct {
  uint32_t processor_state_register;
  uint32_t integer_registers [1];
  double float_registers [1];
} CPU_Exception_frame;
 
void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
 
#ifdef RTEMS_EXCEPTION_EXTENSIONS
  RTEMS_NO_RETURN void _CPU_Exception_resume( CPU_Exception_frame *frame );
 
  RTEMS_NO_RETURN void _CPU_Exception_dispatch_and_resume(
    CPU_Exception_frame *frame
  );
 
  void _CPU_Exception_disable_thread_dispatch( void );
 
  int _CPU_Exception_frame_get_signal( CPU_Exception_frame *frame );
 
  void _CPU_Exception_frame_set_resume( CPU_Exception_frame *frame, void *address );
 
  void _CPU_Exception_frame_make_resume_next_instruction( CPU_Exception_frame *frame );
#endif
 
static inline uint32_t CPU_swap_u32(
  uint32_t value
)
{
  uint32_t byte1, byte2, byte3, byte4, swapped;
 
  byte4 = (value >> 24) & 0xff;
  byte3 = (value >> 16) & 0xff;
  byte2 = (value >> 8)  & 0xff;
  byte1 =  value        & 0xff;
 
  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
  return swapped;
}
 
#define CPU_swap_u16( value ) \
  (((value&0xff) << 8) | ((value >> 8)&0xff))
  
typedef uint32_t CPU_Counter_ticks;
 
uint32_t _CPU_Counter_frequency( void );
 
CPU_Counter_ticks _CPU_Counter_read( void );
 
#ifdef RTEMS_SMP
  uint32_t _CPU_SMP_Initialize( void );
 
  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
 
  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
 
  void _CPU_SMP_Prepare_start_multitasking( void );
 
  static inline uint32_t _CPU_SMP_Get_current_processor( void )
  {
    return 123;
  }
 
  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
 
  static inline bool _CPU_Context_Get_is_executing(
    const Context_Control *context
  )
  {
    return context->is_executing;
  }
 
  static inline void _CPU_Context_Set_is_executing(
    Context_Control *context,
    bool is_executing
  )
  {
    context->is_executing = is_executing;
  }
 
typedef uintptr_t CPU_Uint32ptr;
 
#endif
 
#ifdef __cplusplus
}
#endif
 
#endif