- x -

XBAR_CLOCKS : fsl_clock.h
XBARA1 : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARA1_BASE : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARA_BASE_ADDRS : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARA_BASE_PTRS : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARA_CLOCKS : fsl_clock.h
XBARA_CTRL0_DEN0 : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARA_CTRL0_DEN1 : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARA_CTRL0_EDGE0 : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARA_CTRL0_EDGE1 : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARA_CTRL0_IEN0 : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARA_CTRL0_IEN1 : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARA_CTRL0_STS0 : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARA_CTRL0_STS1 : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARA_CTRL1_DEN2 : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARA_CTRL1_DEN3 : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARA_CTRL1_EDGE2 : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARA_CTRL1_EDGE3 : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARA_CTRL1_IEN2 : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARA_CTRL1_IEN3 : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARA_CTRL1_STS2 : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARA_CTRL1_STS3 : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARB2 : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARB2_BASE : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARB3 : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARB3_BASE : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARB_BASE_ADDRS : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARB_BASE_PTRS : MIMXRT1052.h, MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XBARB_CLOCKS : fsl_clock.h
XDMAC_CHANNEL_NUM : xdmac.h
XDMAC_CONTROLLER_NUM : xdmac.h
XDMAC_MAX_BT_SIZE : xdmac.h
XECC_BASE_ADDRS : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_BASE_PTRS : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_CLOCKS : fsl_clock.h
XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0 : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1 : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2 : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3 : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_ECC_CTRL_ECC_EN : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_ECC_CTRL_RECC_EN : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_ECC_CTRL_SWAP_EN : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_ECC_CTRL_WECC_EN : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_ECC_END_ADDR0_ECC_END_ADDR0 : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_ECC_END_ADDR1_ECC_END_ADDR1 : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_ECC_END_ADDR2_ECC_END_ADDR2 : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_ECC_END_ADDR3_ECC_END_ADDR3 : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_ERR_DATA_INJ_ERR_DATA_INJ : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_ERR_ECC_INJ_ERR_ECC_INJ : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_ERR_SIG_EN_Reserved1 : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_ERR_STAT_EN_Reserved1 : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_ERR_STATUS_MULTI_ERR : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_ERR_STATUS_Reserved1 : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_ERR_STATUS_SINGLE_ERR : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_FLEXSPI1 : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_FLEXSPI1_BASE : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_FLEXSPI2 : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_FLEXSPI2_BASE : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_MULTI_ERR_BIT_FIELD_Reserved1 : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_MULTI_ERR_DATA_MULTI_ERR_DATA : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_MULTI_ERR_ECC_MULTI_ERR_ECC : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_SEMC : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_SEMC_BASE : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_SINGLE_ERR_BIT_FIELD_Reserved1 : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XECC_SINGLE_ERR_POS_SINGLE_ERR_POS : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XMIT_RESET : uart.h
XNANDPSU_BB_PATTERN : xnandpsu_bbm.h
XNANDPSU_BB_PTRN_LEN_LARGE_PAGE : xnandpsu_bbm.h
XNANDPSU_BB_PTRN_LEN_SML_PAGE : xnandpsu_bbm.h
XNANDPSU_BB_PTRN_OFF_LARGE_PAGE : xnandpsu_bbm.h
XNANDPSU_BB_PTRN_OFF_SML_PAGE : xnandpsu_bbm.h
XNANDPSU_BBT_BLOCK_SHIFT : xnandpsu_bbm.h
XNANDPSU_BBT_DESC_MAX_BLOCKS : xnandpsu_bbm.h
XNANDPSU_BBT_DESC_PAGE_OFFSET : xnandpsu_bbm.h
XNANDPSU_BBT_DESC_SIG_LEN : xnandpsu_bbm.h
XNANDPSU_BBT_DESC_SIG_OFFSET : xnandpsu_bbm.h
XNANDPSU_BBT_DESC_VER_OFFSET : xnandpsu_bbm.h
XNANDPSU_BBT_ENTRY_NUM_BLOCKS : xnandpsu_bbm.h
XNANDPSU_BBT_SCAN_2ND_PAGE : xnandpsu_bbm.h
XNandPsu_BbtBlockShift : xnandpsu_bbm.h
XNANDPSU_BCH : xnandpsu.h
XNANDPSU_BLOCK_BAD : xnandpsu_bbm.h
XNANDPSU_BLOCK_FACTORY_BAD : xnandpsu_bbm.h
XNANDPSU_BLOCK_GOOD : xnandpsu_bbm.h
XNANDPSU_BLOCK_RESERVED : xnandpsu_bbm.h
XNANDPSU_BLOCK_SHIFT_MASK : xnandpsu_bbm.h
XNANDPSU_BLOCK_TYPE_MASK : xnandpsu_bbm.h
XNANDPSU_BUF_DATA_PORT_OFFSET : xnandpsu_hw.h
XNandPsu_ClrBits : xnandpsu.h
XNANDPSU_CMD_ADDR_CYCLES_MASK : xnandpsu_hw.h
XNANDPSU_CMD_ADDR_CYCLES_SHIFT : xnandpsu_hw.h
XNANDPSU_CMD_CMD1_MASK : xnandpsu_hw.h
XNANDPSU_CMD_CMD2_MASK : xnandpsu_hw.h
XNANDPSU_CMD_CMD2_SHIFT : xnandpsu_hw.h
XNANDPSU_CMD_DMA_EN_MASK : xnandpsu_hw.h
XNANDPSU_CMD_DMA_EN_SHIFT : xnandpsu_hw.h
XNANDPSU_CMD_ECC_ON_MASK : xnandpsu_hw.h
XNANDPSU_CMD_ECC_ON_SHIFT : xnandpsu_hw.h
XNANDPSU_CMD_OFFSET : xnandpsu_hw.h
XNANDPSU_CMD_PG_SIZE_MASK : xnandpsu_hw.h
XNANDPSU_CMD_PG_SIZE_SHIFT : xnandpsu_hw.h
XNANDPSU_CPU_REL_OFFSET : xnandpsu_hw.h
XNANDPSU_DATA_INTF_DATA_INTF_MASK : xnandpsu_hw.h
XNANDPSU_DATA_INTF_DATA_INTF_SHIFT : xnandpsu_hw.h
XNANDPSU_DATA_INTF_NVDDR2_MASK : xnandpsu_hw.h
XNANDPSU_DATA_INTF_NVDDR_MASK : xnandpsu_hw.h
XNANDPSU_DATA_INTF_NVDDR_SHIFT : xnandpsu_hw.h
XNANDPSU_DATA_INTF_OFFSET : xnandpsu_hw.h
XNANDPSU_DATA_INTF_SDR_MASK : xnandpsu_hw.h
XNANDPSU_DMA_BUF_BND_BND_MASK : xnandpsu_hw.h
XNANDPSU_DMA_BUF_BND_OFFSET : xnandpsu_hw.h
XNANDPSU_DMA_SYS_ADDR0_OFFSET : xnandpsu_hw.h
XNANDPSU_DMA_SYS_ADDR1_OFFSET : xnandpsu_hw.h
XNANDPSU_ECC_ADDR_MASK : xnandpsu_hw.h
XNANDPSU_ECC_CNT_1BIT_OFFSET : xnandpsu_hw.h
XNANDPSU_ECC_CNT_2BIT_OFFSET : xnandpsu_hw.h
XNANDPSU_ECC_CNT_3BIT_OFFSET : xnandpsu_hw.h
XNANDPSU_ECC_CNT_4BIT_OFFSET : xnandpsu_hw.h
XNANDPSU_ECC_CNT_5BIT_OFFSET : xnandpsu_hw.h
XNANDPSU_ECC_CNT_6BIT_OFFSET : xnandpsu_hw.h
XNANDPSU_ECC_CNT_7BIT_OFFSET : xnandpsu_hw.h
XNANDPSU_ECC_CNT_8BIT_OFFSET : xnandpsu_hw.h
XNANDPSU_ECC_ERR_CNT_OFFSET : xnandpsu_hw.h
XNANDPSU_ECC_ERR_CNT_PG_BND_ERR_CNT_MASK : xnandpsu_hw.h
XNANDPSU_ECC_ERR_CNT_PKT_BND_ERR_CNT_MASK : xnandpsu_hw.h
XNANDPSU_ECC_HAMMING_BCH_MASK : xnandpsu_hw.h
XNANDPSU_ECC_OFFSET : xnandpsu_hw.h
XNANDPSU_ECC_SIZE_MASK : xnandpsu_hw.h
XNANDPSU_ECC_SPR_CMD_ECC_ADDR_CYCLES_MASK : xnandpsu_hw.h
XNANDPSU_ECC_SPR_CMD_OFFSET : xnandpsu_hw.h
XNANDPSU_ECC_SPR_CMD_SPR_CMD_MASK : xnandpsu_hw.h
XNANDPSU_FLASH_BLOCK_BAD : xnandpsu_bbm.h
XNANDPSU_FLASH_BLOCK_FAC_BAD : xnandpsu_bbm.h
XNANDPSU_FLASH_BLOCK_GOOD : xnandpsu_bbm.h
XNANDPSU_FLASH_BLOCK_RESERVED : xnandpsu_bbm.h
XNANDPSU_FLASH_STS_FLASH_STS_MASK : xnandpsu_hw.h
XNANDPSU_FLASH_STS_OFFSET : xnandpsu_hw.h
XNANDPSU_HAMMING : xnandpsu.h
XNANDPSU_ID2_DEVICE_ID2_MASK : xnandpsu_hw.h
XNANDPSU_INTR_BUFF_RD_RDY_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_BUFF_WR_RDY_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_DMA_INT_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_ERR_AHB_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_ERR_INTR_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_MUL_BIT_ERR_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_SIG_EN_BUFF_RD_RDY_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_SIG_EN_BUFF_WR_RDY_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_SIG_EN_DMA_INT_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_SIG_EN_ERR_AHB_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_SIG_EN_ERR_INTR_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_SIG_EN_MUL_BIT_ERR_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_SIG_EN_OFFSET : xnandpsu_hw.h
XNANDPSU_INTR_SIG_EN_TRANS_COMP_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_STS_DMA_INT_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_STS_EN_ERR_AHB_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_STS_EN_ERR_INTR_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_STS_EN_OFFSET : xnandpsu_hw.h
XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_STS_ERR_AHB_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_STS_OFFSET : xnandpsu_hw.h
XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK : xnandpsu_hw.h
XNANDPSU_INTR_TRANS_COMP_STS_EN_MASK : xnandpsu_hw.h
XNandPsu_IntrSigClear : xnandpsu.h
XNandPsu_IntrSigEnable : xnandpsu.h
XNandPsu_IntrStsEnable : xnandpsu.h
XNANDPSU_MAX_BLOCKS : xnandpsu.h
XNANDPSU_MAX_LUNS : xnandpsu.h
XNANDPSU_MAX_PAGE_SIZE : xnandpsu.h
XNANDPSU_MAX_PAGES_PER_BLOCK : xnandpsu.h
XNANDPSU_MAX_PKT_COUNT : xnandpsu.h
XNANDPSU_MAX_PKT_SIZE : xnandpsu.h
XNANDPSU_MAX_SPARE_SIZE : xnandpsu.h
XNANDPSU_MAX_TARGETS : xnandpsu.h
XNANDPSU_MEM_ADDR1_COL_ADDR_MASK : xnandpsu_hw.h
XNANDPSU_MEM_ADDR1_OFFSET : xnandpsu_hw.h
XNANDPSU_MEM_ADDR1_PG_ADDR_MASK : xnandpsu_hw.h
XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT : xnandpsu_hw.h
XNANDPSU_MEM_ADDR2_BUS_WIDTH_MASK : xnandpsu_hw.h
XNANDPSU_MEM_ADDR2_BUS_WIDTH_SHIFT : xnandpsu_hw.h
XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK : xnandpsu_hw.h
XNANDPSU_MEM_ADDR2_CHIP_SEL_SHIFT : xnandpsu_hw.h
XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK : xnandpsu_hw.h
XNANDPSU_MEM_ADDR2_MODE_MASK : xnandpsu_hw.h
XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_MASK : xnandpsu_hw.h
XNANDPSU_MEM_ADDR2_OFFSET : xnandpsu_hw.h
XNANDPSU_NO_OOB_BBT_DESC_SIG_OFFSET : xnandpsu_bbm.h
XNANDPSU_NO_OOB_BBT_DESC_VER_OFFSET : xnandpsu_bbm.h
XNANDPSU_PAGE_SIZE_16K : xnandpsu.h
XNANDPSU_PAGE_SIZE_1K_16BIT : xnandpsu.h
XNANDPSU_PAGE_SIZE_2K : xnandpsu.h
XNANDPSU_PAGE_SIZE_4K : xnandpsu.h
XNANDPSU_PAGE_SIZE_512 : xnandpsu.h
XNANDPSU_PAGE_SIZE_8K : xnandpsu.h
XNANDPSU_PKT_OFFSET : xnandpsu_hw.h
XNANDPSU_PKT_PKT_CNT_MASK : xnandpsu_hw.h
XNANDPSU_PKT_PKT_CNT_SHIFT : xnandpsu_hw.h
XNANDPSU_PKT_PKT_SIZE_MASK : xnandpsu_hw.h
XNANDPSU_PROG_BLK_ERASE_MASK : xnandpsu_hw.h
XNANDPSU_PROG_CHNG_RD_COL_ENH_MASK : xnandpsu_hw.h
XNANDPSU_PROG_CHNG_ROW_ADDR_END_MASK : xnandpsu_hw.h
XNANDPSU_PROG_CHNG_ROW_ADDR_MASK : xnandpsu_hw.h
XNANDPSU_PROG_COPY_BACK_INTRLVD_MASK : xnandpsu_hw.h
XNANDPSU_PROG_GET_FEATURES_MASK : xnandpsu_hw.h
XNANDPSU_PROG_MUL_DIE_MASK : xnandpsu_hw.h
XNANDPSU_PROG_MUL_DIE_RD_MASK : xnandpsu_hw.h
XNANDPSU_PROG_ODT_CONF_MASK : xnandpsu_hw.h
XNANDPSU_PROG_OFFSET : xnandpsu_hw.h
XNANDPSU_PROG_PG_PROG_MASK : xnandpsu_hw.h
XNANDPSU_PROG_PGM_PG_CLR_MASK : xnandpsu_hw.h
XNANDPSU_PROG_RD_CACHE_END_MASK : xnandpsu_hw.h
XNANDPSU_PROG_RD_CACHE_RAND_MASK : xnandpsu_hw.h
XNANDPSU_PROG_RD_CACHE_SEQ_MASK : xnandpsu_hw.h
XNANDPSU_PROG_RD_CACHE_START_MASK : xnandpsu_hw.h
XNANDPSU_PROG_RD_ID_MASK : xnandpsu_hw.h
XNANDPSU_PROG_RD_INTRLVD_MASK : xnandpsu_hw.h
XNANDPSU_PROG_RD_MASK : xnandpsu_hw.h
XNANDPSU_PROG_RD_PRM_PG_MASK : xnandpsu_hw.h
XNANDPSU_PROG_RD_STS_ENH_MASK : xnandpsu_hw.h
XNANDPSU_PROG_RD_STS_MASK : xnandpsu_hw.h
XNANDPSU_PROG_RD_UNQ_ID_MASK : xnandpsu_hw.h
XNANDPSU_PROG_RST_LUN_MASK : xnandpsu_hw.h
XNANDPSU_PROG_RST_MASK : xnandpsu_hw.h
XNANDPSU_PROG_SET_FEATURES_MASK : xnandpsu_hw.h
XNANDPSU_PROG_SMALL_DATA_MOVE_MASK : xnandpsu_hw.h
XNANDPSU_PROG_VOL_SEL_MASK : xnandpsu_hw.h
XNandPsu_ReadModifyWrite : xnandpsu.h
XNandPsu_ReadReg : xnandpsu_hw.h
XNANDPSU_READY_BUSY_OFFSET : xnandpsu_hw.h
XNandPsu_SetBits : xnandpsu.h
XNANDPSU_SLV_DMA_CONF_DMA_BURST_SIZE_MASK : xnandpsu_hw.h
XNANDPSU_SLV_DMA_CONF_DMA_TMOUT_CNT_VAL_MASK : xnandpsu_hw.h
XNANDPSU_SLV_DMA_CONF_DMA_TRANS_CNT_MASK : xnandpsu_hw.h
XNANDPSU_SLV_DMA_CONF_OFFSET : xnandpsu_hw.h
XNANDPSU_SLV_DMA_CONF_SDMA_EN_MASK : xnandpsu_hw.h
XNANDPSU_SLV_DMA_CONF_SDMA_TX_RX_MASK : xnandpsu_hw.h
XNANDPSU_TIMING_DQS_BUFF_SEL_MASK : xnandpsu_hw.h
XNANDPSU_TIMING_OFFSET : xnandpsu_hw.h
XNANDPSU_TIMING_SLOW_FAST_TCAD_MASK : xnandpsu_hw.h
XNANDPSU_TIMING_TADL_TIME_MASK : xnandpsu_hw.h
XNANDPSU_TIMING_TCCS_TIME_MASK : xnandpsu_hw.h
XNandPsu_WriteReg : xnandpsu_hw.h
xPSR_C_Msk : core_cm33.h, core_cm4.h, core_cm7.h
xPSR_C_Pos : core_cm33.h, core_cm4.h, core_cm7.h
xPSR_GE_Msk : core_cm33.h, core_cm4.h, core_cm7.h
xPSR_GE_Pos : core_cm33.h, core_cm4.h, core_cm7.h
xPSR_ICI_IT_1_Msk : core_cm4.h, core_cm7.h
xPSR_ICI_IT_1_Pos : core_cm4.h, core_cm7.h
xPSR_ICI_IT_2_Msk : core_cm4.h, core_cm7.h
xPSR_ICI_IT_2_Pos : core_cm4.h, core_cm7.h
xPSR_ISR_Msk : core_cm33.h, core_cm4.h, core_cm7.h
xPSR_ISR_Pos : core_cm33.h, core_cm4.h, core_cm7.h
xPSR_IT_Msk : core_cm33.h
xPSR_IT_Pos : core_cm33.h
xPSR_N_Msk : core_cm33.h, core_cm4.h, core_cm7.h
xPSR_N_Pos : core_cm33.h, core_cm4.h, core_cm7.h
xPSR_Q_Msk : core_cm33.h, core_cm4.h, core_cm7.h
xPSR_Q_Pos : core_cm33.h, core_cm4.h, core_cm7.h
xPSR_T_Msk : core_cm33.h, core_cm4.h, core_cm7.h
xPSR_T_Pos : core_cm33.h, core_cm4.h, core_cm7.h
xPSR_V_Msk : core_cm33.h, core_cm4.h, core_cm7.h
xPSR_V_Pos : core_cm33.h, core_cm4.h, core_cm7.h
xPSR_Z_Msk : core_cm33.h, core_cm4.h, core_cm7.h
xPSR_Z_Pos : core_cm33.h, core_cm4.h, core_cm7.h
XQSPIPS_BASEADDR : xqspipsu_hw.h
XQSPIPS_EN_REG : xqspipsu_hw.h
XQSPIPS_LQSPI_CFG_RST_STATE : xqspipsu_hw.h
XQSPIPS_LQSPI_CR_4_BYTE_STATE : xqspipsu_hw.h
XQSPIPS_LQSPI_CR_INST_MASK : xqspipsu_hw.h
XQSPIPS_LQSPI_CR_RST_STATE : xqspipsu_hw.h
XQSPIPSU_CFG_OFFSET : xqspipsu_hw.h
XQSPIPSU_CLK_ACTIVE_LOW_OPTION : xqspipsu.h
XQSPIPSU_CLK_PHASE_1_OPTION : xqspipsu.h
XQSPIPSU_CLK_PRESCALE_128 : xqspipsu.h
XQSPIPSU_CLK_PRESCALE_16 : xqspipsu.h
XQSPIPSU_CLK_PRESCALE_2 : xqspipsu.h
XQSPIPSU_CLK_PRESCALE_256 : xqspipsu.h
XQSPIPSU_CLK_PRESCALE_32 : xqspipsu.h
XQSPIPSU_CLK_PRESCALE_4 : xqspipsu.h
XQSPIPSU_CLK_PRESCALE_64 : xqspipsu.h
XQSPIPSU_CLK_PRESCALE_8 : xqspipsu.h
XQSPIPSU_CONNECTION_MODE_PARALLEL : xqspipsu.h
XQSPIPSU_CONNECTION_MODE_SINGLE : xqspipsu.h
XQSPIPSU_CONNECTION_MODE_STACKED : xqspipsu.h
XQSPIPSU_CR_PRESC_MAXIMUM : xqspipsu.h
XQSPIPSU_DATA_DLY_ADJ_OFFSET : xqspipsu_hw.h
XQspiPsu_Disable : xqspipsu.h
XQSPIPSU_DMA_BYTES_MAX : xqspipsu.h
XQSPIPSU_EN_OFFSET : xqspipsu_hw.h
XQspiPsu_Enable : xqspipsu.h
XQSPIPSU_FIFO_CTRL_OFFSET : xqspipsu_hw.h
XQSPIPSU_FREQ_100MHZ : xqspipsu.h
XQSPIPSU_FREQ_150MHZ : xqspipsu.h
XQSPIPSU_FREQ_37_5MHZ : xqspipsu.h
XQSPIPSU_FREQ_40MHZ : xqspipsu.h
XQSPIPSU_GEN_FIFO_OFFSET : xqspipsu_hw.h
XQSPIPSU_GENFIFO_CS_HOLD : xqspipsu.h
XQSPIPSU_GENFIFO_CS_SETUP : xqspipsu.h
XQSPIPSU_GENFIFO_EXP_START : xqspipsu.h
XQSPIPSU_GENFIFO_IMM_DATA_MASK : xqspipsu_hw.h
XQspiPsu_GetLqspiConfigReg : xqspipsu.h
XQSPIPSU_GF_SNAPSHOT_OFFSET : xqspipsu_hw.h
XQSPIPSU_GF_THRESHOLD_OFFSET : xqspipsu_hw.h
XQSPIPSU_GPIO_OFFSET : xqspipsu_hw.h
XQSPIPSU_H_ : xqspipsu.h
XQSPIPSU_HW_H : xqspipsu_hw.h
XQSPIPSU_IDR_OFFSET : xqspipsu_hw.h
XQSPIPSU_IER_OFFSET : xqspipsu_hw.h
XQSPIPSU_IMR_OFFSET : xqspipsu_hw.h
XQspiPsu_In32 : xqspipsu_hw.h
XQSPIPSU_ISR_OFFSET : xqspipsu_hw.h
XQSPIPSU_LPBK_DLY_ADJ_OFFSET : xqspipsu_hw.h
XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK : xqspipsu_hw.h
XQSPIPSU_LQSPI_CR_LINEAR_MASK : xqspipsu_hw.h
XQSPIPSU_LQSPI_CR_MODE_BITS_MASK : xqspipsu_hw.h
XQSPIPSU_LQSPI_CR_MODE_EN_MASK : xqspipsu_hw.h
XQSPIPSU_LQSPI_CR_MODE_ON_MASK : xqspipsu_hw.h
XQSPIPSU_LQSPI_CR_OFFSET : xqspipsu_hw.h
XQSPIPSU_LQSPI_CR_SEP_BUS_MASK : xqspipsu_hw.h
XQSPIPSU_LQSPI_CR_TWO_MEM_MASK : xqspipsu_hw.h
XQSPIPSU_LQSPI_CR_U_PAGE_MASK : xqspipsu_hw.h
XQSPIPSU_LQSPI_LESS_THEN_SIXTEENMB : xqspipsu.h
XQSPIPSU_LQSPI_MODE_OPTION : xqspipsu.h
XQSPIPSU_MANUAL_START_OPTION : xqspipsu.h
XQSPIPSU_MOD_ID_OFFSET : xqspipsu_hw.h
XQSPIPSU_MSG_FLAG_POLL : xqspipsu.h
XQSPIPSU_MSG_FLAG_RX : xqspipsu.h
XQSPIPSU_MSG_FLAG_STRIPE : xqspipsu.h
XQSPIPSU_MSG_FLAG_TX : xqspipsu.h
XQSPIPSU_NUM_OPTIONS : xqspipsu_options.c
XQspiPsu_Out32 : xqspipsu_hw.h
XQSPIPSU_POLL_CFG_OFFSET : xqspipsu_hw.h
XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET : xqspipsu_hw.h
XQSPIPSU_READMODE_DMA : xqspipsu.h
XQSPIPSU_READMODE_IO : xqspipsu.h
XQspiPsu_ReadReg : xqspipsu_hw.h
XQSPIPSU_RX_COPY_OFFSET : xqspipsu_hw.h
XQSPIPSU_RXADDR_OVER_32BIT : xqspipsu.h
XQSPIPSU_RXD_OFFSET : xqspipsu_hw.h
XQSPIPSU_SEL_OFFSET : xqspipsu_hw.h
XQspiPsu_Select : xqspipsu.h
XQSPIPSU_SELECT_FLASH_BUS_BOTH : xqspipsu.h
XQSPIPSU_SELECT_FLASH_BUS_LOWER : xqspipsu.h
XQSPIPSU_SELECT_FLASH_BUS_UPPER : xqspipsu.h
XQSPIPSU_SELECT_FLASH_CS_BOTH : xqspipsu.h
XQSPIPSU_SELECT_FLASH_CS_LOWER : xqspipsu.h
XQSPIPSU_SELECT_FLASH_CS_UPPER : xqspipsu.h
XQSPIPSU_SELECT_MODE_DUALSPI : xqspipsu.h
XQSPIPSU_SELECT_MODE_QUADSPI : xqspipsu.h
XQSPIPSU_SELECT_MODE_SPI : xqspipsu.h
XQSPIPSU_SET_WP : xqspipsu.h
XQSPIPSU_TX_THRESHOLD_OFFSET : xqspipsu_hw.h
XQSPIPSU_TXD_OFFSET : xqspipsu_hw.h
XQspiPsu_WriteReg : xqspipsu_hw.h
XQSPIPSU_XFER_STS_OFFSET : xqspipsu_hw.h
XRDC2_BASE_ADDRS : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_BASE_PTRS : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_D0 : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_D0_BASE : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_D1 : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_D1_BASE : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MCR_GCL : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MCR_GVLDC : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MCR_GVLDM : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MDAC_MDA_W0_MASK : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MDAC_MDA_W0_MATCH : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MDAC_MDA_W1_DID : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MDAC_MDA_W1_DL : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MDAC_MDA_W1_PA : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MDAC_MDA_W1_SA : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MDAC_MDA_W1_VLD : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W0_SRTADDR : MIMXRT1166_cm7.h, MIMXRT1166_cm4.h
XRDC2_MRC_MRGD_W1_SRTADDR : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W2_ENDADDR : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W3_ENDADDR : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W5_D0ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W5_D1ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W5_D2ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W5_D3ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W5_D4ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W5_D5ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W5_D6ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W5_D7ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W5_EALO : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W6_D10ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W6_D11ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W6_D12ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W6_D13ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W6_D14ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W6_D15ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W6_D8ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W6_D9ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W6_DL2 : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W6_EAL : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MRC_MRGD_W6_VLD : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MSC_MSAC_W0_D0ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MSC_MSAC_W0_D1ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MSC_MSAC_W0_D2ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MSC_MSAC_W0_D3ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MSC_MSAC_W0_D4ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MSC_MSAC_W0_D5ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MSC_MSAC_W0_D6ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MSC_MSAC_W0_D7ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MSC_MSAC_W0_EALO : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MSC_MSAC_W1_D10ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MSC_MSAC_W1_D11ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MSC_MSAC_W1_D12ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MSC_MSAC_W1_D13ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MSC_MSAC_W1_D14ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MSC_MSAC_W1_D15ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MSC_MSAC_W1_D8ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MSC_MSAC_W1_D9ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MSC_MSAC_W1_DL2 : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MSC_MSAC_W1_EAL : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_MSC_MSAC_W1_VLD : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_PAC_PDAC_W0_D0ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_PAC_PDAC_W0_D1ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_PAC_PDAC_W0_D2ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_PAC_PDAC_W0_D3ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_PAC_PDAC_W0_D4ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_PAC_PDAC_W0_D5ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_PAC_PDAC_W0_D6ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_PAC_PDAC_W0_D7ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_PAC_PDAC_W0_EALO : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_PAC_PDAC_W1_D10ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_PAC_PDAC_W1_D11ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_PAC_PDAC_W1_D12ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_PAC_PDAC_W1_D13ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_PAC_PDAC_W1_D14ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_PAC_PDAC_W1_D15ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_PAC_PDAC_W1_D8ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_PAC_PDAC_W1_D9ACP : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_PAC_PDAC_W1_DL2 : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_PAC_PDAC_W1_EAL : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_PAC_PDAC_W1_VLD : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_SR_DIN : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_SR_GCLO : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XRDC2_SR_HRL : MIMXRT1166_cm4.h, MIMXRT1166_cm7.h
XSPI_ABR_ALTERNATE : stm32u5g9xx.h
XSPI_ABR_ALTERNATE_Msk : stm32u5g9xx.h
XSPI_AR_ADDRESS : stm32u5g9xx.h
XSPI_AR_ADDRESS_Msk : stm32u5g9xx.h
XSPI_CCR_ABDTR : stm32u5g9xx.h
XSPI_CCR_ABDTR_Msk : stm32u5g9xx.h
XSPI_CCR_ABMODE : stm32u5g9xx.h
XSPI_CCR_ABMODE_0 : stm32u5g9xx.h
XSPI_CCR_ABMODE_1 : stm32u5g9xx.h
XSPI_CCR_ABMODE_2 : stm32u5g9xx.h
XSPI_CCR_ABMODE_Msk : stm32u5g9xx.h
XSPI_CCR_ABSIZE : stm32u5g9xx.h
XSPI_CCR_ABSIZE_0 : stm32u5g9xx.h
XSPI_CCR_ABSIZE_1 : stm32u5g9xx.h
XSPI_CCR_ABSIZE_Msk : stm32u5g9xx.h
XSPI_CCR_ADDTR : stm32u5g9xx.h
XSPI_CCR_ADDTR_Msk : stm32u5g9xx.h
XSPI_CCR_ADMODE : stm32u5g9xx.h
XSPI_CCR_ADMODE_0 : stm32u5g9xx.h
XSPI_CCR_ADMODE_1 : stm32u5g9xx.h
XSPI_CCR_ADMODE_2 : stm32u5g9xx.h
XSPI_CCR_ADMODE_Msk : stm32u5g9xx.h
XSPI_CCR_ADSIZE : stm32u5g9xx.h
XSPI_CCR_ADSIZE_0 : stm32u5g9xx.h
XSPI_CCR_ADSIZE_1 : stm32u5g9xx.h
XSPI_CCR_ADSIZE_Msk : stm32u5g9xx.h
XSPI_CCR_DDTR : stm32u5g9xx.h
XSPI_CCR_DDTR_Msk : stm32u5g9xx.h
XSPI_CCR_DMODE : stm32u5g9xx.h
XSPI_CCR_DMODE_0 : stm32u5g9xx.h
XSPI_CCR_DMODE_1 : stm32u5g9xx.h
XSPI_CCR_DMODE_2 : stm32u5g9xx.h
XSPI_CCR_DMODE_Msk : stm32u5g9xx.h
XSPI_CCR_DQSE : stm32u5g9xx.h
XSPI_CCR_DQSE_Msk : stm32u5g9xx.h
XSPI_CCR_IDTR : stm32u5g9xx.h
XSPI_CCR_IDTR_Msk : stm32u5g9xx.h
XSPI_CCR_IMODE : stm32u5g9xx.h
XSPI_CCR_IMODE_0 : stm32u5g9xx.h
XSPI_CCR_IMODE_1 : stm32u5g9xx.h
XSPI_CCR_IMODE_2 : stm32u5g9xx.h
XSPI_CCR_IMODE_Msk : stm32u5g9xx.h
XSPI_CCR_ISIZE : stm32u5g9xx.h
XSPI_CCR_ISIZE_0 : stm32u5g9xx.h
XSPI_CCR_ISIZE_1 : stm32u5g9xx.h
XSPI_CCR_ISIZE_Msk : stm32u5g9xx.h
XSPI_CCR_SIOO : stm32u5g9xx.h
XSPI_CCR_SIOO_Msk : stm32u5g9xx.h
XSPI_CR_ABORT : stm32u5g9xx.h
XSPI_CR_ABORT_Msk : stm32u5g9xx.h
XSPI_CR_APMS : stm32u5g9xx.h
XSPI_CR_APMS_Msk : stm32u5g9xx.h
XSPI_CR_DMAEN : stm32u5g9xx.h
XSPI_CR_DMAEN_Msk : stm32u5g9xx.h
XSPI_CR_DMM : stm32u5g9xx.h
XSPI_CR_DMM_Msk : stm32u5g9xx.h
XSPI_CR_EN : stm32u5g9xx.h
XSPI_CR_EN_Msk : stm32u5g9xx.h
XSPI_CR_FMODE : stm32u5g9xx.h
XSPI_CR_FMODE_0 : stm32u5g9xx.h
XSPI_CR_FMODE_1 : stm32u5g9xx.h
XSPI_CR_FMODE_Msk : stm32u5g9xx.h
XSPI_CR_FTHRES : stm32u5g9xx.h
XSPI_CR_FTHRES_Msk : stm32u5g9xx.h
XSPI_CR_FTIE : stm32u5g9xx.h
XSPI_CR_FTIE_Msk : stm32u5g9xx.h
XSPI_CR_PMM : stm32u5g9xx.h
XSPI_CR_PMM_Msk : stm32u5g9xx.h
XSPI_CR_SMIE : stm32u5g9xx.h
XSPI_CR_SMIE_Msk : stm32u5g9xx.h
XSPI_CR_TCEN : stm32u5g9xx.h
XSPI_CR_TCEN_Msk : stm32u5g9xx.h
XSPI_CR_TCIE : stm32u5g9xx.h
XSPI_CR_TCIE_Msk : stm32u5g9xx.h
XSPI_CR_TEIE : stm32u5g9xx.h
XSPI_CR_TEIE_Msk : stm32u5g9xx.h
XSPI_CR_TOIE : stm32u5g9xx.h
XSPI_CR_TOIE_Msk : stm32u5g9xx.h
XSPI_DCR1_CKMODE : stm32u5g9xx.h
XSPI_DCR1_CKMODE_Msk : stm32u5g9xx.h
XSPI_DCR1_CSHT : stm32u5g9xx.h
XSPI_DCR1_CSHT_Msk : stm32u5g9xx.h
XSPI_DCR1_DEVSIZE : stm32u5g9xx.h
XSPI_DCR1_DEVSIZE_Msk : stm32u5g9xx.h
XSPI_DCR1_FRCK : stm32u5g9xx.h
XSPI_DCR1_FRCK_Msk : stm32u5g9xx.h
XSPI_DCR1_MTYP : stm32u5g9xx.h
XSPI_DCR1_MTYP_0 : stm32u5g9xx.h
XSPI_DCR1_MTYP_1 : stm32u5g9xx.h
XSPI_DCR1_MTYP_2 : stm32u5g9xx.h
XSPI_DCR1_MTYP_Msk : stm32u5g9xx.h
XSPI_DCR2_PRESCALER : stm32u5g9xx.h
XSPI_DCR2_PRESCALER_Msk : stm32u5g9xx.h
XSPI_DCR2_WRAPSIZE : stm32u5g9xx.h
XSPI_DCR2_WRAPSIZE_0 : stm32u5g9xx.h
XSPI_DCR2_WRAPSIZE_1 : stm32u5g9xx.h
XSPI_DCR2_WRAPSIZE_2 : stm32u5g9xx.h
XSPI_DCR2_WRAPSIZE_Msk : stm32u5g9xx.h
XSPI_DCR3_CSBOUND : stm32u5g9xx.h
XSPI_DCR3_CSBOUND_Msk : stm32u5g9xx.h
XSPI_DCR4_REFRESH : stm32u5g9xx.h
XSPI_DCR4_REFRESH_Msk : stm32u5g9xx.h
XSPI_DLR_DL : stm32u5g9xx.h
XSPI_DLR_DL_Msk : stm32u5g9xx.h
XSPI_DR_DATA : stm32u5g9xx.h
XSPI_DR_DATA_Msk : stm32u5g9xx.h
XSPI_FCR_CSMF : stm32u5g9xx.h
XSPI_FCR_CSMF_Msk : stm32u5g9xx.h
XSPI_FCR_CTCF : stm32u5g9xx.h
XSPI_FCR_CTCF_Msk : stm32u5g9xx.h
XSPI_FCR_CTEF : stm32u5g9xx.h
XSPI_FCR_CTEF_Msk : stm32u5g9xx.h
XSPI_FCR_CTOF : stm32u5g9xx.h
XSPI_FCR_CTOF_Msk : stm32u5g9xx.h
XSPI_HLCR_LM : stm32u5g9xx.h
XSPI_HLCR_LM_Msk : stm32u5g9xx.h
XSPI_HLCR_TACC : stm32u5g9xx.h
XSPI_HLCR_TACC_Msk : stm32u5g9xx.h
XSPI_HLCR_TRWR : stm32u5g9xx.h
XSPI_HLCR_TRWR_Msk : stm32u5g9xx.h
XSPI_HLCR_WZL : stm32u5g9xx.h
XSPI_HLCR_WZL_Msk : stm32u5g9xx.h
XSPI_HSPI_CALFCR_CALMAX : stm32u5g9xx.h
XSPI_HSPI_CALFCR_CALMAX_Msk : stm32u5g9xx.h
XSPI_HSPI_CALFCR_COARSE : stm32u5g9xx.h
XSPI_HSPI_CALFCR_COARSE_Msk : stm32u5g9xx.h
XSPI_HSPI_CALFCR_FINE : stm32u5g9xx.h
XSPI_HSPI_CALFCR_FINE_Msk : stm32u5g9xx.h
XSPI_HSPI_CALMR_COARSE : stm32u5g9xx.h
XSPI_HSPI_CALMR_COARSE_Msk : stm32u5g9xx.h
XSPI_HSPI_CALMR_FINE : stm32u5g9xx.h
XSPI_HSPI_CALMR_FINE_Msk : stm32u5g9xx.h
XSPI_HSPI_CALSIR_COARSE : stm32u5g9xx.h
XSPI_HSPI_CALSIR_COARSE_Msk : stm32u5g9xx.h
XSPI_HSPI_CALSIR_FINE : stm32u5g9xx.h
XSPI_HSPI_CALSIR_FINE_Msk : stm32u5g9xx.h
XSPI_HSPI_CALSOR_COARSE : stm32u5g9xx.h
XSPI_HSPI_CALSOR_COARSE_Msk : stm32u5g9xx.h
XSPI_HSPI_CALSOR_FINE : stm32u5g9xx.h
XSPI_HSPI_CALSOR_FINE_Msk : stm32u5g9xx.h
XSPI_HSPI_CR_MSEL : stm32u5g9xx.h
XSPI_HSPI_CR_MSEL_0 : stm32u5g9xx.h
XSPI_HSPI_CR_MSEL_1 : stm32u5g9xx.h
XSPI_HSPI_CR_MSEL_Msk : stm32u5g9xx.h
XSPI_IR_INSTRUCTION : stm32u5g9xx.h
XSPI_IR_INSTRUCTION_Msk : stm32u5g9xx.h
XSPI_LPTR_TIMEOUT : stm32u5g9xx.h
XSPI_LPTR_TIMEOUT_Msk : stm32u5g9xx.h
XSPI_OCTOSPI_CR_MSEL : stm32u5g9xx.h
XSPI_OCTOSPI_CR_MSEL_Msk : stm32u5g9xx.h
XSPI_OCTOSPI_DCR1_DLYBYP : stm32u5g9xx.h
XSPI_OCTOSPI_DCR1_DLYBYP_Msk : stm32u5g9xx.h
XSPI_OCTOSPI_DCR3_MAXTRAN : stm32u5g9xx.h
XSPI_OCTOSPI_DCR3_MAXTRAN_Msk : stm32u5g9xx.h
XSPI_PIR_INTERVAL : stm32u5g9xx.h
XSPI_PIR_INTERVAL_Msk : stm32u5g9xx.h
XSPI_PSMAR_MATCH : stm32u5g9xx.h
XSPI_PSMAR_MATCH_Msk : stm32u5g9xx.h
XSPI_PSMKR_MASK : stm32u5g9xx.h
XSPI_PSMKR_MASK_Msk : stm32u5g9xx.h
XSPI_SR_BUSY : stm32u5g9xx.h
XSPI_SR_BUSY_Msk : stm32u5g9xx.h
XSPI_SR_FLEVEL : stm32u5g9xx.h
XSPI_SR_FLEVEL_Msk : stm32u5g9xx.h
XSPI_SR_FTF : stm32u5g9xx.h
XSPI_SR_FTF_Msk : stm32u5g9xx.h
XSPI_SR_SMF : stm32u5g9xx.h
XSPI_SR_SMF_Msk : stm32u5g9xx.h
XSPI_SR_TCF : stm32u5g9xx.h
XSPI_SR_TCF_Msk : stm32u5g9xx.h
XSPI_SR_TEF : stm32u5g9xx.h
XSPI_SR_TEF_Msk : stm32u5g9xx.h
XSPI_SR_TOF : stm32u5g9xx.h
XSPI_SR_TOF_Msk : stm32u5g9xx.h
XSPI_TCR_DCYC : stm32u5g9xx.h
XSPI_TCR_DCYC_Msk : stm32u5g9xx.h
XSPI_TCR_DHQC : stm32u5g9xx.h
XSPI_TCR_DHQC_Msk : stm32u5g9xx.h
XSPI_TCR_SSHIFT : stm32u5g9xx.h
XSPI_TCR_SSHIFT_Msk : stm32u5g9xx.h
XSPI_WABR_ALTERNATE : stm32u5g9xx.h
XSPI_WABR_ALTERNATE_Msk : stm32u5g9xx.h
XSPI_WCCR_ABDTR : stm32u5g9xx.h
XSPI_WCCR_ABDTR_Msk : stm32u5g9xx.h
XSPI_WCCR_ABMODE : stm32u5g9xx.h
XSPI_WCCR_ABMODE_0 : stm32u5g9xx.h
XSPI_WCCR_ABMODE_1 : stm32u5g9xx.h
XSPI_WCCR_ABMODE_2 : stm32u5g9xx.h
XSPI_WCCR_ABMODE_Msk : stm32u5g9xx.h
XSPI_WCCR_ABSIZE : stm32u5g9xx.h
XSPI_WCCR_ABSIZE_0 : stm32u5g9xx.h
XSPI_WCCR_ABSIZE_1 : stm32u5g9xx.h
XSPI_WCCR_ABSIZE_Msk : stm32u5g9xx.h
XSPI_WCCR_ADDTR : stm32u5g9xx.h
XSPI_WCCR_ADDTR_Msk : stm32u5g9xx.h
XSPI_WCCR_ADMODE : stm32u5g9xx.h
XSPI_WCCR_ADMODE_0 : stm32u5g9xx.h
XSPI_WCCR_ADMODE_1 : stm32u5g9xx.h
XSPI_WCCR_ADMODE_2 : stm32u5g9xx.h
XSPI_WCCR_ADMODE_Msk : stm32u5g9xx.h
XSPI_WCCR_ADSIZE : stm32u5g9xx.h
XSPI_WCCR_ADSIZE_0 : stm32u5g9xx.h
XSPI_WCCR_ADSIZE_1 : stm32u5g9xx.h
XSPI_WCCR_ADSIZE_Msk : stm32u5g9xx.h
XSPI_WCCR_DDTR : stm32u5g9xx.h
XSPI_WCCR_DDTR_Msk : stm32u5g9xx.h
XSPI_WCCR_DMODE : stm32u5g9xx.h
XSPI_WCCR_DMODE_0 : stm32u5g9xx.h
XSPI_WCCR_DMODE_1 : stm32u5g9xx.h
XSPI_WCCR_DMODE_2 : stm32u5g9xx.h
XSPI_WCCR_DMODE_Msk : stm32u5g9xx.h
XSPI_WCCR_DQSE : stm32u5g9xx.h
XSPI_WCCR_DQSE_Msk : stm32u5g9xx.h
XSPI_WCCR_IDTR : stm32u5g9xx.h
XSPI_WCCR_IDTR_Msk : stm32u5g9xx.h
XSPI_WCCR_IMODE : stm32u5g9xx.h
XSPI_WCCR_IMODE_0 : stm32u5g9xx.h
XSPI_WCCR_IMODE_1 : stm32u5g9xx.h
XSPI_WCCR_IMODE_2 : stm32u5g9xx.h
XSPI_WCCR_IMODE_Msk : stm32u5g9xx.h
XSPI_WCCR_ISIZE : stm32u5g9xx.h
XSPI_WCCR_ISIZE_0 : stm32u5g9xx.h
XSPI_WCCR_ISIZE_1 : stm32u5g9xx.h
XSPI_WCCR_ISIZE_Msk : stm32u5g9xx.h
XSPI_WIR_INSTRUCTION : stm32u5g9xx.h
XSPI_WIR_INSTRUCTION_Msk : stm32u5g9xx.h
XSPI_WPABR_ALTERNATE : stm32u5g9xx.h
XSPI_WPABR_ALTERNATE_Msk : stm32u5g9xx.h
XSPI_WPCCR_ABDTR : stm32u5g9xx.h
XSPI_WPCCR_ABDTR_Msk : stm32u5g9xx.h
XSPI_WPCCR_ABMODE : stm32u5g9xx.h
XSPI_WPCCR_ABMODE_0 : stm32u5g9xx.h
XSPI_WPCCR_ABMODE_1 : stm32u5g9xx.h
XSPI_WPCCR_ABMODE_2 : stm32u5g9xx.h
XSPI_WPCCR_ABMODE_Msk : stm32u5g9xx.h
XSPI_WPCCR_ABSIZE : stm32u5g9xx.h
XSPI_WPCCR_ABSIZE_0 : stm32u5g9xx.h
XSPI_WPCCR_ABSIZE_1 : stm32u5g9xx.h
XSPI_WPCCR_ABSIZE_Msk : stm32u5g9xx.h
XSPI_WPCCR_ADDTR : stm32u5g9xx.h
XSPI_WPCCR_ADDTR_Msk : stm32u5g9xx.h
XSPI_WPCCR_ADMODE : stm32u5g9xx.h
XSPI_WPCCR_ADMODE_0 : stm32u5g9xx.h
XSPI_WPCCR_ADMODE_1 : stm32u5g9xx.h
XSPI_WPCCR_ADMODE_2 : stm32u5g9xx.h
XSPI_WPCCR_ADMODE_Msk : stm32u5g9xx.h
XSPI_WPCCR_ADSIZE : stm32u5g9xx.h
XSPI_WPCCR_ADSIZE_0 : stm32u5g9xx.h
XSPI_WPCCR_ADSIZE_1 : stm32u5g9xx.h
XSPI_WPCCR_ADSIZE_Msk : stm32u5g9xx.h
XSPI_WPCCR_DDTR : stm32u5g9xx.h
XSPI_WPCCR_DDTR_Msk : stm32u5g9xx.h
XSPI_WPCCR_DMODE : stm32u5g9xx.h
XSPI_WPCCR_DMODE_0 : stm32u5g9xx.h
XSPI_WPCCR_DMODE_1 : stm32u5g9xx.h
XSPI_WPCCR_DMODE_2 : stm32u5g9xx.h
XSPI_WPCCR_DMODE_Msk : stm32u5g9xx.h
XSPI_WPCCR_DQSE : stm32u5g9xx.h
XSPI_WPCCR_DQSE_Msk : stm32u5g9xx.h
XSPI_WPCCR_IDTR : stm32u5g9xx.h
XSPI_WPCCR_IDTR_Msk : stm32u5g9xx.h
XSPI_WPCCR_IMODE : stm32u5g9xx.h
XSPI_WPCCR_IMODE_0 : stm32u5g9xx.h
XSPI_WPCCR_IMODE_1 : stm32u5g9xx.h
XSPI_WPCCR_IMODE_2 : stm32u5g9xx.h
XSPI_WPCCR_IMODE_Msk : stm32u5g9xx.h
XSPI_WPCCR_ISIZE : stm32u5g9xx.h
XSPI_WPCCR_ISIZE_0 : stm32u5g9xx.h
XSPI_WPCCR_ISIZE_1 : stm32u5g9xx.h
XSPI_WPCCR_ISIZE_Msk : stm32u5g9xx.h
XSPI_WPIR_INSTRUCTION : stm32u5g9xx.h
XSPI_WPIR_INSTRUCTION_Msk : stm32u5g9xx.h
XSPI_WPTCR_DCYC : stm32u5g9xx.h
XSPI_WPTCR_DCYC_Msk : stm32u5g9xx.h
XSPI_WPTCR_DHQC : stm32u5g9xx.h
XSPI_WPTCR_DHQC_Msk : stm32u5g9xx.h
XSPI_WPTCR_SSHIFT : stm32u5g9xx.h
XSPI_WPTCR_SSHIFT_Msk : stm32u5g9xx.h
XSPI_WTCR_DCYC : stm32u5g9xx.h
XSPI_WTCR_DCYC_Msk : stm32u5g9xx.h
XSPIM_CR_MUXEN : stm32u5g9xx.h
XSPIM_CR_MUXEN_Msk : stm32u5g9xx.h
XSPIM_CR_REQ2ACK_TIME : stm32u5g9xx.h
XSPIM_CR_REQ2ACK_TIME_Msk : stm32u5g9xx.h
XSPIM_PCR_CLKEN : stm32u5g9xx.h
XSPIM_PCR_CLKEN_Msk : stm32u5g9xx.h
XSPIM_PCR_CLKSRC : stm32u5g9xx.h
XSPIM_PCR_CLKSRC_Msk : stm32u5g9xx.h
XSPIM_PCR_DQSEN : stm32u5g9xx.h
XSPIM_PCR_DQSEN_Msk : stm32u5g9xx.h
XSPIM_PCR_DQSSRC : stm32u5g9xx.h
XSPIM_PCR_DQSSRC_Msk : stm32u5g9xx.h
XSPIM_PCR_IOHEN : stm32u5g9xx.h
XSPIM_PCR_IOHEN_Msk : stm32u5g9xx.h
XSPIM_PCR_IOHSRC : stm32u5g9xx.h
XSPIM_PCR_IOHSRC_0 : stm32u5g9xx.h
XSPIM_PCR_IOHSRC_1 : stm32u5g9xx.h
XSPIM_PCR_IOHSRC_Msk : stm32u5g9xx.h
XSPIM_PCR_IOLEN : stm32u5g9xx.h
XSPIM_PCR_IOLEN_Msk : stm32u5g9xx.h
XSPIM_PCR_IOLSRC : stm32u5g9xx.h
XSPIM_PCR_IOLSRC_0 : stm32u5g9xx.h
XSPIM_PCR_IOLSRC_1 : stm32u5g9xx.h
XSPIM_PCR_IOLSRC_Msk : stm32u5g9xx.h
XSPIM_PCR_NCSEN : stm32u5g9xx.h
XSPIM_PCR_NCSEN_Msk : stm32u5g9xx.h
XSPIM_PCR_NCSSRC : stm32u5g9xx.h
XSPIM_PCR_NCSSRC_Msk : stm32u5g9xx.h
XTALOSC24M : MIMXRT1052.h
XTALOSC24M_BASE : MIMXRT1052.h
XTALOSC24M_BASE_ADDRS : MIMXRT1052.h
XTALOSC24M_BASE_PTRS : MIMXRT1052.h
XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL : MIMXRT1052.h
XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL : MIMXRT1052.h
XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN : MIMXRT1052.h
XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY : MIMXRT1052.h
XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT : MIMXRT1052.h
XTALOSC24M_LOWPWR_CTRL_LPBG_SEL : MIMXRT1052.h
XTALOSC24M_LOWPWR_CTRL_OSC_SEL : MIMXRT1052.h
XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN : MIMXRT1052.h
XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL : MIMXRT1052.h
XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL : MIMXRT1052.h
XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN : MIMXRT1052.h
XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY : MIMXRT1052.h
XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT : MIMXRT1052.h
XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL : MIMXRT1052.h
XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL : MIMXRT1052.h
XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN : MIMXRT1052.h
XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY : MIMXRT1052.h
XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT : MIMXRT1052.h
XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY : MIMXRT1052.h
XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT : MIMXRT1052.h
XTALOSC24M_MISC0_CLKGATE_CTRL : MIMXRT1052.h
XTALOSC24M_MISC0_CLKGATE_DELAY : MIMXRT1052.h
XTALOSC24M_MISC0_CLR_CLKGATE_CTRL : MIMXRT1052.h
XTALOSC24M_MISC0_CLR_CLKGATE_DELAY : MIMXRT1052.h
XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS : MIMXRT1052.h
XTALOSC24M_MISC0_CLR_OSC_I : MIMXRT1052.h
XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF : MIMXRT1052.h
XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ : MIMXRT1052.h
XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE : MIMXRT1052.h
XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG : MIMXRT1052.h
XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV : MIMXRT1052.h
XTALOSC24M_MISC0_DISCON_HIGH_SNVS : MIMXRT1052.h
XTALOSC24M_MISC0_OSC_I : MIMXRT1052.h
XTALOSC24M_MISC0_REFTOP_SELFBIASOFF : MIMXRT1052.h
XTALOSC24M_MISC0_REFTOP_VBGADJ : MIMXRT1052.h
XTALOSC24M_MISC0_RTC_XTAL_SOURCE : MIMXRT1052.h
XTALOSC24M_MISC0_SET_CLKGATE_CTRL : MIMXRT1052.h
XTALOSC24M_MISC0_SET_CLKGATE_DELAY : MIMXRT1052.h
XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS : MIMXRT1052.h
XTALOSC24M_MISC0_SET_OSC_I : MIMXRT1052.h
XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF : MIMXRT1052.h
XTALOSC24M_MISC0_SET_REFTOP_VBGADJ : MIMXRT1052.h
XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE : MIMXRT1052.h
XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG : MIMXRT1052.h
XTALOSC24M_MISC0_SET_VID_PLL_PREDIV : MIMXRT1052.h
XTALOSC24M_MISC0_STOP_MODE_CONFIG : MIMXRT1052.h
XTALOSC24M_MISC0_TOG_CLKGATE_CTRL : MIMXRT1052.h
XTALOSC24M_MISC0_TOG_CLKGATE_DELAY : MIMXRT1052.h
XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS : MIMXRT1052.h
XTALOSC24M_MISC0_TOG_OSC_I : MIMXRT1052.h
XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF : MIMXRT1052.h
XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ : MIMXRT1052.h
XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE : MIMXRT1052.h
XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG : MIMXRT1052.h
XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV : MIMXRT1052.h
XTALOSC24M_MISC0_VID_PLL_PREDIV : MIMXRT1052.h
XTTCPS_CLK_CNTRL_EXT_EDGE_MASK : xttcps_hw.h
XTTCPS_CLK_CNTRL_OFFSET : xttcps_hw.h
XTTCPS_CLK_CNTRL_PS_DISABLE : xttcps_hw.h
XTTCPS_CLK_CNTRL_PS_EN_MASK : xttcps_hw.h
XTTCPS_CLK_CNTRL_PS_VAL_MASK : xttcps_hw.h
XTTCPS_CLK_CNTRL_PS_VAL_SHIFT : xttcps_hw.h
XTTCPS_CLK_CNTRL_SRC_MASK : xttcps_hw.h
XTTCPS_CNT_CNTRL_DECR_MASK : xttcps_hw.h
XTTCPS_CNT_CNTRL_DIS_MASK : xttcps_hw.h
XTTCPS_CNT_CNTRL_EN_WAVE_MASK : xttcps_hw.h
XTTCPS_CNT_CNTRL_INT_MASK : xttcps_hw.h
XTTCPS_CNT_CNTRL_MATCH_MASK : xttcps_hw.h
XTTCPS_CNT_CNTRL_OFFSET : xttcps_hw.h
XTTCPS_CNT_CNTRL_POL_WAVE_MASK : xttcps_hw.h
XTTCPS_CNT_CNTRL_RESET_VALUE : xttcps_hw.h
XTTCPS_CNT_CNTRL_RST_MASK : xttcps_hw.h
XTTCPS_COUNT_VALUE_MASK : xttcps_hw.h
XTTCPS_COUNT_VALUE_OFFSET : xttcps_hw.h
XTTCPS_IER_OFFSET : xttcps_hw.h
XTTCPS_INTERVAL_VAL_MASK : xttcps_hw.h
XTTCPS_INTERVAL_VAL_OFFSET : xttcps_hw.h
XTTCPS_ISR_OFFSET : xttcps_hw.h
XTTCPS_IXR_ALL_MASK : xttcps_hw.h
XTTCPS_IXR_CNT_OVR_MASK : xttcps_hw.h
XTTCPS_IXR_INTERVAL_MASK : xttcps_hw.h
XTTCPS_IXR_MATCH_0_MASK : xttcps_hw.h
XTTCPS_IXR_MATCH_1_MASK : xttcps_hw.h
XTTCPS_IXR_MATCH_2_MASK : xttcps_hw.h
XTTCPS_MATCH_0_OFFSET : xttcps_hw.h
XTTCPS_MATCH_1_OFFSET : xttcps_hw.h
XTTCPS_MATCH_2_OFFSET : xttcps_hw.h
XTTCPS_MATCH_MASK : xttcps_hw.h
XTtcPs_Match_N_Offset : xttcps_hw.h
XTTCPS_NUM_MATCH_REG : xttcps_hw.h
XTtcPs_ReadReg : xttcps_hw.h
XTtcPs_WriteReg : xttcps_hw.h