RTEMS 7.0-rc1
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core_cm33.h
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1/*
2 * The file was modified by RTEMS contributors.
3 */
4/**************************************************************************/
10/*
11 * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
12 *
13 * SPDX-License-Identifier: Apache-2.0
14 *
15 * Licensed under the Apache License, Version 2.0 (the License); you may
16 * not use this file except in compliance with the License.
17 * You may obtain a copy of the License at
18 *
19 * www.apache.org/licenses/LICENSE-2.0
20 *
21 * Unless required by applicable law or agreed to in writing, software
22 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
23 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
24 * See the License for the specific language governing permissions and
25 * limitations under the License.
26 */
27
28#if defined ( __ICCARM__ )
29 #pragma system_include /* treat file as system include file for MISRA check */
30#elif defined (__clang__)
31 #pragma clang system_header /* treat file as system include file */
32#elif defined ( __GNUC__ )
33 #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
34#endif
35
36#ifndef __CORE_CM33_H_GENERIC
37#define __CORE_CM33_H_GENERIC
38
39#include <stdint.h>
40
41#ifdef __cplusplus
42 extern "C" {
43#endif
44
60/*******************************************************************************
61 * CMSIS definitions
62 ******************************************************************************/
68#include "cmsis_version.h"
69
70/* CMSIS CM33 definitions */
71#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
72#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
73#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
74 __CM33_CMSIS_VERSION_SUB )
76#define __CORTEX_M (33U)
81#if defined ( __CC_ARM )
82 #if defined (__TARGET_FPU_VFP)
83 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
84 #define __FPU_USED 1U
85 #else
86 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
87 #define __FPU_USED 0U
88 #endif
89 #else
90 #define __FPU_USED 0U
91 #endif
92
93 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
94 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
95 #define __DSP_USED 1U
96 #else
97 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
98 #define __DSP_USED 0U
99 #endif
100 #else
101 #define __DSP_USED 0U
102 #endif
103
104#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
105 #if defined (__ARM_FP)
106 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
107 #define __FPU_USED 1U
108 #else
109 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
110 #define __FPU_USED 0U
111 #endif
112 #else
113 #define __FPU_USED 0U
114 #endif
115
116 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
117 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
118 #define __DSP_USED 1U
119 #else
120 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
121 #define __DSP_USED 0U
122 #endif
123 #else
124 #define __DSP_USED 0U
125 #endif
126
127#elif defined (__ti__)
128 #if defined (__ARM_FP)
129 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
130 #define __FPU_USED 1U
131 #else
132 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
133 #define __FPU_USED 0U
134 #endif
135 #else
136 #define __FPU_USED 0U
137 #endif
138
139 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
140 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
141 #define __DSP_USED 1U
142 #else
143 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
144 #define __DSP_USED 0U
145 #endif
146 #else
147 #define __DSP_USED 0U
148 #endif
149
150#elif defined ( __GNUC__ )
151 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
152 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
153 #define __FPU_USED 1U
154 #else
155 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
156 #define __FPU_USED 0U
157 #endif
158 #else
159 #define __FPU_USED 0U
160 #endif
161
162 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
163 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
164 #define __DSP_USED 1U
165 #else
166 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
167 #define __DSP_USED 0U
168 #endif
169 #else
170 #define __DSP_USED 0U
171 #endif
172
173#elif defined ( __ICCARM__ )
174 #if defined (__ARMVFP__)
175 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
176 #define __FPU_USED 1U
177 #else
178 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
179 #define __FPU_USED 0U
180 #endif
181 #else
182 #define __FPU_USED 0U
183 #endif
184
185 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
186 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
187 #define __DSP_USED 1U
188 #else
189 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
190 #define __DSP_USED 0U
191 #endif
192 #else
193 #define __DSP_USED 0U
194 #endif
195
196#elif defined ( __TI_ARM__ )
197 #if defined (__TI_VFP_SUPPORT__)
198 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
199 #define __FPU_USED 1U
200 #else
201 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
202 #define __FPU_USED 0U
203 #endif
204 #else
205 #define __FPU_USED 0U
206 #endif
207
208#elif defined ( __TASKING__ )
209 #if defined (__FPU_VFP__)
210 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
211 #define __FPU_USED 1U
212 #else
213 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
214 #define __FPU_USED 0U
215 #endif
216 #else
217 #define __FPU_USED 0U
218 #endif
219
220#elif defined ( __CSMC__ )
221 #if ( __CSMC__ & 0x400U)
222 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
223 #define __FPU_USED 1U
224 #else
225 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
226 #define __FPU_USED 0U
227 #endif
228 #else
229 #define __FPU_USED 0U
230 #endif
231
232#endif
233
234#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
235
236
237#ifdef __cplusplus
238}
239#endif
240
241#endif /* __CORE_CM33_H_GENERIC */
242
243#ifndef __CMSIS_GENERIC
244
245#ifndef __CORE_CM33_H_DEPENDANT
246#define __CORE_CM33_H_DEPENDANT
247
248#ifdef __cplusplus
249 extern "C" {
250#endif
251
252/* check device defines and use defaults */
253#if defined __CHECK_DEVICE_DEFINES
254 #ifndef __CM33_REV
255 #define __CM33_REV 0x0000U
256 #warning "__CM33_REV not defined in device header file; using default!"
257 #endif
258
259 #ifndef __FPU_PRESENT
260 #define __FPU_PRESENT 0U
261 #warning "__FPU_PRESENT not defined in device header file; using default!"
262 #endif
263
264 #ifndef __MPU_PRESENT
265 #define __MPU_PRESENT 0U
266 #warning "__MPU_PRESENT not defined in device header file; using default!"
267 #endif
268
269 #ifndef __SAUREGION_PRESENT
270 #define __SAUREGION_PRESENT 0U
271 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
272 #endif
273
274 #ifndef __DSP_PRESENT
275 #define __DSP_PRESENT 0U
276 #warning "__DSP_PRESENT not defined in device header file; using default!"
277 #endif
278
279 #ifndef __VTOR_PRESENT
280 #define __VTOR_PRESENT 1U
281 #warning "__VTOR_PRESENT not defined in device header file; using default!"
282 #endif
283
284 #ifndef __NVIC_PRIO_BITS
285 #define __NVIC_PRIO_BITS 3U
286 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
287 #endif
288
289 #ifndef __Vendor_SysTickConfig
290 #define __Vendor_SysTickConfig 0U
291 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
292 #endif
293#endif
294
295/* IO definitions (access restrictions to peripheral registers) */
303#ifdef __cplusplus
304 #define __I volatile
305#else
306 #define __I volatile const
307#endif
308#define __O volatile
309#define __IO volatile
311/* following defines should be used for structure members */
312#define __IM volatile const
313#define __OM volatile
314#define __IOM volatile
320/*******************************************************************************
321 * Register Abstraction
322 Core Register contain:
323 - Core Register
324 - Core NVIC Register
325 - Core SCB Register
326 - Core SysTick Register
327 - Core Debug Register
328 - Core MPU Register
329 - Core SAU Register
330 - Core FPU Register
331 ******************************************************************************/
347typedef union
348{
349 struct
350 {
351 uint32_t _reserved0:16;
352 uint32_t GE:4;
353 uint32_t _reserved1:7;
354 uint32_t Q:1;
355 uint32_t V:1;
356 uint32_t C:1;
357 uint32_t Z:1;
358 uint32_t N:1;
359 } b;
360 uint32_t w;
361} APSR_Type;
362
363/* APSR Register Definitions */
364#define APSR_N_Pos 31U
365#define APSR_N_Msk (1UL << APSR_N_Pos)
367#define APSR_Z_Pos 30U
368#define APSR_Z_Msk (1UL << APSR_Z_Pos)
370#define APSR_C_Pos 29U
371#define APSR_C_Msk (1UL << APSR_C_Pos)
373#define APSR_V_Pos 28U
374#define APSR_V_Msk (1UL << APSR_V_Pos)
376#define APSR_Q_Pos 27U
377#define APSR_Q_Msk (1UL << APSR_Q_Pos)
379#define APSR_GE_Pos 16U
380#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)
386typedef union
387{
388 struct
389 {
390 uint32_t ISR:9;
391 uint32_t _reserved0:23;
392 } b;
393 uint32_t w;
394} IPSR_Type;
395
396/* IPSR Register Definitions */
397#define IPSR_ISR_Pos 0U
398#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
404typedef union
405{
406 struct
407 {
408 uint32_t ISR:9;
409 uint32_t _reserved0:7;
410 uint32_t GE:4;
411 uint32_t _reserved1:4;
412 uint32_t T:1;
413 uint32_t IT:2;
414 uint32_t Q:1;
415 uint32_t V:1;
416 uint32_t C:1;
417 uint32_t Z:1;
418 uint32_t N:1;
419 } b;
420 uint32_t w;
421} xPSR_Type;
422
423/* xPSR Register Definitions */
424#define xPSR_N_Pos 31U
425#define xPSR_N_Msk (1UL << xPSR_N_Pos)
427#define xPSR_Z_Pos 30U
428#define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
430#define xPSR_C_Pos 29U
431#define xPSR_C_Msk (1UL << xPSR_C_Pos)
433#define xPSR_V_Pos 28U
434#define xPSR_V_Msk (1UL << xPSR_V_Pos)
436#define xPSR_Q_Pos 27U
437#define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
439#define xPSR_IT_Pos 25U
440#define xPSR_IT_Msk (3UL << xPSR_IT_Pos)
442#define xPSR_T_Pos 24U
443#define xPSR_T_Msk (1UL << xPSR_T_Pos)
445#define xPSR_GE_Pos 16U
446#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
448#define xPSR_ISR_Pos 0U
449#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
455typedef union
456{
457 struct
458 {
459 uint32_t nPRIV:1;
460 uint32_t SPSEL:1;
461 uint32_t FPCA:1;
462 uint32_t SFPA:1;
463 uint32_t _reserved1:28;
464 } b;
465 uint32_t w;
466} CONTROL_Type;
467
468/* CONTROL Register Definitions */
469#define CONTROL_SFPA_Pos 3U
470#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)
472#define CONTROL_FPCA_Pos 2U
473#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
475#define CONTROL_SPSEL_Pos 1U
476#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
478#define CONTROL_nPRIV_Pos 0U
479#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
494typedef struct
495{
496 __IOM uint32_t ISER[16U];
497 uint32_t RESERVED0[16U];
498 __IOM uint32_t ICER[16U];
499 uint32_t RSERVED1[16U];
500 __IOM uint32_t ISPR[16U];
501 uint32_t RESERVED2[16U];
502 __IOM uint32_t ICPR[16U];
503 uint32_t RESERVED3[16U];
504 __IOM uint32_t IABR[16U];
505 uint32_t RESERVED4[16U];
506 __IOM uint32_t ITNS[16U];
507 uint32_t RESERVED5[16U];
508 __IOM uint8_t IPR[496U];
509 uint32_t RESERVED6[580U];
510 __OM uint32_t STIR;
511} NVIC_Type;
512
513/* Software Triggered Interrupt Register Definitions */
514#define NVIC_STIR_INTID_Pos 0U
515#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
530typedef struct
531{
532 __IM uint32_t CPUID;
533 __IOM uint32_t ICSR;
534 __IOM uint32_t VTOR;
535 __IOM uint32_t AIRCR;
536 __IOM uint32_t SCR;
537 __IOM uint32_t CCR;
538 __IOM uint8_t SHPR[12U];
539 __IOM uint32_t SHCSR;
540 __IOM uint32_t CFSR;
541 __IOM uint32_t HFSR;
542 __IOM uint32_t DFSR;
543 __IOM uint32_t MMFAR;
544 __IOM uint32_t BFAR;
545 __IOM uint32_t AFSR;
546 __IM uint32_t ID_PFR[2U];
547 __IM uint32_t ID_DFR;
548 __IM uint32_t ID_AFR;
549 __IM uint32_t ID_MMFR[4U];
550 __IM uint32_t ID_ISAR[6U];
551 __IM uint32_t CLIDR;
552 __IM uint32_t CTR;
553 __IM uint32_t CCSIDR;
554 __IOM uint32_t CSSELR;
555 __IOM uint32_t CPACR;
556 __IOM uint32_t NSACR;
557 uint32_t RESERVED7[21U];
558 __IOM uint32_t SFSR;
559 __IOM uint32_t SFAR;
560 uint32_t RESERVED3[69U];
561 __OM uint32_t STIR;
562 uint32_t RESERVED4[15U];
563 __IM uint32_t MVFR0;
564 __IM uint32_t MVFR1;
565 __IM uint32_t MVFR2;
566 uint32_t RESERVED5[1U];
567 __OM uint32_t ICIALLU;
568 uint32_t RESERVED6[1U];
569 __OM uint32_t ICIMVAU;
570 __OM uint32_t DCIMVAC;
571 __OM uint32_t DCISW;
572 __OM uint32_t DCCMVAU;
573 __OM uint32_t DCCMVAC;
574 __OM uint32_t DCCSW;
575 __OM uint32_t DCCIMVAC;
576 __OM uint32_t DCCISW;
577 __OM uint32_t BPIALL;
578} SCB_Type;
579
580/* SCB CPUID Register Definitions */
581#define SCB_CPUID_IMPLEMENTER_Pos 24U
582#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
584#define SCB_CPUID_VARIANT_Pos 20U
585#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
587#define SCB_CPUID_ARCHITECTURE_Pos 16U
588#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
590#define SCB_CPUID_PARTNO_Pos 4U
591#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
593#define SCB_CPUID_REVISION_Pos 0U
594#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
596/* SCB Interrupt Control State Register Definitions */
597#define SCB_ICSR_PENDNMISET_Pos 31U
598#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)
600#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos
601#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk
603#define SCB_ICSR_PENDNMICLR_Pos 30U
604#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)
606#define SCB_ICSR_PENDSVSET_Pos 28U
607#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
609#define SCB_ICSR_PENDSVCLR_Pos 27U
610#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
612#define SCB_ICSR_PENDSTSET_Pos 26U
613#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
615#define SCB_ICSR_PENDSTCLR_Pos 25U
616#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
618#define SCB_ICSR_STTNS_Pos 24U
619#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)
621#define SCB_ICSR_ISRPREEMPT_Pos 23U
622#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
624#define SCB_ICSR_ISRPENDING_Pos 22U
625#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
627#define SCB_ICSR_VECTPENDING_Pos 12U
628#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
630#define SCB_ICSR_RETTOBASE_Pos 11U
631#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
633#define SCB_ICSR_VECTACTIVE_Pos 0U
634#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
636/* SCB Vector Table Offset Register Definitions */
637#define SCB_VTOR_TBLOFF_Pos 7U
638#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
640/* SCB Application Interrupt and Reset Control Register Definitions */
641#define SCB_AIRCR_VECTKEY_Pos 16U
642#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
644#define SCB_AIRCR_VECTKEYSTAT_Pos 16U
645#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
647#define SCB_AIRCR_ENDIANESS_Pos 15U
648#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
650#define SCB_AIRCR_PRIS_Pos 14U
651#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)
653#define SCB_AIRCR_BFHFNMINS_Pos 13U
654#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)
656#define SCB_AIRCR_PRIGROUP_Pos 8U
657#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
659#define SCB_AIRCR_SYSRESETREQS_Pos 3U
660#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
662#define SCB_AIRCR_SYSRESETREQ_Pos 2U
663#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
665#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
666#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
668/* SCB System Control Register Definitions */
669#define SCB_SCR_SEVONPEND_Pos 4U
670#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
672#define SCB_SCR_SLEEPDEEPS_Pos 3U
673#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)
675#define SCB_SCR_SLEEPDEEP_Pos 2U
676#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
678#define SCB_SCR_SLEEPONEXIT_Pos 1U
679#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
681/* SCB Configuration Control Register Definitions */
682#define SCB_CCR_BP_Pos 18U
683#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
685#define SCB_CCR_IC_Pos 17U
686#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
688#define SCB_CCR_DC_Pos 16U
689#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
691#define SCB_CCR_STKOFHFNMIGN_Pos 10U
692#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
694#define SCB_CCR_BFHFNMIGN_Pos 8U
695#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
697#define SCB_CCR_DIV_0_TRP_Pos 4U
698#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
700#define SCB_CCR_UNALIGN_TRP_Pos 3U
701#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
703#define SCB_CCR_USERSETMPEND_Pos 1U
704#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
706/* SCB System Handler Control and State Register Definitions */
707#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U
708#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
710#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U
711#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
713#define SCB_SHCSR_SECUREFAULTENA_Pos 19U
714#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
716#define SCB_SHCSR_USGFAULTENA_Pos 18U
717#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
719#define SCB_SHCSR_BUSFAULTENA_Pos 17U
720#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
722#define SCB_SHCSR_MEMFAULTENA_Pos 16U
723#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
725#define SCB_SHCSR_SVCALLPENDED_Pos 15U
726#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
728#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
729#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
731#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
732#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
734#define SCB_SHCSR_USGFAULTPENDED_Pos 12U
735#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
737#define SCB_SHCSR_SYSTICKACT_Pos 11U
738#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
740#define SCB_SHCSR_PENDSVACT_Pos 10U
741#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
743#define SCB_SHCSR_MONITORACT_Pos 8U
744#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
746#define SCB_SHCSR_SVCALLACT_Pos 7U
747#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
749#define SCB_SHCSR_NMIACT_Pos 5U
750#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)
752#define SCB_SHCSR_SECUREFAULTACT_Pos 4U
753#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
755#define SCB_SHCSR_USGFAULTACT_Pos 3U
756#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
758#define SCB_SHCSR_HARDFAULTACT_Pos 2U
759#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
761#define SCB_SHCSR_BUSFAULTACT_Pos 1U
762#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
764#define SCB_SHCSR_MEMFAULTACT_Pos 0U
765#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
767/* SCB Configurable Fault Status Register Definitions */
768#define SCB_CFSR_USGFAULTSR_Pos 16U
769#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
771#define SCB_CFSR_BUSFAULTSR_Pos 8U
772#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
774#define SCB_CFSR_MEMFAULTSR_Pos 0U
775#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
777/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
778#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U)
779#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
781#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U)
782#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)
784#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U)
785#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
787#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U)
788#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
790#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U)
791#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
793#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U)
794#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
796/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
797#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
798#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
800#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)
801#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)
803#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
804#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
806#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
807#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
809#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
810#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
812#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
813#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
815#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
816#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
818/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
819#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
820#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
822#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
823#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
825#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)
826#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)
828#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
829#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
831#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
832#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
834#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
835#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
837#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
838#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
840/* SCB Hard Fault Status Register Definitions */
841#define SCB_HFSR_DEBUGEVT_Pos 31U
842#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
844#define SCB_HFSR_FORCED_Pos 30U
845#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
847#define SCB_HFSR_VECTTBL_Pos 1U
848#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
850/* SCB Debug Fault Status Register Definitions */
851#define SCB_DFSR_EXTERNAL_Pos 4U
852#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
854#define SCB_DFSR_VCATCH_Pos 3U
855#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
857#define SCB_DFSR_DWTTRAP_Pos 2U
858#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
860#define SCB_DFSR_BKPT_Pos 1U
861#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
863#define SCB_DFSR_HALTED_Pos 0U
864#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
866/* SCB Non-Secure Access Control Register Definitions */
867#define SCB_NSACR_CP11_Pos 11U
868#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)
870#define SCB_NSACR_CP10_Pos 10U
871#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)
873#define SCB_NSACR_CPn_Pos 0U
874#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/)
876/* SCB Cache Level ID Register Definitions */
877#define SCB_CLIDR_LOUU_Pos 27U
878#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
880#define SCB_CLIDR_LOC_Pos 24U
881#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)
883/* SCB Cache Type Register Definitions */
884#define SCB_CTR_FORMAT_Pos 29U
885#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
887#define SCB_CTR_CWG_Pos 24U
888#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
890#define SCB_CTR_ERG_Pos 20U
891#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
893#define SCB_CTR_DMINLINE_Pos 16U
894#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
896#define SCB_CTR_IMINLINE_Pos 0U
897#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
899/* SCB Cache Size ID Register Definitions */
900#define SCB_CCSIDR_WT_Pos 31U
901#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)
903#define SCB_CCSIDR_WB_Pos 30U
904#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)
906#define SCB_CCSIDR_RA_Pos 29U
907#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)
909#define SCB_CCSIDR_WA_Pos 28U
910#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)
912#define SCB_CCSIDR_NUMSETS_Pos 13U
913#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
915#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U
916#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
918#define SCB_CCSIDR_LINESIZE_Pos 0U
919#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
921/* SCB Cache Size Selection Register Definitions */
922#define SCB_CSSELR_LEVEL_Pos 1U
923#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)
925#define SCB_CSSELR_IND_Pos 0U
926#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)
928/* SCB Software Triggered Interrupt Register Definitions */
929#define SCB_STIR_INTID_Pos 0U
930#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
932/* SCB D-Cache Invalidate by Set-way Register Definitions */
933#define SCB_DCISW_WAY_Pos 30U
934#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)
936#define SCB_DCISW_SET_Pos 5U
937#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)
939/* SCB D-Cache Clean by Set-way Register Definitions */
940#define SCB_DCCSW_WAY_Pos 30U
941#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)
943#define SCB_DCCSW_SET_Pos 5U
944#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)
946/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
947#define SCB_DCCISW_WAY_Pos 30U
948#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)
950#define SCB_DCCISW_SET_Pos 5U
951#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)
966typedef struct
967{
968 uint32_t RESERVED0[1U];
969 __IM uint32_t ICTR;
970 __IOM uint32_t ACTLR;
971 __IOM uint32_t CPPWR;
972} SCnSCB_Type;
973
974/* Interrupt Controller Type Register Definitions */
975#define SCnSCB_ICTR_INTLINESNUM_Pos 0U
976#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
991typedef struct
992{
993 __IOM uint32_t CTRL;
994 __IOM uint32_t LOAD;
995 __IOM uint32_t VAL;
996 __IM uint32_t CALIB;
997} SysTick_Type;
998
999/* SysTick Control / Status Register Definitions */
1000#define SysTick_CTRL_COUNTFLAG_Pos 16U
1001#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
1003#define SysTick_CTRL_CLKSOURCE_Pos 2U
1004#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
1006#define SysTick_CTRL_TICKINT_Pos 1U
1007#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
1009#define SysTick_CTRL_ENABLE_Pos 0U
1010#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
1012/* SysTick Reload Register Definitions */
1013#define SysTick_LOAD_RELOAD_Pos 0U
1014#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
1016/* SysTick Current Register Definitions */
1017#define SysTick_VAL_CURRENT_Pos 0U
1018#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
1020/* SysTick Calibration Register Definitions */
1021#define SysTick_CALIB_NOREF_Pos 31U
1022#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
1024#define SysTick_CALIB_SKEW_Pos 30U
1025#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
1027#define SysTick_CALIB_TENMS_Pos 0U
1028#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
1043typedef struct
1044{
1045 __OM union
1046 {
1047 __OM uint8_t u8;
1048 __OM uint16_t u16;
1049 __OM uint32_t u32;
1050 } PORT [32U];
1051 uint32_t RESERVED0[864U];
1052 __IOM uint32_t TER;
1053 uint32_t RESERVED1[15U];
1054 __IOM uint32_t TPR;
1055 uint32_t RESERVED2[15U];
1056 __IOM uint32_t TCR;
1057 uint32_t RESERVED3[32U];
1058 uint32_t RESERVED4[43U];
1059 __OM uint32_t LAR;
1060 __IM uint32_t LSR;
1061 uint32_t RESERVED5[1U];
1062 __IM uint32_t DEVARCH;
1063 uint32_t RESERVED6[4U];
1064 __IM uint32_t PID4;
1065 __IM uint32_t PID5;
1066 __IM uint32_t PID6;
1067 __IM uint32_t PID7;
1068 __IM uint32_t PID0;
1069 __IM uint32_t PID1;
1070 __IM uint32_t PID2;
1071 __IM uint32_t PID3;
1072 __IM uint32_t CID0;
1073 __IM uint32_t CID1;
1074 __IM uint32_t CID2;
1075 __IM uint32_t CID3;
1076} ITM_Type;
1077
1078/* ITM Stimulus Port Register Definitions */
1079#define ITM_STIM_DISABLED_Pos 1U
1080#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)
1082#define ITM_STIM_FIFOREADY_Pos 0U
1083#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
1085/* ITM Trace Privilege Register Definitions */
1086#define ITM_TPR_PRIVMASK_Pos 0U
1087#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
1089/* ITM Trace Control Register Definitions */
1090#define ITM_TCR_BUSY_Pos 23U
1091#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
1093#define ITM_TCR_TRACEBUSID_Pos 16U
1094#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
1096#define ITM_TCR_GTSFREQ_Pos 10U
1097#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
1099#define ITM_TCR_TSPRESCALE_Pos 8U
1100#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)
1102#define ITM_TCR_STALLENA_Pos 5U
1103#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)
1105#define ITM_TCR_SWOENA_Pos 4U
1106#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
1108#define ITM_TCR_DWTENA_Pos 3U
1109#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
1111#define ITM_TCR_SYNCENA_Pos 2U
1112#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
1114#define ITM_TCR_TSENA_Pos 1U
1115#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
1117#define ITM_TCR_ITMENA_Pos 0U
1118#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
1120/* ITM Lock Status Register Definitions */
1121#define ITM_LSR_ByteAcc_Pos 2U
1122#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
1124#define ITM_LSR_Access_Pos 1U
1125#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
1127#define ITM_LSR_Present_Pos 0U
1128#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /* end of group CMSIS_ITM */
1131
1132
1143typedef struct
1144{
1145 __IOM uint32_t CTRL;
1146 __IOM uint32_t CYCCNT;
1147 __IOM uint32_t CPICNT;
1148 __IOM uint32_t EXCCNT;
1149 __IOM uint32_t SLEEPCNT;
1150 __IOM uint32_t LSUCNT;
1151 __IOM uint32_t FOLDCNT;
1152 __IM uint32_t PCSR;
1153 __IOM uint32_t COMP0;
1154 uint32_t RESERVED1[1U];
1155 __IOM uint32_t FUNCTION0;
1156 uint32_t RESERVED2[1U];
1157 __IOM uint32_t COMP1;
1158 uint32_t RESERVED3[1U];
1159 __IOM uint32_t FUNCTION1;
1160 uint32_t RESERVED4[1U];
1161 __IOM uint32_t COMP2;
1162 uint32_t RESERVED5[1U];
1163 __IOM uint32_t FUNCTION2;
1164 uint32_t RESERVED6[1U];
1165 __IOM uint32_t COMP3;
1166 uint32_t RESERVED7[1U];
1167 __IOM uint32_t FUNCTION3;
1168 uint32_t RESERVED8[1U];
1169 __IOM uint32_t COMP4;
1170 uint32_t RESERVED9[1U];
1171 __IOM uint32_t FUNCTION4;
1172 uint32_t RESERVED10[1U];
1173 __IOM uint32_t COMP5;
1174 uint32_t RESERVED11[1U];
1175 __IOM uint32_t FUNCTION5;
1176 uint32_t RESERVED12[1U];
1177 __IOM uint32_t COMP6;
1178 uint32_t RESERVED13[1U];
1179 __IOM uint32_t FUNCTION6;
1180 uint32_t RESERVED14[1U];
1181 __IOM uint32_t COMP7;
1182 uint32_t RESERVED15[1U];
1183 __IOM uint32_t FUNCTION7;
1184 uint32_t RESERVED16[1U];
1185 __IOM uint32_t COMP8;
1186 uint32_t RESERVED17[1U];
1187 __IOM uint32_t FUNCTION8;
1188 uint32_t RESERVED18[1U];
1189 __IOM uint32_t COMP9;
1190 uint32_t RESERVED19[1U];
1191 __IOM uint32_t FUNCTION9;
1192 uint32_t RESERVED20[1U];
1193 __IOM uint32_t COMP10;
1194 uint32_t RESERVED21[1U];
1195 __IOM uint32_t FUNCTION10;
1196 uint32_t RESERVED22[1U];
1197 __IOM uint32_t COMP11;
1198 uint32_t RESERVED23[1U];
1199 __IOM uint32_t FUNCTION11;
1200 uint32_t RESERVED24[1U];
1201 __IOM uint32_t COMP12;
1202 uint32_t RESERVED25[1U];
1203 __IOM uint32_t FUNCTION12;
1204 uint32_t RESERVED26[1U];
1205 __IOM uint32_t COMP13;
1206 uint32_t RESERVED27[1U];
1207 __IOM uint32_t FUNCTION13;
1208 uint32_t RESERVED28[1U];
1209 __IOM uint32_t COMP14;
1210 uint32_t RESERVED29[1U];
1211 __IOM uint32_t FUNCTION14;
1212 uint32_t RESERVED30[1U];
1213 __IOM uint32_t COMP15;
1214 uint32_t RESERVED31[1U];
1215 __IOM uint32_t FUNCTION15;
1216 uint32_t RESERVED32[934U];
1217 __IM uint32_t LSR;
1218 uint32_t RESERVED33[1U];
1219 __IM uint32_t DEVARCH;
1220} DWT_Type;
1221
1222/* DWT Control Register Definitions */
1223#define DWT_CTRL_NUMCOMP_Pos 28U
1224#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
1226#define DWT_CTRL_NOTRCPKT_Pos 27U
1227#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
1229#define DWT_CTRL_NOEXTTRIG_Pos 26U
1230#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
1232#define DWT_CTRL_NOCYCCNT_Pos 25U
1233#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
1235#define DWT_CTRL_NOPRFCNT_Pos 24U
1236#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
1238#define DWT_CTRL_CYCDISS_Pos 23U
1239#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos)
1241#define DWT_CTRL_CYCEVTENA_Pos 22U
1242#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
1244#define DWT_CTRL_FOLDEVTENA_Pos 21U
1245#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
1247#define DWT_CTRL_LSUEVTENA_Pos 20U
1248#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
1250#define DWT_CTRL_SLEEPEVTENA_Pos 19U
1251#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
1253#define DWT_CTRL_EXCEVTENA_Pos 18U
1254#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
1256#define DWT_CTRL_CPIEVTENA_Pos 17U
1257#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
1259#define DWT_CTRL_EXCTRCENA_Pos 16U
1260#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
1262#define DWT_CTRL_PCSAMPLENA_Pos 12U
1263#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
1265#define DWT_CTRL_SYNCTAP_Pos 10U
1266#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
1268#define DWT_CTRL_CYCTAP_Pos 9U
1269#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
1271#define DWT_CTRL_POSTINIT_Pos 5U
1272#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
1274#define DWT_CTRL_POSTPRESET_Pos 1U
1275#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
1277#define DWT_CTRL_CYCCNTENA_Pos 0U
1278#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
1280/* DWT CPI Count Register Definitions */
1281#define DWT_CPICNT_CPICNT_Pos 0U
1282#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
1284/* DWT Exception Overhead Count Register Definitions */
1285#define DWT_EXCCNT_EXCCNT_Pos 0U
1286#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
1288/* DWT Sleep Count Register Definitions */
1289#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
1290#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
1292/* DWT LSU Count Register Definitions */
1293#define DWT_LSUCNT_LSUCNT_Pos 0U
1294#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
1296/* DWT Folded-instruction Count Register Definitions */
1297#define DWT_FOLDCNT_FOLDCNT_Pos 0U
1298#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
1300/* DWT Comparator Function Register Definitions */
1301#define DWT_FUNCTION_ID_Pos 27U
1302#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)
1304#define DWT_FUNCTION_MATCHED_Pos 24U
1305#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
1307#define DWT_FUNCTION_DATAVSIZE_Pos 10U
1308#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
1310#define DWT_FUNCTION_ACTION_Pos 4U
1311#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos)
1313#define DWT_FUNCTION_MATCH_Pos 0U
1314#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /* end of group CMSIS_DWT */
1317
1318
1329typedef struct
1330{
1331 __IM uint32_t SSPSR;
1332 __IOM uint32_t CSPSR;
1333 uint32_t RESERVED0[2U];
1334 __IOM uint32_t ACPR;
1335 uint32_t RESERVED1[55U];
1336 __IOM uint32_t SPPR;
1337 uint32_t RESERVED2[131U];
1338 __IM uint32_t FFSR;
1339 __IOM uint32_t FFCR;
1340 __IOM uint32_t PSCR;
1341 uint32_t RESERVED3[759U];
1342 __IM uint32_t TRIGGER;
1343 __IM uint32_t ITFTTD0;
1344 __IOM uint32_t ITATBCTR2;
1345 uint32_t RESERVED4[1U];
1346 __IM uint32_t ITATBCTR0;
1347 __IM uint32_t ITFTTD1;
1348 __IOM uint32_t ITCTRL;
1349 uint32_t RESERVED5[39U];
1350 __IOM uint32_t CLAIMSET;
1351 __IOM uint32_t CLAIMCLR;
1352 uint32_t RESERVED7[8U];
1353 __IM uint32_t DEVID;
1354 __IM uint32_t DEVTYPE;
1355} TPI_Type;
1356
1357/* TPI Asynchronous Clock Prescaler Register Definitions */
1358#define TPI_ACPR_PRESCALER_Pos 0U
1359#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
1361/* TPI Selected Pin Protocol Register Definitions */
1362#define TPI_SPPR_TXMODE_Pos 0U
1363#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
1365/* TPI Formatter and Flush Status Register Definitions */
1366#define TPI_FFSR_FtNonStop_Pos 3U
1367#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1369#define TPI_FFSR_TCPresent_Pos 2U
1370#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1372#define TPI_FFSR_FtStopped_Pos 1U
1373#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1375#define TPI_FFSR_FlInProg_Pos 0U
1376#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
1378/* TPI Formatter and Flush Control Register Definitions */
1379#define TPI_FFCR_TrigIn_Pos 8U
1380#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1382#define TPI_FFCR_FOnMan_Pos 6U
1383#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
1385#define TPI_FFCR_EnFCont_Pos 1U
1386#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1388/* TPI TRIGGER Register Definitions */
1389#define TPI_TRIGGER_TRIGGER_Pos 0U
1390#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
1392/* TPI Integration Test FIFO Test Data 0 Register Definitions */
1393#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U
1394#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)
1396#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U
1397#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)
1399#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U
1400#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)
1402#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U
1403#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)
1405#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U
1406#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
1408#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U
1409#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
1411#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U
1412#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/)
1414/* TPI Integration Test ATB Control Register 2 Register Definitions */
1415#define TPI_ITATBCTR2_AFVALID2S_Pos 1U
1416#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)
1418#define TPI_ITATBCTR2_AFVALID1S_Pos 1U
1419#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)
1421#define TPI_ITATBCTR2_ATREADY2S_Pos 0U
1422#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)
1424#define TPI_ITATBCTR2_ATREADY1S_Pos 0U
1425#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)
1427/* TPI Integration Test FIFO Test Data 1 Register Definitions */
1428#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U
1429#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)
1431#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U
1432#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)
1434#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U
1435#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)
1437#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U
1438#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)
1440#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U
1441#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
1443#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U
1444#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
1446#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U
1447#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/)
1449/* TPI Integration Test ATB Control Register 0 Definitions */
1450#define TPI_ITATBCTR0_AFVALID2S_Pos 1U
1451#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)
1453#define TPI_ITATBCTR0_AFVALID1S_Pos 1U
1454#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)
1456#define TPI_ITATBCTR0_ATREADY2S_Pos 0U
1457#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)
1459#define TPI_ITATBCTR0_ATREADY1S_Pos 0U
1460#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)
1462/* TPI Integration Mode Control Register Definitions */
1463#define TPI_ITCTRL_Mode_Pos 0U
1464#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
1466/* TPI DEVID Register Definitions */
1467#define TPI_DEVID_NRZVALID_Pos 11U
1468#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1470#define TPI_DEVID_MANCVALID_Pos 10U
1471#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1473#define TPI_DEVID_PTINVALID_Pos 9U
1474#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1476#define TPI_DEVID_FIFOSZ_Pos 6U
1477#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
1479#define TPI_DEVID_NrTraceInput_Pos 0U
1480#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
1482/* TPI DEVTYPE Register Definitions */
1483#define TPI_DEVTYPE_SubType_Pos 4U
1484#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
1486#define TPI_DEVTYPE_MajorType_Pos 0U
1487#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /* end of group CMSIS_TPI */
1490
1491
1492#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1503typedef struct
1504{
1505 __IM uint32_t TYPE;
1506 __IOM uint32_t CTRL;
1507 __IOM uint32_t RNR;
1508 __IOM uint32_t RBAR;
1509 __IOM uint32_t RLAR;
1510 __IOM uint32_t RBAR_A1;
1511 __IOM uint32_t RLAR_A1;
1512 __IOM uint32_t RBAR_A2;
1513 __IOM uint32_t RLAR_A2;
1514 __IOM uint32_t RBAR_A3;
1515 __IOM uint32_t RLAR_A3;
1516 uint32_t RESERVED0[1];
1517 union {
1518 __IOM uint32_t MAIR[2];
1519 struct {
1520 __IOM uint32_t MAIR0;
1521 __IOM uint32_t MAIR1;
1522 };
1523 };
1524} MPU_Type;
1525
1526#define MPU_TYPE_RALIASES 4U
1527
1528/* MPU Type Register Definitions */
1529#define MPU_TYPE_IREGION_Pos 16U
1530#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1532#define MPU_TYPE_DREGION_Pos 8U
1533#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1535#define MPU_TYPE_SEPARATE_Pos 0U
1536#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
1538/* MPU Control Register Definitions */
1539#define MPU_CTRL_PRIVDEFENA_Pos 2U
1540#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1542#define MPU_CTRL_HFNMIENA_Pos 1U
1543#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1545#define MPU_CTRL_ENABLE_Pos 0U
1546#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
1548/* MPU Region Number Register Definitions */
1549#define MPU_RNR_REGION_Pos 0U
1550#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
1552/* MPU Region Base Address Register Definitions */
1553#define MPU_RBAR_BASE_Pos 5U
1554#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
1556#define MPU_RBAR_SH_Pos 3U
1557#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
1559#define MPU_RBAR_AP_Pos 1U
1560#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
1562#define MPU_RBAR_XN_Pos 0U
1563#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/)
1565/* MPU Region Limit Address Register Definitions */
1566#define MPU_RLAR_LIMIT_Pos 5U
1567#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
1569#define MPU_RLAR_AttrIndx_Pos 1U
1570#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
1572#define MPU_RLAR_EN_Pos 0U
1573#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/)
1575/* MPU Memory Attribute Indirection Register 0 Definitions */
1576#define MPU_MAIR0_Attr3_Pos 24U
1577#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
1579#define MPU_MAIR0_Attr2_Pos 16U
1580#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
1582#define MPU_MAIR0_Attr1_Pos 8U
1583#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
1585#define MPU_MAIR0_Attr0_Pos 0U
1586#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)
1588/* MPU Memory Attribute Indirection Register 1 Definitions */
1589#define MPU_MAIR1_Attr7_Pos 24U
1590#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
1592#define MPU_MAIR1_Attr6_Pos 16U
1593#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
1595#define MPU_MAIR1_Attr5_Pos 8U
1596#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
1598#define MPU_MAIR1_Attr4_Pos 0U
1599#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)
1602#endif
1603
1604
1605#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1616typedef struct
1617{
1618 __IOM uint32_t CTRL;
1619 __IM uint32_t TYPE;
1620#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1621 __IOM uint32_t RNR;
1622 __IOM uint32_t RBAR;
1623 __IOM uint32_t RLAR;
1624#else
1625 uint32_t RESERVED0[3];
1626#endif
1627 __IOM uint32_t SFSR;
1628 __IOM uint32_t SFAR;
1629} SAU_Type;
1630
1631/* SAU Control Register Definitions */
1632#define SAU_CTRL_ALLNS_Pos 1U
1633#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos)
1635#define SAU_CTRL_ENABLE_Pos 0U
1636#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/)
1638/* SAU Type Register Definitions */
1639#define SAU_TYPE_SREGION_Pos 0U
1640#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)
1642#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1643/* SAU Region Number Register Definitions */
1644#define SAU_RNR_REGION_Pos 0U
1645#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/)
1647/* SAU Region Base Address Register Definitions */
1648#define SAU_RBAR_BADDR_Pos 5U
1649#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)
1651/* SAU Region Limit Address Register Definitions */
1652#define SAU_RLAR_LADDR_Pos 5U
1653#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)
1655#define SAU_RLAR_NSC_Pos 1U
1656#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos)
1658#define SAU_RLAR_ENABLE_Pos 0U
1659#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/)
1661#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1662
1663/* Secure Fault Status Register Definitions */
1664#define SAU_SFSR_LSERR_Pos 7U
1665#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos)
1667#define SAU_SFSR_SFARVALID_Pos 6U
1668#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos)
1670#define SAU_SFSR_LSPERR_Pos 5U
1671#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos)
1673#define SAU_SFSR_INVTRAN_Pos 4U
1674#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos)
1676#define SAU_SFSR_AUVIOL_Pos 3U
1677#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos)
1679#define SAU_SFSR_INVER_Pos 2U
1680#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos)
1682#define SAU_SFSR_INVIS_Pos 1U
1683#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos)
1685#define SAU_SFSR_INVEP_Pos 0U
1686#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/)
1689#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1690
1691
1702typedef struct
1703{
1704 uint32_t RESERVED0[1U];
1705 __IOM uint32_t FPCCR;
1706 __IOM uint32_t FPCAR;
1707 __IOM uint32_t FPDSCR;
1708 __IM uint32_t MVFR0;
1709 __IM uint32_t MVFR1;
1710 __IM uint32_t MVFR2;
1711} FPU_Type;
1712
1713/* Floating-Point Context Control Register Definitions */
1714#define FPU_FPCCR_ASPEN_Pos 31U
1715#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
1717#define FPU_FPCCR_LSPEN_Pos 30U
1718#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
1720#define FPU_FPCCR_LSPENS_Pos 29U
1721#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)
1723#define FPU_FPCCR_CLRONRET_Pos 28U
1724#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)
1726#define FPU_FPCCR_CLRONRETS_Pos 27U
1727#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)
1729#define FPU_FPCCR_TS_Pos 26U
1730#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)
1732#define FPU_FPCCR_UFRDY_Pos 10U
1733#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)
1735#define FPU_FPCCR_SPLIMVIOL_Pos 9U
1736#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
1738#define FPU_FPCCR_MONRDY_Pos 8U
1739#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
1741#define FPU_FPCCR_SFRDY_Pos 7U
1742#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)
1744#define FPU_FPCCR_BFRDY_Pos 6U
1745#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
1747#define FPU_FPCCR_MMRDY_Pos 5U
1748#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
1750#define FPU_FPCCR_HFRDY_Pos 4U
1751#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
1753#define FPU_FPCCR_THREAD_Pos 3U
1754#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
1756#define FPU_FPCCR_S_Pos 2U
1757#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)
1759#define FPU_FPCCR_USER_Pos 1U
1760#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
1762#define FPU_FPCCR_LSPACT_Pos 0U
1763#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
1765/* Floating-Point Context Address Register Definitions */
1766#define FPU_FPCAR_ADDRESS_Pos 3U
1767#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
1769/* Floating-Point Default Status Control Register Definitions */
1770#define FPU_FPDSCR_AHP_Pos 26U
1771#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
1773#define FPU_FPDSCR_DN_Pos 25U
1774#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
1776#define FPU_FPDSCR_FZ_Pos 24U
1777#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
1779#define FPU_FPDSCR_RMode_Pos 22U
1780#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
1782/* Media and VFP Feature Register 0 Definitions */
1783#define FPU_MVFR0_FP_rounding_modes_Pos 28U
1784#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
1786#define FPU_MVFR0_Short_vectors_Pos 24U
1787#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
1789#define FPU_MVFR0_Square_root_Pos 20U
1790#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
1792#define FPU_MVFR0_Divide_Pos 16U
1793#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
1795#define FPU_MVFR0_FP_excep_trapping_Pos 12U
1796#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
1798#define FPU_MVFR0_Double_precision_Pos 8U
1799#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
1801#define FPU_MVFR0_Single_precision_Pos 4U
1802#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
1804#define FPU_MVFR0_A_SIMD_registers_Pos 0U
1805#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
1807/* Media and VFP Feature Register 1 Definitions */
1808#define FPU_MVFR1_FP_fused_MAC_Pos 28U
1809#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
1811#define FPU_MVFR1_FP_HPFP_Pos 24U
1812#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
1814#define FPU_MVFR1_D_NaN_mode_Pos 4U
1815#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
1817#define FPU_MVFR1_FtZ_mode_Pos 0U
1818#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
1820/* Media and VFP Feature Register 2 Definitions */
1821#define FPU_MVFR2_FPMisc_Pos 4U
1822#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos)
1826/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
1837typedef struct
1838{
1839 __IOM uint32_t DHCSR;
1840 __OM uint32_t DCRSR;
1841 __IOM uint32_t DCRDR;
1842 __IOM uint32_t DEMCR;
1843 uint32_t RESERVED0[1U];
1844 __IOM uint32_t DAUTHCTRL;
1845 __IOM uint32_t DSCSR;
1846} CoreDebug_Type;
1847
1848/* Debug Halting Control and Status Register Definitions */
1849#define CoreDebug_DHCSR_DBGKEY_Pos 16U
1850#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1852#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U
1853#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
1855#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1856#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1858#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1859#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1861#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1862#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1864#define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1865#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1867#define CoreDebug_DHCSR_S_HALT_Pos 17U
1868#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1870#define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1871#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1873#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
1874#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1876#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1877#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1879#define CoreDebug_DHCSR_C_STEP_Pos 2U
1880#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1882#define CoreDebug_DHCSR_C_HALT_Pos 1U
1883#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1885#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1886#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
1888/* Debug Core Register Selector Register Definitions */
1889#define CoreDebug_DCRSR_REGWnR_Pos 16U
1890#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1892#define CoreDebug_DCRSR_REGSEL_Pos 0U
1893#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
1895/* Debug Exception and Monitor Control Register Definitions */
1896#define CoreDebug_DEMCR_TRCENA_Pos 24U
1897#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1899#define CoreDebug_DEMCR_MON_REQ_Pos 19U
1900#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1902#define CoreDebug_DEMCR_MON_STEP_Pos 18U
1903#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1905#define CoreDebug_DEMCR_MON_PEND_Pos 17U
1906#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1908#define CoreDebug_DEMCR_MON_EN_Pos 16U
1909#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1911#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1912#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1914#define CoreDebug_DEMCR_VC_INTERR_Pos 9U
1915#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1917#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
1918#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1920#define CoreDebug_DEMCR_VC_STATERR_Pos 7U
1921#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1923#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
1924#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1926#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
1927#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1929#define CoreDebug_DEMCR_VC_MMERR_Pos 4U
1930#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1932#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1933#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
1935/* Debug Authentication Control Register Definitions */
1936#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U
1937#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
1939#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U
1940#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
1942#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U
1943#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
1945#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U
1946#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
1948/* Debug Security Control and Status Register Definitions */
1949#define CoreDebug_DSCSR_CDS_Pos 16U
1950#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)
1952#define CoreDebug_DSCSR_SBRSEL_Pos 1U
1953#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
1955#define CoreDebug_DSCSR_SBRSELEN_Pos 0U
1956#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
1971typedef struct
1972{
1973 __IOM uint32_t DHCSR;
1974 __OM uint32_t DCRSR;
1975 __IOM uint32_t DCRDR;
1976 __IOM uint32_t DEMCR;
1977 uint32_t RESERVED0[1U];
1978 __IOM uint32_t DAUTHCTRL;
1979 __IOM uint32_t DSCSR;
1980} DCB_Type;
1981
1982/* DHCSR, Debug Halting Control and Status Register Definitions */
1983#define DCB_DHCSR_DBGKEY_Pos 16U
1984#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
1986#define DCB_DHCSR_S_RESTART_ST_Pos 26U
1987#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
1989#define DCB_DHCSR_S_RESET_ST_Pos 25U
1990#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
1992#define DCB_DHCSR_S_RETIRE_ST_Pos 24U
1993#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
1995#define DCB_DHCSR_S_SDE_Pos 20U
1996#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)
1998#define DCB_DHCSR_S_LOCKUP_Pos 19U
1999#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
2001#define DCB_DHCSR_S_SLEEP_Pos 18U
2002#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
2004#define DCB_DHCSR_S_HALT_Pos 17U
2005#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)
2007#define DCB_DHCSR_S_REGRDY_Pos 16U
2008#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
2010#define DCB_DHCSR_C_SNAPSTALL_Pos 5U
2011#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
2013#define DCB_DHCSR_C_MASKINTS_Pos 3U
2014#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
2016#define DCB_DHCSR_C_STEP_Pos 2U
2017#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)
2019#define DCB_DHCSR_C_HALT_Pos 1U
2020#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)
2022#define DCB_DHCSR_C_DEBUGEN_Pos 0U
2023#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
2025/* DCRSR, Debug Core Register Select Register Definitions */
2026#define DCB_DCRSR_REGWnR_Pos 16U
2027#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)
2029#define DCB_DCRSR_REGSEL_Pos 0U
2030#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
2032/* DCRDR, Debug Core Register Data Register Definitions */
2033#define DCB_DCRDR_DBGTMP_Pos 0U
2034#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
2036/* DEMCR, Debug Exception and Monitor Control Register Definitions */
2037#define DCB_DEMCR_TRCENA_Pos 24U
2038#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)
2040#define DCB_DEMCR_MONPRKEY_Pos 23U
2041#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
2043#define DCB_DEMCR_UMON_EN_Pos 21U
2044#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos)
2046#define DCB_DEMCR_SDME_Pos 20U
2047#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos)
2049#define DCB_DEMCR_MON_REQ_Pos 19U
2050#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos)
2052#define DCB_DEMCR_MON_STEP_Pos 18U
2053#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos)
2055#define DCB_DEMCR_MON_PEND_Pos 17U
2056#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos)
2058#define DCB_DEMCR_MON_EN_Pos 16U
2059#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos)
2061#define DCB_DEMCR_VC_SFERR_Pos 11U
2062#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
2064#define DCB_DEMCR_VC_HARDERR_Pos 10U
2065#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
2067#define DCB_DEMCR_VC_INTERR_Pos 9U
2068#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
2070#define DCB_DEMCR_VC_BUSERR_Pos 8U
2071#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
2073#define DCB_DEMCR_VC_STATERR_Pos 7U
2074#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
2076#define DCB_DEMCR_VC_CHKERR_Pos 6U
2077#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
2079#define DCB_DEMCR_VC_NOCPERR_Pos 5U
2080#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
2082#define DCB_DEMCR_VC_MMERR_Pos 4U
2083#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
2085#define DCB_DEMCR_VC_CORERESET_Pos 0U
2086#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
2088/* DAUTHCTRL, Debug Authentication Control Register Definitions */
2089#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U
2090#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
2092#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U
2093#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
2095#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U
2096#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
2098#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U
2099#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
2101/* DSCSR, Debug Security Control and Status Register Definitions */
2102#define DCB_DSCSR_CDSKEY_Pos 17U
2103#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)
2105#define DCB_DSCSR_CDS_Pos 16U
2106#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)
2108#define DCB_DSCSR_SBRSEL_Pos 1U
2109#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)
2111#define DCB_DSCSR_SBRSELEN_Pos 0U
2112#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
2128typedef struct
2129{
2130 __OM uint32_t DLAR;
2131 __IM uint32_t DLSR;
2132 __IM uint32_t DAUTHSTATUS;
2133 __IM uint32_t DDEVARCH;
2134 __IM uint32_t DDEVTYPE;
2135} DIB_Type;
2136
2137/* DLAR, SCS Software Lock Access Register Definitions */
2138#define DIB_DLAR_KEY_Pos 0U
2139#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */)
2141/* DLSR, SCS Software Lock Status Register Definitions */
2142#define DIB_DLSR_nTT_Pos 2U
2143#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos )
2145#define DIB_DLSR_SLK_Pos 1U
2146#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos )
2148#define DIB_DLSR_SLI_Pos 0U
2149#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/)
2151/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
2152#define DIB_DAUTHSTATUS_SNID_Pos 6U
2153#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )
2155#define DIB_DAUTHSTATUS_SID_Pos 4U
2156#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos )
2158#define DIB_DAUTHSTATUS_NSNID_Pos 2U
2159#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )
2161#define DIB_DAUTHSTATUS_NSID_Pos 0U
2162#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)
2164/* DDEVARCH, SCS Device Architecture Register Definitions */
2165#define DIB_DDEVARCH_ARCHITECT_Pos 21U
2166#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )
2168#define DIB_DDEVARCH_PRESENT_Pos 20U
2169#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )
2171#define DIB_DDEVARCH_REVISION_Pos 16U
2172#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos )
2174#define DIB_DDEVARCH_ARCHVER_Pos 12U
2175#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )
2177#define DIB_DDEVARCH_ARCHPART_Pos 0U
2178#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)
2180/* DDEVTYPE, SCS Device Type Register Definitions */
2181#define DIB_DDEVTYPE_SUB_Pos 4U
2182#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos )
2184#define DIB_DDEVTYPE_MAJOR_Pos 0U
2185#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)
2204#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
2205
2212#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
2213
2224/* Memory mapping of Core Hardware */
2225 #define SCS_BASE (0xE000E000UL)
2226 #define ITM_BASE (0xE0000000UL)
2227 #define DWT_BASE (0xE0001000UL)
2228 #define TPI_BASE (0xE0040000UL)
2229 #define CoreDebug_BASE (0xE000EDF0UL)
2230 #define DCB_BASE (0xE000EDF0UL)
2231 #define DIB_BASE (0xE000EFB0UL)
2232 #define SysTick_BASE (SCS_BASE + 0x0010UL)
2233 #define NVIC_BASE (SCS_BASE + 0x0100UL)
2234 #define SCB_BASE (SCS_BASE + 0x0D00UL)
2236 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
2237 #define SCB ((SCB_Type *) SCB_BASE )
2238 #define SysTick ((SysTick_Type *) SysTick_BASE )
2239 #define NVIC ((NVIC_Type *) NVIC_BASE )
2240 #define ITM ((ITM_Type *) ITM_BASE )
2241 #define DWT ((DWT_Type *) DWT_BASE )
2242 #define TPI ((TPI_Type *) TPI_BASE )
2243 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )
2244 #define DCB ((DCB_Type *) DCB_BASE )
2245 #define DIB ((DIB_Type *) DIB_BASE )
2247 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2248 #define MPU_BASE (SCS_BASE + 0x0D90UL)
2249 #define MPU ((MPU_Type *) MPU_BASE )
2250 #endif
2251
2252 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2253 #define SAU_BASE (SCS_BASE + 0x0DD0UL)
2254 #define SAU ((SAU_Type *) SAU_BASE )
2255 #endif
2256
2257 #define FPU_BASE (SCS_BASE + 0x0F30UL)
2258 #define FPU ((FPU_Type *) FPU_BASE )
2260#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2261 #define SCS_BASE_NS (0xE002E000UL)
2262 #define CoreDebug_BASE_NS (0xE002EDF0UL)
2263 #define DCB_BASE_NS (0xE002EDF0UL)
2264 #define DIB_BASE_NS (0xE002EFB0UL)
2265 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL)
2266 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL)
2267 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL)
2269 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS )
2270 #define SCB_NS ((SCB_Type *) SCB_BASE_NS )
2271 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS )
2272 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS )
2273 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS)
2274 #define DCB_NS ((DCB_Type *) DCB_BASE_NS )
2275 #define DIB_NS ((DIB_Type *) DIB_BASE_NS )
2277 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2278 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL)
2279 #define MPU_NS ((MPU_Type *) MPU_BASE_NS )
2280 #endif
2281
2282 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL)
2283 #define FPU_NS ((FPU_Type *) FPU_BASE_NS )
2285#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2295#define ID_ADR (ID_AFR)
2299/*******************************************************************************
2300 * Hardware Abstraction Layer
2301 Core Function Interface contains:
2302 - Core NVIC Functions
2303 - Core SysTick Functions
2304 - Core Debug Functions
2305 - Core Register Access Functions
2306 ******************************************************************************/
2313/* ########################## NVIC functions #################################### */
2321#ifdef CMSIS_NVIC_VIRTUAL
2322 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
2323 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
2324 #endif
2325 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
2326#else
2327 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
2328 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
2329 #define NVIC_EnableIRQ __NVIC_EnableIRQ
2330 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
2331 #define NVIC_DisableIRQ __NVIC_DisableIRQ
2332 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
2333 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
2334 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
2335 #define NVIC_GetActive __NVIC_GetActive
2336 #define NVIC_SetPriority __NVIC_SetPriority
2337 #define NVIC_GetPriority __NVIC_GetPriority
2338 #define NVIC_SystemReset __NVIC_SystemReset
2339#endif /* CMSIS_NVIC_VIRTUAL */
2340
2341#ifdef CMSIS_VECTAB_VIRTUAL
2342 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2343 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
2344 #endif
2345 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2346#else
2347 #define NVIC_SetVector __NVIC_SetVector
2348 #define NVIC_GetVector __NVIC_GetVector
2349#endif /* (CMSIS_VECTAB_VIRTUAL) */
2350
2351#define NVIC_USER_IRQ_OFFSET 16
2352
2353
2354/* Special LR values for Secure/Non-Secure call handling and exception handling */
2355
2356/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
2357#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
2358
2359/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
2360#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
2361#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
2362#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
2363#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
2364#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
2365#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
2366#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
2367
2368/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
2369#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
2370#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
2371#else
2372#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
2373#endif
2374
2375
2385__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
2386{
2387 uint32_t reg_value;
2388 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2389
2390 reg_value = SCB->AIRCR; /* read old register configuration */
2391 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2392 reg_value = (reg_value |
2393 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2394 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2395 SCB->AIRCR = reg_value;
2396}
2397
2398
2404__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
2405{
2406 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2407}
2408
2409
2416__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
2417{
2418 if ((int32_t)(IRQn) >= 0)
2419 {
2420 __COMPILER_BARRIER();
2421 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2422 __COMPILER_BARRIER();
2423 }
2424}
2425
2426
2435__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
2436{
2437 if ((int32_t)(IRQn) >= 0)
2438 {
2439 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2440 }
2441 else
2442 {
2443 return(0U);
2444 }
2445}
2446
2447
2454__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
2455{
2456 if ((int32_t)(IRQn) >= 0)
2457 {
2458 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2459 __DSB();
2460 __ISB();
2461 }
2462}
2463
2464
2473__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2474{
2475 if ((int32_t)(IRQn) >= 0)
2476 {
2477 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2478 }
2479 else
2480 {
2481 return(0U);
2482 }
2483}
2484
2485
2492__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2493{
2494 if ((int32_t)(IRQn) >= 0)
2495 {
2496 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2497 }
2498}
2499
2500
2507__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2508{
2509 if ((int32_t)(IRQn) >= 0)
2510 {
2511 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2512 }
2513}
2514
2515
2524__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2525{
2526 if ((int32_t)(IRQn) >= 0)
2527 {
2528 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2529 }
2530 else
2531 {
2532 return(0U);
2533 }
2534}
2535
2536
2537#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2546__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
2547{
2548 if ((int32_t)(IRQn) >= 0)
2549 {
2550 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2551 }
2552 else
2553 {
2554 return(0U);
2555 }
2556}
2557
2558
2567__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
2568{
2569 if ((int32_t)(IRQn) >= 0)
2570 {
2571 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2572 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2573 }
2574 else
2575 {
2576 return(0U);
2577 }
2578}
2579
2580
2589__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
2590{
2591 if ((int32_t)(IRQn) >= 0)
2592 {
2593 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2594 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2595 }
2596 else
2597 {
2598 return(0U);
2599 }
2600}
2601#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2602
2603
2613__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2614{
2615 if ((int32_t)(IRQn) >= 0)
2616 {
2617 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2618 }
2619 else
2620 {
2621 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2622 }
2623}
2624
2625
2635__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2636{
2637
2638 if ((int32_t)(IRQn) >= 0)
2639 {
2640 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2641 }
2642 else
2643 {
2644 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2645 }
2646}
2647
2648
2660__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2661{
2662 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2663 uint32_t PreemptPriorityBits;
2664 uint32_t SubPriorityBits;
2665
2666 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2667 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2668
2669 return (
2670 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2671 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2672 );
2673}
2674
2675
2687__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2688{
2689 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2690 uint32_t PreemptPriorityBits;
2691 uint32_t SubPriorityBits;
2692
2693 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2694 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2695
2696 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2697 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2698}
2699
2700
2710__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2711{
2712 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2713 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2714 __DSB();
2715}
2716
2717
2726__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2727{
2728 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2729 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2730}
2731
2732
2737__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2738{
2739 __DSB(); /* Ensure all outstanding memory accesses included
2740 buffered write are completed before reset */
2741 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2742 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2743 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2744 __DSB(); /* Ensure completion of memory access */
2745
2746 for(;;) /* wait until reset */
2747 {
2748 __NOP();
2749 }
2750}
2751
2752#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2762__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
2763{
2764 uint32_t reg_value;
2765 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2766
2767 reg_value = SCB_NS->AIRCR; /* read old register configuration */
2768 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2769 reg_value = (reg_value |
2770 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2771 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2772 SCB_NS->AIRCR = reg_value;
2773}
2774
2775
2781__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
2782{
2783 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2784}
2785
2786
2793__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
2794{
2795 if ((int32_t)(IRQn) >= 0)
2796 {
2797 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2798 }
2799}
2800
2801
2810__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
2811{
2812 if ((int32_t)(IRQn) >= 0)
2813 {
2814 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2815 }
2816 else
2817 {
2818 return(0U);
2819 }
2820}
2821
2822
2829__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
2830{
2831 if ((int32_t)(IRQn) >= 0)
2832 {
2833 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2834 }
2835}
2836
2837
2846__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
2847{
2848 if ((int32_t)(IRQn) >= 0)
2849 {
2850 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2851 }
2852 else
2853 {
2854 return(0U);
2855 }
2856}
2857
2858
2865__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
2866{
2867 if ((int32_t)(IRQn) >= 0)
2868 {
2869 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2870 }
2871}
2872
2873
2880__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
2881{
2882 if ((int32_t)(IRQn) >= 0)
2883 {
2884 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2885 }
2886}
2887
2888
2897__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
2898{
2899 if ((int32_t)(IRQn) >= 0)
2900 {
2901 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2902 }
2903 else
2904 {
2905 return(0U);
2906 }
2907}
2908
2909
2919__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2920{
2921 if ((int32_t)(IRQn) >= 0)
2922 {
2923 NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2924 }
2925 else
2926 {
2927 SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2928 }
2929}
2930
2931
2940__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2941{
2942
2943 if ((int32_t)(IRQn) >= 0)
2944 {
2945 return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2946 }
2947 else
2948 {
2949 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2950 }
2951}
2952#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2953
2956/* ########################## MPU functions #################################### */
2957
2958#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2959
2960#include "mpu_armv8.h"
2961
2962#endif
2963
2964#ifdef __rtems__
2965/* ########################## Cache functions #################################### */
2966
2967#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
2968 (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
2969#include "cachel1_armv7.h"
2970#endif
2971
2972#endif /* __rtems__ */
2973/* ########################## FPU functions #################################### */
2989__STATIC_INLINE uint32_t SCB_GetFPUType(void)
2990{
2991 uint32_t mvfr0;
2992
2993 mvfr0 = FPU->MVFR0;
2994 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
2995 {
2996 return 2U; /* Double + Single precision FPU */
2997 }
2998 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2999 {
3000 return 1U; /* Single precision FPU */
3001 }
3002 else
3003 {
3004 return 0U; /* No FPU */
3005 }
3006}
3007
3008
3013/* ########################## SAU functions #################################### */
3021#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3022
3027__STATIC_INLINE void TZ_SAU_Enable(void)
3028{
3029 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
3030}
3031
3032
3033
3038__STATIC_INLINE void TZ_SAU_Disable(void)
3039{
3040 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
3041}
3042
3043#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3044
3050/* ################################## Debug Control function ############################################ */
3064__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
3065{
3066 __DSB();
3067 __ISB();
3068 DCB->DAUTHCTRL = value;
3069 __DSB();
3070 __ISB();
3071}
3072
3073
3079__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
3080{
3081 return (DCB->DAUTHCTRL);
3082}
3083
3084
3085#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3091__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
3092{
3093 __DSB();
3094 __ISB();
3095 DCB_NS->DAUTHCTRL = value;
3096 __DSB();
3097 __ISB();
3098}
3099
3100
3106__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
3107{
3108 return (DCB_NS->DAUTHCTRL);
3109}
3110#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3111
3117/* ################################## Debug Identification function ############################################ */
3131__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
3132{
3133 return (DIB->DAUTHSTATUS);
3134}
3135
3136
3137#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3143__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
3144{
3145 return (DIB_NS->DAUTHSTATUS);
3146}
3147#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3148
3154/* ################################## SysTick function ############################################ */
3162#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
3163
3175__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
3176{
3177 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
3178 {
3179 return (1UL); /* Reload value impossible */
3180 }
3181
3182 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
3183 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
3184 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
3185 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
3186 SysTick_CTRL_TICKINT_Msk |
3187 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
3188 return (0UL); /* Function successful */
3189}
3190
3191#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3204__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
3205{
3206 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
3207 {
3208 return (1UL); /* Reload value impossible */
3209 }
3210
3211 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
3212 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
3213 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
3214 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
3215 SysTick_CTRL_TICKINT_Msk |
3216 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
3217 return (0UL); /* Function successful */
3218}
3219#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3220
3221#endif
3222
3227/* ##################################### Debug In/Output function ########################################### */
3235extern volatile int32_t ITM_RxBuffer;
3236#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
3247__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
3248{
3249 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
3250 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
3251 {
3252 while (ITM->PORT[0U].u32 == 0UL)
3253 {
3254 __NOP();
3255 }
3256 ITM->PORT[0U].u8 = (uint8_t)ch;
3257 }
3258 return (ch);
3259}
3260
3261
3268__STATIC_INLINE int32_t ITM_ReceiveChar (void)
3269{
3270 int32_t ch = -1; /* no character available */
3271
3272 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
3273 {
3274 ch = ITM_RxBuffer;
3275 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
3276 }
3277
3278 return (ch);
3279}
3280
3281
3288__STATIC_INLINE int32_t ITM_CheckChar (void)
3289{
3290
3291 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
3292 {
3293 return (0); /* no character available */
3294 }
3295 else
3296 {
3297 return (1); /* character available */
3298 }
3299}
3300
3306#ifdef __cplusplus
3307}
3308#endif
3309
3310#endif /* __CORE_CM33_H_DEPENDANT */
3311
3312#endif /* __CMSIS_GENERIC */
cachel1_armv7.h
This header file provides CMSIS interfaces.
cmsis_compiler.h
CMSIS compiler generic header file.
cmsis_version.h
CMSIS Core(M) Version definitions.
DCB_SetAuthCtrl
__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
Set Debug Authentication Control Register.
Definition: core_cm33.h:3064
DCB_GetAuthCtrl
__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
Get Debug Authentication Control Register.
Definition: core_cm33.h:3079
DIB_GetAuthStatus
__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
Get Debug Authentication Status Register.
Definition: core_cm33.h:3131
__NOP
#define __NOP()
No Operation.
Definition: cmsis_gcc.h:245
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:286
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:275
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: core_cm33.h:2737
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: core_cm33.h:2710
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_cm33.h:2687
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: core_cm33.h:2726
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm33.h:2613
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm33.h:2507
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm33.h:2473
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_cm33.h:2989
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: core_cm33.h:2416
__NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: core_cm33.h:2404
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_cm33.h:2524
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm33.h:2492
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: core_cm33.h:2435
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_cm33.h:2660
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: core_cm33.h:2454
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm33.h:2635
__NVIC_SetPriorityGrouping
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: core_cm33.h:2385
FPU_MVFR0_Double_precision_Msk
#define FPU_MVFR0_Double_precision_Msk
Definition: core_cm33.h:1799
FPU_MVFR0_Single_precision_Msk
#define FPU_MVFR0_Single_precision_Msk
Definition: core_cm33.h:1802
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: core_cm33.h:1118
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_cm33.h:657
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_cm33.h:642
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm33.h:641
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm33.h:663
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_cm33.h:656
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm33.h:1010
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm33.h:1014
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm33.h:1007
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm33.h:1004
TPI_Type::SSPSR
__IM uint32_t SSPSR
Definition: core_cm33.h:1331
SCB_Type::DCCMVAC
__OM uint32_t DCCMVAC
Definition: core_cm33.h:573
ITM_Type::TCR
__IOM uint32_t TCR
Definition: core_cm33.h:1056
DWT_Type::COMP5
__IOM uint32_t COMP5
Definition: core_cm33.h:1173
SCB_Type::ICSR
__IOM uint32_t ICSR
Definition: core_cm33.h:533
SCB_Type::CFSR
__IOM uint32_t CFSR
Definition: core_cm33.h:540
SCB_Type::SFAR
__IOM uint32_t SFAR
Definition: core_cm33.h:559
TPI_Type::CLAIMCLR
__IOM uint32_t CLAIMCLR
Definition: core_cm33.h:1351
DWT_Type::CYCCNT
__IOM uint32_t CYCCNT
Definition: core_cm33.h:1146
DWT_Type::COMP6
__IOM uint32_t COMP6
Definition: core_cm33.h:1177
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
TPI_Type::SPPR
__IOM uint32_t SPPR
Definition: core_cm33.h:1336
SCnSCB_Type::ACTLR
__IOM uint32_t ACTLR
Definition: core_cm33.h:970
SCB_Type::HFSR
__IOM uint32_t HFSR
Definition: core_cm33.h:541
SCB_Type::VTOR
__IOM uint32_t VTOR
Definition: core_cm33.h:534
SCB_Type::DFSR
__IOM uint32_t DFSR
Definition: core_cm33.h:542
DCB_Type::DSCSR
__IOM uint32_t DSCSR
Definition: core_cm33.h:1979
xPSR_Type::w
uint32_t w
Definition: core_cm33.h:420
DIB_Type::DLSR
__IM uint32_t DLSR
Definition: core_cm33.h:2131
CoreDebug_Type::DAUTHCTRL
__IOM uint32_t DAUTHCTRL
Definition: core_cm33.h:1844
DWT_Type::FOLDCNT
__IOM uint32_t FOLDCNT
Definition: core_cm33.h:1151
xPSR_Type::Z
uint32_t Z
Definition: core_cm33.h:417
DWT_Type::FUNCTION11
__IOM uint32_t FUNCTION11
Definition: core_cm33.h:1199
SCB_Type::CPUID
__IM uint32_t CPUID
Definition: core_cm33.h:532
SCB_Type::DCISW
__OM uint32_t DCISW
Definition: core_cm33.h:571
APSR_Type::Q
uint32_t Q
Definition: core_cm33.h:354
ITM_Type::DEVARCH
__IM uint32_t DEVARCH
Definition: core_cm33.h:1062
SCB_Type::MVFR2
__IM uint32_t MVFR2
Definition: core_cm33.h:565
ITM_Type::PID7
__IM uint32_t PID7
Definition: core_cm33.h:1067
DWT_Type::CPICNT
__IOM uint32_t CPICNT
Definition: core_cm33.h:1147
SCB_Type::MMFAR
__IOM uint32_t MMFAR
Definition: core_cm33.h:543
xPSR_Type::GE
uint32_t GE
Definition: core_cm33.h:410
SCB_Type::CCR
__IOM uint32_t CCR
Definition: core_cm33.h:537
xPSR_Type::N
uint32_t N
Definition: core_cm33.h:418
DWT_Type::FUNCTION5
__IOM uint32_t FUNCTION5
Definition: core_cm33.h:1175
DWT_Type::FUNCTION4
__IOM uint32_t FUNCTION4
Definition: core_cm33.h:1171
ITM_Type::CID0
__IM uint32_t CID0
Definition: core_cm33.h:1072
xPSR_Type::IT
uint32_t IT
Definition: core_cm33.h:413
SCnSCB_Type::ICTR
__IM uint32_t ICTR
Definition: core_cm33.h:969
SCnSCB_Type::CPPWR
__IOM uint32_t CPPWR
Definition: core_cm33.h:971
CONTROL_Type::nPRIV
uint32_t nPRIV
Definition: core_cm33.h:459
DWT_Type::FUNCTION9
__IOM uint32_t FUNCTION9
Definition: core_cm33.h:1191
NVIC_Type::STIR
__OM uint32_t STIR
Definition: core_cm33.h:510
ITM_Type::LSR
__IM uint32_t LSR
Definition: core_cm33.h:1060
DWT_Type::COMP1
__IOM uint32_t COMP1
Definition: core_cm33.h:1157
SCB_Type::SCR
__IOM uint32_t SCR
Definition: core_cm33.h:536
APSR_Type::Z
uint32_t Z
Definition: core_cm33.h:357
xPSR_Type::ISR
uint32_t ISR
Definition: core_cm33.h:408
TPI_Type::FFCR
__IOM uint32_t FFCR
Definition: core_cm33.h:1339
SCB_Type::BFAR
__IOM uint32_t BFAR
Definition: core_cm33.h:544
xPSR_Type::C
uint32_t C
Definition: core_cm33.h:416
DWT_Type::SLEEPCNT
__IOM uint32_t SLEEPCNT
Definition: core_cm33.h:1149
DWT_Type::LSR
__IM uint32_t LSR
Definition: core_cm33.h:1217
ITM_Type::CID3
__IM uint32_t CID3
Definition: core_cm33.h:1075
DWT_Type::COMP7
__IOM uint32_t COMP7
Definition: core_cm33.h:1181
SysTick_Type::LOAD
__IOM uint32_t LOAD
Definition: core_cm33.h:994
FPU_Type::MVFR2
__IM uint32_t MVFR2
Definition: core_cm33.h:1710
IPSR_Type::w
uint32_t w
Definition: core_cm33.h:393
SCB_Type::DCIMVAC
__OM uint32_t DCIMVAC
Definition: core_cm33.h:570
TPI_Type::ITFTTD0
__IM uint32_t ITFTTD0
Definition: core_cm33.h:1343
TPI_Type::TRIGGER
__IM uint32_t TRIGGER
Definition: core_cm33.h:1342
FPU_Type::MVFR0
__IM uint32_t MVFR0
Definition: core_cm33.h:1708
SCB_Type::DCCIMVAC
__OM uint32_t DCCIMVAC
Definition: core_cm33.h:575
DIB_Type::DLAR
__OM uint32_t DLAR
Definition: core_cm33.h:2130
DWT_Type::FUNCTION12
__IOM uint32_t FUNCTION12
Definition: core_cm33.h:1203
SCB_Type::NSACR
__IOM uint32_t NSACR
Definition: core_cm33.h:556
DWT_Type::FUNCTION3
__IOM uint32_t FUNCTION3
Definition: core_cm33.h:1167
FPU_Type::FPCAR
__IOM uint32_t FPCAR
Definition: core_cm33.h:1706
SCB_Type::ICIALLU
__OM uint32_t ICIALLU
Definition: core_cm33.h:567
DWT_Type::FUNCTION0
__IOM uint32_t FUNCTION0
Definition: core_cm33.h:1155
ITM_Type::u32
__OM uint32_t u32
Definition: core_cm33.h:1049
FPU_Type::FPDSCR
__IOM uint32_t FPDSCR
Definition: core_cm33.h:1707
DWT_Type::COMP2
__IOM uint32_t COMP2
Definition: core_cm33.h:1161
SCB_Type::ICIMVAU
__OM uint32_t ICIMVAU
Definition: core_cm33.h:569
DWT_Type::COMP0
__IOM uint32_t COMP0
Definition: core_cm33.h:1153
DWT_Type::PCSR
__IM uint32_t PCSR
Definition: core_cm33.h:1152
DCB_Type::DEMCR
__IOM uint32_t DEMCR
Definition: core_cm33.h:1976
DWT_Type::FUNCTION10
__IOM uint32_t FUNCTION10
Definition: core_cm33.h:1195
FPU_Type::MVFR1
__IM uint32_t MVFR1
Definition: core_cm33.h:1709
CONTROL_Type::w
uint32_t w
Definition: core_cm33.h:465
TPI_Type::FFSR
__IM uint32_t FFSR
Definition: core_cm33.h:1338
DWT_Type::FUNCTION15
__IOM uint32_t FUNCTION15
Definition: core_cm33.h:1215
DCB_Type::DHCSR
__IOM uint32_t DHCSR
Definition: core_cm33.h:1973
SCB_Type::MVFR1
__IM uint32_t MVFR1
Definition: core_cm33.h:564
xPSR_Type::_reserved1
uint32_t _reserved1
Definition: core_cm33.h:411
SCB_Type::MVFR0
__IM uint32_t MVFR0
Definition: core_cm33.h:563
SCB_Type::SHCSR
__IOM uint32_t SHCSR
Definition: core_cm33.h:539
APSR_Type::N
uint32_t N
Definition: core_cm33.h:358
xPSR_Type::T
uint32_t T
Definition: core_cm33.h:412
ITM_Type::LAR
__OM uint32_t LAR
Definition: core_cm33.h:1059
ITM_Type::CID2
__IM uint32_t CID2
Definition: core_cm33.h:1074
APSR_Type::V
uint32_t V
Definition: core_cm33.h:355
ITM_Type::PID2
__IM uint32_t PID2
Definition: core_cm33.h:1070
DWT_Type::FUNCTION14
__IOM uint32_t FUNCTION14
Definition: core_cm33.h:1211
DWT_Type::COMP14
__IOM uint32_t COMP14
Definition: core_cm33.h:1209
DWT_Type::COMP3
__IOM uint32_t COMP3
Definition: core_cm33.h:1165
DWT_Type::COMP4
__IOM uint32_t COMP4
Definition: core_cm33.h:1169
APSR_Type::C
uint32_t C
Definition: core_cm33.h:356
SysTick_Type::CTRL
__IOM uint32_t CTRL
Definition: core_cm33.h:993
TPI_Type::CSPSR
__IOM uint32_t CSPSR
Definition: core_cm33.h:1332
ITM_Type::PID1
__IM uint32_t PID1
Definition: core_cm33.h:1069
DIB_Type::DDEVTYPE
__IM uint32_t DDEVTYPE
Definition: core_cm33.h:2134
CONTROL_Type::SPSEL
uint32_t SPSEL
Definition: core_cm33.h:460
DWT_Type::FUNCTION1
__IOM uint32_t FUNCTION1
Definition: core_cm33.h:1159
DWT_Type::COMP12
__IOM uint32_t COMP12
Definition: core_cm33.h:1201
DCB_Type::DCRDR
__IOM uint32_t DCRDR
Definition: core_cm33.h:1975
ITM_Type::u16
__OM uint16_t u16
Definition: core_cm33.h:1048
SysTick_Type::VAL
__IOM uint32_t VAL
Definition: core_cm33.h:995
SCB_Type::ID_AFR
__IM uint32_t ID_AFR
Definition: core_cm33.h:548
TPI_Type::ACPR
__IOM uint32_t ACPR
Definition: core_cm33.h:1334
DWT_Type::EXCCNT
__IOM uint32_t EXCCNT
Definition: core_cm33.h:1148
DWT_Type::COMP11
__IOM uint32_t COMP11
Definition: core_cm33.h:1197
DWT_Type::COMP15
__IOM uint32_t COMP15
Definition: core_cm33.h:1213
SCB_Type::SFSR
__IOM uint32_t SFSR
Definition: core_cm33.h:558
CONTROL_Type::_reserved1
uint32_t _reserved1
Definition: core_cm33.h:463
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: core_cm33.h:3236
DWT_Type::FUNCTION6
__IOM uint32_t FUNCTION6
Definition: core_cm33.h:1179
TPI_Type::ITCTRL
__IOM uint32_t ITCTRL
Definition: core_cm33.h:1348
TPI_Type::ITATBCTR0
__IM uint32_t ITATBCTR0
Definition: core_cm33.h:1346
CoreDebug_Type::DCRDR
__IOM uint32_t DCRDR
Definition: core_cm33.h:1841
ITM_Type::PID4
__IM uint32_t PID4
Definition: core_cm33.h:1064
SCB_Type::DCCMVAU
__OM uint32_t DCCMVAU
Definition: core_cm33.h:572
TPI_Type::ITFTTD1
__IM uint32_t ITFTTD1
Definition: core_cm33.h:1347
SCB_Type::BPIALL
__OM uint32_t BPIALL
Definition: core_cm33.h:577
DWT_Type::FUNCTION2
__IOM uint32_t FUNCTION2
Definition: core_cm33.h:1163
TPI_Type::ITATBCTR2
__IOM uint32_t ITATBCTR2
Definition: core_cm33.h:1344
IPSR_Type::ISR
uint32_t ISR
Definition: core_cm33.h:390
ITM_Type::PID0
__IM uint32_t PID0
Definition: core_cm33.h:1068
SCB_Type::AFSR
__IOM uint32_t AFSR
Definition: core_cm33.h:545
SCB_Type::DCCSW
__OM uint32_t DCCSW
Definition: core_cm33.h:574
DWT_Type::FUNCTION7
__IOM uint32_t FUNCTION7
Definition: core_cm33.h:1183
TPI_Type::DEVID
__IM uint32_t DEVID
Definition: core_cm33.h:1353
DWT_Type::COMP13
__IOM uint32_t COMP13
Definition: core_cm33.h:1205
DWT_Type::COMP9
__IOM uint32_t COMP9
Definition: core_cm33.h:1189
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: core_cm33.h:3268
ITM_Type::CID1
__IM uint32_t CID1
Definition: core_cm33.h:1073
CONTROL_Type::FPCA
uint32_t FPCA
Definition: core_cm33.h:461
APSR_Type::_reserved1
uint32_t _reserved1
Definition: core_cm33.h:353
SCB_Type::CPACR
__IOM uint32_t CPACR
Definition: core_cm33.h:555
ITM_SendChar
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
ITM Send Character.
Definition: core_cm33.h:3247
DWT_Type::LSUCNT
__IOM uint32_t LSUCNT
Definition: core_cm33.h:1150
ITM_Type::TER
__IOM uint32_t TER
Definition: core_cm33.h:1052
DWT_Type::FUNCTION8
__IOM uint32_t FUNCTION8
Definition: core_cm33.h:1187
DCB_Type::DAUTHCTRL
__IOM uint32_t DAUTHCTRL
Definition: core_cm33.h:1978
DWT_Type::COMP10
__IOM uint32_t COMP10
Definition: core_cm33.h:1193
TPI_Type::PSCR
__IOM uint32_t PSCR
Definition: core_cm33.h:1340
DIB_Type::DDEVARCH
__IM uint32_t DDEVARCH
Definition: core_cm33.h:2133
IPSR_Type::_reserved0
uint32_t _reserved0
Definition: core_cm33.h:391
ITM_Type::PID6
__IM uint32_t PID6
Definition: core_cm33.h:1066
SCB_Type::CSSELR
__IOM uint32_t CSSELR
Definition: core_cm33.h:554
SCB_Type::AIRCR
__IOM uint32_t AIRCR
Definition: core_cm33.h:535
CoreDebug_Type::DHCSR
__IOM uint32_t DHCSR
Definition: core_cm33.h:1839
SCB_Type::STIR
__OM uint32_t STIR
Definition: core_cm33.h:561
DIB_Type::DAUTHSTATUS
__IM uint32_t DAUTHSTATUS
Definition: core_cm33.h:2132
TPI_Type::DEVTYPE
__IM uint32_t DEVTYPE
Definition: core_cm33.h:1354
SCB_Type::CLIDR
__IM uint32_t CLIDR
Definition: core_cm33.h:551
CoreDebug_Type::DSCSR
__IOM uint32_t DSCSR
Definition: core_cm33.h:1845
SCB_Type::ID_DFR
__IM uint32_t ID_DFR
Definition: core_cm33.h:547
CONTROL_Type::SFPA
uint32_t SFPA
Definition: core_cm33.h:462
APSR_Type::GE
uint32_t GE
Definition: core_cm33.h:352
DWT_Type::CTRL
__IOM uint32_t CTRL
Definition: core_cm33.h:1145
xPSR_Type::Q
uint32_t Q
Definition: core_cm33.h:414
DCB_Type::DCRSR
__OM uint32_t DCRSR
Definition: core_cm33.h:1974
APSR_Type::w
uint32_t w
Definition: core_cm33.h:360
DWT_Type::DEVARCH
__IM uint32_t DEVARCH
Definition: core_cm33.h:1219
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: core_cm33.h:3288
ITM_Type::u8
__OM uint8_t u8
Definition: core_cm33.h:1047
ITM_Type::TPR
__IOM uint32_t TPR
Definition: core_cm33.h:1054
CoreDebug_Type::DEMCR
__IOM uint32_t DEMCR
Definition: core_cm33.h:1842
DWT_Type::COMP8
__IOM uint32_t COMP8
Definition: core_cm33.h:1185
xPSR_Type::V
uint32_t V
Definition: core_cm33.h:415
FPU_Type::FPCCR
__IOM uint32_t FPCCR
Definition: core_cm33.h:1705
ITM_Type::PID3
__IM uint32_t PID3
Definition: core_cm33.h:1071
SCB_Type::CTR
__IM uint32_t CTR
Definition: core_cm33.h:552
xPSR_Type::_reserved0
uint32_t _reserved0
Definition: core_cm33.h:409
SCB_Type::DCCISW
__OM uint32_t DCCISW
Definition: core_cm33.h:576
TPI_Type::CLAIMSET
__IOM uint32_t CLAIMSET
Definition: core_cm33.h:1350
CoreDebug_Type::DCRSR
__OM uint32_t DCRSR
Definition: core_cm33.h:1840
ITM_Type::PID5
__IM uint32_t PID5
Definition: core_cm33.h:1065
DWT_Type::FUNCTION13
__IOM uint32_t FUNCTION13
Definition: core_cm33.h:1207
APSR_Type::_reserved0
uint32_t _reserved0
Definition: core_cm33.h:351
SysTick_Type::CALIB
__IM uint32_t CALIB
Definition: core_cm33.h:996
SCB_Type::CCSIDR
__IM uint32_t CCSIDR
Definition: core_cm33.h:553
DCB
#define DCB
Definition: core_cm33.h:2244
SCB
#define SCB
Definition: core_cm33.h:2237
DIB
#define DIB
Definition: core_cm33.h:2245
ITM
#define ITM
Definition: core_cm33.h:2240
FPU
#define FPU
Definition: core_cm33.h:2258
NVIC
#define NVIC
Definition: core_cm33.h:2239
SysTick
#define SysTick
Definition: core_cm33.h:2238
IRQn_Type
IRQn_Type
Definition: stm32u5g9xx.h:52
SysTick_IRQn
@ SysTick_IRQn
Definition: same70j19.h:68
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition: core_cm33.h:1838
DCB_Type
Structure type to access the Debug Control Block Registers (DCB).
Definition: core_cm33.h:1972
DIB_Type
Structure type to access the Debug Identification Block Registers (DIB).
Definition: core_cm33.h:2129
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_cm33.h:1144
FPU_Type
Structure type to access the Floating Point Unit (FPU).
Definition: core_cm33.h:1703
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_cm33.h:1044
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm33.h:495
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_cm33.h:531
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_cm33.h:967
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_cm33.h:992
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_cm33.h:1330
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_cm33.h:348
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_cm33.h:456
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm33.h:387
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm33.h:405
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