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#define | BSP_SHARED_HANDLER_SUPPORT 1 |
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#define | BSP_POWERPC_IRQ_GENERIC_SUPPORT 1 |
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#define | ISA8259_M_ELCR 0x4d0 |
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#define | ISA8259_S_ELCR 0x4d1 |
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#define | ELCRS_INT15_LVL 0x80 |
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#define | ELCRS_INT14_LVL 0x40 |
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#define | ELCRS_INT13_LVL 0x20 |
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#define | ELCRS_INT12_LVL 0x10 |
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#define | ELCRS_INT11_LVL 0x08 |
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#define | ELCRS_INT10_LVL 0x04 |
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#define | ELCRS_INT9_LVL 0x02 |
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#define | ELCRS_INT8_LVL 0x01 |
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#define | ELCRM_INT7_LVL 0x80 |
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#define | ELCRM_INT6_LVL 0x40 |
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#define | ELCRM_INT5_LVL 0x20 |
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#define | ELCRM_INT4_LVL 0x10 |
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#define | ELCRM_INT3_LVL 0x8 |
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#define | ELCRM_INT2_LVL 0x4 |
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#define | ELCRM_INT1_LVL 0x2 |
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#define | ELCRM_INT0_LVL 0x1 |
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#define | PIC_MASTER_COMMAND_IO_PORT 0x20 /* Master PIC command register */ |
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#define | PIC_SLAVE_COMMAND_IO_PORT 0xa0 /* Slave PIC command register */ |
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#define | PIC_MASTER_IMR_IO_PORT 0x21 /* Master PIC Interrupt Mask Register */ |
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#define | PIC_SLAVE_IMR_IO_PORT 0xa1 /* Slave PIC Interrupt Mask Register */ |
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#define | PIC_EOSI 0x60 /* End of Specific Interrupt (EOSI) */ |
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#define | SLAVE_PIC_EOSI 0x62 /* End of Specific Interrupt (EOSI) for cascade */ |
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#define | PIC_EOI 0x20 /* Generic End of Interrupt (EOI) */ |
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#define | BSP_ISA_IRQ_NUMBER (16) |
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#define | BSP_ISA_IRQ_LOWEST_OFFSET (0) |
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#define | BSP_ISA_IRQ_MAX_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1) |
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#define | BSP_PCI_IRQ_NUMBER (16) |
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#define | BSP_PCI_IRQ_LOWEST_OFFSET (BSP_ISA_IRQ_NUMBER) |
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#define | BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) |
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#define | BSP_PROCESSOR_IRQ_NUMBER (1) |
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#define | BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1) |
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#define | BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) |
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#define | BSP_MISC_IRQ_NUMBER (8) |
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#define | BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) |
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#define | BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1) |
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#define | BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1) |
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#define | BSP_LOWEST_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET) |
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#define | BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET) |
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#define | BSP_INTERRUPT_VECTOR_COUNT (BSP_MAX_OFFSET + 1) |
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#define | BSP_ISA_PERIODIC_TIMER (0) |
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#define | BSP_ISA_KEYBOARD (1) |
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#define | BSP_ISA_UART_COM2_IRQ (3) |
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#define | BSP_ISA_UART_COM1_IRQ (4) |
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#define | BSP_ISA_RT_TIMER1 (8) |
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#define | BSP_ISA_RT_TIMER3 (10) |
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#define | BSP_PCI_IRQ0 (BSP_PCI_IRQ_LOWEST_OFFSET) |
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#define | BSP_PCI_ISA_BRIDGE_IRQ (BSP_PCI_IRQ0) |
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#define | BSP_UART_COM1_IRQ BSP_ISA_UART_COM1_IRQ |
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#define | BSP_UART_COM2_IRQ BSP_ISA_UART_COM2_IRQ |
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#define | BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) |
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void | BSP_i8259s_init (void) |
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| int | BSP_irq_disable_at_i8259s (const rtems_irq_number irqLine) |
| | function to disable a particular irq at 8259 level.
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| int | BSP_irq_enable_at_i8259s (const rtems_irq_number irqLine) |
| | function to enable a particular irq at 8259 level.
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| int | BSP_irq_ack_at_i8259s (const rtems_irq_number irqLine) |
| | function to acknowledge a particular irq at 8259 level.
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int | BSP_irq_enabled_at_i8259s (const rtems_irq_number irqLine) |
| | function to check if a particular irq is enabled at 8259 level.
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unsigned short | BSP_irq_suspend_i8259s (unsigned short mask) |
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void | BSP_irq_resume_i8259s (unsigned short in_progress_save) |
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void | BSP_rtems_irq_mng_init (unsigned cpuId) |
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Interrupt Handler Support.
This include file describe the data structure and the functions implemented by RTEMS to write interrupt handlers.
This code is heavily inspired by the public specification of STREAM V2 that can be found at :