RTEMS 7.0-rc1
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memory.h
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1
9/*
10 * Copyright (C) 2024 embedded brains GmbH & Co. KG
11 * Copyright (C) 2023 Reflex Aerospace GmbH
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef LIBBSP_ARM_XILINX_VERSAL_RPU_BSP_MEMORY_H
36#define LIBBSP_ARM_XILINX_VERSAL_RPU_BSP_MEMORY_H
37
38#include <rtems/score/armv7-pmsa.h>
39
40#ifdef __cplusplus
41extern "C" {
42#endif /* __cplusplus */
43
50extern char versal_memory_atcm_begin[];
51extern char versal_memory_atcm_end[];
52extern char versal_memory_atcm_size[];
53
54extern char versal_memory_btcm_begin[];
55extern char versal_memory_btcm_end[];
56extern char versal_memory_btcm_size[];
57
58extern char versal_memory_ddr_begin[];
59extern char versal_memory_ddr_end[];
60extern char versal_memory_ddr_size[];
61
62extern char versal_memory_nocache_begin[];
63extern char versal_memory_nocache_end[];
64extern char versal_memory_nocache_size[];
65
66extern char versal_memory_devps_begin[];
67extern char versal_memory_devps_end[];
68extern char versal_memory_devps_size[];
69
70extern char versal_memory_ocm_begin[];
71extern char versal_memory_ocm_end[];
72extern char versal_memory_ocm_size[];
73
79void versal_setup_mpu_and_cache(void);
80
89extern const ARMV7_PMSA_Region versal_mpu_regions[];
90
95extern const size_t versal_mpu_region_count;
96
99#ifdef __cplusplus
100}
101#endif /* __cplusplus */
102
103#endif /* LIBBSP_ARM_XILINX_VERSAL_RPU_BSP_MEMORY_H */
armv7-pmsa.h
This header file provides the API to manage an Arm PMSAv7 based Memory Protection Unit (MPU).
versal_setup_mpu_and_cache
void versal_setup_mpu_and_cache(void)
Versal Adaptive SoC specific set up of the MMU.
versal_mpu_region_count
const size_t versal_mpu_region_count
This constant contains the entry count of the versal_mpu_regions table.
Definition: mpu-config.c:72
versal_mpu_regions
const ARMV7_PMSA_Region versal_mpu_regions[]
This table defines the Versal Adaptive SoC specific MPU regions.
Definition: mpu-config.c:43
ARMV7_PMSA_Region
The region definition is used to initialize the Memory Protection Unit (MPU).
Definition: armv7-pmsa.h:232
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