RTEMS 7.0-rc1
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io.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
9/*
10 * Copyright (C) 2012 Sebastian Huber
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#ifndef LIBBSP_ARM_STM32F4_IO_H
35#define LIBBSP_ARM_STM32F4_IO_H
36
37#include <stdbool.h>
38#include <stdint.h>
39#include <bspopts.h>
40
41#ifdef __cplusplus
42extern "C" {
43#endif /* __cplusplus */
44
52#define STM32F4_GPIO_PIN(port, index) ((((port) << 4) | (index)) & 0xff)
53
54#define STM32F4_GPIO_PORT_OF_PIN(pin) (((pin) >> 4) & 0xf)
55
56#define STM32F4_GPIO_INDEX_OF_PIN(pin) ((pin) & 0xf)
57
58#ifdef STM32F4_FAMILY_F4XXXX
59
65typedef enum {
66 STM32F4_GPIO_MODE_INPUT,
67 STM32F4_GPIO_MODE_OUTPUT,
68 STM32F4_GPIO_MODE_AF,
69 STM32F4_GPIO_MODE_ANALOG
70} stm32f4_gpio_mode;
71
72typedef enum {
73 STM32F4_GPIO_OTYPE_PUSH_PULL,
74 STM32F4_GPIO_OTYPE_OPEN_DRAIN
75} stm32f4_gpio_otype;
76
77typedef enum {
78 STM32F4_GPIO_OSPEED_2_MHZ,
79 STM32F4_GPIO_OSPEED_25_MHZ,
80 STM32F4_GPIO_OSPEED_50_MHZ,
81 STM32F4_GPIO_OSPEED_100_MHZ
82} stm32f4_gpio_ospeed;
83
84typedef enum {
85 STM32F4_GPIO_NO_PULL,
86 STM32F4_GPIO_PULL_UP,
87 STM32F4_GPIO_PULL_DOWN
88} stm32f4_gpio_pull;
89
90typedef enum {
91 STM32F4_GPIO_AF_SYSTEM = 0,
92 STM32F4_GPIO_AF_TIM1 = 1,
93 STM32F4_GPIO_AF_TIM2 = 1,
94 STM32F4_GPIO_AF_TIM3 = 2,
95 STM32F4_GPIO_AF_TIM4 = 2,
96 STM32F4_GPIO_AF_TIM5 = 2,
97 STM32F4_GPIO_AF_TIM8 = 3,
98 STM32F4_GPIO_AF_TIM9 = 3,
99 STM32F4_GPIO_AF_TIM10 = 3,
100 STM32F4_GPIO_AF_TIM11 = 3,
101 STM32F4_GPIO_AF_I2C1 = 4,
102 STM32F4_GPIO_AF_I2C2 = 4,
103 STM32F4_GPIO_AF_I2C3 = 4,
104 STM32F4_GPIO_AF_SPI1 = 5,
105 STM32F4_GPIO_AF_SPI2 = 5,
106 STM32F4_GPIO_AF_SPI3 = 6,
107 STM32F4_GPIO_AF_USART1 = 7,
108 STM32F4_GPIO_AF_USART2 = 7,
109 STM32F4_GPIO_AF_USART3 = 7,
110 STM32F4_GPIO_AF_UART4 = 8,
111 STM32F4_GPIO_AF_UART5 = 8,
112 STM32F4_GPIO_AF_USART6 = 8,
113 STM32F4_GPIO_AF_CAN1 = 9,
114 STM32F4_GPIO_AF_CAN2 = 9,
115 STM32F4_GPIO_AF_TIM12 = 9,
116 STM32F4_GPIO_AF_TIM13 = 9,
117 STM32F4_GPIO_AF_TIM14 = 9,
118 STM32F4_GPIO_AF_OTG_FS = 10,
119 STM32F4_GPIO_AF_OTG_HS = 10,
120 STM32F4_GPIO_AF_ETH = 11,
121 STM32F4_GPIO_AF_FSMC = 12,
122 STM32F4_GPIO_AF_OTG_HS_FS = 12,
123 STM32F4_GPIO_AF_SDIO = 12,
124 STM32F4_GPIO_AF_DCMI = 13,
125 STM32F4_GPIO_AF_EVENTOUT = 15
126} stm32f4_gpio_af;
127
128typedef union {
129 struct {
130 uint32_t pin_first : 8;
131 uint32_t pin_last : 8;
132 uint32_t mode : 2;
133 uint32_t otype : 1;
134 uint32_t ospeed : 2;
135 uint32_t pupd : 2;
136 uint32_t output : 1;
137 uint32_t af : 4;
138 uint32_t reserved : 4;
139 } fields;
140
141 uint32_t value;
142} stm32f4_gpio_config;
143
144#define STM32F4_GPIO_CONFIG_TERMINAL \
145 { { 0xff, 0xff, 0x3, 0x1, 0x3, 0x3, 0x1, 0xf, 0xf } }
146
149#endif /* STM32F4_FAMILY_F4XXXX */
150#ifdef STM32F4_FAMILY_F10XXX
151
157typedef enum {
158 STM32F4_GPIO_MODE_INPUT,
159 STM32F4_GPIO_MODE_OUTPUT_10MHz,
160 STM32F4_GPIO_MODE_OUTPUT_2MHz,
161 STM32F4_GPIO_MODE_OUTPUT_50MHz
162} stm32f4_gpio_mode;
163
164typedef enum {
165 STM32F4_GPIO_CNF_IN_ANALOG = 0,
166 STM32F4_GPIO_CNF_IN_FLOATING = 1,
167 STM32F4_GPIO_CNF_IN_PULL_UPDOWN = 2,
168
169 STM32F4_GPIO_CNF_OUT_GPIO_PP = 0,
170 STM32F4_GPIO_CNF_OUT_GPIO_OD = 1,
171 STM32F4_GPIO_CNF_OUT_AF_PP = 2,
172 STM32F4_GPIO_CNF_OUT_AF_OD = 3,
173} stm32f4_gpio_cnf;
174
175typedef enum {
176 STM32F4_GPIO_REMAP_DONT_CHANGE,
177 STM32F4_GPIO_REMAP_SPI1_0,
178 STM32F4_GPIO_REMAP_SPI1_1,
179 STM32F4_GPIO_REMAP_I2C1_0,
180 STM32F4_GPIO_REMAP_I2C1_1,
181 STM32F4_GPIO_REMAP_USART1_0,
182 STM32F4_GPIO_REMAP_USART1_1,
183 STM32F4_GPIO_REMAP_USART2_0,
184 STM32F4_GPIO_REMAP_USART2_1,
185 STM32F4_GPIO_REMAP_USART3_0,
186 STM32F4_GPIO_REMAP_USART3_1,
187 STM32F4_GPIO_REMAP_USART3_3,
188 STM32F4_GPIO_REMAP_TIM1_0,
189 STM32F4_GPIO_REMAP_TIM1_1,
190 STM32F4_GPIO_REMAP_TIM1_3,
191 STM32F4_GPIO_REMAP_TIM2_0,
192 STM32F4_GPIO_REMAP_TIM2_1,
193 STM32F4_GPIO_REMAP_TIM2_2,
194 STM32F4_GPIO_REMAP_TIM2_3,
195 STM32F4_GPIO_REMAP_TIM3_0,
196 STM32F4_GPIO_REMAP_TIM3_2,
197 STM32F4_GPIO_REMAP_TIM3_3,
198 STM32F4_GPIO_REMAP_TIM4_0,
199 STM32F4_GPIO_REMAP_TIM4_1,
200 STM32F4_GPIO_REMAP_CAN1_0,
201 STM32F4_GPIO_REMAP_CAN1_2,
202 STM32F4_GPIO_REMAP_CAN1_3,
203 STM32F4_GPIO_REMAP_PD01_0,
204 STM32F4_GPIO_REMAP_PD01_1,
205 STM32F4_GPIO_REMAP_TIM5CH4_0,
206 STM32F4_GPIO_REMAP_TIM5CH4_1,
207 STM32F4_GPIO_REMAP_ADC1_ETRGINJ_0,
208 STM32F4_GPIO_REMAP_ADC1_ETRGINJ_1,
209 STM32F4_GPIO_REMAP_ADC1_ETRGREG_0,
210 STM32F4_GPIO_REMAP_ADC1_ETRGREG_1,
211 STM32F4_GPIO_REMAP_ADC2_ETRGINJ_0,
212 STM32F4_GPIO_REMAP_ADC2_ETRGINJ_1,
213 STM32F4_GPIO_REMAP_ADC2_ETRGREG_0,
214 STM32F4_GPIO_REMAP_ADC2_ETRGREG_1,
215 STM32F4_GPIO_REMAP_ETH_0,
216 STM32F4_GPIO_REMAP_ETH_1,
217 STM32F4_GPIO_REMAP_CAN2_0,
218 STM32F4_GPIO_REMAP_CAN2_1,
219 STM32F4_GPIO_REMAP_MII_RMII_0,
220 STM32F4_GPIO_REMAP_MII_RMII_1,
221 STM32F4_GPIO_REMAP_SWJ_0,
222 STM32F4_GPIO_REMAP_SWJ_1,
223 STM32F4_GPIO_REMAP_SWJ_2,
224 STM32F4_GPIO_REMAP_SWJ_4,
225 STM32F4_GPIO_REMAP_SPI3_0,
226 STM32F4_GPIO_REMAP_SPI3_1,
227 STM32F4_GPIO_REMAP_TIM2ITR1_0,
228 STM32F4_GPIO_REMAP_TIM2ITR1_1,
229 STM32F4_GPIO_REMAP_PTP_PPS_0,
230 STM32F4_GPIO_REMAP_PTP_PPS_1,
231 STM32F4_GPIO_REMAP_TIM15_0,
232 STM32F4_GPIO_REMAP_TIM15_1,
233 STM32F4_GPIO_REMAP_TIM16_0,
234 STM32F4_GPIO_REMAP_TIM16_1,
235 STM32F4_GPIO_REMAP_TIM17_0,
236 STM32F4_GPIO_REMAP_TIM17_1,
237 STM32F4_GPIO_REMAP_CEC_0,
238 STM32F4_GPIO_REMAP_CEC_1,
239 STM32F4_GPIO_REMAP_TIM1_DMA_0,
240 STM32F4_GPIO_REMAP_TIM1_DMA_1,
241 STM32F4_GPIO_REMAP_TIM9_0,
242 STM32F4_GPIO_REMAP_TIM9_1,
243 STM32F4_GPIO_REMAP_TIM10_0,
244 STM32F4_GPIO_REMAP_TIM10_1,
245 STM32F4_GPIO_REMAP_TIM11_0,
246 STM32F4_GPIO_REMAP_TIM11_1,
247 STM32F4_GPIO_REMAP_TIM13_0,
248 STM32F4_GPIO_REMAP_TIM13_1,
249 STM32F4_GPIO_REMAP_TIM14_0,
250 STM32F4_GPIO_REMAP_TIM14_1,
251 STM32F4_GPIO_REMAP_FSMC_0,
252 STM32F4_GPIO_REMAP_FSMC_1,
253 STM32F4_GPIO_REMAP_TIM67_DAC_DMA_0,
254 STM32F4_GPIO_REMAP_TIM67_DAC_DMA_1,
255 STM32F4_GPIO_REMAP_TIM12_0,
256 STM32F4_GPIO_REMAP_TIM12_1,
257 STM32F4_GPIO_REMAP_MISC_0,
258 STM32F4_GPIO_REMAP_MISC_1,
259} stm32f4_gpio_remap;
260
261typedef union {
262 struct {
263 uint32_t pin_first : 8;
264 uint32_t pin_last : 8;
265 uint32_t mode : 2;
266 uint32_t cnf : 2;
267 uint32_t output : 1;
268 uint32_t remap : 8;
269 uint32_t reserved : 3;
270 } fields;
271
272 uint32_t value;
273} stm32f4_gpio_config;
274
275#define STM32F4_GPIO_CONFIG_TERMINAL \
276 { { 0xff, 0xff, 0x3, 0x3, 0x1, 0xff, 0x7 } }
277
280#endif /* STM32F4_FAMILY_F10XXX */
281
282extern const stm32f4_gpio_config stm32f4_start_config_gpio [];
283
284void stm32f4_gpio_set_clock(int pin, bool set);
285
286void stm32f4_gpio_set_config(const stm32f4_gpio_config *config);
287
292void stm32f4_gpio_set_config_array(const stm32f4_gpio_config *configs);
293
294void stm32f4_gpio_set_output(int pin, bool set);
295
296bool stm32f4_gpio_get_input(int pin);
297
298#ifdef STM32F4_FAMILY_F4XXXX
299
305#define STM32F4_PIN_USART(port, idx, altfunc) \
306 { \
307 { \
308 .pin_first = STM32F4_GPIO_PIN(port, idx), \
309 .pin_last = STM32F4_GPIO_PIN(port, idx), \
310 .mode = STM32F4_GPIO_MODE_AF, \
311 .otype = STM32F4_GPIO_OTYPE_PUSH_PULL, \
312 .ospeed = STM32F4_GPIO_OSPEED_2_MHZ, \
313 .pupd = STM32F4_GPIO_PULL_UP, \
314 .af = altfunc \
315 } \
316 }
317
318#define STM32F4_PIN_USART1_TX_PA9 STM32F4_PIN_USART(0, 9, STM32F4_GPIO_AF_USART1)
319#define STM32F4_PIN_USART1_TX_PB6 STM32F4_PIN_USART(1, 6, STM32F4_GPIO_AF_USART1)
320#define STM32F4_PIN_USART1_RX_PA10 STM32F4_PIN_USART(0, 10, STM32F4_GPIO_AF_USART1)
321#define STM32F4_PIN_USART1_RX_PB7 STM32F4_PIN_USART(1, 7, STM32F4_GPIO_AF_USART1)
322
323#define STM32F4_PIN_USART2_TX_PA2 STM32F4_PIN_USART(0, 2, STM32F4_GPIO_AF_USART2)
324#define STM32F4_PIN_USART2_TX_PD5 STM32F4_PIN_USART(3, 5, STM32F4_GPIO_AF_USART2)
325#define STM32F4_PIN_USART2_RX_PA3 STM32F4_PIN_USART(0, 3, STM32F4_GPIO_AF_USART2)
326#define STM32F4_PIN_USART2_RX_PD6 STM32F4_PIN_USART(3, 6, STM32F4_GPIO_AF_USART2)
327
328#define STM32F4_PIN_USART3_TX_PC10 STM32F4_PIN_USART(2, 10, STM32F4_GPIO_AF_USART3)
329#define STM32F4_PIN_USART3_TX_PD8 STM32F4_PIN_USART(3, 8, STM32F4_GPIO_AF_USART3)
330#define STM32F4_PIN_USART3_RX_PC11 STM32F4_PIN_USART(2, 11, STM32F4_GPIO_AF_USART3)
331#define STM32F4_PIN_USART3_RX_PD9 STM32F4_PIN_USART(3, 9, STM32F4_GPIO_AF_USART3)
332
333#define STM32F4_PIN_UART4_TX_PA0 STM32F4_PIN_USART(0, 0, STM32F4_GPIO_AF_UART4)
334#define STM32F4_PIN_UART4_TX_PC10 STM32F4_PIN_USART(2, 10, STM32F4_GPIO_AF_UART4)
335#define STM32F4_PIN_UART4_RX_PA1 STM32F4_PIN_USART(0, 1, STM32F4_GPIO_AF_UART4)
336#define STM32F4_PIN_UART4_RX_PC11 STM32F4_PIN_USART(2, 11, STM32F4_GPIO_AF_UART4)
337
338#define STM32F4_PIN_UART5_TX_PC12 STM32F4_PIN_USART(2, 12, STM32F4_GPIO_AF_UART5)
339#define STM32F4_PIN_UART5_RX_PD2 STM32F4_PIN_USART(3, 2, STM32F4_GPIO_AF_UART5)
340
341#define STM32F4_PIN_USART6_TX_PC6 STM32F4_PIN_USART(2, 6, STM32F4_GPIO_AF_USART6)
342#define STM32F4_PIN_USART6_RX_PC7 STM32F4_PIN_USART(2, 7, STM32F4_GPIO_AF_USART6)
343
346#endif /* STM32F4_FAMILY_F4XXXX */
347#ifdef STM32F4_FAMILY_F10XXX
348
354#define STM32F4_PIN_USART_TX(port, idx, remapvalue) \
355 { \
356 { \
357 .pin_first = STM32F4_GPIO_PIN(port, idx), \
358 .pin_last = STM32F4_GPIO_PIN(port, idx), \
359 .mode = STM32F4_GPIO_MODE_OUTPUT_2MHz, \
360 .cnf = STM32F4_GPIO_CNF_OUT_AF_PP, \
361 .output = 0, \
362 .remap = remapvalue \
363 } \
364 }
365
366#define STM32F4_PIN_USART_RX(port, idx, remapvalue) \
367 { \
368 { \
369 .pin_first = STM32F4_GPIO_PIN(port, idx), \
370 .pin_last = STM32F4_GPIO_PIN(port, idx), \
371 .mode = STM32F4_GPIO_MODE_INPUT, \
372 .cnf = STM32F4_GPIO_CNF_IN_FLOATING, \
373 .output = 0, \
374 .remap = remapvalue \
375 } \
376 }
377
378#define STM32F4_PIN_USART1_TX_MAP_0 STM32F4_PIN_USART_TX(0, 9, STM32F4_GPIO_REMAP_USART1_0)
379#define STM32F4_PIN_USART1_RX_MAP_0 STM32F4_PIN_USART_RX(0, 10, STM32F4_GPIO_REMAP_USART1_0)
380#define STM32F4_PIN_USART1_TX_MAP_1 STM32F4_PIN_USART_TX(1, 6, STM32F4_GPIO_REMAP_USART1_1)
381#define STM32F4_PIN_USART1_RX_MAP_1 STM32F4_PIN_USART_RX(1, 7, STM32F4_GPIO_REMAP_USART1_1)
382
383#define STM32F4_PIN_USART2_TX_MAP_0 STM32F4_PIN_USART_TX(0, 2, STM32F4_GPIO_REMAP_USART2_0)
384#define STM32F4_PIN_USART2_RX_MAP_0 STM32F4_PIN_USART_RX(0, 3, STM32F4_GPIO_REMAP_USART2_0)
385#define STM32F4_PIN_USART2_TX_MAP_1 STM32F4_PIN_USART_TX(3, 5, STM32F4_GPIO_REMAP_USART2_1)
386#define STM32F4_PIN_USART2_RX_MAP_1 STM32F4_PIN_USART_RX(3, 6, STM32F4_GPIO_REMAP_USART2_1)
387
388#define STM32F4_PIN_USART3_TX_MAP_0 STM32F4_PIN_USART_TX(1, 10, STM32F4_GPIO_REMAP_USART3_0)
389#define STM32F4_PIN_USART3_RX_MAP_0 STM32F4_PIN_USART_RX(1, 11, STM32F4_GPIO_REMAP_USART3_0)
390#define STM32F4_PIN_USART3_TX_MAP_1 STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_USART3_1)
391#define STM32F4_PIN_USART3_RX_MAP_1 STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_USART3_1)
392#define STM32F4_PIN_USART3_TX_MAP_3 STM32F4_PIN_USART_TX(3, 8, STM32F4_GPIO_REMAP_USART3_3)
393#define STM32F4_PIN_USART3_RX_MAP_3 STM32F4_PIN_USART_RX(3, 9, STM32F4_GPIO_REMAP_USART3_3)
394
395#define STM32F4_PIN_UART4_TX STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_DONT_CHANGE)
396#define STM32F4_PIN_UART4_RX STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_DONT_CHANGE)
397
398#define STM32F4_PIN_UART5_TX STM32F4_PIN_USART_TX(2, 12, STM32F4_GPIO_REMAP_DONT_CHANGE)
399#define STM32F4_PIN_UART5_RX STM32F4_PIN_USART_RX(3, 2, STM32F4_GPIO_REMAP_DONT_CHANGE)
400
401#define STM32F4_PIN_I2C(port, idx, remapvalue) \
402 { \
403 { \
404 .pin_first = STM32F4_GPIO_PIN(port, idx), \
405 .pin_last = STM32F4_GPIO_PIN(port, idx), \
406 .mode = STM32F4_GPIO_MODE_OUTPUT_2MHz, \
407 .cnf = STM32F4_GPIO_CNF_OUT_AF_OD, \
408 .output = 0, \
409 .remap = remapvalue \
410 } \
411 }
412
413#define STM32F4_PIN_I2C1_SCL_MAP0 STM32F4_PIN_I2C(1, 6, STM32F4_GPIO_REMAP_I2C1_0)
414#define STM32F4_PIN_I2C1_SDA_MAP0 STM32F4_PIN_I2C(1, 7, STM32F4_GPIO_REMAP_I2C1_0)
415#define STM32F4_PIN_I2C1_SCL_MAP1 STM32F4_PIN_I2C(1, 8, STM32F4_GPIO_REMAP_I2C1_1)
416#define STM32F4_PIN_I2C1_SDA_MAP1 STM32F4_PIN_I2C(1, 9, STM32F4_GPIO_REMAP_I2C1_1)
417
418#define STM32F4_PIN_I2C2_SCL STM32F4_PIN_I2C(1, 10, STM32F4_GPIO_REMAP_DONT_CHANGE)
419#define STM32F4_PIN_I2C2_SDA STM32F4_PIN_I2C(1, 11, STM32F4_GPIO_REMAP_DONT_CHANGE)
420
423#endif /* STM32F4_FAMILY_F10XXX */
424
425#ifdef __cplusplus
426}
427#endif /* __cplusplus */
428
429#endif /* LIBBSP_ARM_STM32F4_IO_H */
stm32f4_gpio_set_config_array
void stm32f4_gpio_set_config_array(const stm32f4_gpio_config *configs)
Sets the GPIO configuration of an array terminated by STM32F4_GPIO_CONFIG_TERMINAL.
Definition: io.c:235
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