xiltemac.h

/* SPDX-License-Identifier: GPL-2.0+-with-RTEMS-exception */
 
/*
 * Driver for plb inteface of the xilinx temac 3.00a
 *
 * Author: Keith Robertson <kjrobert@alumni.uwaterloo.ca>
 * Copyright (c) 2007 Linn Products Ltd, Scotland.
 *
 * The license and distribution terms for this file may be
 * found in the file LICENSE in this distribution or at
 * http://www.rtems.org/license/LICENSE.
 *
 */
 
#ifndef _XILINX_TEMAC_
#define _XILINX_TEMAC_
#include <rtems/irq.h>
 
 
#define XILTEMAC_DRIVER_PREFIX   "xiltemac"
 
#define DRIVER_PREFIX XILTEMAC_DRIVER_PREFIX
 
 
#define XTE_DISR_OFFSET  0x00000000  
#define XTE_DIPR_OFFSET  0x00000004  
#define XTE_DIER_OFFSET  0x00000008  
#define XTE_DIIR_OFFSET  0x00000018  
#define XTE_DGIE_OFFSET  0x0000001C  
#define XTE_IPISR_OFFSET 0x00000020  
#define XTE_IPIER_OFFSET 0x00000028  
#define XTE_DSR_OFFSET   0x00000040  
#define XTE_PFIFO_TX_BASE_OFFSET    0x00002000  
#define XTE_PFIFO_TX_VACANCY_OFFSET 0x00002004  
#define XTE_PFIFO_TX_DATA_OFFSET    0x00002100  
#define XTE_PFIFO_RX_BASE_OFFSET    0x00002010  
#define XTE_PFIFO_RX_VACANCY_OFFSET 0x00002014  
#define XTE_PFIFO_RX_DATA_OFFSET    0x00002200  
#define XTE_PFIFO_COUNT_MASK     0x00FFFFFF
 
#define XTE_DMA_SEND_OFFSET      0x00002300  
#define XTE_DMA_RECV_OFFSET      0x00002340  
#define XTE_CR_OFFSET           0x00001000  
#define XTE_TPLR_OFFSET         0x00001004  
#define XTE_TSR_OFFSET          0x00001008  
#define XTE_RPLR_OFFSET         0x0000100C  
#define XTE_RSR_OFFSET          0x00001010  
#define XTE_IFGP_OFFSET         0x00001014  
#define XTE_TPPR_OFFSET         0x00001018  
#define XTE_HOST_IPIF_OFFSET    0x00003000  
#define XTE_ERXC0_OFFSET        (XTE_HOST_IPIF_OFFSET + 0x00000200)  
#define XTE_ERXC1_OFFSET        (XTE_HOST_IPIF_OFFSET + 0x00000240)  
#define XTE_ETXC_OFFSET         (XTE_HOST_IPIF_OFFSET + 0x00000280)  
#define XTE_EFCC_OFFSET         (XTE_HOST_IPIF_OFFSET + 0x000002C0)  
#define XTE_ECFG_OFFSET         (XTE_HOST_IPIF_OFFSET + 0x00000300)  
#define XTE_EGMIC_OFFSET        (XTE_HOST_IPIF_OFFSET + 0x00000320)  
#define XTE_EMC_OFFSET          (XTE_HOST_IPIF_OFFSET + 0x00000340)  
#define XTE_EUAW0_OFFSET        (XTE_HOST_IPIF_OFFSET + 0x00000380)  
#define XTE_EUAW1_OFFSET        (XTE_HOST_IPIF_OFFSET + 0x00000384)  
#define XTE_EMAW0_OFFSET        (XTE_HOST_IPIF_OFFSET + 0x00000388)  
#define XTE_EMAW1_OFFSET        (XTE_HOST_IPIF_OFFSET + 0x0000038C)  
#define XTE_EAFM_OFFSET         (XTE_HOST_IPIF_OFFSET + 0x00000390)  
#define XTE_EIRS_OFFSET         (XTE_HOST_IPIF_OFFSET + 0x000003A0)  
#define XTE_EIREN_OFFSET        (XTE_HOST_IPIF_OFFSET + 0x000003A4)  
#define XTE_EMIID_OFFSET        (XTE_HOST_IPIF_OFFSET + 0x000003B0)  
#define XTE_EMIIC_OFFSET        (XTE_HOST_IPIF_OFFSET + 0x000003B4)  
/* Register masks. The following constants define bit locations of various
 * control bits in the registers. Constants are not defined for those registers
 * that have a single bit field representing all 32 bits. For further
 * information on the meaning of the various bit masks, refer to the HW spec.
 */
 
#define XTE_DXR_SEND_FIFO_MASK          0x00000040 
#define XTE_DXR_RECV_FIFO_MASK          0x00000020 
#define XTE_DXR_RECV_DMA_MASK           0x00000010 
#define XTE_DXR_SEND_DMA_MASK           0x00000008 
#define XTE_DXR_CORE_MASK               0x00000004 
#define XTE_DXR_DPTO_MASK               0x00000002 
#define XTE_DXR_TERR_MASK               0x00000001 
#define XTE_IPXR_XMIT_DONE_MASK         0x00000001 
#define XTE_IPXR_RECV_DONE_MASK         0x00000002 
#define XTE_IPXR_AUTO_NEG_MASK          0x00000004 
#define XTE_IPXR_RECV_REJECT_MASK       0x00000008 
#define XTE_IPXR_XMIT_SFIFO_EMPTY_MASK  0x00000010 
#define XTE_IPXR_RECV_LFIFO_EMPTY_MASK  0x00000020 
#define XTE_IPXR_XMIT_LFIFO_FULL_MASK   0x00000040 
#define XTE_IPXR_RECV_LFIFO_OVER_MASK   0x00000080 
#define XTE_IPXR_RECV_LFIFO_UNDER_MASK  0x00000100 
#define XTE_IPXR_XMIT_SFIFO_OVER_MASK   0x00000200 
#define XTE_IPXR_XMIT_SFIFO_UNDER_MASK  0x00000400 
#define XTE_IPXR_XMIT_LFIFO_OVER_MASK   0x00000800 
#define XTE_IPXR_XMIT_LFIFO_UNDER_MASK  0x00001000 
#define XTE_IPXR_RECV_PFIFO_ABORT_MASK  0x00002000 
#define XTE_IPXR_RECV_LFIFO_ABORT_MASK  0x00004000 
#define XTE_IPXR_RECV_DROPPED_MASK                                      \
    (XTE_IPXR_RECV_REJECT_MASK |                                        \
     XTE_IPXR_RECV_PFIFO_ABORT_MASK |                                   \
     XTE_IPXR_RECV_LFIFO_ABORT_MASK)    
#define XTE_IPXR_XMIT_ERROR_MASK                                        \
    (XTE_IPXR_XMIT_SFIFO_OVER_MASK |                                    \
     XTE_IPXR_XMIT_SFIFO_UNDER_MASK |                                   \
     XTE_IPXR_XMIT_LFIFO_OVER_MASK |                                    \
     XTE_IPXR_XMIT_LFIFO_UNDER_MASK)    
#define XTE_IPXR_RECV_ERROR_MASK                                        \
    (XTE_IPXR_RECV_DROPPED_MASK |                                       \
     XTE_IPXR_RECV_LFIFO_UNDER_MASK)    
#define XTE_IPXR_FIFO_FATAL_ERROR_MASK          \
    (XTE_IPXR_XMIT_SFIFO_OVER_MASK |            \
     XTE_IPXR_XMIT_SFIFO_UNDER_MASK |           \
     XTE_IPXR_XMIT_LFIFO_OVER_MASK |            \
     XTE_IPXR_XMIT_LFIFO_UNDER_MASK |           \
     XTE_IPXR_RECV_LFIFO_UNDER_MASK)    
#define XTE_DSR_RESET_MASK      0x0000000A  
#define XTE_DGIE_ENABLE_MASK    0x80000000  
#define XTE_CR_HTRST_MASK       0x00000008   
#define XTE_CR_BCREJ_MASK       0x00000004   
#define XTE_CR_MCREJ_MASK       0x00000002   
#define XTE_CR_HDUPLEX_MASK     0x00000001   
#define XTE_TPLR_TXPL_MASK      0x00003FFF   
#define XTE_TSR_TXED_MASK       0x80000000   
#define XTE_TSR_PFIFOU_MASK     0x40000000   
#define XTE_TSR_TXA_MASK        0x3E000000   
#define XTE_TSR_TXLC_MASK       0x01000000   
#define XTE_TSR_TPCF_MASK       0x00000001   
#define XTE_TSR_ERROR_MASK                 \
    (XTE_TSR_TXED_MASK |                   \
     XTE_TSR_PFIFOU_MASK |                 \
     XTE_TSR_TXLC_MASK)                      
#define XTE_RPLR_RXPL_MASK      0x00003FFF   
#define XTE_RSR_RPCF_MASK       0x00000001   
#define XTE_IFG_IFGD_MASK       0x000000FF   
#define XTE_TPPR_TPPD_MASK      0x0000FFFF   
#define XTE_ERXC1_RXRST_MASK    0x80000000   
#define XTE_ERXC1_RXJMBO_MASK   0x40000000   
#define XTE_ERXC1_RXFCS_MASK    0x20000000   
#define XTE_ERXC1_RXEN_MASK     0x10000000   
#define XTE_ERXC1_RXVLAN_MASK   0x08000000   
#define XTE_ERXC1_RXHD_MASK     0x04000000   
#define XTE_ERXC1_RXLT_MASK     0x02000000   
#define XTE_ERXC1_ERXC1_MASK    0x0000FFFF   
#define XTE_ETXC_TXRST_MASK     0x80000000   
#define XTE_ETXC_TXJMBO_MASK    0x40000000   
#define XTE_ETXC_TXFCS_MASK     0x20000000   
#define XTE_ETXC_TXEN_MASK      0x10000000   
#define XTE_ETXC_TXVLAN_MASK    0x08000000   
#define XTE_ETXC_TXHD_MASK      0x04000000   
#define XTE_ETXC_TXIFG_MASK     0x02000000   
#define XTE_EFCC_TXFLO_MASK     0x40000000   
#define XTE_EFCC_RXFLO_MASK     0x20000000   
#define XTE_ECFG_LINKSPD_MASK   0xC0000000   
#define XTE_ECFG_RGMII_MASK     0x20000000   
#define XTE_ECFG_SGMII_MASK     0x10000000   
#define XTE_ECFG_1000BASEX_MASK 0x08000000   
#define XTE_ECFG_HOSTEN_MASK    0x04000000   
#define XTE_ECFG_TX16BIT        0x02000000   
#define XTE_ECFG_RX16BIT        0x01000000   
#define XTE_ECFG_LINKSPD_10     0x00000000   
#define XTE_ECFG_LINKSPD_100    0x40000000   
#define XTE_ECFG_LINKSPD_1000   0x80000000   
#define XTE_EGMIC_RGLINKSPD_MASK    0xC0000000   
#define XTE_EGMIC_SGLINKSPD_MASK    0x0000000C   
#define XTE_EGMIC_RGSTATUS_MASK     0x00000002   
#define XTE_EGMIC_RGHALFDUPLEX_MASK 0x00000001   
#define XTE_EGMIC_RGLINKSPD_10      0x00000000   
#define XTE_EGMIC_RGLINKSPD_100     0x40000000   
#define XTE_EGMIC_RGLINKSPD_1000    0x80000000   
#define XTE_EGMIC_SGLINKSPD_10      0x00000000   
#define XTE_EGMIC_SGLINKSPD_100     0x00000004   
#define XTE_EGMIC_SGLINKSPD_1000    0x00000008   
#define XTE_EMC_MDIO_MASK       0x00000040   
#define XTE_EMC_CLK_DVD_MAX     0x3F         
#define XTE_EUAW1_MASK          0x0000FFFF   
#define XTE_EMAW1_CAMRNW_MASK   0x00800000   
#define XTE_EMAW1_CAMADDR_MASK  0x00030000   
#define XTE_EUAW1_MASK          0x0000FFFF   
#define XTE_EMAW1_CAMMADDR_SHIFT_MASK 16     
#define XTE_EAFM_EPPRM_MASK         0x80000000   
#define XTE_EMIID_MIIMWRDATA_MASK   0x0000FFFF   
#define XTE_EMIID_MIIMDECADDR_MASK  0x0000FFFF   
struct XilTemacStats
{
  volatile uint32_t iInterrupts;
 
  volatile uint32_t iRxInterrupts;
  volatile uint32_t iRxRejectedInterrupts;
  volatile uint32_t iRxRejectedInvalidFrame;
  volatile uint32_t iRxRejectedDataFifoFull;
  volatile uint32_t iRxRejectedLengthFifoFull;
  volatile uint32_t iRxMaxDrained;
  volatile uint32_t iRxStrayEvents;
 
  volatile uint32_t iTxInterrupts;
  volatile uint32_t iTxMaxDrained;
};
 
#define MAX_UNIT_BYTES 50
 
struct XilTemac
{
  struct arpcom         iArpcom;
  struct XilTemacStats  iStats;
  struct ifnet*         iIfp;
 
  char                  iUnitName[MAX_UNIT_BYTES];
 
  uint32_t              iAddr;
  rtems_event_set       iIoEvent;
 
  int                   iIsrVector;
 
#if PPC_HAS_CLASSIC_EXCEPTIONS
  rtems_isr_entry       iOldHandler;
#else
  rtems_irq_connect_data iOldHandler;
#endif
  int                   iIsPresent;
};
 
 
#endif /* _XILINX_EMAC_*/