RTEMS
7.0-rc1
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bsps
arm
csb337
include
sed1356_16bit.h
Go to the documentation of this file.
1
19
/*
20
* sed1356.h: SED1356 LCD/CRT Controllers for KIT637_V6 (CSB637)
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* 16-Bit access mode
22
*
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* Based upon code from MicroMonitor 1.17 from http://www.umonfw.com/
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* which includes this notice:
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*
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**************************************************************************
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* General notice:
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* This code is part of a boot-monitor package developed as a generic base
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* platform for embedded system designs. As such, it is likely to be
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* distributed to various projects beyond the control of the original
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* author. Please notify the author of any enhancements made or bugs found
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* so that all may benefit from the changes. In addition, notification back
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* to the author will allow the new user to pick up changes that may have
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* been made by other users after this version of the code was distributed.
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*
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* Note1: the majority of this code was edited with 4-space tabs.
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* Note2: as more and more contributions are accepted, the term "author"
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* is becoming a mis-representation of credit.
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*
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* Original author: Ed Sutter
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* Email: esutter@alcatel-lucent.com
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* Phone: 908-582-2351
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**************************************************************************
44
*
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* Ed Sutter has been informed that this code is being used in RTEMS.
46
*
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* The code has been reformatted by Joel Sherrill from OAR Corporation and
48
* Fernando Nicodemos <fgnicodemos@terra.com.br> from NCB - Sistemas
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* Embarcados Ltda. (Brazil) to be more compliant with RTEMS coding standards
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* and to eliminate C++ style comments.
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*/
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#ifndef __sed1356_16bit_h
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#define __sed1356_16bit_h
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56
#include "
bits.h
"
57
/*------------------------------------------------------------------------
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* cpu specific code must define the following board specific macros.
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* in cpuio.h. These examples assume the SED135x has been placed in
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* the correct endian mode via hardware.
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* #define SED_MEM_BASE 0xf0600000 <-- just example addresses,
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* #define SED_REG_BASE 0xf0400000 <-- define for each board
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* #define SED_STEP 1 <-- 1 = device is on 16-bit boundry, 2 = 32-bit boundry, 4 = 64-bit boundry
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* #define SED_REG16(_x_) *(vushortr *)(SED_REG_BASE + (_x_ * SED_STEP)) // Control/Status Registers
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* #define RD_FB16(_reg_,_val_) ((_val_) = *((vushort *)((SED_MEM_BASE + (_reg_ * SED_STEP)))))
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* #define WR_FB16(_reg_,_val_) (*((vushort *)((SED_MEM_BASE + (_reg_ * 2)))) = (_val_))
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* Big endian processors
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* #define H2SED(_x_) ((((x) & 0xff00U) >> 8) | (((x) & 0x00ffU) << 8))
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* Little endian
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* #define H2SED(_x_) (_x_)
71
*
72
*/
73
74
/*
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* SED1356 registers - 16-Bit Access Mode. The first register
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* referenced is the even addressed register. The byte offsets
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* of the odd registers are shown in the comments
78
*/
79
#define SED1356_REG_REV_and_MISC SED_REG16(0x00)
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#define SED1356_REG_GPIO_CFG SED_REG16(0x04)
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#define SED1356_REG_GPIO_CTL SED_REG16(0x08)
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#define SED1356_REG_MD_CFG_RD_LO_and_HI SED_REG16(0x0c)
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#define SED1356_REG_MCLK_CFG SED_REG16(0x10)
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#define SED1356_REG_LCD_PCLK_CFG SED_REG16(0x14)
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#define SED1356_REG_CRT_PCLK_CFG SED_REG16(0x18)
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#define SED1356_REG_MEDIA_PCLK_CFG SED_REG16(0x1c)
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#define SED1356_REG_WAIT_STATE SED_REG16(0x1e)
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#define SED1356_REG_MEM_CFG_and_REF_RATE SED_REG16(0x20)
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#define SED1356_REG_MEM_TMG0_and_1 SED_REG16(0x2a)
90
#define SED1356_REG_PANEL_TYPE_and_MOD_RATE SED_REG16(0x30)
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/* LCD Control registers */
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#define SED1356_REG_LCD_HOR_DISP SED_REG16(0x32)
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#define SED1356_REG_LCD_HOR_NONDISP_and_START SED_REG16(0x34)
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#define SED1356_REG_LCD_HOR_PULSE SED_REG16(0x36)
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#define SED1356_REG_LCD_VER_DISP_HT_LO_and_HI SED_REG16(0x38)
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#define SED1356_REG_LCD_VER_NONDISP_and_START SED_REG16(0x3a)
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#define SED1356_REG_LCD_VER_PULSE SED_REG16(0x3c)
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#define SED1356_REG_LCD_DISP_MODE_and_MISC SED_REG16(0x40)
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#define SED1356_REG_LCD_DISP_START_LO_and_MID SED_REG16(0x42)
100
#define SED1356_REG_LCD_DISP_START_HI SED_REG16(0x44)
101
#define SED1356_REG_LCD_ADD_OFFSET_LO_and_HI SED_REG16(0x46)
102
#define SED1356_REG_LCD_PIXEL_PAN SED_REG16(0x48)
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#define SED1356_REG_LCD_FIFO_THRESH_LO_and_HI SED_REG16(0x4a)
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/* CRT/TV Control registers */
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#define SED1356_REG_CRT_HOR_DISP SED_REG16(0x50)
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#define SED1356_REG_CRT_HOR_NONDISP_and_START SED_REG16(0x52)
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#define SED1356_REG_CRT_HOR_PULSE SED_REG16(0x54)
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#define SED1356_REG_CRT_VER_DISP_HT_LO_and_HI SED_REG16(0x56)
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#define SED1356_REG_CRT_VER_NONDISP_and_START SED_REG16(0x58)
110
#define SED1356_REG_CRT_VER_PULSE_and_OUT_CTL SED_REG16(0x5a)
111
#define SED1356_REG_CRT_DISP_MODE SED_REG16(0x60)
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#define SED1356_REG_CRT_DISP_START_LO_and_MID SED_REG16(0x62)
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#define SED1356_REG_CRT_DISP_START_HI SED_REG16(0x64)
114
#define SED1356_REG_CRT_ADD_OFFSET_LO_and_HI SED_REG16(0x66)
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#define SED1356_REG_CRT_PIXEL_PAN SED_REG16(0x68)
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#define SED1356_REG_CRT_FIFO_THRESH_LO_and_HI SED_REG16(0x6a)
117
/* LCD Cursor Control Registers */
118
#define SED1356_REG_LCD_CURSOR_CTL_and_START_ADD SED_REG16(0x70)
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#define SED1356_REG_LCD_CURSOR_X_POS_LO_and_HI SED_REG16(0x72)
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#define SED1356_REG_LCD_CURSOR_Y_POS_LO_and_HI SED_REG16(0x74)
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#define SED1356_REG_LCD_CURSOR_BLUE_and_GREEN_CLR_0 SED_REG16(0x76)
122
#define SED1356_REG_LCD_CURSOR_RED_CLR_0 SED_REG16(0x78)
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#define SED1356_REG_LCD_CURSOR_BLUE_and_GREEN_CLR_1 SED_REG16(0x7a)
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#define SED1356_REG_LCD_CURSOR_RED_CLR_1 SED_REG16(0x7c)
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#define SED1356_REG_LCD_CURSOR_FIFO_THRESH SED_REG16(0x7e)
126
/* CRT Cursor Control Registers */
127
#define SED1356_REG_CRT_CURSOR_CTL_and_START_ADD SED_REG16(0x80)
128
#define SED1356_REG_CRT_CURSOR_X_POS_LO_and_HI SED_REG16(0x82)
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#define SED1356_REG_CRT_CURSOR_Y_POS_LO_and_HI SED_REG16(0x84)
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#define SED1356_REG_CRT_CURSOR_BLUE_and_GREEN_CLR_0 SED_REG16(0x86)
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#define SED1356_REG_CRT_CURSOR_RED_CLR_0 SED_REG16(0x88)
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#define SED1356_REG_CRT_CURSOR_BLUE_and_GREEN_CLR_1 SED_REG16(0x8a)
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#define SED1356_REG_CRT_CURSOR_RED_CLR_1 SED_REG16(0x8c)
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#define SED1356_REG_CRT_CURSOR_FIFO_THRESH SED_REG16(0x8e)
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/* BitBlt Control Registers */
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#define SED1356_REG_BLT_CTL_0_and_1 SED_REG16(0x100)
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#define SED1356_REG_BLT_ROP_CODE_and_BLT_OP SED_REG16(0x102)
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#define SED1356_REG_BLT_SRC_START_LO_and_MID SED_REG16(0x104)
139
#define SED1356_REG_BLT_SRC_START_HI SED_REG16(0x106)
140
#define SED1356_REG_BLT_DEST_START_LO_and_MID SED_REG16(0x108)
141
#define SED1356_REG_BLT_DEST_START_HI SED_REG16(0x10a)
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#define SED1356_REG_BLT_ADD_OFFSET_LO_and_HI SED_REG16(0x10c)
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#define SED1356_REG_BLT_WID_LO_and_HI SED_REG16(0x110)
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#define SED1356_REG_BLT_HGT_LO_and_HI SED_REG16(0x112)
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#define SED1356_REG_BLT_BG_CLR_LO_and_HI SED_REG16(0x114)
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#define SED1356_REG_BLT_FG_CLR_LO_and_HI SED_REG16(0x118)
147
/* Look-Up Table Control Registers */
148
#define SED1356_REG_LUT_MODE SED_REG16(0x1e0)
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#define SED1356_REG_LUT_ADD SED_REG16(0x1e2)
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#define SED1356_REG_LUT_DATA SED_REG16(0x1e4)
151
/* Power and Miscellaneous Control Registers */
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#define SED1356_REG_PWR_CFG_and_STAT SED_REG16(0x1f0)
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#define SED1356_REG_WATCHDOG_CTL SED_REG16(0x1f4)
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#define SED1356_REG_DISP_MODE SED_REG16(0x1fc)
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156
/*
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* Bit Assignments - Little Endian, Use H2SED() macro to access
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*
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* SED1356_REG_REV_and_MISC - even
160
*/
161
#define SED1356_REV_ID_MASK 0xfc
/* ID bits - masks off the rev bits */
162
#define SED1356_REV_ID_1356 BIT4
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#define SED1356_REV_ID_1355 BIT3
164
165
/* SED1356_REG_REV_and_MISC - odd */
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#define SED1356_MISC_HOST_DIS BIT7 << 8
/* 0 = enable host access, 1 = disable */
167
168
/* SED1356_REG_GPIO_CFG and SED1356_REG_GPIO_STAT */
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#define SED1356_GPIO_GPIO3 BIT3
/* 0 = input, 1 = output, if configured as GPIO */
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#define SED1356_GPIO_GPIO2 BIT2
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#define SED1356_GPIO_GPIO1 BIT1
172
173
/* SED1356_REG_MCLK_CFG */
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#define SED1356_MCLK_DIV2 BIT4
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#define SED1356_MCLK_SRC_BCLK BIT0
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#define SED1356_MCLK_SRC_CLKI 0x00
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178
/* SED1356_REG_LCD_PCLK_CFG, SED1356_REG_CRT_PCLK_CFG
179
* and SED1356_REG_MEDIA_PCLK_CFG
180
*/
181
#define SED1356_PCLK_X2 BIT7
/* SED1356_REG_CRT_PCLK_CFG only */
182
#define SED1356_PCLK_DIV1 0x00 << 4
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#define SED1356_PCLK_DIV2 0x01 << 4
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#define SED1356_PCLK_DIV3 0x02 << 4
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#define SED1356_PCLK_DIV4 0x03 << 4
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#define SED1356_PCLK_SRC_CLKI 0x00
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#define SED1356_PCLK_SRC_BCLK 0x01
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#define SED1356_PCLK_SRC_CLKI2 0x02
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#define SED1356_PCLK_SRC_MCLK 0x03
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191
/* SED1356_REG_MEM_CFG_and_REF_RATE - even */
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#define SED1356_MEM_CFG_2CAS_EDO 0x00
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#define SED1356_MEM_CFG_2CAS_FPM 0x01
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#define SED1356_MEM_CFG_2WE_EDO 0x02
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#define SED1356_MEM_CFG_2WE_FPM 0x03
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#define SED1356_MEM_CFG_MASK 0x03
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198
/* SED1356_REG_MEM_CFG_and_REF_RATE - odd */
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#define SED1356_REF_TYPE_CBR 0x00 << 6 << 8
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#define SED1356_REF_TYPE_SELF 0x01 << 6 << 8
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#define SED1356_REF_TYPE_NONE 0x02 << 6 << 8
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#define SED1356_REF_TYPE_MASK 0x03 << 6 << 8
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#define SED1356_REF_RATE_64 0x00 << 0 << 8
/* MCLK / 64 */
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#define SED1356_REF_RATE_128 0x01 << 0 << 8
/* MCLK / 128 */
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#define SED1356_REF_RATE_256 0x02 << 0 << 8
/* MCLK / 256 */
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#define SED1356_REF_RATE_512 0x03 << 0 << 8
/* MCLK / 512 */
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#define SED1356_REF_RATE_1024 0x04 << 0 << 8
/* MCLK / 1024 */
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#define SED1356_REF_RATE_2048 0x05 << 0 << 8
/* MCLK / 2048 */
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#define SED1356_REF_RATE_4096 0x06 << 0 << 8
/* MCLK / 4096 */
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#define SED1356_REF_RATE_8192 0x07 << 0 << 8
/* MCLK / 8192 */
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#define SED1356_REF_RATE_MASK 0x07 << 0 << 8
/* MCLK / 8192 */
212
213
/* SED1356_REG_MEM_TMG0_and_1 - even */
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#define SED1356_MEM_TMG0_EDO50_MCLK40 0x01
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#define SED1356_MEM_TMG0_EDO50_MCLK33 0x01
216
#define SED1356_MEM_TMG0_EDO60_MCLK33 0x01
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#define SED1356_MEM_TMG0_EDO50_MCLK30 0x12
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#define SED1356_MEM_TMG0_EDO60_MCLK30 0x01
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#define SED1356_MEM_TMG0_EDO70_MCLK30 0x00
220
#define SED1356_MEM_TMG0_EDO50_MCLK25 0x12
221
#define SED1356_MEM_TMG0_EDO60_MCLK25 0x12
222
#define SED1356_MEM_TMG0_EDO70_MCLK25 0x01
223
#define SED1356_MEM_TMG0_EDO80_MCLK25 0x00
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#define SED1356_MEM_TMG0_EDO50_MCLK20 0x12
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#define SED1356_MEM_TMG0_EDO60_MCLK20 0x12
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#define SED1356_MEM_TMG0_EDO70_MCLK20 0x12
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#define SED1356_MEM_TMG0_EDO80_MCLK20 0x01
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#define SED1356_MEM_TMG0_FPM50_MCLK25 0x12
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#define SED1356_MEM_TMG0_FPM60_MCLK25 0x01
230
#define SED1356_MEM_TMG0_FPM50_MCLK20 0x12
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#define SED1356_MEM_TMG0_FPM60_MCLK20 0x12
232
#define SED1356_MEM_TMG0_FPM70_MCLK20 0x11
233
#define SED1356_MEM_TMG0_FPM80_MCLK20 0x01
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235
/* SED1356_REG_MEM_TMG0_and_1 - odd */
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#define SED1356_MEM_TMG1_EDO50_MCLK40 0x01 << 8
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#define SED1356_MEM_TMG1_EDO50_MCLK33 0x01 << 8
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#define SED1356_MEM_TMG1_EDO60_MCLK33 0x01 << 8
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#define SED1356_MEM_TMG1_EDO50_MCLK30 0x02 << 8
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#define SED1356_MEM_TMG1_EDO60_MCLK30 0x01 << 8
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#define SED1356_MEM_TMG1_EDO70_MCLK30 0x00 << 8
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#define SED1356_MEM_TMG1_EDO50_MCLK25 0x02 << 8
243
#define SED1356_MEM_TMG1_EDO60_MCLK25 0x02 << 8
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#define SED1356_MEM_TMG1_EDO70_MCLK25 0x01 << 8
245
#define SED1356_MEM_TMG1_EDO80_MCLK25 0x01 << 8
246
#define SED1356_MEM_TMG1_EDO50_MCLK20 0x02 << 8
247
#define SED1356_MEM_TMG1_EDO60_MCLK20 0x02 << 8
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#define SED1356_MEM_TMG1_EDO70_MCLK20 0x02 << 8
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#define SED1356_MEM_TMG1_EDO80_MCLK20 0x01 << 8
250
#define SED1356_MEM_TMG1_FPM50_MCLK25 0x02 << 8
251
#define SED1356_MEM_TMG1_FPM60_MCLK25 0x01 << 8
252
#define SED1356_MEM_TMG1_FPM50_MCLK20 0x02 << 8
253
#define SED1356_MEM_TMG1_FPM60_MCLK20 0x02 << 8
254
#define SED1356_MEM_TMG1_FPM70_MCLK20 0x02 << 8
255
#define SED1356_MEM_TMG1_FPM80_MCLK20 0x01 << 8
256
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/* Bit definitions
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*
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* SED1356_REG_PANEL_TYPE_AND_MOD_RATE - even
261
*/
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#define SED1356_PANEL_TYPE_EL BIT7
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#define SED1356_PANEL_TYPE_4_9 (0x00 << 4)
/* Passive 4-Bit, TFT 9-Bit */
264
#define SED1356_PANEL_TYPE_8_12 (0x01 << 4)
/* Passive 8-Bit, TFT 12-Bit */
265
#define SED1356_PANEL_TYPE_16 (0x02 << 4)
/* Passive 16-Bit, or TFT 18-Bit */
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#define SED1356_PANEL_TYPE_MASK (0x03 << 4)
267
#define SED1356_PANEL_TYPE_FMT BIT3
/* 0 = Passive Format 1, 1 = Passive Format 2 */
268
#define SED1356_PANEL_TYPE_CLR BIT2
/* 0 = Passive Mono, 1 = Passive Color */
269
#define SED1356_PANEL_TYPE_DUAL BIT1
/* 0 = Passive Single, 1 = Passive Dual */
270
#define SED1356_PANEL_TYPE_TFT BIT0
/* 0 = Passive, 1 = TFT (DUAL, FMT & CLR are don't cares) */
271
272
/* SED1356_REG_CRT_HOR_PULSE, SED1356_REG_CRT_VER_PULSE,
273
* SED1356_REG_LCD_HOR_PULSE and SED1356_REG_LCD_VER_PULSE
274
*/
275
#define SED1356_PULSE_POL_HIGH BIT7
/* 0 = CRT/TFT Pulse is Low, Passive is High, 1 = CRT/TFT Pulse is High, Passive is Low */
276
#define SED1356_PULSE_POL_LOW 0x00
/* 0 = CRT/TFT Pulse is Low, Passive is High, 1 = CRT/TFT Pulse is High, Passive is Low */
277
#define SED1356_PULSE_WID(_x_) (_x_ & 0x0f)
/* Pulse Width in Pixels */
278
279
/* SED1356_LCD_DISP_MODE_and_MISC - even */
280
#define SED1356_LCD_DISP_BLANK BIT7
/* 1 = Blank LCD Display */
281
#define SED1356_LCD_DISP_SWIV_NORM (0x00 << 4)
/* Used with SED1356_REG_DISP_MODE Bit 6 */
282
#define SED1356_LCD_DISP_SWIV_90 (0x00 << 4)
283
#define SED1356_LCD_DISP_SWIV_180 (0x01 << 4)
284
#define SED1356_LCD_DISP_SWIV_270 (0x01 << 4)
285
#define SED1356_LCD_DISP_SWIV_MASK (0x01 << 4)
286
#define SED1356_LCD_DISP_16BPP 0x05
/* Bit Per Pixel Selection */
287
#define SED1356_LCD_DISP_15BPP 0x04
288
#define SED1356_LCD_DISP_8BPP 0x03
289
#define SED1356_LCD_DISP_4BPP 0x02
290
#define SED1356_LCD_DISP_BPP_MASK 0x07
291
292
/* SED1356_LCD_DISP_MODE_and_MISC - odd */
293
#define SED1356_LCD_MISC_DITH BIT1 << 8
/* 1 = Dither Disable, Passive Panel Only */
294
#define SED1356_LCD_MISC_DUAL BIT0 << 8
/* 1 = Dual Panel Disable, Passive Panel Only */
295
296
/* SED1356_REG_CRT_VER_PULSE_and_OUT_CTL - odd */
297
#define SED1356_CRT_OUT_CHROM BIT5 << 8
/* 1 = TV Chrominance Filter Enable */
298
#define SED1356_CRT_OUT_LUM BIT4 << 8
/* 1 = TV Luminance Filter Enable */
299
#define SED1356_CRT_OUT_DAC_LVL BIT3 << 8
/* 1 = 4.6ma IREF, 0 = 9.2 IREF */
300
#define SED1356_CRT_OUT_SVIDEO BIT1 << 8
/* 1 = S-Video Output, 0 = Composite Video Output */
301
#define SED1356_CRT_OUT_PAL BIT0 << 8
/* 1 = PAL Format Output, 0 = NTSC Format Output */
302
303
/* SED1356_REG_CRT_DISP_MODE */
304
#define SED1356_CRT_DISP_BLANK BIT7
/* 1 = Blank CRT Display */
305
#define SED1356_CRT_DISP_16BPP 0x05
/* Bit Per Pixel Selection */
306
#define SED1356_CRT_DISP_15BPP 0x04
307
#define SED1356_CRT_DISP_8BPP 0x03
308
#define SED1356_CRT_DISP_4BPP 0x02
309
#define SED1356_CRT_DISP_BPP_MASK 0x07
310
311
/* SED1356_DISP_MODE */
312
#define SED1356_DISP_SWIV_NORM (0x00 << 6)
/* Used with SED1356_LCD_DISP_MODE Bit 4 */
313
#define SED1356_DISP_SWIV_90 (0x01 << 6)
314
#define SED1356_DISP_SWIV_180 (0x00 << 6)
315
#define SED1356_DISP_SWIV_270 (0x01 << 6)
316
#define SED1356_DISP_MODE_OFF 0x00
/* All Displays Off */
317
#define SED1356_DISP_MODE_LCD 0x01
/* LCD Only */
318
#define SED1356_DISP_MODE_CRT 0x02
/* CRT Only */
319
#define SED1356_DISP_MODE_LCD_CRT 0x03
/* Simultaneous LCD and CRT */
320
#define SED1356_DISP_MODE_TV 0x04
/* TV Only, Flicker Filter Off */
321
#define SED1356_DISP_MODE_TV_LCD 0x05
/* Simultaneous LCD and TV, Flicker Filter Off */
322
#define SED1356_DISP_MODE_TV_FLICK 0x06
/* TV Only, Flicker Filter On */
323
#define SED1356_DISP_MODE_TV_LCD_FLICK 0x07
/* Simultaneous LCD and TV, Flicker Filter On */
324
325
/* SED1356_REG_PWR_CFG and SED1356_REG_PWR_STAT */
326
#define SED1356_PWR_PCLK BIT1
/* SED1356_REG_PWR_STAT only */
327
#define SED1356_PWR_MCLK BIT0
328
329
/* SED1356_REG_VER_NONDISP */
330
#define SED1356_VER_NONDISP BIT7
/* vertical retrace status 1 = in retrace */
331
332
/* Display size defines */
333
extern
long
PIXELS_PER_ROW;
334
extern
long
PIXELS_PER_COL;
335
#define BYTES_PER_PIXEL 2
336
extern
long
COLS_PER_SCREEN;
337
extern
long
ROWS_PER_SCREEN;
338
339
/* 16-bit pixels are RGB 565 - LSB of RED and BLUE are tied low at the */
340
/* LCD Interface, while the LSB of GREEN is loaded as 0 */
341
#define RED_SUBPIXEL(n) ((n & 0x1f) << 11)
342
#define GREEN_SUBPIXEL(n) ((n & 0x1f) << 5)
343
#define BLUE_SUBPIXEL(n) ((n & 0x1f) << 0)
344
345
/* define a simple VGA style 16-color pallette */
346
#if 0
347
#define LU_BLACK (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00))
348
#define LU_BLUE (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x0f))
349
#define LU_GREEN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x00))
350
#define LU_CYAN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x0f))
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#define LU_RED (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00))
352
#define LU_VIOLET (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x0f))
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#define LU_YELLOW (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x00))
354
#define LU_GREY (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x0f))
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#define LU_WHITE (RED_SUBPIXEL(0x17) | GREEN_SUBPIXEL(0x17) | BLUE_SUBPIXEL(0x17))
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#define LU_BRT_BLUE (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x1f))
357
#define LU_BRT_GREEN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x00))
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#define LU_BRT_CYAN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x1f))
359
#define LU_BRT_RED (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00))
360
#define LU_BRT_VIOLET (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x1f))
361
#define LU_BRT_YELLOW (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x00))
362
#define LU_BRT_WHITE (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x1f))
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/* RED, GREEN, BLUE Entry */
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{ 0x00, 0x00, 0x00, },
/* LU_BLACK */
365
{ 0x00, 0x00, 0xA0, },
/* LU_BLUE */
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{ 0x00, 0xA0, 0x00, },
/* LU_GREEN */
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{ 0x00, 0xA0, 0xA0, },
/* LU_CYAN */
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{ 0xA0, 0x00, 0x00, },
/* LU_RED */
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{ 0xA0, 0x00, 0xA0, },
/* LU_VIOLET */
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{ 0xA0, 0xA0, 0x00, },
/* LU_YELLOW */
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{ 0xA0, 0xA0, 0xA0, },
/* LU_WHITE */
372
{ 0x50, 0x50, 0x50, },
/* LU_GREY */
373
{ 0x50, 0x50, 0xF0, },
/* LU_BRT_BLUE */
374
{ 0x50, 0xF0, 0x50, },
/* LU_BRT_GREEN */
375
{ 0x50, 0xF0, 0xF0, },
/* LU_BRT_CYAN */
376
{ 0xF0, 0x50, 0x50, },
/* LU_BRT_RED */
377
{ 0xF0, 0x50, 0xF0, },
/* LU_BRT_VIOLET */
378
{ 0xF0, 0xF0, 0x50, },
/* LU_BRT_YELLOW */
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{ 0xF0, 0xF0, 0xF0, },
/* LU_BRT_WHITE */
380
#endif
381
382
#define BLUE (0x14 << 0)
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#define GREEN (0x14 << 6)
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#define RED (0x14 << 11)
385
386
#define HALF_BLUE (0x0a << 0)
387
#define HALF_GREEN (0x0a << 6)
388
#define HALF_RED (0x0a << 11)
389
390
391
#define BRT_BLUE (0x1e << 0)
392
#define BRT_GREEN (0x1e << 6)
393
#define BRT_RED (0x1e << 11)
394
395
#define LU_BLACK 0
396
#define LU_BLUE (BLUE)
397
#define LU_GREEN (GREEN)
398
#define LU_CYAN (GREEN | BLUE)
399
#define LU_RED (RED)
400
#define LU_VIOLET (RED | BLUE)
401
#define LU_YELLOW (RED | GREEN)
402
#define LU_WHITE (RED | GREEN | BLUE)
403
#define LU_GREY (HALF_RED | HALF_GREEN | HALF_BLUE)
404
#define LU_BRT_BLUE (HALF_RED | HALF_GREEN | BRT_BLUE)
405
#define LU_BRT_GREEN (HALF_RED | BRT_GREEN | HALF_BLUE)
406
#define LU_BRT_CYAN (HALF_RED | BRT_GREEN | BRT_BLUE)
407
#define LU_BRT_RED (BRT_RED | HALF_GREEN | HALF_BLUE)
408
#define LU_BRT_VIOLET (BRT_RED | HALF_GREEN | BRT_BLUE)
409
#define LU_BRT_YELLOW (BRT_RED | BRT_GREEN | HALF_BLUE)
410
#define LU_BRT_WHITE (BRT_RED | BRT_GREEN | BRT_BLUE)
411
412
const
ushort vga_lookup[] = {
413
LU_BLACK,
/* 0 */
414
LU_BLUE,
/* 1 */
415
LU_GREEN,
/* 2 */
416
LU_CYAN,
/* 3 */
417
LU_RED,
/* 4 */
418
LU_VIOLET,
/* 5 */
419
LU_YELLOW,
/* 6 */
420
LU_WHITE,
/* 7 */
421
LU_GREY,
/* 8 */
422
LU_BRT_BLUE,
/* 9 */
423
LU_BRT_GREEN,
/* 10 */
424
LU_BRT_CYAN,
/* 11 */
425
LU_BRT_RED,
/* 12 */
426
LU_BRT_VIOLET,
/* 13 */
427
LU_BRT_YELLOW,
/* 14 */
428
LU_BRT_WHITE
/* 15 */
429
};
430
431
/* default foreground and background colors */
432
#define SED_BG_DEF 1
433
#define SED_FG_DEF 14
434
435
/* Draw defines */
436
#define TOP 0
437
#define BOTTOM (PIXELS_PER_COL-1)
438
#define LEFT 0
439
#define RIGHT (PIXELS_PER_ROW-1)
440
#define CENTER_X (PIXELS_PER_ROW/2)
441
#define CENTER_Y (PIXELS_PER_COL/2)
442
443
444
/* Vertical and Horizontal Pulse, Start and Non-Display values vary depending
445
* upon the mode. The following section gives some insight into how the
446
* values are arrived at.
447
* ms = milliseconds, us = microseconds, ns = nanoseconds
448
* Mhz = Megaherz, Khz = Kiloherz, Hz = Herz
449
*
450
* ***************************************************************************************************
451
* CRT Mode is 640x480 @ 72Hz VESA compatible timing. PCLK = 31.5Mhz (31.75ns)
452
* ***************************************************************************************************
453
*
454
* CRT MODE HORIZONTAL TIMING PARAMETERS
455
*
456
* |<-------Tha------->|
457
* |___________________| ______
458
* Display Enable _____________________| |____________________|
459
* | |
460
* Horizontal Pulse __ ________|___________________|________ __________
461
* |_________| | | |________|
462
* |<- Thp ->| | | |
463
* | |<-Thbp->| | |
464
* | |<-Thfp->|
465
* |<----------------------Tht-------------------->|
466
*
467
* Tha - Active Display Time = 640 pixels
468
* Thp - Horizontal Pulse = 1.27us/31.75ns = 40 pixels
469
* Thbp - Horizontal Front Porch = 1.016us/31.75ns = 32 pixels
470
* Thfp - Horizontal Back Porch = 3.8us/31.75ns = 120 pixels
471
* Tht - Total Horizontal Time = 832 pixels x 32.75ns/pixel = 26.416us or 38.785Khz
472
*
473
* Correlation between horizontal timing parameters and SED registers
474
*/
475
#define SED_HOR_PULSE_WIDTH_CRT 0x07
/* Horizontal Pulse Width Register = (Thp/8) - 1 */
476
#define SED_HOR_PULSE_START_CRT 0x02
/* Horizontal Pulse Start Position Register = ((Thfp + 2)/8) - 1 */
477
#define SED_HOR_NONDISP_CRT 0x17
/* Horizontal Non-Display Period Register = ((Thp + Thfp + Thbp)/8) - 1 */
478
/*
479
* CRT MODE VERTICAL TIMING PARAMTERS
480
*
481
* |<-------Tva------->|
482
* |___________________| ______
483
* Display Enable _____________________| |_____________________|
484
* | |
485
* Vertical Pulse __ ________|___________________|________ __________
486
* |_________| | | |________|
487
* |<- Tvp ->| | | |
488
* | |<-Tvbp->| | |
489
* | |<-Tvfp->|
490
* |<----------------------Tvt-------------------->|
491
*
492
* Tva - Active Display Time = 480 lines
493
* Tvp - Vertical Pulse = 3 lines
494
* Tvfp - Vertical Front Porch = 9 lines
495
* Tvbp - Vertical Back Porch = 28 lines
496
* Tvt - Total Horizontal Time = 520 lines x 26.416us/line = 13.73632ms or 72.8Hz
497
*
498
* Correlation between vertical timing parameters and SED registers
499
*/
500
#define SED_VER_PULSE_WIDTH_CRT 0x02
// VRTC/FPFRAME Pulse Width Register = Tvp - 1
501
#define SED_VER_PULSE_START_CRT 0x08
// VRTC/FPFRAME Start Position Register = Tvfp - 1
502
#define SED_VER_NONDISP_CRT 0x27
// Vertical Non-Display Period Register = (Tvp + Tvfp + Tvbp) - 1
503
/*
504
*****************************************************************************************************
505
* DUAL LCD Mode is 640x480 @ 60Hz VGA compatible timing. PCLK = 25.175Mhz (39.722ns)
506
*****************************************************************************************************
507
*
508
* LCD MODE HORIZONTAL TIMING PARAMTERS
509
*
510
* |<-------Tha------->|
511
* |___________________| ______
512
* Display Enable _____________________| |____________________|
513
* | |
514
* Horizontal Pulse __ ________|___________________|________ __________
515
* |_________| | | |________|
516
* |<- Thp ->| | | |
517
* | |<-Thbp->| | |
518
* | |<-Thfp->|
519
* |<----------------------Tht-------------------->|
520
*
521
* Tha - Active Display Time = 640 pixels
522
* Thp - Horizontal Pulse = 3.8us/39.72ns = 96 pixels
523
* Thfp - Horizontal Front Porch = .595us/39.72ns = 16 pixels
524
* Thbp - Horizontal Backporch = 1.9us/39.72ns = 48 pixels
525
* Tht - Total Horizontal Time = = 800 pixels @ 39.72ns/pixel = 31.776us or 31.47Khz
526
*
527
* Correlation between horizontal timing parameters and SED registers
528
*#define SED_HOR_PULSE_WIDTH_LCD 0x0b // HRTC/FPLINE Pulse Width Register = (Thp/8) - 1
529
*#define SED_HOR_PULSE_START_LCD 0x02 // HRTC/FPLINE Start Position Register = (Thfp/8) - 2
530
*#define SED_HOR_NONDISP_LCD 0x13 // Horizontal Non-Display Period Register = ((Thp + Thfp + Thbp)/8) - 1
531
*/
532
extern
long
SED_HOR_PULSE_WIDTH_LCD;
533
extern
long
SED_HOR_PULSE_START_LCD;
534
extern
long
SED_HOR_NONDISP_LCD;
535
536
/*
537
*
538
* LCD MODE VERTICAL TIMING PARAMTERS
539
*
540
* |<-------Tva------->|
541
* |___________________| ______
542
* Display Enable _____________________| |_____________________|
543
* | |
544
* Vertical Pulse __ ________|___________________|________ __________
545
* |_________| | | |________|
546
* |<- Tvp ->| | | |
547
* | |<-Tvbp->| | |
548
* | |<-Tvfp->|
549
* |<----------------------Tvt-------------------->|
550
*
551
* Tva - Active Display Time = 480 lines
552
* Tvp - Vertical Pulse = 2 lines
553
* Tvfp - Vertical Front Porch = 10 lines
554
* Tvbp - Vertical Backporch = 33 lines
555
* Tvt - Total Horizontal Time = 525 lines @ 31.776us/line = 16.682ms or 60Hz
556
*
557
* Correlation between vertical timing parameters and SED registers
558
*#define SED_VER_PULSE_WIDTH_LCD 0x01 // VRTC/FPFRAME Pulse Width Register = Tvp - 1
559
*#define SED_VER_PULSE_START_LCD 0x09 // VRTC/FPFRAME Start Position Register = Tvfp - 1
560
*#define SED_VER_NONDISP_LCD 0x2c // Vertical Non-Display Period Register = (Tvp + Tvfp + Tvbp) - 1
561
*/
562
extern
long
SED_VER_PULSE_WIDTH_LCD;
563
extern
long
SED_VER_PULSE_START_LCD;
564
extern
long
SED_VER_NONDISP_LCD;
565
566
#endif
bits.h
Contains bit position definitions.
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