RTEMS 7.0-rc1
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s3c2410.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2008 Ray Xu <rayx.cn@gmail.com>
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#ifndef S3C2410_H_
37#define S3C2410_H_
38
39/* to be used in assembly code */
40#define rINTOFFSET_ADDR 0x4A000014
41/* Memory control */
42#define rBWSCON (*(volatile unsigned *)0x48000000)
43#define rBANKCON0 (*(volatile unsigned *)0x48000004)
44#define rBANKCON1 (*(volatile unsigned *)0x48000008)
45#define rBANKCON2 (*(volatile unsigned *)0x4800000C)
46#define rBANKCON3 (*(volatile unsigned *)0x48000010)
47#define rBANKCON4 (*(volatile unsigned *)0x48000014)
48#define rBANKCON5 (*(volatile unsigned *)0x48000018)
49#define rBANKCON6 (*(volatile unsigned *)0x4800001C)
50#define rBANKCON7 (*(volatile unsigned *)0x48000020)
51#define rREFRESH (*(volatile unsigned *)0x48000024)
52#define rBANKSIZE (*(volatile unsigned *)0x48000028)
53#define rMRSRB6 (*(volatile unsigned *)0x4800002C)
54#define rMRSRB7 (*(volatile unsigned *)0x48000030)
55
56/* USB Host Controller */
57#define rHcRevision (*(volatile unsigned *)0x49000000)
58#define rHcControl (*(volatile unsigned *)0x49000004)
59#define rHcCommonStatus (*(volatile unsigned *)0x49000008)
60#define rHcInterruptStatus (*(volatile unsigned *)0x4900000C)
61#define rHcInterruptEnable (*(volatile unsigned *)0x49000010)
62#define rHcInterruptDisable (*(volatile unsigned *)0x49000014)
63#define rHcHCCA (*(volatile unsigned *)0x49000018)
64#define rHcPeriodCuttendED (*(volatile unsigned *)0x4900001C)
65#define rHcControlHeadED (*(volatile unsigned *)0x49000020)
66#define rHcControlCurrentED (*(volatile unsigned *)0x49000024)
67#define rHcBulkHeadED (*(volatile unsigned *)0x49000028)
68#define rHcBuldCurrentED (*(volatile unsigned *)0x4900002C)
69#define rHcDoneHead (*(volatile unsigned *)0x49000030)
70#define rHcRmInterval (*(volatile unsigned *)0x49000034)
71#define rHcFmRemaining (*(volatile unsigned *)0x49000038)
72#define rHcFmNumber (*(volatile unsigned *)0x4900003C)
73#define rHcPeriodicStart (*(volatile unsigned *)0x49000040)
74#define rHcLSThreshold (*(volatile unsigned *)0x49000044)
75#define rHcRhDescriptorA (*(volatile unsigned *)0x49000048)
76#define rHcRhDescriptorB (*(volatile unsigned *)0x4900004C)
77#define rHcRhStatus (*(volatile unsigned *)0x49000050)
78#define rHcRhPortStatus1 (*(volatile unsigned *)0x49000054)
79#define rHcRhPortStatus2 (*(volatile unsigned *)0x49000058)
80
81/* INTERRUPT */
82#define rSRCPND (*(volatile unsigned *)0x4A000000)
83#define rINTMOD (*(volatile unsigned *)0x4A000004)
84#define rINTMSK (*(volatile unsigned *)0x4A000008)
85#define rPRIORITY (*(volatile unsigned *)0x4A00000C)
86#define rINTPND (*(volatile unsigned *)0x4A000010)
87#define rINTOFFSET (*(volatile unsigned *)0x4A000014)
88#define rSUBSRCPND (*(volatile unsigned *)0x4A000018)
89#define rINTSUBMSK (*(volatile unsigned *)0x4A00001c)
90
91
92/* DMA */
93#define rDISRC0 (*(volatile unsigned *)0x4B000000)
94#define rDISRCC0 (*(volatile unsigned *)0x4B000004)
95#define rDIDST0 (*(volatile unsigned *)0x4B000008)
96#define rDIDSTC0 (*(volatile unsigned *)0x4B00000C)
97#define rDCON0 (*(volatile unsigned *)0x4B000010)
98#define rDSTAT0 (*(volatile unsigned *)0x4B000014)
99#define rDCSRC0 (*(volatile unsigned *)0x4B000018)
100#define rDCDST0 (*(volatile unsigned *)0x4B00001C)
101#define rDMASKTRIG0 (*(volatile unsigned *)0x4B000020)
102#define rDISRC1 (*(volatile unsigned *)0x4B000040)
103#define rDISRCC1 (*(volatile unsigned *)0x4B000044)
104#define rDIDST1 (*(volatile unsigned *)0x4B000048)
105#define rDIDSTC1 (*(volatile unsigned *)0x4B00004C)
106#define rDCON1 (*(volatile unsigned *)0x4B000050)
107#define rDSTAT1 (*(volatile unsigned *)0x4B000054)
108#define rDCSRC1 (*(volatile unsigned *)0x4B000058)
109#define rDCDST1 (*(volatile unsigned *)0x4B00005C)
110#define rDMASKTRIG1 (*(volatile unsigned *)0x4B000060)
111#define rDISRC2 (*(volatile unsigned *)0x4B000080)
112#define rDISRCC2 (*(volatile unsigned *)0x4B000084)
113#define rDIDST2 (*(volatile unsigned *)0x4B000088)
114#define rDIDSTC2 (*(volatile unsigned *)0x4B00008C)
115#define rDCON2 (*(volatile unsigned *)0x4B000090)
116#define rDSTAT2 (*(volatile unsigned *)0x4B000094)
117#define rDCSRC2 (*(volatile unsigned *)0x4B000098)
118#define rDCDST2 (*(volatile unsigned *)0x4B00009C)
119#define rDMASKTRIG2 (*(volatile unsigned *)0x4B0000A0)
120#define rDISRC3 (*(volatile unsigned *)0x4B0000C0)
121#define rDISRCC3 (*(volatile unsigned *)0x4B0000C4)
122#define rDIDST3 (*(volatile unsigned *)0x4B0000C8)
123#define rDIDSTC3 (*(volatile unsigned *)0x4B0000CC)
124#define rDCON3 (*(volatile unsigned *)0x4B0000D0)
125#define rDSTAT3 (*(volatile unsigned *)0x4B0000D4)
126#define rDCSRC3 (*(volatile unsigned *)0x4B0000D8)
127#define rDCDST3 (*(volatile unsigned *)0x4B0000DC)
128#define rDMASKTRIG3 (*(volatile unsigned *)0x4B0000E0)
129
130
131/* CLOCK & POWER MANAGEMENT */
132#define rLOCKTIME (*(volatile unsigned *)0x4C000000)
133#define rMPLLCON (*(volatile unsigned *)0x4C000004)
134#define rUPLLCON (*(volatile unsigned *)0x4C000008)
135#define rCLKCON (*(volatile unsigned *)0x4C00000C)
136#define rCLKSLOW (*(volatile unsigned *)0x4C000010)
137#define rCLKDIVN (*(volatile unsigned *)0x4C000014)
138
139
140/* LCD CONTROLLER */
141#define rLCDCON1 (*(volatile unsigned *)0x4D000000)
142#define rLCDCON2 (*(volatile unsigned *)0x4D000004)
143#define rLCDCON3 (*(volatile unsigned *)0x4D000008)
144#define rLCDCON4 (*(volatile unsigned *)0x4D00000C)
145#define rLCDCON5 (*(volatile unsigned *)0x4D000010)
146#define rLCDSADDR1 (*(volatile unsigned *)0x4D000014)
147#define rLCDSADDR2 (*(volatile unsigned *)0x4D000018)
148#define rLCDSADDR3 (*(volatile unsigned *)0x4D00001C)
149#define rREDLUT (*(volatile unsigned *)0x4D000020)
150#define rGREENLUT (*(volatile unsigned *)0x4D000024)
151#define rBLUELUT (*(volatile unsigned *)0x4D000028)
152#define rREDLUT (*(volatile unsigned *)0x4D000020)
153#define rGREENLUT (*(volatile unsigned *)0x4D000024)
154#define rBLUELUT (*(volatile unsigned *)0x4D000028)
155#define rDITHMODE (*(volatile unsigned *)0x4D00004C)
156#define rTPAL (*(volatile unsigned *)0x4D000050)
157#define rLCDINTPND (*(volatile unsigned *)0x4D000054)
158#define rLCDSRCPND (*(volatile unsigned *)0x4D000058)
159#define rLCDINTMSK (*(volatile unsigned *)0x4D00005C)
160#define rTCONSEL (*(volatile unsigned *)0x4D000060)
161#define PALETTE 0x4d000400
162
163/* NAND Flash */
164#define rNFCONF (*(volatile unsigned *)0x4E000000)
165#define rNFCMD (*(volatile unsigned *)0x4E000004)
166#define rNFADDR (*(volatile unsigned *)0x4E000008)
167#define rNFDATA (*(volatile unsigned *)0x4E00000C)
168#define rNFSTAT (*(volatile unsigned *)0x4E000010)
169#define rNFECC (*(volatile unsigned *)0x4E000014)
170
171/* UART */
172#define rULCON0 (*(volatile unsigned char *)0x50000000)
173#define rUCON0 (*(volatile unsigned short *)0x50000004)
174#define rUFCON0 (*(volatile unsigned char *)0x50000008)
175#define rUMCON0 (*(volatile unsigned char *)0x5000000C)
176#define rUTRSTAT0 (*(volatile unsigned char *)0x50000010)
177#define rUERSTAT0 (*(volatile unsigned char *)0x50000014)
178#define rUFSTAT0 (*(volatile unsigned short *)0x50000018)
179#define rUMSTAT0 (*(volatile unsigned char *)0x5000001C)
180#define rUBRDIV0 (*(volatile unsigned short *)0x50000028)
181
182#define rULCON1 (*(volatile unsigned char *)0x50004000)
183#define rUCON1 (*(volatile unsigned short *)0x50004004)
184#define rUFCON1 (*(volatile unsigned char *)0x50004008)
185#define rUMCON1 (*(volatile unsigned char *)0x5000400C)
186#define rUTRSTAT1 (*(volatile unsigned char *)0x50004010)
187#define rUERSTAT1 (*(volatile unsigned char *)0x50004014)
188#define rUFSTAT1 (*(volatile unsigned short *)0x50004018)
189#define rUMSTAT1 (*(volatile unsigned char *)0x5000401C)
190#define rUBRDIV1 (*(volatile unsigned short *)0x50004028)
191
192#define rULCON2 (*(volatile unsigned char *)0x50008000)
193#define rUCON2 (*(volatile unsigned short *)0x50008004)
194#define rUFCON2 (*(volatile unsigned char *)0x50008008)
195#define rUTRSTAT2 (*(volatile unsigned char *)0x50008010)
196#define rUERSTAT2 (*(volatile unsigned char *)0x50008014)
197#define rUFSTAT2 (*(volatile unsigned short *)0x50008018)
198#define rUBRDIV2 (*(volatile unsigned short *)0x50008028)
199
200#ifdef __BIG_ENDIAN
201#define rUTXH0 (*(volatile unsigned char *)0x50000023)
202#define rURXH0 (*(volatile unsigned char *)0x50000027)
203#define rUTXH1 (*(volatile unsigned char *)0x50004023)
204#define rURXH1 (*(volatile unsigned char *)0x50004027)
205#define rUTXH2 (*(volatile unsigned char *)0x50008023)
206#define rURXH2 (*(volatile unsigned char *)0x50008027)
207
208#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch)
209#define RdURXH0() (*(volatile unsigned char *)0x50000027)
210#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch)
211#define RdURXH1() (*(volatile unsigned char *)0x50004027)
212#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch)
213#define RdURXH2() (*(volatile unsigned char *)0x50008027)
214
215#define UTXH0 (0x50000020+3) /* byte_access address by DMA */
216#define URXH0 (0x50000024+3)
217#define UTXH1 (0x50004020+3)
218#define URXH1 (0x50004024+3)
219#define UTXH2 (0x50008020+3)
220#define URXH2 (0x50008024+3)
221
222#else /* Little Endian */
223#define rUTXH0 (*(volatile unsigned char *)0x50000020)
224#define rURXH0 (*(volatile unsigned char *)0x50000024)
225#define rUTXH1 (*(volatile unsigned char *)0x50004020)
226#define rURXH1 (*(volatile unsigned char *)0x50004024)
227#define rUTXH2 (*(volatile unsigned char *)0x50008020)
228#define rURXH2 (*(volatile unsigned char *)0x50008024)
229
230#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch)
231#define RdURXH0() (*(volatile unsigned char *)0x50000024)
232#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch)
233#define RdURXH1() (*(volatile unsigned char *)0x50004024)
234#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch)
235#define RdURXH2() (*(volatile unsigned char *)0x50008024)
236
237#define UTXH0 (0x50000020)
238#define URXH0 (0x50000024)
239#define UTXH1 (0x50004020)
240#define URXH1 (0x50004024)
241#define UTXH2 (0x50008020)
242#define URXH2 (0x50008024)
243#endif
244
245
246/* PWM TIMER */
247#define rTCFG0 (*(volatile unsigned *)0x51000000)
248#define rTCFG1 (*(volatile unsigned *)0x51000004)
249#define rTCON (*(volatile unsigned *)0x51000008)
250#define rTCNTB0 (*(volatile unsigned *)0x5100000C)
251#define rTCMPB0 (*(volatile unsigned *)0x51000010)
252#define rTCNTO0 (*(volatile unsigned *)0x51000014)
253#define rTCNTB1 (*(volatile unsigned *)0x51000018)
254#define rTCMPB1 (*(volatile unsigned *)0x5100001C)
255#define rTCNTO1 (*(volatile unsigned *)0x51000020)
256#define rTCNTB2 (*(volatile unsigned *)0x51000024)
257#define rTCMPB2 (*(volatile unsigned *)0x51000028)
258#define rTCNTO2 (*(volatile unsigned *)0x5100002C)
259#define rTCNTB3 (*(volatile unsigned *)0x51000030)
260#define rTCMPB3 (*(volatile unsigned *)0x51000034)
261#define rTCNTO3 (*(volatile unsigned *)0x51000038)
262#define rTCNTB4 (*(volatile unsigned *)0x5100003C)
263#define rTCNTO4 (*(volatile unsigned *)0x51000040)
264
265
266/* USB DEVICE */
267#ifdef __BIG_ENDIAN
268#define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000143) //Function address
269#define rPWR_REG (*(volatile unsigned char *)0x52000147) //Power management
270#define rEP_INT_REG (*(volatile unsigned char *)0x5200014b) //EP Interrupt pending and clear
271#define rUSB_INT_REG (*(volatile unsigned char *)0x5200015b) //USB Interrupt pending and clear
272#define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015f) //Interrupt enable
273#define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016f)
274#define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000173) //Frame number lower byte
275#define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000177) //Frame number higher byte
276#define rINDEX_REG (*(volatile unsigned char *)0x5200017b) //Register index
277#define rMAXP_REG (*(volatile unsigned char *)0x52000183) //Endpoint max packet
278#define rEP0_CSR (*(volatile unsigned char *)0x52000187) //Endpoint 0 status
279#define rIN_CSR1_REG (*(volatile unsigned char *)0x52000187) //In endpoint control status
280#define rIN_CSR2_REG (*(volatile unsigned char *)0x5200018b)
281#define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000193) //Out endpoint control status
282#define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000197)
283#define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019b) //Endpoint out write count
284#define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019f)
285#define rEP0_FIFO (*(volatile unsigned char *)0x520001c3) //Endpoint 0 FIFO
286#define rEP1_FIFO (*(volatile unsigned char *)0x520001c7) //Endpoint 1 FIFO
287#define rEP2_FIFO (*(volatile unsigned char *)0x520001cb) //Endpoint 2 FIFO
288#define rEP3_FIFO (*(volatile unsigned char *)0x520001cf) //Endpoint 3 FIFO
289#define rEP4_FIFO (*(volatile unsigned char *)0x520001d3) //Endpoint 4 FIFO
290#define rEP1_DMA_CON (*(volatile unsigned char *)0x52000203) //EP1 DMA interface control
291#define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000207) //EP1 DMA Tx unit counter
292#define rEP1_DMA_FIFO (*(volatile unsigned char *)0x5200020b) //EP1 DMA Tx FIFO counter
293#define rEP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020f) //EP1 DMA total Tx counter
294#define rEP1_DMA_TTC_M (*(volatile unsigned char *)0x52000213)
295#define rEP1_DMA_TTC_H (*(volatile unsigned char *)0x52000217)
296#define rEP2_DMA_CON (*(volatile unsigned char *)0x5200021b) //EP2 DMA interface control
297#define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021f) //EP2 DMA Tx unit counter
298#define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000223) //EP2 DMA Tx FIFO counter
299#define rEP2_DMA_TTC_L (*(volatile unsigned char *)0x52000227) //EP2 DMA total Tx counter
300#define rEP2_DMA_TTC_M (*(volatile unsigned char *)0x5200022b)
301#define rEP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022f)
302#define rEP3_DMA_CON (*(volatile unsigned char *)0x52000243) //EP3 DMA interface control
303#define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000247) //EP3 DMA Tx unit counter
304#define rEP3_DMA_FIFO (*(volatile unsigned char *)0x5200024b) //EP3 DMA Tx FIFO counter
305#define rEP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024f) //EP3 DMA total Tx counter
306#define rEP3_DMA_TTC_M (*(volatile unsigned char *)0x52000253)
307#define rEP3_DMA_TTC_H (*(volatile unsigned char *)0x52000257)
308#define rEP4_DMA_CON (*(volatile unsigned char *)0x5200025b) //EP4 DMA interface control
309#define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025f) //EP4 DMA Tx unit counter
310#define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000263) //EP4 DMA Tx FIFO counter
311#define rEP4_DMA_TTC_L (*(volatile unsigned char *)0x52000267) //EP4 DMA total Tx counter
312#define rEP4_DMA_TTC_M (*(volatile unsigned char *)0x5200026b)
313#define rEP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026f)
314
315#else // Little Endian
316#define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000140) //Function address
317#define rPWR_REG (*(volatile unsigned char *)0x52000144) //Power management
318#define rEP_INT_REG (*(volatile unsigned char *)0x52000148) //EP Interrupt pending and clear
319#define rUSB_INT_REG (*(volatile unsigned char *)0x52000158) //USB Interrupt pending and clear
320#define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015c) //Interrupt enable
321#define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016c)
322#define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000170) //Frame number lower byte
323#define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000174) //Frame number higher byte
324#define rINDEX_REG (*(volatile unsigned char *)0x52000178) //Register index
325#define rMAXP_REG (*(volatile unsigned char *)0x52000180) //Endpoint max packet
326#define rEP0_CSR (*(volatile unsigned char *)0x52000184) //Endpoint 0 status
327#define rIN_CSR1_REG (*(volatile unsigned char *)0x52000184) //In endpoint control status
328#define rIN_CSR2_REG (*(volatile unsigned char *)0x52000188)
329#define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000190) //Out endpoint control status
330#define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000194)
331#define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198) //Endpoint out write count
332#define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019c)
333#define rEP0_FIFO (*(volatile unsigned char *)0x520001c0) //Endpoint 0 FIFO
334#define rEP1_FIFO (*(volatile unsigned char *)0x520001c4) //Endpoint 1 FIFO
335#define rEP2_FIFO (*(volatile unsigned char *)0x520001c8) //Endpoint 2 FIFO
336#define rEP3_FIFO (*(volatile unsigned char *)0x520001cc) //Endpoint 3 FIFO
337#define rEP4_FIFO (*(volatile unsigned char *)0x520001d0) //Endpoint 4 FIFO
338#define rEP1_DMA_CON (*(volatile unsigned char *)0x52000200) //EP1 DMA interface control
339#define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000204) //EP1 DMA Tx unit counter
340#define rEP1_DMA_FIFO (*(volatile unsigned char *)0x52000208) //EP1 DMA Tx FIFO counter
341#define rEP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020c) //EP1 DMA total Tx counter
342#define rEP1_DMA_TTC_M (*(volatile unsigned char *)0x52000210)
343#define rEP1_DMA_TTC_H (*(volatile unsigned char *)0x52000214)
344#define rEP2_DMA_CON (*(volatile unsigned char *)0x52000218) //EP2 DMA interface control
345#define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021c) //EP2 DMA Tx unit counter
346#define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000220) //EP2 DMA Tx FIFO counter
347#define rEP2_DMA_TTC_L (*(volatile unsigned char *)0x52000224) //EP2 DMA total Tx counter
348#define rEP2_DMA_TTC_M (*(volatile unsigned char *)0x52000228)
349#define rEP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022c)
350#define rEP3_DMA_CON (*(volatile unsigned char *)0x52000240) //EP3 DMA interface control
351#define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000244) //EP3 DMA Tx unit counter
352#define rEP3_DMA_FIFO (*(volatile unsigned char *)0x52000248) //EP3 DMA Tx FIFO counter
353#define rEP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024c) //EP3 DMA total Tx counter
354#define rEP3_DMA_TTC_M (*(volatile unsigned char *)0x52000250)
355#define rEP3_DMA_TTC_H (*(volatile unsigned char *)0x52000254)
356#define rEP4_DMA_CON (*(volatile unsigned char *)0x52000258) //EP4 DMA interface control
357#define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025c) //EP4 DMA Tx unit counter
358#define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000260) //EP4 DMA Tx FIFO counter
359#define rEP4_DMA_TTC_L (*(volatile unsigned char *)0x52000264) //EP4 DMA total Tx counter
360#define rEP4_DMA_TTC_M (*(volatile unsigned char *)0x52000268)
361#define rEP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026c)
362#endif // __BIG_ENDIAN
363
364/* WATCH DOG TIMER */
365#define rWTCON (*(volatile unsigned *)0x53000000)
366#define rWTDAT (*(volatile unsigned *)0x53000004)
367#define rWTCNT (*(volatile unsigned *)0x53000008)
368
369
370/* IIC */
371#define rIICCON (*(volatile unsigned *)0x54000000)
372#define rIICSTAT (*(volatile unsigned *)0x54000004)
373#define rIICADD (*(volatile unsigned *)0x54000008)
374#define rIICDS (*(volatile unsigned *)0x5400000C)
375
376
377/* IIS */
378#define rIISCON (*(volatile unsigned *)0x55000000)
379#define rIISMOD (*(volatile unsigned *)0x55000004)
380#define rIISPSR (*(volatile unsigned *)0x55000008)
381#define rIISFIFCON (*(volatile unsigned *)0x5500000C)
382
383#ifdef __BIG_ENDIAN
384#define IISFIFO ((volatile unsigned short *)0x55000012)
385
386#else /* Little Endian */
387#define IISFIFO ((volatile unsigned short *)0x55000010)
388#endif
389
390
391/* I/O PORT */
392#define rGPACON (*(volatile unsigned *)0x56000000) //Port A control
393#define rGPADAT (*(volatile unsigned *)0x56000004) //Port A data
394
395#define rGPBCON (*(volatile unsigned *)0x56000010) //Port B control
396#define rGPBDAT (*(volatile unsigned *)0x56000014) //Port B data
397#define rGPBUP (*(volatile unsigned *)0x56000018) //Pull-up control B
398
399#define rGPCCON (*(volatile unsigned *)0x56000020) //Port C control
400#define rGPCDAT (*(volatile unsigned *)0x56000024) //Port C data
401#define rGPCUP (*(volatile unsigned *)0x56000028) //Pull-up control C
402
403#define rGPDCON (*(volatile unsigned *)0x56000030) //Port D control
404#define rGPDDAT (*(volatile unsigned *)0x56000034) //Port D data
405#define rGPDUP (*(volatile unsigned *)0x56000038) //Pull-up control D
406
407#define rGPECON (*(volatile unsigned *)0x56000040) //Port E control
408#define rGPEDAT (*(volatile unsigned *)0x56000044) //Port E data
409#define rGPEUP (*(volatile unsigned *)0x56000048) //Pull-up control E
410
411#define rGPFCON (*(volatile unsigned *)0x56000050) //Port F control
412#define rGPFDAT (*(volatile unsigned *)0x56000054) //Port F data
413#define rGPFUP (*(volatile unsigned *)0x56000058) //Pull-up control F
414
415#define rGPGCON (*(volatile unsigned *)0x56000060) //Port G control
416#define rGPGDAT (*(volatile unsigned *)0x56000064) //Port G data
417#define rGPGUP (*(volatile unsigned *)0x56000068) //Pull-up control G
418
419#define rGPHCON (*(volatile unsigned *)0x56000070) //Port H control
420#define rGPHDAT (*(volatile unsigned *)0x56000074) //Port H data
421#define rGPHUP (*(volatile unsigned *)0x56000078) //Pull-up control H
422
423#define rMISCCR (*(volatile unsigned *)0x56000080) //Miscellaneous control
424#define rDCLKCON (*(volatile unsigned *)0x56000084) //DCLK0/1 control
425#define rEXTINT0 (*(volatile unsigned *)0x56000088) //External interrupt control register 0
426#define rEXTINT1 (*(volatile unsigned *)0x5600008c) //External interrupt control register 1
427#define rEXTINT2 (*(volatile unsigned *)0x56000090) //External interrupt control register 2
428#define rEINTFLT0 (*(volatile unsigned *)0x56000094) //Reserved
429#define rEINTFLT1 (*(volatile unsigned *)0x56000098) //Reserved
430#define rEINTFLT2 (*(volatile unsigned *)0x5600009c) //External interrupt filter control register 2
431#define rEINTFLT3 (*(volatile unsigned *)0x560000a0) //External interrupt filter control register 3
432#define rEINTMASK (*(volatile unsigned *)0x560000a4) //External interrupt mask
433#define rEINTPEND (*(volatile unsigned *)0x560000a8) //External interrupt pending
434#define rGSTATUS0 (*(volatile unsigned *)0x560000ac) //External pin status
435#define rGSTATUS1 (*(volatile unsigned *)0x560000b0) //Chip ID(0x32440000)
436
437/* RTC */
438#ifdef __BIG_ENDIAN
439#define rRTCCON (*(volatile unsigned char *)0x57000043) //RTC control
440#define rTICNT (*(volatile unsigned char *)0x57000047) //Tick time count
441#define rRTCALM (*(volatile unsigned char *)0x57000053) //RTC alarm control
442#define rALMSEC (*(volatile unsigned char *)0x57000057) //Alarm second
443#define rALMMIN (*(volatile unsigned char *)0x5700005b) //Alarm minute
444#define rALMHOUR (*(volatile unsigned char *)0x5700005f) //Alarm Hour
445#define rALMDATE (*(volatile unsigned char *)0x57000063) //Alarm date //edited by junon
446#define rALMMON (*(volatile unsigned char *)0x57000067) //Alarm month
447#define rALMYEAR (*(volatile unsigned char *)0x5700006b) //Alarm year
448#define rRTCRST (*(volatile unsigned char *)0x5700006f) //RTC round reset
449#define rBCDSEC (*(volatile unsigned char *)0x57000073) //BCD second
450#define rBCDMIN (*(volatile unsigned char *)0x57000077) //BCD minute
451#define rBCDHOUR (*(volatile unsigned char *)0x5700007b) //BCD hour
452#define rBCDDATE (*(volatile unsigned char *)0x5700007f) //BCD date //edited by junon
453#define rBCDDAY (*(volatile unsigned char *)0x57000083) //BCD day //edited by junon
454#define rBCDMON (*(volatile unsigned char *)0x57000087) //BCD month
455#define rBCDYEAR (*(volatile unsigned char *)0x5700008b) //BCD year
456
457#else //Little Endian
458#define rRTCCON (*(volatile unsigned char *)0x57000040) //RTC control
459#define rTICNT (*(volatile unsigned char *)0x57000044) //Tick time count
460#define rRTCALM (*(volatile unsigned char *)0x57000050) //RTC alarm control
461#define rALMSEC (*(volatile unsigned char *)0x57000054) //Alarm second
462#define rALMMIN (*(volatile unsigned char *)0x57000058) //Alarm minute
463#define rALMHOUR (*(volatile unsigned char *)0x5700005c) //Alarm Hour
464#define rALMDATE (*(volatile unsigned char *)0x57000060) //Alarm date // edited by junon
465#define rALMMON (*(volatile unsigned char *)0x57000064) //Alarm month
466#define rALMYEAR (*(volatile unsigned char *)0x57000068) //Alarm year
467#define rRTCRST (*(volatile unsigned char *)0x5700006c) //RTC round reset
468#define rBCDSEC (*(volatile unsigned char *)0x57000070) //BCD second
469#define rBCDMIN (*(volatile unsigned char *)0x57000074) //BCD minute
470#define rBCDHOUR (*(volatile unsigned char *)0x57000078) //BCD hour
471#define rBCDDATE (*(volatile unsigned char *)0x5700007c) //BCD date //edited by junon
472#define rBCDDAY (*(volatile unsigned char *)0x57000080) //BCD day //edited by junon
473#define rBCDMON (*(volatile unsigned char *)0x57000084) //BCD month
474#define rBCDYEAR (*(volatile unsigned char *)0x57000088) //BCD year
475#endif //RTC
476
477
478/* ADC */
479#define rADCCON (*(volatile unsigned *)0x58000000)
480#define rADCTSC (*(volatile unsigned *)0x58000004)
481#define rADCDLY (*(volatile unsigned *)0x58000008)
482#define rADCDAT0 (*(volatile unsigned *)0x5800000c)
483#define rADCDAT1 (*(volatile unsigned *)0x58000010)
484
485
486/* SPI */
487#define rSPCON0 (*(volatile unsigned *)0x59000000) //SPI0 control
488#define rSPSTA0 (*(volatile unsigned *)0x59000004) //SPI0 status
489#define rSPPIN0 (*(volatile unsigned *)0x59000008) //SPI0 pin control
490#define rSPPRE0 (*(volatile unsigned *)0x5900000c) //SPI0 baud rate prescaler
491#define rSPTDAT0 (*(volatile unsigned *)0x59000010) //SPI0 Tx data
492#define rSPRDAT0 (*(volatile unsigned *)0x59000014) //SPI0 Rx data
493
494#define rSPCON1 (*(volatile unsigned *)0x59000020) //SPI1 control
495#define rSPSTA1 (*(volatile unsigned *)0x59000024) //SPI1 status
496#define rSPPIN1 (*(volatile unsigned *)0x59000028) //SPI1 pin control
497#define rSPPRE1 (*(volatile unsigned *)0x5900002c) //SPI1 baud rate prescaler
498#define rSPTDAT1 (*(volatile unsigned *)0x59000030) //SPI1 Tx data
499#define rSPRDAT1 (*(volatile unsigned *)0x59000034) //SPI1 Rx data
500
501/* SD interface */
502#define rSDICON (*(volatile unsigned *)0x5a000000) //SDI control
503#define rSDIPRE (*(volatile unsigned *)0x5a000004) //SDI baud rate prescaler
504#define rSDICARG (*(volatile unsigned *)0x5a000008) //SDI command argument
505#define rSDICCON (*(volatile unsigned *)0x5a00000c) //SDI command control
506#define rSDICSTA (*(volatile unsigned *)0x5a000010) //SDI command status
507#define rSDIRSP0 (*(volatile unsigned *)0x5a000014) //SDI response 0
508#define rSDIRSP1 (*(volatile unsigned *)0x5a000018) //SDI response 1
509#define rSDIRSP2 (*(volatile unsigned *)0x5a00001c) //SDI response 2
510#define rSDIRSP3 (*(volatile unsigned *)0x5a000020) //SDI response 3
511#define rSDIDTIMER (*(volatile unsigned *)0x5a000024) //SDI data/busy timer
512#define rSDIBSIZE (*(volatile unsigned *)0x5a000028) //SDI block size
513#define rSDIDATCON (*(volatile unsigned *)0x5a00002c) //SDI data control
514#define rSDIDATCNT (*(volatile unsigned *)0x5a000030) //SDI data remain counter
515#define rSDIDATSTA (*(volatile unsigned *)0x5a000034) //SDI data status
516#define rSDIFSTA (*(volatile unsigned *)0x5a000038) //SDI FIFO status
517#define rSDIIMSK (*(volatile unsigned *)0x5a000040) //SDI interrupt mask. edited for 2440A
518
519#ifdef __BIG_ENDIAN
520#define rSDIDAT (*(volatile unsigned *)0x5a00003F) //SDI data
521#define SDIDAT 0x5a00003F
522#else // Little Endian
523#define rSDIDAT (*(volatile unsigned *)0x5a00003C) //SDI data
524#define SDIDAT 0x5a00003C
525#endif //SD Interface
526
527
528#define _ISR_STARTADDRESS rtems_vector_table
529/* ISR */
530#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0))
531#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4))
532#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8))
533#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xC))
534#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10))
535#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14))
536#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18))
537#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1C))
538
539#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20))
540#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24))
541#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28))
542#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2C))
543#define pISR_EINT4_7 (*(unsigned *)(_ISR_STARTADDRESS+0x30))
544#define pISR_EINT8_23 (*(unsigned *)(_ISR_STARTADDRESS+0x34))
545#define pISR_BAT_FLT (*(unsigned *)(_ISR_STARTADDRESS+0x3C))
546#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40))
547#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44))
548#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48))
549#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4C))
550#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50))
551#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54))
552#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58))
553#define pISR_UART2 (*(unsigned *)(_ISR_STARTADDRESS+0x5C))
554#define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60))
555#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64))
556#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68))
557#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6C))
558#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70))
559#define pISR_SDI (*(unsigned *)(_ISR_STARTADDRESS+0x74))
560#define pISR_SPI0 (*(unsigned *)(_ISR_STARTADDRESS+0x78))
561#define pISR_UART1 (*(unsigned *)(_ISR_STARTADDRESS+0x7C))
562#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84))
563#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88))
564#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8C))
565#define pISR_UART0 (*(unsigned *)(_ISR_STARTADDRESS+0x90))
566#define pISR_SPI1 (*(unsigned *)(_ISR_STARTADDRESS+0x94))
567#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98))
568#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xA0))
569
570
571/* PENDING BIT */
572#define BIT_EINT0 (0x1)
573#define BIT_EINT1 (0x1<<1)
574#define BIT_EINT2 (0x1<<2)
575#define BIT_EINT3 (0x1<<3)
576#define BIT_EINT4_7 (0x1<<4)
577#define BIT_EINT8_23 (0x1<<5)
578#define BIT_BAT_FLT (0x1<<7)
579#define BIT_TICK (0x1<<8)
580#define BIT_WDT (0x1<<9)
581#define BIT_TIMER0 (0x1<<10)
582#define BIT_TIMER1 (0x1<<11)
583#define BIT_TIMER2 (0x1<<12)
584#define BIT_TIMER3 (0x1<<13)
585#define BIT_TIMER4 (0x1<<14)
586#define BIT_UART2 (0x1<<15)
587#define BIT_LCD (0x1<<16)
588#define BIT_DMA0 (0x1<<17)
589#define BIT_DMA1 (0x1<<18)
590#define BIT_DMA2 (0x1<<19)
591#define BIT_DMA3 (0x1<<20)
592#define BIT_SDI (0x1<<21)
593#define BIT_SPI0 (0x1<<22)
594#define BIT_UART1 (0x1<<23)
595#define BIT_USBD (0x1<<25)
596#define BIT_USBH (0x1<<26)
597#define BIT_IIC (0x1<<27)
598#define BIT_UART0 (0x1<<28)
599#define BIT_SPI1 (0x1<<29)
600#define BIT_RTC (0x1<<30)
601#define BIT_ADC (0x1<<31)
602#define BIT_ALLMSK (0xFFFFFFFF)
603
604#define ClearPending(bit) {\
605 rSRCPND = bit;\
606 rINTPND = bit;\
607 rINTPND;\
608 }
609/* Wait until rINTPND is changed for the case that the ISR is very short. */
610#ifndef ASM
611/* Typedefs */
612typedef union {
613 struct _reg {
614 unsigned SM_BIT:1; /* Enters STOP mode. This bit isn't be */
615 /* cleared automatically. */
616 unsigned Reserved:1; /* SL_IDLE mode option. This bit isn't cleared */
617 /* automatically. To enter SL_IDLE mode, */
618 /* CLKCON register has to be 0xe. */
619 unsigned IDLE_BIT:1; /* Enters IDLE mode. This bit isn't be cleared */
620 /* automatically. */
621 unsigned POWER_OFF:1;
622 unsigned NAND_flash:1;
623 unsigned LCDC:1; /* Controls HCLK into LCDC block */
624 unsigned USB_host:1; /* Controls HCLK into USB host block */
625 unsigned USB_device:1; /* Controls PCLK into USB device block */
626 unsigned PWMTIMER:1; /* Controls PCLK into PWMTIMER block */
627 unsigned SDI:1; /* Controls PCLK into MMC interface block */
628 unsigned UART0:1; /* Controls PCLK into UART0 block */
629 unsigned UART1:1; /* Controls PCLK into UART1 block */
630 unsigned UART2:1; /* Controls PCLK into UART1 block */
631 unsigned GPIO:1; /* Controls PCLK into GPIO block */
632 unsigned RTC:1; /* Controls PCLK into RTC control block. Even if */
633 /* this bit is cleared to 0, RTC timer is alive. */
634 unsigned ADC:1; /* Controls PCLK into ADC block */
635 unsigned IIC:1; /* Controls PCLK into IIC block */
636 unsigned IIS:1; /* Controls PCLK into IIS block */
637 unsigned SPI:1; /* Controls PCLK into SPI block */
638 } reg;
639 unsigned long all;
640} CLKCON;
641
642typedef union
643{
644 struct {
645 unsigned ENVID:1; /* LCD video output and the logic 1=enable/0=disable. */
646 unsigned BPPMODE:4; /* 1011 = 8 bpp for TFT, 1100 = 16 bpp for TFT, */
647 /* 1110 = 16 bpp TFT skipmode */
648 unsigned PNRMODE:2; /* TFT: 3 */
649 unsigned MMODE:1; /* This bit determines the toggle rate of the VM. */
650 /* 0 = Each Frame, 1 = The rate defined by the MVAL */
651 unsigned CLKVAL:10; /* TFT: VCLK = HCLK / [(CLKVAL+1) x 2] (CLKVAL >= 1) */
652 unsigned LINECNT:10; /* (read only) These bits provide the status of the */
653 /* line counter. Down count from LINEVAL to 0 */
654 } reg;
655 unsigned long all;
656} LCDCON1;
657
658typedef union {
659 struct {
660 unsigned VSPW:6; /* TFT: Vertical sync pulse width determines the */
661 /* VSYNC pulse's high level width by counting the */
662 /* number of inactive lines. */
663 unsigned VFPD:8; /* TFT: Vertical front porch is the number of */
664 /* inactive lines at the end of a frame, before */
665 /* vertical synchronization period. */
666 unsigned LINEVAL:10; /* TFT/STN: These bits determine the vertical size */
667 /* of LCD panel. */
668 unsigned VBPD:8; /* TFT: Vertical back porch is the number of inactive */
669 /* lines at the start of a frame, after */
670 /* vertical synchronization period. */
671 } reg;
672 unsigned long all;
673} LCDCON2;
674
675typedef union {
676 struct {
677 unsigned HFPD:8; /* TFT: Horizontal front porch is the number of */
678 /* VCLK periods between the end of active data */
679 /* and the rising edge of HSYNC. */
680 unsigned HOZVAL:11; /* TFT/STN: These bits determine the horizontal */
681 /* size of LCD panel. 2n bytes. */
682 unsigned HBPD:7; /* TFT: Horizontal back porch is the number of VCLK */
683 /* periods between the falling edge of HSYNC and */
684 /* the start of active data. */
685 } reg;
686 unsigned long all;
687} LCDCON3;
688
689typedef union {
690 struct {
691 unsigned HSPW:8; /* TFT: Horizontal sync pulse width determines the */
692 /* HSYNC pulse's high level width by counting the */
693 /* number of the VCLK. */
694 unsigned MVAL:8; /* STN: */
695 } reg;
696 unsigned long all;
697} LCDCON4;
698
699typedef union {
700 struct {
701 unsigned HWSWP:1; /* STN/TFT: Half-Word swap control bit. */
702 /* 0 = Swap Disable 1 = Swap Enable */
703 unsigned BSWP:1; /* STN/TFT: Byte swap control bit. */
704 /* 0 = Swap Disable 1 = Swap Enable */
705 unsigned ENLEND:1; /* TFT: LEND output signal enable/disable. */
706 /* 0 = Disable LEND signal. */
707 /* 1 = Enable LEND signal */
708 unsigned PWREN:1;
709 unsigned INVLEND:1;/* TFT: This bit indicates the LEND signal */
710 /* polarity. 0 = normal 1 = inverted */
711 unsigned INVPWREN:1;
712 unsigned INVVDEN:1; /* TFT: This bit indicates the VDEN signal */
713 /* polarity. */
714 /* 0 = normal 1 = inverted */
715 unsigned INVVD:1; /* STN/TFT: This bit indicates the VD (video data) */
716 /* pulse polarity. 0 = Normal. */
717 /* 1 = VD is inverted. */
718 unsigned INVVFRAME:1; /* STN/TFT: This bit indicates the VFRAME/VSYNC */
719 /* pulse polarity. 0 = normal 1 = inverted */
720 unsigned INVVLINE:1; /* STN/TFT: This bit indicates the VLINE/HSYNC */
721 /* pulse polarity. 0 = normal 1 = inverted */
722 unsigned INVVCLK:1; /* STN/TFT: This bit controls the polarity of the */
723 /* VCLK active edge. 0 = The video data is */
724 /* fetched at VCLK falling edge. 1 = The video */
725 /* data is fetched at VCLK rising edge */
726 unsigned FRM565:1;
727 unsigned BPP24BL:1;
728 unsigned HSTATUS:2; /* TFT: Horizontal Status (Read only) */
729 /* 00 = HSYNC */
730 /* 01 = BACK Porch. */
731 /* 10 = ACTIVE */
732 /* 11 = FRONT Porch */
733 unsigned _VSTATUS:2; /* TFT: Vertical Status (Read only). */
734 /* 00 = VSYNC */
735 /* 01 = BACK Porch. */
736 /* 10 = ACTIVE */
737 /* 11 = FRONT Porch */
738 unsigned RESERVED:16;
739 } reg;
740 unsigned long all;
741} LCDCON5;
742
743typedef union {
744 struct {
745 unsigned LCDBASEU:21; /* For single-scan LCD: These bits indicate */
746 /* A[21:1] of the start address of the LCD */
747 /* frame buffer. */
748 unsigned LCDBANK:9; /* A[28:22] */
749 } reg;
750 unsigned long all;
751} LCDSADDR1;
752
753typedef union {
754 struct {
755 unsigned LCDBASEL:21; /* For single scan LCD: These bits indicate A[21:1]*/
756 /* of the end address of the LCD frame buffer. */
757 /* LCDBASEL = ((the fame end address) >>1) + 1 */
758 /* = LCDBASEU + (PAGEWIDTH+OFFSIZE)x(LINEVAL+1) */
759 } reg;
760 unsigned long all;
761} LCDSADDR2;
762
763typedef union {
764 struct {
765 unsigned PAGEWIDTH:11; /* Virtual screen page width(the number of half */
766 /* words) This value defines the width of the */
767 /* view port in the frame */
768 unsigned OFFSIZE:11; /* Virtual screen offset size(the number of half */
769 /* words) This value defines the difference */
770 /* between the address of the last half word */
771 /* displayed on the previous LCD line and the */
772 /* address of the first half word to be */
773 /* displayed in the new LCD line. */
774 } reg;
775 unsigned long all;
776} LCDSADDR3;
777
778/*
779 *
780 */
781
782typedef union {
783 struct {
784 unsigned IISIFENA:1; /* IIS interface enable (start) */
785 unsigned IISPSENA:1; /* IIS prescaler enable */
786 unsigned RXCHIDLE:1; /* Receive channel idle command */
787 unsigned TXCHIDLE:1; /* Transmit channel idle command */
788 unsigned RXDMAENA:1; /* Receive DMA service request enable */
789 unsigned TXDMAENA:1; /* Transmit DMA service request enable */
790 unsigned RXFIFORDY:1; /* Receive FIFO ready flag (read only) */
791 unsigned TXFIFORDY:1; /* Transmit FIFO ready flag (read only) */
792 unsigned LRINDEX:1; /* Left/right channel index (read only) */
793 } reg;
794 unsigned long all;
795} IISCON;
796
797typedef union {
798 struct {
799 unsigned SBCLKFS:2; /* Serial bit clock frequency select */
800 unsigned MCLKFS:1; /* Master clock frequency select */
801 unsigned SDBITS:1; /* Serial data bit per channel */
802 unsigned SIFMT:1; /* Serial interface format */
803 unsigned ACTLEVCH:1; /* Active level pf left/right channel */
804 unsigned TXRXMODE:2; /* Transmit/receive mode select */
805 unsigned MODE:1; /* Master/slave mode select */
806 } reg;
807 unsigned long all;
808} IISMOD;
809
810typedef union {
811 struct {
812 unsigned PSB:5; /* Prescaler control B */
813 unsigned PSA:5; /* Prescaler control A */
814 } reg;
815 unsigned long all;
816} IISPSR;
817
818typedef union {
819 struct {
820 unsigned RXFIFOCNT:6; /* (read only) */
821 unsigned TXFIFOCNT:6; /* (read only) */
822 unsigned RXFIFOENA:1; /* */
823 unsigned TXFIFOENA:1; /* */
824 unsigned RXFIFOMODE:1; /* */
825 unsigned TXFIFOMODE:1; /* */
826 } reg;
827 unsigned long all;
828} IISSFIFCON;
829
830typedef union {
831 struct {
832 unsigned FENTRY:16; /* */
833 } reg;
834 unsigned long all;
835} IISSFIF;
836#endif //ASM
837
838#define LCD_WIDTH 240
839#define LCD_HEIGHT 320
840#define LCD_ASPECT ((float)(LCD_WIDTH/LCD_HEIGHT))
841
842#define SMDK2410_KEY_SELECT 512
843#define SMDK2410_KEY_START 256
844#define SMDK2410_KEY_A 64
845#define SMDK2410_KEY_B 32
846#define SMDK2410_KEY_L 16
847#define SMDK2410_KEY_R 128
848#define SMDK2410_KEY_UP 8
849#define SMDK2410_KEY_DOWN 2
850#define SMDK2410_KEY_LEFT 1
851#define SMDK2410_KEY_RIGHT 4
852
853#endif /*S3C2410_H_*/
CLKCON
Definition: s3c2400.h:445
IISCON
Definition: s3c2400.h:616
IISMOD
Definition: s3c2400.h:631
IISPSR
Definition: s3c2400.h:644
IISSFIFCON
Definition: s3c2400.h:652
IISSFIF
Definition: s3c2400.h:664
LCDCON1
Definition: s3c2400.h:473
LCDCON2
Definition: s3c2400.h:488
LCDCON3
Definition: s3c2400.h:505
LCDCON4
Definition: s3c2400.h:519
LCDCON5
Definition: s3c2400.h:532
LCDSADDR1
Definition: s3c2400.h:577
LCDSADDR2
Definition: s3c2400.h:587
LCDSADDR3
Definition: s3c2400.h:597
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