RTEMS 7.0-rc1
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mpc8260.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Submitted by:
13 * Andy Dachs
14 * Surrey Satellite Technology Limited
15 * http://www.sstl.co.uk
16 * a.dachs@sstl.co.uk
17 *
18 * Based on previous submissions for other PPC variants by:
19 * Eric Norum <eric.norum.ca>
20 *
21 * Modified for use with the MPC860 (original code was for MC68360) **
22 * by
23 * Jay Monkman
24 * Frasca International, Inc.
25 * 906 E. Airport Rd.
26 * Urbana, IL, 61801
27 *
28 * Redistribution and use in source and binary forms, with or without
29 * modification, are permitted provided that the following conditions
30 * are met:
31 * 1. Redistributions of source code must retain the above copyright
32 * notice, this list of conditions and the following disclaimer.
33 * 2. Redistributions in binary form must reproduce the above copyright
34 * notice, this list of conditions and the following disclaimer in the
35 * documentation and/or other materials provided with the distribution.
36 *
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
38 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
39 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
40 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
41 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
42 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
43 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
44 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
45 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
46 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
47 * POSSIBILITY OF SUCH DAMAGE.
48 */
49
50/* buggy version of CPU */
51#define REV_0_2
52
53#ifndef _MPC8260_H
54#define _MPC8260_H
55
56#ifndef ASM
57/*
58 Macros for SPRs
59*/
60
61
62
63
64/*
65*************************************************************************
66* REGISTER SUBBLOCKS *
67*************************************************************************
68*/
69
70
71/*
72 * Memory controller registers
73 */
74typedef struct m8260MEMCRegisters_ {
75 uint32_t br;
76 uint32_t _or; /* or is a C++ keyword :( */
77} m8260MEMCRegisters_t;
78
79
80/*
81 * Fast Communication Controller Registers
82*/
83typedef struct m8260FCCRegisters_ {
84 uint32_t gfmr;
85 uint32_t fpsmr;
86 uint16_t ftodr;
87 uint8_t fcc_pad0[2];
88 uint16_t fdsr;
89 uint8_t fcc_pad1[2];
90 uint32_t fcce;
91 uint32_t fccm;
92 uint8_t fccs;
93 uint8_t fcc_pad2[3];
94 uint8_t ftirr_phy0; /* n/a on FCC3 */
95 uint8_t ftirr_phy1; /* n/a on FCC3 */
96 uint8_t ftirr_phy2; /* n/a on FCC3 */
97 uint8_t ftirr_phy3; /* n/a on FCC3 */
98} m8260FCCRegisters_t;
99
100
101/*
102 * Serial Communications Controller registers
103 */
104typedef struct m8260SCCRegisters_ {
105 uint32_t gsmr_l;
106 uint32_t gsmr_h;
107 uint16_t psmr;
108 uint8_t scc_pad0[2];
109 uint16_t todr;
110 uint16_t dsr;
111 uint16_t scce;
112 uint8_t scc_pad2[2];
113 uint16_t sccm;
114 uint8_t scc_pad3[1];
115 uint8_t sccs;
116 uint8_t scc_pad1[8];
117} m8260SCCRegisters_t;
118
119/*
120 * Serial Management Controller registers
121 */
122typedef struct m8260SMCRegisters_ {
123 uint8_t smc_pad0[2];
124 uint16_t smcmr;
125 uint8_t smc_pad2[2];
126 uint8_t smce;
127 uint8_t smc_pad3[3];
128 uint8_t smcm;
129 uint8_t smc_pad1[5];
130} m8260SMCRegisters_t;
131
132
133/*
134 * Serial Interface With Time Slot Assigner Registers
135 */
136typedef struct m8260SIRegisters_ {
137 uint16_t siamr;
138 uint16_t sibmr;
139 uint16_t sicmr;
140 uint16_t sidmr;
141 uint8_t sigmr;
142 uint8_t si_pad0[1];
143 uint8_t sicmdr;
144 uint8_t si_pad1[1];
145 uint8_t sistr;
146 uint8_t si_pad2[1];
147 uint16_t sirsr;
148} m8260SIRegisters_t;
149
150
151/*
152 * Multi Channel Controller registers
153 */
154typedef struct m8260MCCRegisters_ {
155 uint16_t mcce;
156 uint8_t mcc_pad2[2];
157 uint16_t mccm;
158 uint16_t mcc_pad0;
159 uint8_t mccf;
160 uint8_t mcc_pad1[7];
161} m8260MCCRegisters_t;
162
163
164/*
165*************************************************************************
166* RISC Timers *
167*************************************************************************
168*/
169/*
170typedef struct m8260TimerParms_ {
171 uint16_t tm_base;
172 uint16_t _tm_ptr;
173 uint16_t _r_tmr;
174 uint16_t _r_tmv;
175 uint32_t tm_cmd;
176 uint32_t tm_cnt;
177} m8260TimerParms_t;
178*/
179
180/*
181 * RISC Controller Configuration Register (RCCR)
182 * All other bits in this register are reserved.
183 */
184#define M8260_RCCR_TIME (1<<31) /* Enable timer */
185#define M8260_RCCR_TIMEP(x) ((x)<<24) /* Timer period */
186#define M8260_RCCR_DR1M (1<<23) /* IDMA Rqst 1 Mode */
187#define M8260_RCCR_DR2M (1<<22) /* IDMA Rqst 2 Mode */
188#define M8260_RCCR_DR1QP(x) ((x)<<20) /* IDMA1 Rqst Priority */
189#define M8260_RCCR_EIE (1<<19) /* External Interrupt Enable */
190#define M8260_RCCR_SCD (1<<18) /* Scheduler Configuration */
191#define M8260_RCCR_DR2QP(x) ((x)<<16) /* IDMA2 Rqst Priority */
192#define M8260_RCCR_ERAM(x) ((x)<<13) /* Enable RAM Microcode */
193#define M8260_RCCR_EDM1 (1<<11) /* DRQ1 Edge detect mode */
194#define M8260_RCCR_EDM2 (1<<10) /* DRQ2 Edge detect mode */
195#define M8260_RCCR_EDM3 (1<<9) /* DRQ3 Edge detect mode */
196#define M8260_RCCR_EDM4 (1<<8) /* DRQ4 Edge detect mode */
197#define M8260_RCCR_DR3M (1<<7) /* IDMA Rqst 1 Mode */
198#define M8260_RCCR_DR4M (1<<6) /* IDMA Rqst 2 Mode */
199#define M8260_RCCR_DR3QP(x) ((x)<<4) /* IDMA3 Rqst Priority */
200#define M8260_RCCR_DEM12 (1<<3) /* DONE1,2 Edge detect mode */
201#define M8260_RCCR_DEM34 (1<<2) /* DONE3,4 Edge detect mode */
202#define M8260_RCCR_DR4QP(x) (x) /* IDMA4 Rqst Priority */
203
204
205
206/*
207 * Command register
208 * Set up this register before issuing a M8260_CR_OP_SET_TIMER command.
209 */
210#if 0
211#define M8260_TM_CMD_V (1<<31) /* Set to enable timer */
212#define M8260_TM_CMD_R (1<<30) /* Set for automatic restart */
213#define M8260_TM_CMD_PWM (1<<29) /* Set for PWM operation */
214#define M8260_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */
215#define M8260_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */
216#endif
217
218/*
219*************************************************************************
220* DMA Controllers *
221*************************************************************************
222*/
223typedef struct m8260IDMAparms_ {
224 uint16_t ibase;
225 uint16_t dcm;
226 uint16_t ibdptr;
227 uint16_t dpr_buf;
228 uint16_t _buf_inv;
229 uint16_t ssmax;
230 uint16_t _dpr_in_ptr;
231 uint16_t sts;
232 uint16_t _dpr_out_ptr;
233 uint16_t seob;
234 uint16_t deob;
235 uint16_t dts;
236 uint16_t _ret_add;
237 uint16_t reserved;
238 uint32_t _bd_cnt;
239 uint32_t _s_ptr;
240 uint32_t _d_ptr;
241 uint32_t istate;
242} m8260IDMAparms_t;
243
244
245/*
246*************************************************************************
247* Serial Communication Controllers *
248*************************************************************************
249*/
250
251
252typedef struct m8260SCCparms_ {
253 uint16_t rbase;
254 uint16_t tbase;
255 uint8_t rfcr;
256 uint8_t tfcr;
257 uint16_t mrblr;
258 uint32_t _rstate;
259 uint32_t _pad0;
260 uint16_t _rbptr;
261 uint16_t _pad1;
262 uint32_t _pad2;
263 uint32_t _tstate;
264 uint32_t _pad3;
265 uint16_t _tbptr;
266 uint16_t _pad4;
267 uint32_t _pad5;
268 uint32_t _rcrc;
269 uint32_t _tcrc;
270 union {
271 struct {
272 uint32_t _res0;
273 uint32_t _res1;
274 uint16_t max_idl;
275 uint16_t idlc;
276 uint16_t brkcr;
277 uint16_t parec;
278 uint16_t frmec;
279 uint16_t nosec;
280 uint16_t brkec;
281 uint16_t brklen;
282 uint16_t uaddr[2];
283 uint16_t rtemp;
284 uint16_t toseq;
285 uint16_t character[8];
286 uint16_t rccm;
287 uint16_t rccr;
288 uint16_t rlbc;
289 } uart;
290 struct {
291 uint32_t _pad0;
292 uint32_t c_mask;
293 uint32_t c_pres;
294 uint16_t disfc;
295 uint16_t crcec;
296 uint16_t abtsc;
297 uint16_t nmarc;
298 uint16_t retrc;
299 uint16_t mflr;
300 uint16_t _max_cnt;
301 uint16_t rfthr;
302 uint16_t _rfcnt;
303 uint16_t hmask;
304 uint16_t haddr1;
305 uint16_t haddr2;
306 uint16_t haddr3;
307 uint16_t haddr4;
308 uint16_t _tmp;
309 uint16_t _tmp_mb;
310 } hdlc;
311 struct {
312 uint32_t _pad0;
313 uint32_t crcc;
314 uint16_t prcrc;
315 uint16_t ptcrc;
316 uint16_t parec;
317 uint16_t bsync;
318 uint16_t bdle;
319 uint16_t character[8];
320 uint16_t rccm;
321 } bisync;
322 struct {
323 uint32_t _crc_p;
324 uint32_t _crc_c;
325 } transparent;
326 struct {
327 uint32_t c_pres;
328 uint32_t c_mask;
329 uint32_t crcec;
330 uint32_t alec;
331 uint32_t disfc;
332 uint16_t pads;
333 uint16_t ret_lim;
334 uint16_t _ret_cnt;
335 uint16_t mflr;
336 uint16_t minflr;
337 uint16_t maxd1;
338 uint16_t maxd2;
339 uint16_t _maxd;
340 uint16_t _dma_cnt;
341 uint16_t _max_b;
342 uint16_t gaddr1;
343 uint16_t gaddr2;
344 uint16_t gaddr3;
345 uint16_t gaddr4;
346 uint32_t _tbuf0data0;
347 uint32_t _tbuf0data1;
348 uint32_t _tbuf0rba0;
349 uint32_t _tbuf0crc;
350 uint16_t _tbuf0bcnt;
351 uint16_t paddr_h;
352 uint16_t paddr_m;
353 uint16_t paddr_l;
354 uint16_t p_per;
355 uint16_t _rfbd_ptr;
356 uint16_t _tfbd_ptr;
357 uint16_t _tlbd_ptr;
358 uint32_t _tbuf1data0;
359 uint32_t _tbuf1data1;
360 uint32_t _tbuf1rba0;
361 uint32_t _tbuf1crc;
362 uint16_t _tbuf1bcnt;
363 uint16_t _tx_len;
364 uint16_t iaddr1;
365 uint16_t iaddr2;
366 uint16_t iaddr3;
367 uint16_t iaddr4;
368 uint16_t _boff_cnt;
369 uint16_t taddr_l;
370 uint16_t taddr_m;
371 uint16_t taddr_h;
372 } ethernet;
373 } un;
374} m8260SCCparms_t;
375
376
377/*
378 * Event and mask registers (SCCE, SCCM)
379 */
380#define M8260_SCCE_BRKE (1<<6)
381#define M8260_SCCE_BRK (1<<5)
382#define M8260_SCCE_TXE (1<<4)
383#define M8260_SCCE_RXF (1<<3)
384#define M8260_SCCE_BSY (1<<2)
385#define M8260_SCCE_TX (1<<1)
386#define M8260_SCCE_RX (1<<0)
387
388
389/*
390*************************************************************************
391* Fast Serial Communication Controllers *
392*************************************************************************
393*/
394
395
396typedef struct m8260FCCparms_ {
397 uint16_t riptr;
398 uint16_t tiptr;
399 uint16_t _pad0;
400 uint16_t mrblr;
401 uint32_t rstate;
402 uint32_t rbase;
403 uint16_t _rbdstat;
404 uint16_t _rbdlen;
405 uint32_t _rdptr;
406 uint32_t tstate;
407 uint32_t tbase;
408 uint16_t _tbdstat;
409 uint16_t _tbdlen;
410 uint32_t _tdptr;
411 uint32_t _rbptr;
412 uint32_t _tbptr;
413 uint32_t _rcrc;
414 uint32_t _pad1;
415 uint32_t _tcrc;
416
417 union {
418 struct {
419 uint32_t _pad0;
420 uint32_t _pad1;
421 uint32_t c_mask;
422 uint32_t c_pres;
423 uint16_t disfc;
424 uint16_t crcec;
425 uint16_t abtsc;
426 uint16_t nmarc;
427 uint32_t _max_cnt;
428 uint16_t mflr;
429 uint16_t rfthr;
430 uint16_t rfcnt;
431 uint16_t hmask;
432 uint16_t haddr1;
433 uint16_t haddr2;
434 uint16_t haddr3;
435 uint16_t haddr4;
436 uint16_t _ts_tmp;
437 uint16_t _tmp_mb;
438 } hdlc;
439 struct {
440 uint32_t _pad0;
441 uint32_t _pad1;
442 uint32_t c_mask;
443 uint32_t c_pres;
444 uint16_t disfc;
445 uint16_t crcec;
446 uint16_t abtsc;
447 uint16_t nmarc;
448 uint32_t _max_cnt;
449 uint16_t mflr;
450 uint16_t rfthr;
451 uint16_t rfcnt;
452 uint16_t hmask;
453 uint16_t haddr1;
454 uint16_t haddr2;
455 uint16_t haddr3;
456 uint16_t haddr4;
457 uint16_t _ts_tmp;
458 uint16_t _tmp_mb;
459 } transparent;
460 struct {
461 uint32_t _stat_buf;
462 uint32_t cam_ptr;
463 uint32_t c_mask;
464 uint32_t c_pres;
465 uint32_t crcec;
466 uint32_t alec;
467 uint32_t disfc;
468 uint16_t ret_lim;
469 uint16_t _ret_cnt;
470 uint16_t p_per;
471 uint16_t _boff_cnt;
472 uint32_t gaddr_h;
473 uint32_t gaddr_l;
474 uint16_t tfcstat;
475 uint16_t tfclen;
476 uint32_t tfcptr;
477 uint16_t mflr;
478 uint16_t paddr1_h;
479 uint16_t paddr1_m;
480 uint16_t paddr1_l;
481 uint16_t _ibd_cnt;
482 uint16_t _ibd_start;
483 uint16_t _ibd_end;
484 uint16_t _tx_len;
485 uint16_t _ibd_base;
486 uint32_t iaddr_h;
487 uint32_t iaddr_l;
488 uint16_t minflr;
489 uint16_t taddr_h;
490 uint16_t taddr_m;
491 uint16_t taddr_l;
492 uint16_t pad_ptr;
493 uint16_t _pad0;
494 uint16_t _cf_range;
495 uint16_t _max_b;
496 uint16_t maxd1;
497 uint16_t maxd2;
498 uint16_t _maxd;
499 uint16_t _dma_cnt;
500 uint32_t octc;
501 uint32_t colc;
502 uint32_t broc;
503 uint32_t mulc;
504 uint32_t uspc;
505 uint32_t frgc;
506 uint32_t ospc;
507 uint32_t jbrc;
508 uint32_t p64c;
509 uint32_t p65c;
510 uint32_t p128c;
511 uint32_t p256c;
512 uint32_t p512c;
513 uint32_t p1024c;
514 uint32_t _cam_buf;
515 uint32_t _pad1;
516 } ethernet;
517 } un;
518} m8260FCCparms_t;
519
520
521/*
522 * Receive and transmit function code register bits
523 * These apply to the function code registers of all devices, not just SCC.
524 */
525#define M8260_RFCR_BO(x) ((x)<<3)
526#define M8260_RFCR_MOT (2<<3)
527#define M8260_RFCR_LOCAL_BUS (2)
528#define M8260_RFCR_60X_BUS (0)
529#define M8260_TFCR_BO(x) ((x)<<3)
530#define M8260_TFCR_MOT (2<<3)
531#define M8260_TFCR_LOCAL_BUS (2)
532#define M8260_TFCR_60X_BUS (0)
533
534/*
535*************************************************************************
536* Serial Management Controllers *
537*************************************************************************
538*/
539typedef struct m8260SMCparms_ {
540 uint16_t rbase;
541 uint16_t tbase;
542 uint8_t rfcr;
543 uint8_t tfcr;
544 uint16_t mrblr;
545 uint32_t _rstate;
546 uint32_t _pad0;
547 uint16_t _rbptr;
548 uint16_t _pad1;
549 uint32_t _pad2;
550 uint32_t _tstate;
551 uint32_t _pad3;
552 uint16_t _tbptr;
553 uint16_t _pad4;
554 uint32_t _pad5;
555 union {
556 struct {
557 uint16_t max_idl;
558 uint16_t _idlc;
559 uint16_t _brkln;
560 uint16_t brkec;
561 uint16_t brkcr;
562 uint16_t _r_mask;
563 } uart;
564 struct {
565 uint16_t _pad0[6];
566 } transparent;
567 } un;
568 uint32_t _pad6;
569} m8260SMCparms_t;
570
571/*
572 * Mode register
573 */
574#define M8260_SMCMR_CLEN(x) ((x)<<11) /* Character length */
575#define M8260_SMCMR_2STOP (1<<10) /* 2 stop bits */
576#define M8260_SMCMR_PARITY (1<<9) /* Enable parity */
577#define M8260_SMCMR_EVEN (1<<8) /* Even parity */
578#define M8260_SMCMR_SM_GCI (0<<4) /* GCI Mode */
579#define M8260_SMCMR_SM_UART (2<<4) /* UART Mode */
580#define M8260_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */
581#define M8260_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */
582#define M8260_SMCMR_DM_ECHO (2<<2) /* Echo mode */
583#define M8260_SMCMR_TEN (1<<1) /* Enable transmitter */
584#define M8260_SMCMR_REN (1<<0) /* Enable receiver */
585
586/*
587 * Event and mask registers (SMCE, SMCM)
588 */
589#define M8260_SMCE_TXE (1<<4)
590#define M8260_SMCE_BSY (1<<2)
591#define M8260_SMCE_TX (1<<1)
592#define M8260_SMCE_RX (1<<0)
593
594/*
595*************************************************************************
596* Serial Peripheral Interface *
597*************************************************************************
598*/
599typedef struct m8260SPIparms_ {
600 uint16_t rbase;
601 uint16_t tbase;
602 uint8_t rfcr;
603 uint8_t tfcr;
604 uint16_t mrblr;
605 uint32_t _rstate;
606 uint32_t _pad0;
607 uint16_t _rbptr;
608 uint16_t _pad1;
609 uint32_t _pad2;
610 uint32_t _tstate;
611 uint32_t _pad3;
612 uint16_t _tbptr;
613 uint16_t _pad4;
614 uint32_t _pad5;
615} m8260SPIparms_t;
616
617/*
618 * Mode register (SPMODE)
619 */
620#define M8260_SPMODE_LOOP (1<<14) /* Local loopback mode */
621#define M8260_SPMODE_CI (1<<13) /* Clock invert */
622#define M8260_SPMODE_CP (1<<12) /* Clock phase */
623#define M8260_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */
624#define M8260_SPMODE_REV (1<<10) /* Reverse data */
625#define M8260_SPMODE_MASTER (1<<9) /* SPI is master */
626#define M8260_SPMODE_EN (1<<8) /* Enable SPI */
627#define M8260_SPMODE_CLEN(x) ((x)<<4) /* Character length */
628#define M8260_SPMODE_PM(x) (x) /* Prescaler modulus */
629
630/*
631 * Mode register (SPCOM)
632 */
633#define M8260_SPCOM_STR (1<<7) /* Start transmit */
634
635/*
636 * Event and mask registers (SPIE, SPIM)
637 */
638#define M8260_SPIE_MME (1<<5) /* Multi-master error */
639#define M8260_SPIE_TXE (1<<4) /* Tx error */
640#define M8260_SPIE_BSY (1<<2) /* Busy condition*/
641#define M8260_SPIE_TXB (1<<1) /* Tx buffer */
642#define M8260_SPIE_RXB (1<<0) /* Rx buffer */
643
644/*
645*************************************************************************
646* SDMA (SCC, SMC, SPI) Buffer Descriptors *
647*************************************************************************
648*/
649typedef struct m8260BufferDescriptor_ {
650 uint16_t status;
651 uint16_t length;
652 volatile void *buffer;
653} m8260BufferDescriptor_t;
654
655/*
656 * Bits in receive buffer descriptor status word
657 */
658#define M8260_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
659#define M8260_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
660#define M8260_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
661#define M8260_BD_LAST (1<<11) /* Ethernet, SPI */
662#define M8260_BD_CONTROL_CHAR (1<<11) /* SCC UART */
663#define M8260_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */
664#define M8260_BD_ADDRESS (1<<10) /* SCC UART */
665#define M8260_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */
666#define M8260_BD_MISS (1<<8) /* Ethernet */
667#define M8260_BD_IDLE (1<<8) /* SCC UART, SMC UART */
668#define M8260_BD_ADDRSS_MATCH (1<<7) /* SCC UART */
669#define M8260_BD_LONG (1<<5) /* Ethernet, SCC HDLC */
670#define M8260_BD_BREAK (1<<5) /* SCC UART, SMC UART */
671#define M8260_BD_NONALIGNED (1<<4) /* Ethernet, SCC HDLC */
672#define M8260_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */
673#define M8260_BD_SHORT (1<<3) /* Ethernet */
674#define M8260_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */
675#define M8260_BD_ABORT (1<<3) /* SCC HDLC */
676#define M8260_BD_CRC_ERROR (1<<2) /* Ethernet, SCC HDLC */
677#define M8260_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */
678#define M8260_BD_COLLISION (1<<0) /* Ethernet */
679#define M8260_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */
680#define M8260_BD_MASTER_ERROR (1<<0) /* SPI */
681
682#define M8xx_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
683#define M8xx_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
684#define M8xx_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
685#define M8xx_BD_LAST (1<<11) /* Ethernet, SPI */
686#define M8xx_BD_CONTROL_CHAR (1<<11) /* SCC UART */
687#define M8xx_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */
688#define M8xx_BD_ADDRESS (1<<10) /* SCC UART */
689#define M8xx_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */
690#define M8xx_BD_MISS (1<<8) /* Ethernet */
691#define M8xx_BD_IDLE (1<<8) /* SCC UART, SMC UART */
692#define M8xx_BD_ADDRSS_MATCH (1<<7) /* SCC UART */
693#define M8xx_BD_LONG (1<<5) /* Ethernet, SCC HDLC */
694#define M8xx_BD_BREAK (1<<5) /* SCC UART, SMC UART */
695#define M8xx_BD_NONALIGNED (1<<4) /* Ethernet, SCC HDLC */
696#define M8xx_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */
697#define M8xx_BD_SHORT (1<<3) /* Ethernet */
698#define M8xx_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */
699#define M8xx_BD_ABORT (1<<3) /* SCC HDLC */
700#define M8xx_BD_CRC_ERROR (1<<2) /* Ethernet, SCC HDLC */
701#define M8xx_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */
702#define M8xx_BD_COLLISION (1<<0) /* Ethernet */
703#define M8xx_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */
704#define M8xx_BD_MASTER_ERROR (1<<0) /* SPI */
705
706/*
707 * Bits in transmit buffer descriptor status word
708 * Many bits have the same meaning as those in receiver buffer descriptors.
709 */
710#define M8260_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
711#define M8260_BD_PAD (1<<14) /* Ethernet */
712#define M8260_BD_CTS_REPORT (1<<11) /* SCC UART */
713#define M8260_BD_TX_CRC (1<<10) /* Ethernet */
714#define M8260_BD_DEFER (1<<9) /* Ethernet */
715#define M8260_BD_HEARTBEAT (1<<8) /* Ethernet */
716#define M8260_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */
717#define M8260_BD_LATE_COLLISION (1<<7) /* Ethernet */
718#define M8260_BD_NO_STOP_BIT (1<<7) /* SCC UART */
719#define M8260_BD_RETRY_LIMIT (1<<6) /* Ethernet */
720#define M8260_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */
721#define M8260_BD_UNDERRUN (1<<1) /* Ethernet, SPI, SCC HDLC */
722#define M8260_BD_CARRIER_LOST (1<<0) /* Ethernet */
723#define M8260_BD_CTS_LOST (1<<0) /* SCC UART, SCC HDLC */
724
725#define M8xx_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
726#define M8xx_BD_PAD (1<<14) /* Ethernet */
727#define M8xx_BD_CTS_REPORT (1<<11) /* SCC UART */
728#define M8xx_BD_TX_CRC (1<<10) /* Ethernet */
729#define M8xx_BD_DEFER (1<<9) /* Ethernet */
730#define M8xx_BD_HEARTBEAT (1<<8) /* Ethernet */
731#define M8xx_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */
732#define M8xx_BD_LATE_COLLISION (1<<7) /* Ethernet */
733#define M8xx_BD_NO_STOP_BIT (1<<7) /* SCC UART */
734#define M8xx_BD_RETRY_LIMIT (1<<6) /* Ethernet */
735#define M8xx_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */
736#define M8xx_BD_UNDERRUN (1<<1) /* Ethernet, SPI, SCC HDLC */
737#define M8xx_BD_CARRIER_LOST (1<<0) /* Ethernet */
738#define M8xx_BD_CTS_LOST (1<<0) /* SCC UART, SCC HDLC */
739
740/*
741*************************************************************************
742* IDMA Buffer Descriptors *
743*************************************************************************
744*/
745typedef struct m8260IDMABufferDescriptor_ {
746 uint16_t status;
747 uint8_t dfcr;
748 uint8_t sfcr;
749 uint32_t length;
750 void *source;
751 void *destination;
752} m8260IDMABufferDescriptor_t;
753
754/*
755*************************************************************************
756* RISC Communication Processor Module Command Register (CR) *
757*************************************************************************
758*/
759#define M8260_CR_RST (1<<31) /* Reset communication processor */
760
761#define M8260_CR_FCC1 ((4<<26)|(16<<21)) /* FCC1 page and code */
762#define M8260_CR_FCC1_ATM ((4<<26)|(14<<21)) /* FCC1 ATM mode page and code */
763#define M8260_CR_FCC2 ((5<<26)|(17<<21)) /* FCC2 page and code */
764#define M8260_CR_FCC2_ATM ((5<<26)|(14<<21)) /* FCC2 ATM mode page and code */
765#define M8260_CR_FCC3 ((6<<26)|(18<<21)) /* FCC3 page and code */
766#define M8260_CR_SCC1 ((0<<26)|(4<<21)) /* SCC1 page and code */
767#define M8260_CR_SCC2 ((1<<26)|(5<<21)) /* SCC2 page and code */
768#define M8260_CR_SCC3 ((2<<26)|(6<<21)) /* SCC3 page and code */
769#define M8260_CR_SCC4 ((3<<26)|(7<<21)) /* SCC4 page and code */
770#define M8260_CR_SMC1 ((7<<26)|(8<<21)) /* SMC1 page and code */
771#define M8260_CR_SMC2 ((8<<26)|(9<<21)) /* SMC2 page and code */
772#define M8260_CR_RAND ((10<<26)|(14<<21)) /* SMC2 page and code */
773#define M8260_CR_SPI ((9<<26)|(10<<21)) /* SPI page and code */
774#define M8260_CR_I2C ((10<<26)|(11<<21)) /* I2C page and code */
775#define M8260_CR_TMR ((10<<26)|(15<<21)) /* Timer page and code */
776#define M8260_CR_MCC1 ((7<<26)|(28<<21)) /* MCC1 page and code */
777#define M8260_CR_MCC2 ((8<<26)|(29<<21)) /* MCC2 page and code */
778#define M8260_CR_IDMA1 ((7<<26)|(20<<21)) /* IDMA1 page and code */
779#define M8260_CR_IDMA2 ((8<<26)|(21<<21)) /* IDMA2 page and code */
780#define M8260_CR_IDMA3 ((9<<26)|(22<<21)) /* IDMA3 page and code */
781#define M8260_CR_IDMA4 ((10<<26)|(23<<21)) /* IDMA4 page and code */
782
783#define M8260_CR_FLG (1<<16) /* Command sempahore flag */
784
785#define M8260_CR_MCC_CHAN(x) ((x)<<6) /* MCC channel number */
786#define M8260_CR_FCC_HDLC (0<<6) /* FCC HDLC/Transparent protocol code */
787#define M8260_CR_FCC_ATM (10<<6) /* FCC ATM protocol code */
788#define M8260_CR_FCC_ETH (12<<6) /* FCC Ethernet protocol code */
789
790#define M8260_CR_OP_INIT_RX_TX (0) /* FCC, SCC, SMC UART, SMC GCI, SPI, I2C, MCC */
791#define M8260_CR_OP_INIT_RX (1) /* FCC, SCC, SMC UART, SPI, I2C, MCC */
792#define M8260_CR_OP_INIT_TX (2) /* FCC, SCC, SMC UART, SPI, I2C, MCC */
793#define M8260_CR_OP_INIT_HUNT (3) /* FCC, SCC, SMC UART */
794#define M8260_CR_OP_STOP_TX (4) /* FCC, SCC, SMC UART, MCC */
795#define M8260_CR_OP_GR_STOP_TX (5) /* FCC, SCC */
796#define M8260_CR_OP_RESTART_TX (6) /* FCC, SCC, SMC UART */
797#define M8260_CR_OP_CLOSE_RX_BD (7) /* FCC, SCC, SMC UART, SPI, I2C */
798#define M8260_CR_OP_SET_GRP_ADDR (8) /* FCC, SCC */
799#define M8260_CR_OP_SET_TIMER (8) /* Timer */
800#define M8260_CR_OP_GCI_TIMEOUT (9) /* SMC GCI */
801#define M8260_CR_OP_START_IDMA (9) /* IDMA */
802#define M8260_CR_OP_STOP_RX (9) /* MCC */
803#define M8260_CR_OP_ATM_TX (10) /* FCC */
804#define M8260_CR_OP_RESET_BCS (10) /* SCC */
805#define M8260_CR_OP_GCI_ABORT (10) /* SMC GCI */
806#define M8260_CR_OP_STOP_IDMA (11) /* IDMA */
807#define M8260_CR_OP_RANDOM (12) /* RAND */
808
809/*
810*************************************************************************
811* System Protection Control Register (SYPCR) *
812*************************************************************************
813*/
814#define M8260_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */
815#define M8260_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */
816#define M8260_SYPCR_BME (1<<7) /* Bus monitor enable */
817#define M8260_SYPCR_SWF (1<<3) /* Software watchdog freeze */
818#define M8260_SYPCR_SWE (1<<2) /* Software watchdog enable */
819#define M8260_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */
820#define M8260_SYPCR_SWP (1<<0) /* Software watchdog prescale */
821
822/*
823*************************************************************************
824* Memory Control Registers *
825*************************************************************************
826*/
827#define M8260_UPM_AMX_8col (0<<20) /* 8 column DRAM */
828#define M8260_UPM_AMX_9col (1<<20) /* 9 column DRAM */
829#define M8260_UPM_AMX_10col (2<<20) /* 10 column DRAM */
830#define M8260_UPM_AMX_11col (3<<20) /* 11 column DRAM */
831#define M8260_UPM_AMX_12col (4<<20) /* 12 column DRAM */
832#define M8260_UPM_AMX_13col (5<<20) /* 13 column DRAM */
833#define M8260_MSR_PER(x) (0x100<<(7-x)) /* Perity error bank (x) */
834#define M8260_MSR_WPER (1<<7) /* Write protection error */
835#define M8260_MPTPR_PTP(x) ((x)<<8) /* Periodic timer prescaler */
836#define M8260_BR_BA(x) ((x)&0xffff8000) /* Base address */
837#define M8260_BR_AT(x) ((x)<<12) /* Address type */
838#define M8260_BR_PS8 (1<<10) /* 8 bit port */
839#define M8260_BR_PS16 (2<<10) /* 16 bit port */
840#define M8260_BR_PS32 (0<<10) /* 32 bit port */
841#define M8260_BR_PARE (1<<9) /* Parity checking enable */
842#define M8260_BR_WP (1<<8) /* Write protect */
843#define M8260_BR_MS_GPCM (0<<6) /* GPCM */
844#define M8260_BR_MS_UPMA (2<<6) /* UPM A */
845#define M8260_BR_MS_UPMB (3<<6) /* UPM B */
846#define M8260_MEMC_BR_V (1<<0) /* Base/Option register are valid */
847
848#define M8260_MEMC_OR_32K 0xffff8000 /* Address range */
849#define M8260_MEMC_OR_64K 0xffff0000
850#define M8260_MEMC_OR_128K 0xfffe0000
851#define M8260_MEMC_OR_256K 0xfffc0000
852#define M8260_MEMC_OR_512K 0xfff80000
853#define M8260_MEMC_OR_1M 0xfff00000
854#define M8260_MEMC_OR_2M 0xffe00000
855#define M8260_MEMC_OR_4M 0xffc00000
856#define M8260_MEMC_OR_8M 0xff800000
857#define M8260_MEMC_OR_16M 0xff000000
858#define M8260_MEMC_OR_32M 0xfe000000
859#define M8260_MEMC_OR_64M 0xfc000000
860#define M8260_MEMC_OR_128 0xf8000000
861#define M8260_MEMC_OR_256M 0xf0000000
862#define M8260_MEMC_OR_512M 0xe0000000
863#define M8260_MEMC_OR_1G 0xc0000000
864#define M8260_MEMC_OR_2G 0x80000000
865#define M8260_MEMC_OR_4G 0x00000000
866#define M8260_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */
867#define M8260_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */
868#define M8260_MEMC_OR_SAM (1<<11) /* Address lines are multiplexed */
869#define M8260_MEMC_OR_ACS_NORM (0<<9) /* *CS asserted with addr lines */
870#define M8260_MEMC_OR_ACS_QRTR (2<<9) /* *CS asserted 1/4 after addr */
871#define M8260_MEMC_OR_ACS_HALF (3<<9) /* *CS asserted 1/2 after addr */
872#define M8260_MEMC_OR_BI (1<8) /* Burst inhibit */
873#define M8260_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */
874#define M8260_MEMC_OR_SETA (1<<3) /* *TA generated externally */
875#define M8260_MEMC_OR_TRLX (1<<2) /* Relaxed timing in GPCM */
876#define M8260_MEMC_OR_EHTR (1<<1) /* Extended hold time on reads */
877
878/*
879*************************************************************************
880* UPM Registers (MxMR) *
881*************************************************************************
882*/
883#define M8260_MEMC_MMR_PTP(x) ((x)<<24) /* Periodic timer period */
884#define M8260_MEMC_MMR_PTE (1<<23) /* Periodic timer enable */
885#define M8260_MEMC_MMR_DSP(x) ((x)<<17) /* Disable timer period */
886#define M8260_MEMC_MMR_G0CL(x) ((x)<<13) /* General line 0 control */
887#define M8260_MEMC_MMR_UPWAIT (1<<12) /* GPL_x4 is UPWAITx */
888#define M8260_MEMC_MMR_RLF(x) ((x)<<8) /* Read loop field */
889#define M8260_MEMC_MMR_WLF(x) ((x)<<4) /* Write loop field */
890#define M8260_MEMC_MMR_TLF(x) ((x)<<0) /* Timer loop field */
891/*
892*************************************************************************
893* Memory Command Register (MCR) *
894*************************************************************************
895*/
896#define M8260_MEMC_MCR_WRITE (0<<30) /* WRITE command */
897#define M8260_MEMC_MCR_READ (1<<30) /* READ command */
898#define M8260_MEMC_MCR_RUN (2<<30) /* RUN command */
899#define M8260_MEMC_MCR_UPMA (0<<23) /* Cmd is for UPMA */
900#define M8260_MEMC_MCR_UPMB (1<<23) /* Cmd is for UPMB */
901#define M8260_MEMC_MCR_MB(x) ((x)<<13) /* Memory bank when RUN cmd */
902#define M8260_MEMC_MCR_MCLF(x) ((x)<<8) /* Memory command loop field */
903#define M8260_MEMC_MCR_MAD(x) (x) /* Machine address */
904
905
906
907/*
908*************************************************************************
909* SI Mode Register (SIMODE) *
910*************************************************************************
911*/
912#define M8260_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */
913#define M8260_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */
914#define M8260_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */
915#define M8260_SI_SMC2_BRG2 (1<<28)
916#define M8260_SI_SMC2_BRG3 (2<<28)
917#define M8260_SI_SMC2_BRG4 (3<<28)
918#define M8260_SI_SMC2_CLK5 (0<<28)
919#define M8260_SI_SMC2_CLK6 (1<<28)
920#define M8260_SI_SMC2_CLK7 (2<<28)
921#define M8260_SI_SMC2_CLK8 (3<<28)
922#define M8260_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */
923#define M8260_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */
924#define M8260_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */
925#define M8260_SI_SMC1_BRG2 (1<<12)
926#define M8260_SI_SMC1_BRG3 (2<<12)
927#define M8260_SI_SMC1_BRG4 (3<<12)
928#define M8260_SI_SMC1_CLK1 (0<<12)
929#define M8260_SI_SMC1_CLK2 (1<<12)
930#define M8260_SI_SMC1_CLK3 (2<<12)
931#define M8260_SI_SMC1_CLK4 (3<<12)
932
933/*
934*************************************************************************
935* SDMA Configuration Register (SDCR) *
936*************************************************************************
937*/
938#define M8260_SDCR_FREEZE (2<<13) /* Freeze on next bus cycle */
939#define M8260_SDCR_RAID_5 (1<<0) /* Normal arbitration ID */
940
941/*
942*************************************************************************
943* SDMA Status Register (SDSR) *
944*************************************************************************
945*/
946#define M8260_SDSR_SBER (1<<7) /* SDMA Channel bus error */
947#define M8260_SDSR_DSP2 (1<<1) /* DSP Chain 2 interrupt */
948#define M8260_SDSR_DSP1 (1<<0) /* DSP Chain 1 interrupt */
949
950/*
951*************************************************************************
952* Baud (sic) Rate Generators *
953*************************************************************************
954*/
955#define M8260_BRG_RST (1<<17) /* Reset generator */
956#define M8260_BRG_EN (1<<16) /* Enable generator */
957#define M8260_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */
958#define M8260_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */
959#define M8260_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */
960#define M8260_BRG_ATB (1<<13) /* Autobaud */
961#define M8260_BRG_115200 (21<<1) /* Assume 40 MHz clock */
962#define M8260_BRG_57600 (32<<1)
963#define M8260_BRG_38400 (64<<1)
964#define M8260_BRG_19200 (129<<1)
965#define M8260_BRG_9600 (259<<1)
966#define M8260_BRG_4800 (520<<1)
967#define M8260_BRG_2400 (1040<<1)
968#define M8260_BRG_1200 (2082<<1)
969#define M8260_BRG_600 ((259<<1) | 1)
970#define M8260_BRG_300 ((520<<1) | 1)
971#define M8260_BRG_150 ((1040<<1) | 1)
972#define M8260_BRG_75 ((2080<<1) | 1)
973
974#define M8xx_BRG_RST (1<<17) /* Reset generator */
975#define M8xx_BRG_EN (1<<16) /* Enable generator */
976#define M8xx_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */
977
978#define M8260_BRG1 (1<<7)
979#define M8260_BRG2 (1<<6)
980#define M8260_BRG3 (1<<5)
981#define M8260_BRG4 (1<<4)
982#define M8260_BRG5 (1<<3)
983#define M8260_BRG6 (1<<2)
984#define M8260_BRG7 (1<<1)
985#define M8260_BRG8 (1<<0)
986
987
988
989#define M8260_TGCR_CAS4 (1<<15) /* Cascade timers 3 and 4 */
990#define M8260_TGCR_CAS2 (1<<7) /* Cascade timers 1 and 2 */
991#define M8260_TGCR_FRZ1 (1<<2) /* Halt timer if FREEZE asserted */
992#define M8260_TGCR_FRZ2 (1<<6) /* Halt timer if FREEZE asserted */
993#define M8260_TGCR_FRZ3 (1<<10) /* Halt timer if FREEZE asserted */
994#define M8260_TGCR_FRZ4 (1<<14) /* Halt timer if FREEZE asserted */
995#define M8260_TGCR_STP1 (1<<1) /* Stop timer */
996#define M8260_TGCR_STP2 (1<<5) /* Stop timer */
997#define M8260_TGCR_STP3 (1<<9) /* Stop timer */
998#define M8260_TGCR_STP4 (1<<13) /* Stop timer */
999#define M8260_TGCR_RST1 (1<<0) /* Enable timer */
1000#define M8260_TGCR_RST2 (1<<4) /* Enable timer */
1001#define M8260_TGCR_RST3 (1<<8) /* Enable timer */
1002#define M8260_TGCR_RST4 (1<<12) /* Enable timer */
1003#define M8260_TGCR_GM1 (1<<3) /* Gate Mode 1 for TMR1 or TMR2 */
1004#define M8260_TGCR_GM2 (1<<11) /* Gate Mode 2 for TMR3 or TMR4 */
1005
1006#define M8260_TMR_PS(x) ((x)<<8) /* Timer prescaler */
1007#define M8260_TMR_CE_RISE (1<<6) /* Capture on rising edge */
1008#define M8260_TMR_CE_FALL (2<<6) /* Capture on falling edge */
1009#define M8260_TMR_CE_ANY (3<<6) /* Capture on any edge */
1010#define M8260_TMR_OM_TOGGLE (1<<5) /* Toggle TOUTx pin */
1011#define M8260_TMR_ORI (1<<4) /* Interrupt on reaching reference */
1012#define M8260_TMR_RESTART (1<<3) /* Restart timer after reference */
1013#define M8260_TMR_ICLK_INT (1<<1) /* Internal clock is timer source */
1014#define M8260_TMR_ICLK_INT16 (2<<1) /* Internal clock/16 is tmr src */
1015#define M8260_TMR_ICLK_TIN (3<<1) /* TIN pin is timer source */
1016#define M8260_TMR_TGATE (1<<0) /* TGATE controls timer */
1017
1018#ifdef REV_0_2
1019#define M8260_PISCR_PS (1<<6) /* PIT Interrupt state */
1020#else
1021#define M8260_PISCR_PS (1<<7) /* PIT Interrupt state */
1022#endif
1023#define M8260_PISCR_PIE (1<<2) /* PIT interrupt enable */
1024#define M8260_PISCR_PTF (1<<1) /* Stop timer when freeze asserted */
1025#define M8260_PISCR_PTE (1<<0) /* PIT enable */
1026
1027#if 0
1028#define M8260_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */
1029#define M8260_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */
1030#define M8260_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */
1031#define M8260_TBSCR_REFAE (1<<3) /* Enable ints for REFA */
1032#define M8260_TBSCR_REFBE (1<<2) /* Enable ints for REFB */
1033#define M8260_TBSCR_TBF (1<<1) /* TB stops on FREEZE */
1034#define M8260_TBSCR_TBE (1<<0) /* enable TB and decrementer */
1035#endif
1036
1037#define M8260_TMCNTSC_SEC (1<<7) /* per second flag */
1038#define M8260_TMCNTSC_ALR (1<<6) /* Alarm interrupt flag */
1039#define M8260_TMCNTSC_SIE (1<<3) /* per second interrupt enable */
1040#define M8260_TMCNTSC_ALE (1<<2) /* Alarm interrupt enable */
1041#define M8260_TMCNTSC_TCF (1<<1) /* Time count frequency */
1042#define M8260_TMCNTSC_TCE (1<<0) /* Time count enable */
1043
1044#define M8260_SIMASK_PC0 (1<<31)
1045#define M8260_SIMASK_PC1 (1<<30)
1046#define M8260_SIMASK_PC2 (1<<29)
1047#define M8260_SIMASK_PC3 (1<<28)
1048#define M8260_SIMASK_PC4 (1<<27)
1049#define M8260_SIMASK_PC5 (1<<26)
1050#define M8260_SIMASK_PC6 (1<<25)
1051#define M8260_SIMASK_PC7 (1<<24)
1052#define M8260_SIMASK_PC8 (1<<23)
1053#define M8260_SIMASK_PC9 (1<<22)
1054#define M8260_SIMASK_PC10 (1<<21)
1055#define M8260_SIMASK_PC11 (1<<20)
1056#define M8260_SIMASK_PC12 (1<<19)
1057#define M8260_SIMASK_PC13 (1<<18)
1058#define M8260_SIMASK_PC14 (1<<17)
1059#define M8260_SIMASK_PC15 (1<<16)
1060#define M8260_SIMASK_IRQ1 (1<<14)
1061#define M8260_SIMASK_IRQ2 (1<<13)
1062#define M8260_SIMASK_IRQ3 (1<<12)
1063#define M8260_SIMASK_IRQ4 (1<<11)
1064#define M8260_SIMASK_IRQ5 (1<<10)
1065#define M8260_SIMASK_IRQ6 (1<<9)
1066#define M8260_SIMASK_IRQ7 (1<<8)
1067#define M8260_SIMASK_TMCNT (1<<2)
1068#define M8260_SIMASK_PIT (1<<1)
1069
1070#define M8260_SIMASK_FCC1 (1<<31)
1071#define M8260_SIMASK_FCC2 (1<<30)
1072#define M8260_SIMASK_FCC3 (1<<29)
1073#define M8260_SIMASK_MCC1 (1<<27)
1074#define M8260_SIMASK_MCC2 (1<<26)
1075#define M8260_SIMASK_SCC1 (1<<23)
1076#define M8260_SIMASK_SCC2 (1<<22)
1077#define M8260_SIMASK_SCC3 (1<<21)
1078#define M8260_SIMASK_SCC4 (1<<20)
1079#define M8260_SIMASK_I2C (1<<15)
1080#define M8260_SIMASK_SPI (1<<14)
1081#define M8260_SIMASK_RTT (1<<13)
1082#define M8260_SIMASK_SMC1 (1<<12)
1083#define M8260_SIMASK_SMC2 (1<<11)
1084#define M8260_SIMASK_IDMA1 (1<<10)
1085#define M8260_SIMASK_IDMA2 (1<<9)
1086#define M8260_SIMASK_IDMA3 (1<<8)
1087#define M8260_SIMASK_IDMA4 (1<<7)
1088#define M8260_SIMASK_SDMA (1<<6)
1089#define M8260_SIMASK_TIMER1 (1<<4)
1090#define M8260_SIMASK_TIMER2 (1<<3)
1091#define M8260_SIMASK_TIMER3 (1<<2)
1092#define M8260_SIMASK_TIMER4 (1<<1)
1093
1094#define M8260_SIUMCR_EARB (1<<31)
1095#define M8260_SIUMCR_EARP0 (0<<28)
1096#define M8260_SIUMCR_EARP1 (1<<28)
1097#define M8260_SIUMCR_EARP2 (2<<28)
1098#define M8260_SIUMCR_EARP3 (3<<28)
1099#define M8260_SIUMCR_EARP4 (4<<28)
1100#define M8260_SIUMCR_EARP5 (5<<28)
1101#define M8260_SIUMCR_EARP6 (6<<28)
1102#define M8260_SIUMCR_EARP7 (7<<28)
1103#define M8260_SIUMCR_DSHW (1<<23)
1104#define M8260_SIUMCR_DBGC0 (0<<21)
1105#define M8260_SIUMCR_DBGC1 (1<<21)
1106#define M8260_SIUMCR_DBGC2 (2<<21)
1107#define M8260_SIUMCR_DBGC3 (3<<21)
1108#define M8260_SIUMCR_DBPC0 (0<<19)
1109#define M8260_SIUMCR_DBPC1 (1<<19)
1110#define M8260_SIUMCR_DBPC2 (2<<19)
1111#define M8260_SIUMCR_DBPC3 (3<<19)
1112#define M8260_SIUMCR_FRC (1<<17)
1113#define M8260_SIUMCR_DLK (1<<16)
1114#define M8260_SIUMCR_PNCS (1<<15)
1115#define M8260_SIUMCR_OPAR (1<<14)
1116#define M8260_SIUMCR_DPC (1<<13)
1117#define M8260_SIUMCR_MPRE (1<<12)
1118#define M8260_SIUMCR_MLRC0 (0<<10)
1119#define M8260_SIUMCR_MLRC1 (1<<10)
1120#define M8260_SIUMCR_MLRC2 (2<<10)
1121#define M8260_SIUMCR_MLRC3 (3<<10)
1122#define M8260_SIUMCR_AEME (1<<9)
1123#define M8260_SIUMCR_SEME (1<<8)
1124#define M8260_SIUMCR_BSC (1<<7)
1125#define M8260_SIUMCR_GB5E (1<<6)
1126#define M8260_SIUMCR_B2DD (1<<5)
1127#define M8260_SIUMCR_B3DD (1<<4)
1128
1129/*
1130*************************************************************************
1131* MPC8260 DUAL-PORT RAM AND REGISTERS *
1132*************************************************************************
1133*/
1134typedef struct m8260_ {
1135
1136 /*
1137 * CPM Dual-Port RAM
1138 */
1139 uint8_t dpram1[16384]; /* 0x0000 - 0x3FFF BD/data/ucode */
1140 uint8_t cpm_pad0[16384]; /* 0x4000 - 0x7FFF Reserved */
1141
1142 m8260SCCparms_t scc1p;
1143 uint8_t pad_scc1[256-sizeof(m8260SCCparms_t)];
1144 m8260SCCparms_t scc2p;
1145 uint8_t pad_scc2[256-sizeof(m8260SCCparms_t)];
1146 m8260SCCparms_t scc3p;
1147 uint8_t pad_scc3[256-sizeof(m8260SCCparms_t)];
1148 m8260SCCparms_t scc4p;
1149 uint8_t pad_scc4[256-sizeof(m8260SCCparms_t)];
1150
1151 m8260FCCparms_t fcc1p;
1152 uint8_t pad_fcc1[256-sizeof(m8260FCCparms_t)];
1153 m8260FCCparms_t fcc2p;
1154 uint8_t pad_fcc2[256-sizeof(m8260FCCparms_t)];
1155 m8260FCCparms_t fcc3p;
1156 uint8_t pad_fcc3[256-sizeof(m8260FCCparms_t)];
1157
1158 uint8_t mcc1p[128];
1159 uint8_t pad_mcc1[124];
1160 uint16_t smc1_base;
1161 uint16_t idma1_base;
1162 uint8_t mcc2p[128];
1163 uint8_t pad_mcc2[124];
1164 uint16_t smc2_base;
1165 uint16_t idma2_base;
1166 uint8_t pad_spi[252];
1167 uint16_t spi_base;
1168 uint16_t idma3_base;
1169 uint8_t pad_risc[224];
1170 uint8_t risc_timers[16];
1171 uint16_t rev_num;
1172 uint16_t cpm_pad7;
1173 uint32_t cpm_pad8;
1174 uint16_t rand;
1175 uint16_t i2c_base;
1176 uint16_t idma4_base;
1177 uint8_t cpm_pad9[1282];
1178
1179 uint8_t cpm_pad1[8192]; /* 0x9000 - 0xAFFF Reserved */
1180
1181 m8260SMCparms_t smc1p;
1182 m8260SMCparms_t smc2p;
1183 uint8_t dpram3[4096-2*sizeof(m8260SMCparms_t)];
1184
1185 uint8_t cpm_pad2[16384]; /* 0xC000 - 0xFFFF Reserved */
1186
1187
1188 /*
1189 * General SIU Block
1190 */
1191 uint32_t siumcr;
1192 uint32_t sypcr;
1193 uint8_t siu_pad0[6];
1194 uint16_t swsr;
1195 uint8_t siu_pad1[20];
1196 uint32_t bcr;
1197 uint8_t ppc_acr;
1198 uint8_t siu_pad4[3];
1199 uint32_t ppc_alrh;
1200 uint32_t ppc_alr1;
1201 uint8_t lcl_acr;
1202 uint8_t siu_pad5[3];
1203 uint32_t lcl_alrh;
1204 uint32_t lcl_alr1;
1205 uint32_t tescr1;
1206 uint32_t tescr2;
1207 uint32_t l_tescr1;
1208 uint32_t l_tescr2;
1209 uint32_t pdtea;
1210 uint8_t pdtem;
1211 uint8_t siu_pad2[3];
1212 uint32_t ldtea;
1213 uint8_t ldtem;
1214 uint8_t siu_pad3[163];
1215
1216
1217 /*
1218 * Memory Controller Block
1219 */
1220 m8260MEMCRegisters_t memc[12];
1221 uint8_t mem_pad0[8];
1222 uint32_t mar;
1223 uint8_t mem_pad1[4];
1224 uint32_t mamr;
1225 uint32_t mbmr;
1226 uint32_t mcmr;
1227 uint32_t mdmr;
1228 uint8_t mem_pad2[4];
1229 uint16_t mptpr;
1230 uint8_t mem_pad5[2];
1231 uint32_t mdr;
1232 uint8_t mem_pad3[4];
1233 uint32_t psdmr;
1234 uint32_t lsdmr;
1235 uint8_t purt;
1236 uint8_t mem_pad6[3];
1237 uint8_t psrt;
1238 uint8_t mem_pad7[3];
1239 uint8_t lurt;
1240 uint8_t mem_pad8[3];
1241 uint8_t lsrt;
1242 uint8_t mem_pad9[3];
1243 uint32_t immr;
1244 uint8_t mem_pad4[84];
1245
1246
1247 /*
1248 * System integration timers
1249 */
1250 uint8_t sit_pad0[32];
1251 uint16_t tmcntsc;
1252 uint8_t sit_pad6[2];
1253 uint32_t tmcnt;
1254 uint32_t tmcntsec;
1255 uint32_t tmcntal;
1256 uint8_t sit_pad2[16];
1257 uint16_t piscr;
1258 uint8_t sit_pad5[2];
1259 uint32_t pitc;
1260 uint32_t pitr;
1261 uint8_t sit_pad3[94];
1262 uint8_t sit_pad4[2390];
1263
1264
1265 /*
1266 * Interrupt Controller
1267 */
1268 uint16_t sicr;
1269 uint8_t ict_pad1[2];
1270 uint32_t sivec;
1271 uint32_t sipnr_h;
1272 uint32_t sipnr_l;
1273 uint32_t siprr;
1274 uint32_t scprr_h;
1275 uint32_t scprr_l;
1276 uint32_t simr_h;
1277 uint32_t simr_l;
1278 uint32_t siexr;
1279 uint8_t ict_pad0[88];
1280
1281
1282 /*
1283 * Clocks and Reset
1284 */
1285 uint32_t sccr;
1286 uint8_t clr_pad1[4];
1287 uint32_t scmr;
1288 uint8_t clr_pad2[4];
1289 uint32_t rsr;
1290 uint32_t rmr;
1291 uint8_t clr_pad0[104];
1292
1293
1294 /*
1295 * Input/ Output Port
1296 */
1297 uint32_t pdira;
1298 uint32_t ppara;
1299 uint32_t psora;
1300 uint32_t podra;
1301 uint32_t pdata;
1302 uint8_t iop_pad0[12];
1303 uint32_t pdirb;
1304 uint32_t pparb;
1305 uint32_t psorb;
1306 uint32_t podrb;
1307 uint32_t pdatb;
1308 uint8_t iop_pad1[12];
1309 uint32_t pdirc;
1310 uint32_t pparc;
1311 uint32_t psorc;
1312 uint32_t podrc;
1313 uint32_t pdatc;
1314 uint8_t iop_pad2[12];
1315 uint32_t pdird;
1316 uint32_t ppard;
1317 uint32_t psord;
1318 uint32_t podrd;
1319 uint32_t pdatd;
1320 uint8_t iop_pad3[12];
1321
1322
1323 /*
1324 * CPM Timers
1325 */
1326 uint8_t tgcr1;
1327 uint8_t cpt_pad0[3];
1328 uint8_t tgcr2;
1329 uint8_t cpt_pad1[11];
1330 uint16_t tmr1;
1331 uint16_t tmr2;
1332 uint16_t trr1;
1333 uint16_t trr2;
1334 uint16_t tcr1;
1335 uint16_t tcr2;
1336 uint16_t tcn1;
1337 uint16_t tcn2;
1338 uint16_t tmr3;
1339 uint16_t tmr4;
1340 uint16_t trr3;
1341 uint16_t trr4;
1342 uint16_t tcr3;
1343 uint16_t tcr4;
1344 uint16_t tcn3;
1345 uint16_t tcn4;
1346 uint16_t ter1;
1347 uint16_t ter2;
1348 uint16_t ter3;
1349 uint16_t ter4;
1350 uint8_t cpt_pad2[608];
1351
1352
1353 /*
1354 * DMA Block
1355 */
1356 uint8_t sdsr;
1357 uint8_t dma_pad0[3];
1358 uint8_t sdmr;
1359 uint8_t dma_pad1[3];
1360
1361 uint8_t idsr1;
1362 uint8_t dma_pad2[3];
1363 uint8_t idmr1;
1364 uint8_t dma_pad3[3];
1365 uint8_t idsr2;
1366 uint8_t dma_pad4[3];
1367 uint8_t idmr2;
1368 uint8_t dma_pad5[3];
1369 uint8_t idsr3;
1370 uint8_t dma_pad6[3];
1371 uint8_t idmr3;
1372 uint8_t dma_pad7[3];
1373 uint8_t idsr4;
1374 uint8_t dma_pad8[3];
1375 uint8_t idmr4;
1376 uint8_t dma_pad9[707];
1377
1378
1379 /*
1380 * FCC Block
1381 */
1382 m8260FCCRegisters_t fcc1;
1383 m8260FCCRegisters_t fcc2;
1384 m8260FCCRegisters_t fcc3;
1385
1386 uint8_t fcc_pad0[656];
1387
1388 /*
1389 * BRG 5-8 Block
1390 */
1391 uint32_t brgc5;
1392 uint32_t brgc6;
1393 uint32_t brgc7;
1394 uint32_t brgc8;
1395 uint8_t brg_pad0[608];
1396
1397
1398 /*
1399 * I2C
1400 */
1401 uint8_t i2mod;
1402 uint8_t i2m_pad0[3];
1403 uint8_t i2add;
1404 uint8_t i2m_pad1[3];
1405 uint8_t i2brg;
1406 uint8_t i2m_pad2[3];
1407 uint8_t i2com;
1408 uint8_t i2m_pad3[3];
1409 uint8_t i2cer;
1410 uint8_t i2m_pad4[3];
1411 uint8_t i2cmr;
1412 uint8_t i2m_pad5[331];
1413
1414
1415 /*
1416 * CPM Block
1417 */
1418 uint32_t cpcr;
1419 uint32_t rccr;
1420 uint8_t cpm_pad3[14];
1421 uint16_t rter;
1422 uint8_t cpm_pad[2];
1423 uint16_t rtmr;
1424 uint16_t rtscr;
1425 uint8_t cpm_pad4[2];
1426 uint32_t rtsr;
1427 uint8_t cpm_pad5[12];
1428
1429
1430 /*
1431 * BRG 1-4 Block
1432 */
1433 uint32_t brgc1;
1434 uint32_t brgc2;
1435 uint32_t brgc3;
1436 uint32_t brgc4;
1437
1438
1439 /*
1440 * SCC Block
1441 */
1442 m8260SCCRegisters_t scc1;
1443 m8260SCCRegisters_t scc2;
1444 m8260SCCRegisters_t scc3;
1445 m8260SCCRegisters_t scc4;
1446
1447
1448 /*
1449 * SMC Block
1450 */
1451 m8260SMCRegisters_t smc1;
1452 m8260SMCRegisters_t smc2;
1453
1454
1455 /*
1456 * SPI Block
1457 */
1458 uint16_t spmode;
1459 uint8_t spi_pad0[4];
1460 uint8_t spie;
1461 uint8_t spi_pad1[3];
1462 uint8_t spim;
1463 uint8_t spi_pad2[2];
1464 uint8_t spcom;
1465 uint8_t spi_pad3[82];
1466
1467
1468 /*
1469 * CPM Mux Block
1470 */
1471 uint8_t cmxsi1cr;
1472 uint8_t cmx_pad0[1];
1473 uint8_t cmxsi2cr;
1474 uint8_t cmx_pad1[1];
1475 uint32_t cmxfcr;
1476 uint32_t cmxscr;
1477 uint8_t cmxsmr;
1478 uint8_t cmx_pad2[1];
1479 uint16_t cmxuar;
1480 uint8_t cmx_pad3[16];
1481
1482
1483 /*
1484 * SI & MCC Blocks
1485 */
1486 m8260SIRegisters_t si1;
1487 m8260MCCRegisters_t mcc1;
1488 m8260SIRegisters_t si2;
1489 m8260MCCRegisters_t mcc2;
1490
1491 uint8_t mcc_pad0[1152];
1492
1493 /*
1494 * SI1 RAM
1495 */
1496 uint8_t si1txram[512];
1497 uint8_t ram_pad0[512];
1498 uint8_t si1rxram[512];
1499 uint8_t ram_pad1[512];
1500
1501
1502 /*
1503 * SI2 RAM
1504 */
1505 uint8_t si2txram[512];
1506 uint8_t ram_pad2[512];
1507 uint8_t si2rxram[512];
1508 uint8_t ram_pad3[512];
1509
1510
1511} m8260_t;
1512
1513extern volatile m8260_t m8260;
1514#endif /* ASM */
1515
1516#endif /* _MPC8260_H */
m8260BufferDescriptor_
Definition: mpc8260.h:649
m8260FCCRegisters_
Definition: mpc8260.h:83
m8260FCCparms_
Definition: mpc8260.h:396
m8260IDMABufferDescriptor_
Definition: mpc8260.h:745
m8260IDMAparms_
Definition: mpc8260.h:223
m8260MCCRegisters_
Definition: mpc8260.h:154
m8260MEMCRegisters_
Definition: mpc8260.h:74
m8260SCCRegisters_
Definition: mpc8260.h:104
m8260SCCparms_
Definition: mpc8260.h:252
m8260SIRegisters_
Definition: mpc8260.h:136
m8260SMCRegisters_
Definition: mpc8260.h:122
m8260SMCparms_
Definition: mpc8260.h:539
m8260SPIparms_
Definition: mpc8260.h:599
m8260_
Definition: mpc8260.h:1134
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