RTEMS 7.0-rc1
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mpc5xx.h
1/* SPDX-License-Identifier: GPL-2.0+-with-RTEMS-exception */
2
3/*
4 *
5 * MPC5xx Internal I/O Definitions
6 */
7
8/*
9 * MPC5xx port sponsored by Defence Research and Development Canada - Suffield
10 * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
11 *
12 * Derived from c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h:
13 *
14 * Submitted By: *
15 * *
16 * Eric Norum <eric@norum.ca> *
17 * *
18 * Modified for use with the MPC860 (original code was for MC68360) *
19 * by *
20 * Jay Monkman *
21 * Frasca International, Inc. *
22 * 906 E. Airport Rd. *
23 * Urbana, IL, 61801 *
24 * *
25 * jmonkman@frasca.com *
26 * *
27 * Modified further for use with the MPC821 by: *
28 * Andrew Bray <andy@chaos.org.uk> *
29 * *
30 * With some corrections/additions by: *
31 * Darlene A. Stewart and *
32 * Charles-Antoine Gauthier *
33 * Institute for Information Technology *
34 * National Research Council of Canada *
35 * Ottawa, ON K1A 0R6 *
36 * *
37 * Darlene.Stewart@iit.nrc.ca *
38 * charles.gauthier@iit.nrc.ca *
39 * *
40 * Corrections/additions: *
41 * Copyright (c) 1999, National Research Council of Canada *
42 *
43 * MPC5xx port sponsored by Defence Research and Development Canada - Suffield
44 * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
45 *
46 * The license and distribution terms for this file may be
47 * found in the file LICENSE in this distribution or at
48 * http://www.rtems.org/license/LICENSE.
49 */
50
51#ifndef _MPC5XX_H
52#define _MPC5XX_H
53
54#include <libcpu/spr.h>
55
56
57#ifndef ASM
58
59#ifdef __cplusplus
60extern "C" {
61#endif
62
63/*
64 * Macros for accessing Special Purpose Registers (SPRs)
65 */
66
67#define _eieio __asm__ volatile ("eieio\n"::)
68#define _sync __asm__ volatile ("sync\n"::)
69#define _isync __asm__ volatile ("isync\n"::)
70
71/*
72 * Core Registers (SPRs)
73 */
74#define DER 149 /* Debug Enable Register */
75#define IMMR 638 /* Internal Memory Map Register */
76#define IMMR_FLEN (1<<11) /* Internal flash ROM enabled */
77
78/*
79 * Interrupt Control Registers (SPRs)
80 */
81#define EIE 80 /* External Interrupt Enable Register */
82#define EID 81 /* External Interrupt Disable Register */
83#define NRI 82 /* Non-Recoverable Interrupt Register */
84
85#define ECR 148 /* Exception Cause Register */
86
87/*
88 * Bus Control Registers (SPRs)
89 */
90#define LCTRL1 156 /* L-Bus Support Control Register 1 */
91#define LCTRL2 157 /* L-Bus Support Control Register 2 */
92#define ICTRL 158 /* I-Bus Support Control Register */
93
94/*
95 * Burst Buffer Control Registers (SPRs)
96 */
97#define BBCMCR 560 /* Burst Buffer Configuration Register */
98#define BBCMCR_BE (1<<13) /* Burst enable */
99#define BBCMCR_ETRE (1<<12) /* Exception table relocation enable */
100
101#define MI_RBA0 784 /* Region 0 Address Register */
102#define MI_RBA1 785 /* Region 1 Address Register */
103#define MI_RBA2 786 /* Region 2 Address Register */
104#define MI_RBA3 787 /* Region 3 Address Register */
105
106#define MI_RA0 816 /* Region 0 Attribute Register */
107#define MI_RA1 817 /* Region 1 Attribute Register */
108#define MI_RA2 818 /* Region 2 Attribute Register */
109#define MI_RA3 819 /* Region 3 Attribute Register */
110#define MI_GRA 528 /* Region Global Attribute Register */
111#define MI_RA_PP (3 << 10) /* Protection bits: */
112#define MI_RA_PP_SUPV (1 << 10) /* Supervisor */
113#define MI_RA_PP_USER (2 << 10) /* User */
114#define MI_RA_G (1 << 6) /* Guarded region */
115
116
117/*
118 * L-Bus to U-Bus Interface (L2U) Registers (SPRs)
119 */
120#define L2U_MCR 568 /* L2U Module Configuration Register */
121
122#define L2U_RBA0 792 /* L2U Region 0 Address Register */
123#define L2U_RBA1 793 /* L2U Region 1 Address Register */
124#define L2U_RBA2 794 /* L2U Region 2 Address Register */
125#define L2U_RBA3 795 /* L2U Region 3 Address Register */
126
127#define L2U_RA0 824 /* L2U Region 0 Attribute Register */
128#define L2U_RA1 825 /* L2U Region 1 Attribute Register */
129#define L2U_RA2 826 /* L2U Region 2 Attribute Register */
130#define L2U_RA3 827 /* L2U Region 3 Attribute Register */
131#define L2U_GRA 536 /* L2U Global Region Attribute Register */
132#define L2U_RA_PP (3 << 10) /* Protection bits: */
133#define L2U_RA_PP_SUPV (1 << 10) /* Supervisor */
134#define L2U_RA_PP_USER (2 << 10) /* User */
135#define L2U_RA_G (1 << 6) /* Guarded region */
136
137
138/*
139 *************************************************************************
140 * REGISTER SUBBLOCKS *
141 *************************************************************************
142 */
143
144/*
145 *************************************************************************
146 * System Protection Control Register (SYPCR) *
147 *************************************************************************
148 */
149#define USIU_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */
150#define USIU_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */
151#define USIU_SYPCR_BME (1<<7) /* Bus monitor enable */
152#define USIU_SYPCR_SWF (1<<3) /* Software watchdog freeze */
153#define USIU_SYPCR_SWE (1<<2) /* Software watchdog enable */
154#define USIU_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */
155#define USIU_SYPCR_SWP (1<<0) /* Software watchdog prescale */
156
157#define USIU_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */
158#define USIU_SYPCR_BME (1<<7) /* Bus monitor enable */
159#define USIU_SYPCR_SWF (1<<3) /* Software watchdog freeze */
160#define USIU_SYPCR_SWE (1<<2) /* Software watchdog enable */
161#define USIU_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */
162#define USIU_SYPCR_SWP (1<<0) /* Software watchdog prescale */
163
164/*
165 *************************************************************************
166 * Software Service Register (SWSR) *
167 *************************************************************************
168 */
169#define TICKLE_WATCHDOG() \
170do { \
171 usiu.swsr = 0x556C; \
172 usiu.swsr = 0xAA39; \
173} while (0) \
174
175/*
176 *************************************************************************
177 * Memory Control Registers *
178 *************************************************************************
179 */
180#define USIU_MEMC_BR_BA(x) (((uint32_t)x)&0xffff8000)
181 /* Base address */
182#define USIU_MEMC_BR_AT(x) ((x)<<12) /* Address type */
183#define USIU_MEMC_BR_PS8 (1<<10) /* 8 bit port */
184#define USIU_MEMC_BR_PS16 (2<<10) /* 16 bit port */
185#define USIU_MEMC_BR_PS32 (0<<10) /* 32 bit port */
186#define USIU_MEMC_BR_WP (1<<8) /* Write protect */
187#define USIU_MEMC_BR_WEBS (1<<5) /* Write enable/byte select */
188#define USIU_MEMC_BR_TBDIP (1<<4) /* Toggle-Burst data in progress*/
189#define USIU_MEMC_BR_LBDIP (1<<3) /* Late-burst data in progress */
190#define USIU_MEMC_BR_SETA (1<<2) /* External transfer acknowledge */
191#define USIU_MEMC_BR_BI (1<<1) /* Burst inhibit */
192#define USIU_MEMC_BR_V (1<<0) /* Base/Option register are valid */
193
194#define USIU_MEMC_OR_32K 0xffff8000 /* Address range */
195#define USIU_MEMC_OR_64K 0xffff0000
196#define USIU_MEMC_OR_128K 0xfffe0000
197#define USIU_MEMC_OR_256K 0xfffc0000
198#define USIU_MEMC_OR_512K 0xfff80000
199#define USIU_MEMC_OR_1M 0xfff00000
200#define USIU_MEMC_OR_2M 0xffe00000
201#define USIU_MEMC_OR_4M 0xffc00000
202#define USIU_MEMC_OR_8M 0xff800000
203#define USIU_MEMC_OR_16M 0xff000000
204#define USIU_MEMC_OR_32M 0xfe000000
205#define USIU_MEMC_OR_64M 0xfc000000
206#define USIU_MEMC_OR_128 0xf8000000
207#define USIU_MEMC_OR_256M 0xf0000000
208#define USIU_MEMC_OR_512M 0xe0000000
209#define USIU_MEMC_OR_1G 0xc0000000
210#define USIU_MEMC_OR_2G 0x80000000
211#define USIU_MEMC_OR_4G 0x00000000
212#define USIU_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */
213#define USIU_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */
214#define USIU_MEMC_OR_ACS_NORM (0<<9) /* *CS asserted with addr lines */
215#define USIU_MEMC_OR_ACS_QRTR (2<<9) /* *CS asserted 1/4 after addr */
216#define USIU_MEMC_OR_ACS_HALF (3<<9) /* *CS asserted 1/2 after addr */
217#define USIU_MEMC_OR_ETHR (1<<8) /* Extended hold time on reads */
218#define USIU_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */
219#define USIU_MEMC_OR_BSCY(x) ((x)<<1) /* Burst beat length in clocks */
220#define USIU_MEMC_OR_TRLX (1<<0) /* Relaxed timing in GPCM */
221
222/*
223 *************************************************************************
224 * Clocks and Reset Controlmer *
225 *************************************************************************
226 */
227
228#define USIU_SCCR_DBCT (1<<31) /* Disable backup clock for timers */
229#define USIU_SCCR_COM(x) ((x)<<29) /* Clock output mode */
230#define USIU_SCCR_RTDIV (1<<24) /* RTC, PIT divide by 256, not 4 */
231#define USIU_PRQEN (1<<21) /* MSR[POW] controls frequency */
232#define USIU_SCCR_EBDF(x) ((x)<<17) /* External bus division factor */
233#define USIU_LME (1<<16) /* Enable limp mode */
234#define USIU_ENGDIV(x) ((x)<<9) /* Set engineering clock divisor */
235
236#define USIU_PLPRCR_MF(x) (((x)-1)<<20) /* PLL mult. factor (true) */
237#define USIU_PLPRCR_SPLS (1<<16) /* System PLL locked */
238#define USIU_PLPRCR_TEXPS (1<<14) /* Assert TEXP always */
239
240/*
241 *************************************************************************
242 * Programmable Interval Timer *
243 *************************************************************************
244 */
245#define USIU_PISCR_PIRQ(x) (1<<(15-x)) /* PIT interrupt level */
246#define USIU_PISCR_PS (1<<7) /* PIT Interrupt state */
247#define USIU_PISCR_PIE (1<<2) /* PIT interrupt enable */
248#define USIU_PISCR_PITF (1<<1) /* Stop timer when freeze asserted */
249#define USIU_PISCR_PTE (1<<0) /* PIT enable */
250
251/*
252 *************************************************************************
253 * Time Base *
254 *************************************************************************
255 */
256#define USIU_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */
257#define USIU_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */
258#define USIU_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */
259#define USIU_TBSCR_REFAE (1<<3) /* Enable ints for REFA */
260#define USIU_TBSCR_REFBE (1<<2) /* Enable ints for REFB */
261#define USIU_TBSCR_TBF (1<<1) /* TB stops on FREEZE */
262#define USIU_TBSCR_TBE (1<<0) /* enable TB and decrementer */
263
264/*
265 *************************************************************************
266 * SIU Interrupt Mask *
267 *************************************************************************
268 */
269#define USIU_SIMASK_IRM0 (1<<31)
270#define USIU_SIMASK_LVM0 (1<<30)
271#define USIU_SIMASK_IRM1 (1<<29)
272#define USIU_SIMASK_LVM1 (1<<28)
273#define USIU_SIMASK_IRM2 (1<<27)
274#define USIU_SIMASK_LVM2 (1<<26)
275#define USIU_SIMASK_IRM3 (1<<25)
276#define USIU_SIMASK_LVM3 (1<<24)
277#define USIU_SIMASK_IRM4 (1<<23)
278#define USIU_SIMASK_LVM4 (1<<22)
279#define USIU_SIMASK_IRM5 (1<<21)
280#define USIU_SIMASK_LVM5 (1<<20)
281#define USIU_SIMASK_IRM6 (1<<19)
282#define USIU_SIMASK_LVM6 (1<<18)
283#define USIU_SIMASK_IRM7 (1<<17)
284#define USIU_SIMASK_LVM7 (1<<16)
285
286/*
287 *************************************************************************
288 * SIU Module Control *
289 *************************************************************************
290 */
291#define USIU_SIUMCR_EARB (1<<31)
292#define USIU_SIUMCR_EARP0 (0<<28)
293#define USIU_SIUMCR_EARP1 (1<<28)
294#define USIU_SIUMCR_EARP2 (2<<28)
295#define USIU_SIUMCR_EARP3 (3<<28)
296#define USIU_SIUMCR_EARP4 (4<<28)
297#define USIU_SIUMCR_EARP5 (5<<28)
298#define USIU_SIUMCR_EARP6 (6<<28)
299#define USIU_SIUMCR_EARP7 (7<<28)
300#define USIU_SIUMCR_DSHW (1<<23)
301#define USIU_SIUMCR_DBGC0 (0<<21)
302#define USIU_SIUMCR_DBGC1 (1<<21)
303#define USIU_SIUMCR_DBGC2 (2<<21)
304#define USIU_SIUMCR_DBGC3 (3<<21)
305#define USIU_SIUMCR_DBPC (1<<20)
306#define USIU_SIUMCR_ATWC (1<<19)
307#define USIU_SIUMCR_GPC0 (0<<17)
308#define USIU_SIUMCR_GPC1 (1<<17)
309#define USIU_SIUMCR_GPC2 (2<<17)
310#define USIU_SIUMCR_GPC3 (3<<17)
311#define USIU_SIUMCR_DLK (1<<16)
312#define USIU_SIUMCR_SC0 (0<<13)
313#define USIU_SIUMCR_SC1 (1<<13)
314#define USIU_SIUMCR_SC2 (2<<13)
315#define USIU_SIUMCR_SC3 (3<<13)
316#define USIU_SIUMCR_RCTX (1<<12)
317#define USIU_SIUMCR_MLRC0 (0<<10)
318#define USIU_SIUMCR_MLRC1 (1<<10)
319#define USIU_SIUMCR_MLRC2 (2<<10)
320#define USIU_SIUMCR_MLRC3 (3<<10)
321#define USIU_SIUMCR_MTSC (1<<7)
322
323/*
324 * Value to write to a key register to unlock the corresponding SIU register
325 */
326#define USIU_UNLOCK_KEY 0x55CCAA33
327
328/*
329 *************************************************************************
330 * UIMB Module Control *
331 *************************************************************************
332 */
333#define UIMB_UMCR_STOP (1<<31)
334#define UIMB_UMCR_IRQMUX(x) ((x)<<29)
335#define UIMB_UMCR_HSPEED (1<<28)
336
337/*
338 *************************************************************************
339 * QSMCM Serial Communications Interface (SCI) *
340 *************************************************************************
341 */
342
343
344#define QSMCM_ILDSCI(x) ((x)<<8) /* SCI interrupt level */
345
346#define QSMCM_SCI_BAUD(x) ((x)&0x1FFF) /* Baud rate field */
347
348#define QSMCM_SCI_LOOPS (1<<14) /* Loopback test mode */
349#define QSMCM_SCI_WOMS (1<<13) /* Wire-or mode select */
350#define QSMCM_SCI_ILT (1<<12) /* Idle-line detect type */
351#define QSMCM_SCI_PT (1<<11) /* Parity type */
352#define QSMCM_SCI_PE (1<<10) /* Parity enable */
353#define QSMCM_SCI_M (1<<9) /* 11-bit mode */
354#define QSMCM_SCI_WAKE (1<<8) /* Wakeup mode */
355
356#define QSMCM_SCI_TIE (1<<7) /* Transmitter interrupt enable */
357#define QSMCM_SCI_TCIE (1<<6) /* Transmit complete intr. enable */
358#define QSMCM_SCI_RIE (1<<5) /* Receiver interrupt enable */
359#define QSMCM_SCI_ILIE (1<<4) /* Idle line interrupt enable */
360#define QSMCM_SCI_TE (1<<3) /* Transmitter enable */
361#define QSMCM_SCI_RE (1<<2) /* Receiver enable */
362#define QSMCM_SCI_RWU (1<<1) /* Receiver wake-up enable */
363#define QSMCM_SCI_SBK (1<<0) /* Send break */
364
365#define QSMCM_SCI_TDRE (1<<8) /* Transmit data register empty */
366#define QSMCM_SCI_TC (1<<7) /* Transmit complete */
367#define QSMCM_SCI_RDRF (1<<6) /* Receive data register full */
368#define QSMCM_SCI_RAF (1<<5) /* Receiver active flag */
369#define QSMCM_SCI_IDLE (1<<4) /* Idle line detected */
370#define QSMCM_SCI_OR (1<<3) /* Receiver overrun error */
371#define QSMCM_SCI_NF (1<<2) /* Receiver noise error flag */
372#define QSMCM_SCI_FE (1<<1) /* Receiver framing error */
373#define QSMCM_SCI_PF (1<<0) /* Receiver parity error */
374
375/*
376 *************************************************************************
377 * Unified System Interface Unit *
378 *************************************************************************
379 */
380
381/*
382 * Memory controller registers
383 */
384typedef struct m5xxMEMCRegisters_ {
385 uint32_t _br;
386 uint32_t _or; /* Used to be called 'or'; reserved ANSI C++ keyword */
387} m5xxMEMCRegisters_t;
388
389/*
390 * USIU itself
391 */
392typedef struct usiu_ {
393 /*
394 * SIU Block
395 */
396 uint32_t siumcr;
397 uint32_t sypcr;
398 uint32_t _pad70;
399 uint16_t _pad0;
400 uint16_t swsr;
401 uint32_t sipend;
402 uint32_t simask;
403 uint32_t siel;
404 uint32_t sivec;
405 uint32_t tesr;
406 uint32_t sgpiodt1;
407 uint32_t sgpiodt2;
408 uint32_t sgpiocr;
409 uint32_t emcr;
410 uint8_t _pad71[0x03C-0x034];
411 uint32_t pdmcr;
412 uint8_t _pad2[0x100-0x40];
413
414 /*
415 * MEMC Block
416 */
417 m5xxMEMCRegisters_t memc[4];
418 uint8_t _pad7[0x140-0x120];
419 uint32_t dmbr;
420 uint32_t dmor;
421 uint8_t _pad8[0x178-0x148];
422 uint16_t mstat;
423 uint8_t _pad9[0x200-0x17A];
424
425 /*
426 * System integration timers
427 */
428 uint16_t tbscr;
429 uint16_t _pad10;
430 uint32_t tbreff0;
431 uint32_t tbreff1;
432 uint8_t _pad11[0x220-0x20c];
433 uint16_t rtcsc;
434 uint16_t _pad12;
435 uint32_t rtc;
436 uint32_t rtsec;
437 uint32_t rtcal;
438 uint32_t _pad13[4];
439 uint16_t piscr;
440 uint16_t _pad14;
441 uint16_t pitc;
442 uint16_t _pad_14_1;
443 uint16_t pitr;
444 uint16_t _pad_14_2;
445 uint8_t _pad15[0x280-0x24c];
446
447 /*
448 * Clocks and Reset
449 */
450 uint32_t sccr;
451 uint32_t plprcr;
452 uint16_t rsr;
453 uint16_t _pad72;
454 uint16_t colir;
455 uint16_t _pad73;
456 uint16_t vsrmcr;
457 uint8_t _pad16[0x300-0x292];
458
459 /*
460 * System integration timers keys
461 */
462 uint32_t tbscrk;
463 uint32_t tbreff0k;
464 uint32_t tbreff1k;
465 uint32_t tbk;
466 uint32_t _pad17[4];
467 uint32_t rtcsk;
468 uint32_t rtck;
469 uint32_t rtseck;
470 uint32_t rtcalk;
471 uint32_t _pad18[4];
472 uint32_t piscrk;
473 uint32_t pitck;
474 uint8_t _pad19[0x380-0x348];
475
476 /*
477 * Clocks and Reset Keys
478 */
479 uint32_t sccrk;
480 uint32_t plprck;
481 uint32_t rsrk;
482 uint8_t _pad20[0x400-0x38c];
483} usiu_t;
484
485extern volatile usiu_t usiu; /* defined in linkcmds */
486
487/*
488 *************************************************************************
489 * Inter-Module Bus and Devices *
490 *************************************************************************
491 */
492
493/*
494 * Dual-Port TPU RAM (DPTRAM)
495 */
496typedef struct m5xxDPTRAMRegisters_ {
497 uint8_t pad[0x4000]; /* define later */
498} m5xxDPTRAMRegisters_t;
499
500/*
501 * Time Processor Unit (TPU)
502 */
503typedef struct m5xxTPU3Registers_ {
504 uint8_t pad[0x400]; /* define later */
505} m5xxTPU3Registers_t;
506
507/*
508 * Queued A/D Converter (QADC)
509 */
510typedef struct m5xxQADC64Registers_ {
511 uint8_t pad[0x400]; /* define later */
512} m5xxQADC64Registers_t;
513
514/*
515 * Serial Communications Interface (SCI)
516 */
517typedef struct m5xxSCIRegisters_ {
518 uint16_t sccr0;
519 uint16_t sccr1;
520 uint16_t scsr;
521 uint16_t scdr;
522} m5xxSCIRegisters_t;
523
524/*
525 * Serial Peripheral Interface (SPI)
526 */
527typedef struct m5xxSPIRegisters_ {
528 uint16_t spcr0;
529 uint16_t spcr1;
530 uint16_t spcr2;
531 uint8_t spcr3;
532 uint8_t spsr;
533} m5xxSPIRegisters_t;
534
535/*
536 * Queued Serial Multi-Channel Module (QSMCM)
537 */
538typedef struct m5xxQSMCMRegisters_ {
539 uint16_t qsmcmmcr;
540 uint16_t qtest;
541 uint16_t qdsci_il;
542 uint16_t qspi_il;
543
544 m5xxSCIRegisters_t sci1;
545
546 uint8_t _pad10[0x14-0x10];
547
548 uint16_t portqs;
549 uint16_t pqspar;
550 m5xxSPIRegisters_t spi;
551
552 m5xxSCIRegisters_t sci2;
553
554 uint16_t qsci1cr;
555 uint16_t qsci1sr;
556 uint16_t sctq[0x10];
557 uint16_t scrq[0x10];
558
559 uint8_t _pad6C[0x140-0x06C];
560
561 uint16_t recram[0x20];
562 uint16_t tranram[0x20];
563 uint16_t comdram[0x20];
564} m5xxQSMCMRegisters_t;
565
566/*
567 * Modular Input/Output System (MIOS)
568 */
569typedef struct m5xxMIOS1Registers_ {
570 uint8_t pad[0x1000]; /* define later */
571} m5xxMIOS1Registers_t;
572
573/*
574 * Can 2.0B Controller (TouCAN)
575 */
576typedef struct m5xxTouCANRegisters_ {
577 uint8_t pad[0x400]; /* define later */
578} m5xxTouCANRegisters_t;
579
580/*
581 * U-Bus to IMB3 Bus Interface Module (UIMB)
582 */
583typedef struct m5xxUIMBRegisters_ {
584 uint32_t umcr;
585 uint32_t utstcreg;
586 uint32_t uipend;
587} m5xxUIMBRegisters_t;
588
589/*
590 * IMB itself
591 */
592typedef struct imb_ {
593 m5xxDPTRAMRegisters_t dptram;
594 m5xxTPU3Registers_t tpu[2];
595 m5xxQADC64Registers_t qadc[2];
596 m5xxQSMCMRegisters_t qsmcm;
597 uint8_t _pad5200[0x6000-0x5200];
598 m5xxMIOS1Registers_t mios;
599 m5xxTouCANRegisters_t toucan[2];
600 uint8_t _pad7800[0x7F80-0x7800];
601 m5xxUIMBRegisters_t uimb;
602} imb_t;
603
604extern volatile imb_t imb; /* defined in linkcmds */
605
606
607/*
608 * Methods shared across libcpu and the BSP.
609 */
610void clockOn(void* unused);
611void clockOff(void* unused);
612int clockIsOn(void* unused);
613rtems_isr Clock_isr(void *unused);
614
615#ifdef __cplusplus
616}
617#endif
618
619#endif /* ASM */
620
621#endif /* _MPC5XX_H */
rtems_isr
ISR_Handler rtems_isr
This type defines the return type of interrupt service routines.
Definition: intr.h:123
imb_
Definition: mpc5xx.h:592
m5xxDPTRAMRegisters_
Definition: mpc5xx.h:496
m5xxMEMCRegisters_
Definition: mpc5xx.h:384
m5xxMIOS1Registers_
Definition: mpc5xx.h:569
m5xxQADC64Registers_
Definition: mpc5xx.h:510
m5xxQSMCMRegisters_
Definition: mpc5xx.h:538
m5xxSCIRegisters_
Definition: mpc5xx.h:517
m5xxSPIRegisters_
Definition: mpc5xx.h:527
m5xxTPU3Registers_
Definition: mpc5xx.h:503
m5xxTouCANRegisters_
Definition: mpc5xx.h:576
m5xxUIMBRegisters_
Definition: mpc5xx.h:583
usiu_
Definition: mpc5xx.h:392
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