RTEMS 7.0-rc1
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mcf5206e.h
1/* SPDX-License-Identifier: GPL-2.0+-with-RTEMS-exception */
2
3/*
4 * Coldfire MCF5206e on-chip peripherial definitions.
5 * Contents of this file based on information provided in
6 * Motorola MCF5206e User's Manual
7 *
8 * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
9 * Author: Victor V. Vengerov <vvv@oktet.ru>
10 *
11 * The license and distribution terms for this file may be
12 * found in the file LICENSE in this distribution or at
13 * http://www.rtems.org/license/LICENSE.
14 */
15
16#ifndef __MCF5206E_H__
17#define __MCF5206E_H__
18
19#ifdef ASM
20#define MCF5206E_REG8(base,ofs) (ofs+base)
21#define MCF5206E_REG16(base,ofs) (ofs+base)
22#define MCF5206E_REG32(base,ofs) (ofs+base)
23#else
24#define MCF5206E_REG8(base,ofs) \
25 (volatile uint8_t*)((uint8_t*)(base) + (ofs))
26#define MCF5206E_REG16(base,ofs) \
27 (volatile uint16_t*)((uint8_t*)(base) + (ofs))
28#define MCF5206E_REG32(base,ofs) \
29 (volatile uint32_t*)((uint8_t*)(base) + (ofs))
30#endif
31
32/*** Instruction Cache -- MCF5206e User's Manual, Chapter 4 ***/
33
34/* CACR - Cache Control Register */
35#define MCF5206E_CACR_CENB (0x80000000) /* Cache Enable */
36#define MCF5206E_CACR_CPDI (0x10000000) /* Disable CPUSHL Invalidation */
37#define MCF5206E_CACR_CFRZ (0x08000000) /* Cache Freeze */
38#define MCF5206E_CACR_CINV (0x01000000) /* Cache Invalidate */
39#define MCF5206E_CACR_CEIB (0x00000400) /* Cache Enable Noncacheable
40 instruction bursting */
41#define MCF5206E_CACR_DCM (0x00000200) /* Default cache mode - noncacheable*/
42#define MCF5206E_CACR_DBWE (0x00000100) /* Default Buffered Write Enable */
43#define MCF5206E_CACR_DWP (0x00000020) /* Default Write Protection */
44#define MCF5206E_CACR_CLNF (0x00000003) /* Cache Line Fill */
45
46/* ACR0, ACR1 - Access Control Registers */
47#define MCF5206E_ACR_AB (0xff000000) /* Address Base */
48#define MCF5206E_ACR_AB_S (24)
49#define MCF5206E_ACR_AM (0x00ff0000) /* Address Mask */
50#define MCF5206E_ACR_AM_S (16)
51#define MCF5206E_ACR_EN (0x00008000) /* Enable ACR */
52#define MCF5206E_ACR_SM (0x00006000) /* Supervisor Mode */
53#define MCF5206E_ACR_SM_USR (0x00000000) /* Match if user mode */
54#define MCF5206E_ACR_SM_SVR (0x00002000) /* Match if supervisor mode */
55#define MCF5206E_ACR_SM_ANY (0x00004000) /* Match Always */
56#define MCF5206E_ACR_CM (0x00000040) /* Cache Mode (1 - noncacheable) */
57#define MCF5206E_ACR_BUFW (0x00000020) /* Buffered Write Enable */
58#define MCF5206E_ACR_WP (0x00000004) /* Write Protect */
59#define MCF5206E_ACR_BASE(base) ((base) & MCF5206E_ACR_AB)
60#define MCF5206E_ACR_MASK(mask) (((mask) >> 8) & MCF5206E_ACR_AM)
61
62/*** SRAM -- MCF5206e User's Manual, Chapter 5 ***/
63
64/* RAMBAR - SRAM Base Address Register */
65#define MCF5206E_RAMBAR_BA (0xffffe000) /* SRAM Base Address */
66#define MCF5206E_RAMBAR_WP (0x00000100) /* Write Protect */
67#define MCF5206E_RAMBAR_CI (0x00000020) /* CPU Space mask */
68#define MCF5206E_RAMBAR_SC (0x00000010) /* Supervisor Code Space Mask */
69#define MCF5206E_RAMBAR_SD (0x00000008) /* Supervisor Data Space Mask */
70#define MCF5206E_RAMBAR_UC (0x00000004) /* User Code Space Mask */
71#define MCF5206E_RAMBAR_UD (0x00000002) /* User Data Space Mask */
72#define MCF5206E_RAMBAR_V (0x00000001) /* Contents of RAMBAR are valid */
73
74/*** DMA Controller Module -- MCF5206e User's Manual, Chapter 7 ***/
75
76/* DMA Source Address Register */
77#define MCF5206E_SAR(mbar,chn) MCF5206E_REG32(mbar,0x200 + ((chn) * 0x40))
78
79/* DMA Destination Address Register */
80#define MCF5206E_DAR(mbar,chn) MCF5206E_REG32(mbar,0x204 + ((chn) * 0x40))
81
82/* DMA Byte Count Register */
83#define MCF5206E_BCR(mbar,chn) MCF5206E_REG16(mbar,0x20C + ((chn) * 0x40))
84
85/* DMA Control Register */
86#define MCF5206E_DCR(mbar,chn) MCF5206E_REG16(mbar,0x208 + ((chn) * 0x40))
87#define MCF5206E_DCR_INT (0x8000) /* Interrupt on completion of transfer */
88#define MCF5206E_DCR_EEXT (0x4000) /* Enable External DMA Request */
89#define MCF5206E_DCR_CS (0x2000) /* Cycle Steal */
90#define MCF5206E_DCR_AA (0x1000) /* Auto Align */
91#define MCF5206E_DCR_BWC (0x0E00) /* Bandwidth Control: */
92#define MCF5206E_DCR_BWC_DISABLE (0x0000) /* Bandwidth Control Disabled */
93#define MCF5206E_DCR_BWC_512 (0x0200) /* 512 bytes */
94#define MCF5206E_DCR_BWC_1024 (0x0400) /* 1024 bytes */
95#define MCF5206E_DCR_BWC_2048 (0x0600) /* 2048 bytes */
96#define MCF5206E_DCR_BWC_4096 (0x0800) /* 4096 bytes */
97#define MCF5206E_DCR_BWC_8192 (0x0A00) /* 8192 bytes */
98#define MCF5206E_DCR_BWC_16384 (0x0C00) /* 16384 bytes */
99#define MCF5206E_DCR_BWC_32768 (0x0E00) /* 32768 bytes */
100#define MCF5206E_DCR_SAA (0x0100) /* Single Address Access */
101#define MCF5206E_DCR_S_RW (0x0080) /* Single Address Access Read/Write Val */
102#define MCF5206E_DCR_SINC (0x0040) /* Source Increment */
103#define MCF5206E_DCR_SSIZE (0x0030) /* Source Size: */
104#define MCF5206E_DCR_SSIZE_LONG (0x0000) /* Longword (4 bytes) */
105#define MCF5206E_DCR_SSIZE_BYTE (0x0010) /* Byte */
106#define MCF5206E_DCR_SSIZE_WORD (0x0020) /* Word (2 bytes) */
107#define MCF5206E_DCR_SSIZE_LINE (0x0030) /* Line (16 bytes) */
108#define MCF5206E_DCR_DINC (0x0008) /* Destination Increment */
109#define MCF5206E_DCR_DSIZE (0x0006) /* Destination Size: */
110#define MCF5206E_DCR_DSIZE_LONG (0x0000) /* Longword (4 bytes) */
111#define MCF5206E_DCR_DSIZE_BYTE (0x0002) /* Byte */
112#define MCF5206E_DCR_DSIZE_WORD (0x0004) /* Word (2 bytes) */
113#define MCF5206E_DCR_DSIZE_LINE (0x0006) /* Line (16 bytes) */
114#define MCF5206E_DCR_START (0x0001) /* Start Transfer */
115
116/* DMA Status Register */
117#define MCF5206E_DSR(mbar,chn) MCF5206E_REG8(mbar,0x210 + ((chn) * 0x40))
118#define MCF5206E_DSR_CE (0x40) /* Configuration Error has occured */
119#define MCF5206E_DSR_BES (0x20) /* Bus Error on Source */
120#define MCF5206E_DSR_BED (0x10) /* Bus Error on Destination */
121#define MCF5206E_DSR_REQ (0x04) /* Request */
122#define MCF5206E_DSR_BSY (0x02) /* Busy */
123#define MCF5206E_DSR_DONE (0x01) /* Transaction Done */
124
125/* DMA Interrupt Vector Register */
126#define MCF5206E_DIVR(mbar,chn) MCF5206E_REG8(mbar,0x214 + ((chn) * 0x40))
127
128
129/*** System Integration Module -- MCF5206e User's Manual, Chapter 8 ***/
130
131/* MBAR - Module Base Address Register */
132#define MCF5206E_MBAR_BA (0xFFFFFC00) /* Base Address */
133#define MCF5206E_MBAR_SC (0x00000010) /* Supervisor Code Space Mask */
134#define MCF5206E_MBAR_SD (0x00000008) /* Supervisor Data Space Mask */
135#define MCF5206E_MBAR_UC (0x00000004) /* User Code Space Mask */
136#define MCF5206E_MBAR_UD (0x00000002) /* User Data Space Mask */
137#define MCF5206E_MBAR_V (0x00000001) /* Contents of MBAR are valid */
138
139/* SIM Configuration Register */
140#define MCF5206E_SIMR(mbar) MCF5206E_REG8(mbar,0x003)
141#define MCF5206E_SIMR_FRZ1 (0x80) /* Disable Soft Wdog Timer when FREEZE */
142#define MCF5206E_SIMR_FRZ0 (0x40) /* Disable Bus Timeout monitor when FREEZE*/
143#define MCF5206E_SIMR_BL (0x01) /* Bus Lock Enable */
144
145/* Interrupt numbers assignment */
146#define MCF5206E_INTR_EXT_IRQ1 (1) /* External IRQ1 */
147#define MCF5206E_INTR_EXT_IPL1 (1) /* External IPL1 */
148#define MCF5206E_INTR_EXT_IPL2 (2) /* External IPL2 */
149#define MCF5206E_INTR_EXT_IPL3 (3) /* External IPL3 */
150#define MCF5206E_INTR_EXT_IRQ4 (4) /* External IRQ4 */
151#define MCF5206E_INTR_EXT_IPL4 (4) /* External IPL4 */
152#define MCF5206E_INTR_EXT_IPL5 (5) /* External IPL5 */
153#define MCF5206E_INTR_EXT_IPL6 (6) /* External IPL6 */
154#define MCF5206E_INTR_EXT_IRQ7 (7) /* External IRQ7 */
155#define MCF5206E_INTR_EXT_IPL7 (7) /* External IPL7 */
156#define MCF5206E_INTR_SWT (8) /* Software Watchdog Timer */
157#define MCF5206E_INTR_TIMER_1 (9) /* Timer 1 interrupt */
158#define MCF5206E_INTR_TIMER_2 (10) /* Timer 2 interrupt */
159#define MCF5206E_INTR_MBUS (11) /* MBUS interrupt */
160#define MCF5206E_INTR_UART_1 (12) /* UART 1 interrupt */
161#define MCF5206E_INTR_UART_2 (13) /* UART 2 interrupt */
162#define MCF5206E_INTR_DMA_0 (14) /* DMA channel 0 interrupt */
163#define MCF5206E_INTR_DMA_1 (15) /* DMA channel 1 interrupt */
164
165#define MCF5206E_INTR_BIT(n) (1 << (n))
166
167/* Interrupt Control Registers (ICR1 - ICR15) */
168#define MCF5206E_ICR(mbar,n) MCF5206E_REG8(mbar,0x014 + (n) - 1)
169
170#define MCF5206E_ICR_AVEC (0x80) /* Autovector Enable */
171#define MCF5206E_ICR_IL (0x1c) /* Interrupt Level */
172#define MCF5206E_ICR_IL_S (2)
173#define MCF5206E_ICR_IP (0x03) /* Interrupt Priority */
174#define MCF5206E_ICR_IP_S (0)
175
176/* Interrupt Mask Register */
177#define MCF5206E_IMR(mbar) MCF5206E_REG16(mbar,0x036)
178
179/* Interrupt Pending Register */
180#define MCF5206E_IPR(mbar) MCF5206E_REG16(mbar,0x03a)
181
182/* Reset Status Register */
183#define MCF5206E_RSR(mbar) MCF5206E_REG8(mbar,0x040)
184#define MCF5206E_RSR_HRST (0x80) /* Hard Reset or System Reset */
185#define MCF5206E_RSR_SWTR (0x20) /* Software Watchdog Timer Reset */
186
187/* System Protection Control Register */
188#define MCF5206E_SYPCR(mbar) MCF5206E_REG8(mbar,0x041)
189#define MCF5206E_SYPCR_SWE (0x80) /* Software Watchdog Enable */
190#define MCF5206E_SYPCR_SWRI (0x40) /* Software Watchdog Reset/Interrupt Sel.*/
191#define MCF5206E_SYPCR_SWP (0x20) /* Software Watchdog Prescaler */
192#define MCF5206E_SYPCR_SWT (0x18) /* Software Watchdog Timing: */
193#define MCF5206E_SYPCR_SWT_S (3)
194#define MCF5206E_SYPCR_SWT_9 (0x00) /* timeout = (1<<9)/sysfreq */
195#define MCF5206E_SYPCR_SWT_11 (0x08) /* timeout = (1<<11)/sysfreq */
196#define MCF5206E_SYPCR_SWT_13 (0x10) /* timeout = (1<<13)/sysfreq */
197#define MCF5206E_SYPCR_SWT_15 (0x18) /* timeout = (1<<15)/sysfreq */
198#define MCF5206E_SYPCR_SWT_18 (0x20) /* timeout = (1<<18)/sysfreq */
199#define MCF5206E_SYPCR_SWT_20 (0x28) /* timeout = (1<<20)/sysfreq */
200#define MCF5206E_SYPCR_SWT_22 (0x30) /* timeout = (1<<22)/sysfreq */
201#define MCF5206E_SYPCR_SWT_24 (0x38) /* timeout = (1<<24)/sysfreq */
202#define MCF5206E_SYPCR_BME (0x04) /* Bus Timeout Monitor Enable */
203#define MCF5206E_SYPCR_BMT (0x03) /* Bus Monitor Timing: */
204#define MCF5206E_SYPCR_BMT_1024 (0x00) /* timeout 1024 system clocks */
205#define MCF5206E_SYPCR_BMT_512 (0x01) /* timeout 512 system clocks */
206#define MCF5206E_SYPCR_BMT_256 (0x02) /* timeout 256 system clocks */
207#define MCF5206E_SYPCR_BMT_128 (0x03) /* timeout 128 system clocks */
208
209/* Software Watchdog Interrupt Vector Register */
210#define MCF5206E_SWIVR(mbar) MCF5206E_REG8(mbar,0x042)
211
212/* Software Watchdog Service Register */
213#define MCF5206E_SWSR(mbar) MCF5206E_REG8(mbar,0x043)
214#define MCF5206E_SWSR_KEY1 (0x55)
215#define MCF5206E_SWSR_KEY2 (0xAA)
216
217/* Pin Assignment Register */
218#define MCF5206E_PAR(mbar) MCF5206E_REG16(mbar,0x0CA)
219#define MCF5206E_PAR_PAR9 (0x200)
220#define MCF5206E_PAR_PAR9_TOUT (0x000) /* Timer 0 output */
221#define MCF5206E_PAR_PAR9_DREQ1 (0x200) /* DMA channel 1 request */
222#define MCF5206E_PAR_PAR8 (0x100)
223#define MCF5206E_PAR_PAR8_TIN0 (0x000) /* Timer 1 input */
224#define MCF5206E_PAR_PAR8_DREQ0 (0x100) /* DMA channel 0 request */
225#define MCF5206E_PAR_PAR7 (0x080)
226#define MCF5206E_PAR_PAR7_RSTO (0x000) /* Reset output */
227#define MCF5206E_PAR_PAR7_UART2 (0x080) /* UART 2 RTS output */
228#define MCF5206E_PAR_PAR6 (0x040)
229#define MCF5206E_PAR_PAR6_IRQ (0x000) /* IRQ7, IRQ4, IRQ1 */
230#define MCF5206E_PAR_PAR6_IPL (0x040) /* IPL2, IPL1, IPL0 */
231#define MCF5206E_PAR_PAR5 (0x020)
232#define MCF5206E_PAR_PAR5_GPIO (0x000) /* General purpose I/O PP7-PP4 */
233#define MCF5206E_PAR_PAR5_PST (0x020) /* BDM signals PST3-PST0 */
234#define MCF5206E_PAR_PAR4 (0x010)
235#define MCF5206E_PAR_PAR4_GPIO (0x000) /* General purpose I/O PP3-PP0 */
236#define MCF5206E_PAR_PAR4_DDATA (0x010) /* BDM signals DDATA3-DDATA0 */
237#define MCF5206E_PAR_PAR3 (0x008)
238#define MCF5206E_PAR_PAR2 (0x004)
239#define MCF5206E_PAR_PAR1 (0x002)
240#define MCF5206E_PAR_PAR0 (0x001)
241#define MCF5206E_PAR_WE0_WE1_WE2_WE3 (0x000)
242#define MCF5206E_PAR_WE0_WE1_CS5_CS4 (0x001)
243#define MCF5206E_PAR_WE0_WE1_CS5_A24 (0x002)
244#define MCF5206E_PAR_WE0_WE1_A25_A24 (0x003)
245#define MCF5206E_PAR_WE0_CS6_CS5_CS4 (0x004)
246#define MCF5206E_PAR_WE0_CS6_CS5_A24 (0x005)
247#define MCF5206E_PAR_WE0_CS6_A25_A24 (0x006)
248#define MCF5206E_PAR_WE0_A26_A25_A24 (0x007)
249#define MCF5206E_PAR_CS7_CS6_CS5_CS4 (0x008)
250#define MCF5206E_PAR_CS7_CS6_CS4_A24 (0x009)
251#define MCF5206E_PAR_CS7_CS6_A25_A24 (0x00A)
252#define MCF5206E_PAR_CS7_A26_A25_A24 (0x00B)
253#define MCF5206E_PAR_A27_A26_A25_A24 (0x00C)
254
255/* Bus Master Arbitration Control */
256#define MCF5206E_MARB(mbar) MCF5206E_REG8(mbar,0x007)
257#define MCF5206E_MARB_NOARB (0x08) /* Arbiter operation disable */
258#define MCF5206E_MARB_ARBCTRL (0x04) /* Arb. order: Internal DMA, Coldfire */
259
260/*** Chip Select Module -- MCF5206e User's Manual, Chapter 9 ***/
261
262/* Chip Select Address Register */
263#define MCF5206E_CSAR(mbar,bank) MCF5206E_REG16(mbar,0x064 + ((bank) * 12))
264
265/* Chip Select Mask Register */
266#define MCF5206E_CSMR(mbar,bank) MCF5206E_REG32(mbar,0x068 + ((bank) * 12))
267#define MCF5206E_CSMR_BAM (0xffff0000) /* Base Address Mask */
268#define MCF5206E_CSMR_BAM_S (16)
269#define MCF5206E_CSMR_MASK_256M (0x0FFF0000)
270#define MCF5206E_CSMR_MASK_128M (0x07FF0000)
271#define MCF5206E_CSMR_MASK_64M (0x03FF0000)
272#define MCF5206E_CSMR_MASK_32M (0x01FF0000)
273#define MCF5206E_CSMR_MASK_16M (0x00FF0000)
274#define MCF5206E_CSMR_MASK_8M (0x007F0000)
275#define MCF5206E_CSMR_MASK_4M (0x003F0000)
276#define MCF5206E_CSMR_MASK_2M (0x001F0000)
277#define MCF5206E_CSMR_MASK_1M (0x000F0000)
278#define MCF5206E_CSMR_MASK_1024K (0x000F0000)
279#define MCF5206E_CSMR_MASK_512K (0x00070000)
280#define MCF5206E_CSMR_MASK_256K (0x00030000)
281#define MCF5206E_CSMR_MASK_128K (0x00010000)
282#define MCF5206E_CSMR_MASK_64K (0x00000000)
283#define MCF5206E_CSMR_CI (0x00000020) /* CPU Space Mask (CSMR1 only) */
284#define MCF5206E_CSMR_SC (0x00000010) /* Supervisor Code Space Mask */
285#define MCF5206E_CSMR_SD (0x00000008) /* Supervisor Data Space Mask */
286#define MCF5206E_CSMR_UC (0x00000004) /* User Code Space Mask */
287#define MCF5206E_CSMR_UD (0x00000002) /* User Data Space Mask */
288
289/* Chip Select Control Register */
290#define MCF5206E_CSCR(mbar,bank) MCF5206E_REG16(mbar,0x6E + ((bank) * 12))
291#define MCF5206E_CSCR_WS (0x3c00) /* Wait States */
292#define MCF5206E_CSCR_WS_S (10)
293#define MCF5206E_CSCR_WS0 (0x0000) /* 0 Wait States */
294#define MCF5206E_CSCR_WS1 (0x0400) /* 1 Wait States */
295#define MCF5206E_CSCR_WS2 (0x0800) /* 2 Wait States */
296#define MCF5206E_CSCR_WS3 (0x0C00) /* 3 Wait States */
297#define MCF5206E_CSCR_WS4 (0x1000) /* 4 Wait States */
298#define MCF5206E_CSCR_WS5 (0x1400) /* 5 Wait States */
299#define MCF5206E_CSCR_WS6 (0x1800) /* 6 Wait States */
300#define MCF5206E_CSCR_WS7 (0x1C00) /* 7 Wait States */
301#define MCF5206E_CSCR_WS8 (0x2000) /* 8 Wait States */
302#define MCF5206E_CSCR_WS9 (0x2400) /* 9 Wait States */
303#define MCF5206E_CSCR_WS10 (0x2800) /* 10 Wait States */
304#define MCF5206E_CSCR_WS11 (0x2C00) /* 11 Wait States */
305#define MCF5206E_CSCR_WS12 (0x3000) /* 12 Wait States */
306#define MCF5206E_CSCR_WS13 (0x3400) /* 13 Wait States */
307#define MCF5206E_CSCR_WS14 (0x3800) /* 14 Wait States */
308#define MCF5206E_CSCR_WS15 (0x3C00) /* 15 Wait States */
309#define MCF5206E_CSCR_BRST (0x0200) /* Burst Enable */
310#define MCF5206E_CSCR_AA (0x0100) /* Coldfire Core Auto Acknowledge
311 Enable */
312#define MCF5206E_CSCR_PS (0x00C0) /* Port Size */
313#define MCF5206E_CSCR_PS_S (6)
314#define MCF5206E_CSCR_PS_32 (0x0000) /* Port Size = 32 bits */
315#define MCF5206E_CSCR_PS_8 (0x0040) /* Port Size = 8 bits */
316#define MCF5206E_CSCR_PS_16 (0x0080) /* Port Size = 16 bits */
317#define MCF5206E_CSCR_EMAA (0x0020) /* External Master Automatic Acknowledge
318 Enable */
319#define MCF5206E_CSCR_ASET (0x0010) /* Address Setup Enable */
320#define MCF5206E_CSCR_WRAH (0x0008) /* Write Address Hold Enable */
321#define MCF5206E_CSCR_RDAH (0x0004) /* Read Address Hold Enable */
322#define MCF5206E_CSCR_WR (0x0002) /* Write Enable */
323#define MCF5206E_CSCR_RD (0x0001) /* Read Enable */
324
325/* Default Memory Control Register */
326#define MCF5206E_DMCR(mbar) MCF5206E_REG16(mbar, 0x0C6)
327
328/*** Parallel Port (GPIO) Module -- MCF5206e User's Manual, Chapter 10 ***/
329
330/* Port A Data Direction Register */
331#define MCF5206E_PPDDR(mbar) MCF5206E_REG8(mbar,0x1C5)
332
333/* Port A Data Register */
334#define MCF5206E_PPDAT(mbar) MCF5206E_REG8(mbar,0x1C9)
335
336#define MCF5206E_PP_DAT0 (0x01)
337#define MCF5206E_PP_DAT1 (0x02)
338#define MCF5206E_PP_DAT2 (0x04)
339#define MCF5206E_PP_DAT3 (0x08)
340#define MCF5206E_PP_DAT4 (0x10)
341#define MCF5206E_PP_DAT5 (0x20)
342#define MCF5206E_PP_DAT6 (0x40)
343#define MCF5206E_PP_DAT7 (0x80)
344
345/*** DRAM Controller -- MCF5206e User's Manual, Chapter 11 ***/
346
347/* DRAM Controller Refresh Register */
348#define MCF5206E_DCRR(mbar) MCF5206E_REG16(mbar,0x046)
349
350/* DRAM Controller Timing Register */
351#define MCF5206E_DCTR(mbar) MCF5206E_REG16(mbar,0x04A)
352#define MCF5206E_DCTR_DAEM (0x8000) /* Drive Multiplexed Address During
353 External Master DRAM Transfers */
354#define MCF5206E_DCTR_EDO (0x4000) /* Extended Data-Out Enable */
355#define MCF5206E_DCTR_RCD (0x1000) /* RAS-to-CAS Delay Time */
356#define MCF5206E_DCTR_RSH (0x0600) /* RAS Hold Time */
357#define MCF5206E_DCTR_RSH_0 (0x0000) /* See User's Manual for details */
358#define MCF5206E_DCTR_RSH_1 (0x0200)
359#define MCF5206E_DCTR_RSH_2 (0x0400)
360#define MCF5206E_DCTR_RP (0x0060) /* RAS Precharge Time */
361#define MCF5206E_DCTR_RP_15 (0x0000) /* RAS Precharges for 1.5 system clks */
362#define MCF5206E_DCTR_RP_25 (0x0020) /* RAS Precharges for 2.5 system clks */
363#define MCF5206E_DCTR_RP_35 (0x0040) /* RAS Precharges for 3.5 system clks */
364#define MCF5206E_DCTR_CAS (0x0008) /* Column Address Strobe Time */
365#define MCF5206E_DCTR_CP (0x0002) /* CAS Precharge Time */
366#define MCF5206E_DCTR_CSR (0x0001) /* CAS Setup Time for CAS before RAS
367 refresh */
368
369/* DRAM Controller Address Registers */
370#define MCF5206E_DCAR(mbar,bank) MCF5206E_REG16(mbar,0x4C + ((bank) * 12))
371
372/* DRAM Controller Mask Registers */
373#define MCF5206E_DCMR(mbar,bank) MCF5206E_REG32(mbar,0x50 + ((bank) * 12))
374#define MCF5206E_DCMR_BAM (0xffff0000) /* Base Address Mask */
375#define MCF5206E_DCMR_BAM_S (16)
376#define MCF5206E_DCMR_MASK_256M (0x0FFE0000)
377#define MCF5206E_DCMR_MASK_128M (0x07FE0000)
378#define MCF5206E_DCMR_MASK_64M (0x03FE0000)
379#define MCF5206E_DCMR_MASK_32M (0x01FE0000)
380#define MCF5206E_DCMR_MASK_16M (0x00FE0000)
381#define MCF5206E_DCMR_MASK_8M (0x007E0000)
382#define MCF5206E_DCMR_MASK_4M (0x003E0000)
383#define MCF5206E_DCMR_MASK_2M (0x001E0000)
384#define MCF5206E_DCMR_MASK_1M (0x000E0000)
385#define MCF5206E_DCMR_MASK_1024K (0x000E0000)
386#define MCF5206E_DCMR_MASK_512K (0x00060000)
387#define MCF5206E_DCMR_MASK_256K (0x00020000)
388#define MCF5206E_DCMR_MASK_128K (0x00000000)
389#define MCF5206E_DCMR_SC (0x00000010) /* Supervisor Code Space Mask */
390#define MCF5206E_DCMR_SD (0x00000008) /* Supervisor Data Space Mask */
391#define MCF5206E_DCMR_UC (0x00000004) /* User Code Space Mask */
392#define MCF5206E_DCMR_UD (0x00000002) /* User Data Space Mask */
393
394/* DRAM Controller Control Register */
395#define MCF5206E_DCCR(mbar,bank) MCF5206E_REG8(mbar, 0x57 + ((bank) * 12))
396#define MCF5206E_DCCR_PS (0xC0) /* Port Size */
397#define MCF5206E_DCCR_PS_32 (0x00) /* 32 bit Port Size */
398#define MCF5206E_DCCR_PS_8 (0x40) /* 8 bit Port Size */
399#define MCF5206E_DCCR_PS_16 (0x80) /* 16 bit Port Size */
400#define MCF5206E_DCCR_BPS (0x30) /* Bank Page Size */
401#define MCF5206E_DCCR_BPS_512 (0x00) /* 512 Byte Page Size */
402#define MCF5206E_DCCR_BPS_1K (0x10) /* 1 KByte Page Size */
403#define MCF5206E_DCCR_BPS_2K (0x20) /* 2 KByte Page Size */
404#define MCF5206E_DCCR_PM (0x0C) /* Page Mode Select */
405#define MCF5206E_DCCR_PM_NORMAL (0x00) /* Normal Mode */
406#define MCF5206E_DCCR_PM_BURSTP (0x04) /* Burst Page Mode */
407#define MCF5206E_DCCR_PM_FASTP (0x0C) /* Fast Page Mode */
408#define MCF5206E_DCCR_WR (0x02) /* Write Enable */
409#define MCF5206E_DCCR_RD (0x01) /* Read Enable */
410
411/*** UART Module -- MCF5206e User's Manual, Chapter 12 ***/
412
413#define MCF5206E_UART_CHANNELS (2)
414/* UART Mode Register */
415#define MCF5206E_UMR(mbar,n) MCF5206E_REG8(mbar,0x140 + (((n)-1) * 0x40))
416#define MCF5206E_UMR1_RXRTS (0x80) /* Receiver Request-to-Send
417 Control */
418#define MCF5206E_UMR1_RXIRQ (0x40) /* Receiver Interrupt Select */
419#define MCF5206E_UMR1_ERR (0x20) /* Error Mode */
420#define MCF5206E_UMR1_PM (0x1C) /* Parity Mode, Parity Type */
421#define MCF5206E_UMR1_PM_EVEN (0x00) /* Even Parity */
422#define MCF5206E_UMR1_PM_ODD (0x04) /* Odd Parity */
423#define MCF5206E_UMR1_PM_FORCE_LOW (0x08) /* Force parity low */
424#define MCF5206E_UMR1_PM_FORCE_HIGH (0x0C) /* Force parity high */
425#define MCF5206E_UMR1_PM_NO_PARITY (0x10) /* No Parity */
426#define MCF5206E_UMR1_PM_MULTI_DATA (0x18) /* Multidrop mode - data char */
427#define MCF5206E_UMR1_PM_MULTI_ADDR (0x1C) /* Multidrop mode - addr char */
428#define MCF5206E_UMR1_BC (0x03) /* Bits per Character */
429#define MCF5206E_UMR1_BC_5 (0x00) /* 5 bits per character */
430#define MCF5206E_UMR1_BC_6 (0x01) /* 6 bits per character */
431#define MCF5206E_UMR1_BC_7 (0x02) /* 7 bits per character */
432#define MCF5206E_UMR1_BC_8 (0x03) /* 8 bits per character */
433
434#define MCF5206E_UMR2_CM (0xC0) /* Channel Mode */
435#define MCF5206E_UMR2_CM_NORMAL (0x00) /* Normal Mode */
436#define MCF5206E_UMR2_CM_AUTO_ECHO (0x40) /* Automatic Echo Mode */
437#define MCF5206E_UMR2_CM_LOCAL_LOOP (0x80) /* Local Loopback Mode */
438#define MCF5206E_UMR2_CM_REMOTE_LOOP (0xC0) /* Remote Loopback Modde */
439#define MCF5206E_UMR2_TXRTS (0x20) /* Transmitter Ready-to-Send op */
440#define MCF5206E_UMR2_TXCTS (0x10) /* Transmitter Clear-to-Send op */
441#define MCF5206E_UMR2_SB (0x0F) /* Stop Bit Length */
442#define MCF5206E_UMR2_SB_1 (0x07) /* 1 Stop Bit for 6-8 bits char */
443#define MCF5206E_UMR2_SB_15 (0x08) /* 1.5 Stop Bits for 6-8 bits chr*/
444#define MCF5206E_UMR2_SB_2 (0x0F) /* 2 Stop Bits for 6-8 bits char */
445#define MCF5206E_UMR2_SB5_1 (0x00) /* 1 Stop Bits for 5 bit char */
446#define MCF5206E_UMR2_SB5_15 (0x07) /* 1.5 Stop Bits for 5 bit char */
447#define MCF5206E_UMR2_SB5_2 (0x0F) /* 2 Stop Bits for 5 bit char */
448
449/* UART Status Register (read only) */
450#define MCF5206E_USR(mbar,n) MCF5206E_REG8(mbar,0x144 + (((n)-1) * 0x40))
451#define MCF5206E_USR_RB (0x80) /* Received Break */
452#define MCF5206E_USR_FE (0x40) /* Framing Error */
453#define MCF5206E_USR_PE (0x20) /* Parity Error */
454#define MCF5206E_USR_OE (0x10) /* Overrun Error */
455#define MCF5206E_USR_TXEMP (0x08) /* Transmitter Empty */
456#define MCF5206E_USR_TXRDY (0x04) /* Transmitter Ready */
457#define MCF5206E_USR_FFULL (0x02) /* FIFO Full */
458#define MCF5206E_USR_RXRDY (0x01) /* Receiver Ready */
459
460/* UART Clock Select Register (write only) */
461#define MCF5206E_UCSR(mbar,n) MCF5206E_REG8(mbar,0x144 + (((n)-1) * 0x40))
462#define MCF5206E_UCSR_RCS (0xF0) /* Receiver Clock Select */
463#define MCF5206E_UCSR_RCS_TIMER (0xD0) /* Timer */
464#define MCF5206E_UCSR_RCS_EXT16 (0xE0) /* External clk x16 */
465#define MCF5206E_UCSR_RCS_EXT (0xF0) /* External clk x1 */
466#define MCF5206E_UCSR_TCS (0x0F) /* Transmitter Clock Select */
467#define MCF5206E_UCSR_TCS_TIMER (0x0D) /* Timer */
468#define MCF5206E_UCSR_TCS_EXT16 (0x0E) /* External clk x16 */
469#define MCF5206E_UCSR_TCS_EXT (0x0F) /* External clk x1 */
470
471/* UART Command Register (write only) */
472#define MCF5206E_UCR(mbar,n) MCF5206E_REG8(mbar,0x148 + (((n)-1) * 0x40))
473#define MCF5206E_UCR_MISC (0x70) /* Miscellaneous Commands: */
474#define MCF5206E_UCR_MISC_NOP (0x00) /* No Command */
475#define MCF5206E_UCR_MISC_RESET_MR (0x10) /* Reset Mode Register Ptr */
476#define MCF5206E_UCR_MISC_RESET_RX (0x20) /* Reset Receiver */
477#define MCF5206E_UCR_MISC_RESET_TX (0x30) /* Reset Transmitter */
478#define MCF5206E_UCR_MISC_RESET_ERR (0x40) /* Reset Error Status */
479#define MCF5206E_UCR_MISC_RESET_BRK (0x50) /* Reset Break-Change Interrupt */
480#define MCF5206E_UCR_MISC_START_BRK (0x60) /* Start Break */
481#define MCF5206E_UCR_MISC_STOP_BRK (0x70) /* Stop Break */
482#define MCF5206E_UCR_TC (0x0C) /* Transmitter Commands: */
483#define MCF5206E_UCR_TC_NOP (0x00) /* No Action Taken */
484#define MCF5206E_UCR_TC_ENABLE (0x04) /* Transmitter Enable */
485#define MCF5206E_UCR_TC_DISABLE (0x08) /* Transmitter Disable */
486#define MCF5206E_UCR_RC (0x03) /* Receiver Commands: */
487#define MCF5206E_UCR_RC_NOP (0x00) /* No Action Taken */
488#define MCF5206E_UCR_RC_ENABLE (0x01) /* Receiver Enable */
489#define MCF5206E_UCR_RC_DISABLE (0x02) /* Receiver Disable */
490
491/* UART Receive Buffer (read only) */
492#define MCF5206E_URB(mbar,n) MCF5206E_REG8(mbar,0x14C + (((n)-1) * 0x40))
493
494/* UART Transmit Buffer (write only) */
495#define MCF5206E_UTB(mbar,n) MCF5206E_REG8(mbar,0x14C + (((n)-1) * 0x40))
496
497/* UART Input Port Change Register (read only) */
498#define MCF5206E_UIPCR(mbar,n) MCF5206E_REG8(mbar,0x150 + (((n)-1) * 0x40))
499#define MCF5206E_UIPCR_COS (0x10) /* Change of State at CTS input */
500#define MCF5206E_UIPCR_CTS (0x01) /* Current State of CTS */
501
502/* UART Auxiliary Control Register (write only) */
503#define MCF5206E_UACR(mbar,n) MCF5206E_REG8(mbar,0x150 + (((n)-1) * 0x40))
504#define MCF5206E_UACR_IEC (0x01) /* Input Enable Control - generate interrupt
505 on CTS change */
506
507/* UART Interrupt Status Register (read only) */
508#define MCF5206E_UISR(mbar,n) MCF5206E_REG8(mbar,0x154 + (((n)-1) * 0x40))
509#define MCF5206E_UISR_COS (0x80) /* Change of State has occured at CTS */
510#define MCF5206E_UISR_DB (0x04) /* Delta Break */
511#define MCF5206E_UISR_RXRDY (0x02) /* Receiver Ready or FIFO Full */
512#define MCF5206E_UISR_TXRDY (0x01) /* Transmitter Ready */
513
514/* UART Interrupt Mask Register (write only) */
515#define MCF5206E_UIMR(mbar,n) MCF5206E_REG8(mbar,0x154 + (((n)-1) * 0x40))
516#define MCF5206E_UIMR_COS (0x80) /* Change of State interrupt enable */
517#define MCF5206E_UIMR_DB (0x04) /* Delta Break interrupt enable */
518#define MCF5206E_UIMR_FFULL (0x02) /* FIFO Full interrupt enable */
519#define MCF5206E_UIMR_TXRDY (0x01) /* Transmitter Ready Interrupt enable */
520
521/* UART Baud Rate Generator Prescale MSB Register */
522#define MCF5206E_UBG1(mbar,n) MCF5206E_REG8(mbar,0x158 + (((n)-1) * 0x40))
523
524/* UART Baud Rate Generator Prescale LSB Register */
525#define MCF5206E_UBG2(mbar,n) MCF5206E_REG8(mbar,0x15C + (((n)-1) * 0x40))
526
527/* UART Interrupt Vector Register */
528#define MCF5206E_UIVR(mbar,n) MCF5206E_REG8(mbar,0x170 + (((n)-1) * 0x40))
529
530/* UART Input Port Register (read only) */
531#define MCF5206E_UIP(mbar,n) MCF5206E_REG8(mbar,0x174 + (((n)-1) * 0x40))
532#define MCF5206E_UIP_CTS (0x01) /* Current state of CTS input */
533
534/* UART Output Port Bit Set Command (address-triggered command, write) */
535#define MCF5206E_UOP1(mbar,n) MCF5206E_REG8(mbar,0x178 + (((n)-1) * 0x40))
536
537/* UART Output Port Bit Reset Command (address-triggered command, write */
538#define MCF5206E_UOP0(mbar,n) MCF5206E_REG8(mbar,0x17C + (((n)-1) * 0x40))
539
540/*** M-BUS (I2C) Module -- MCF5206e User's Manual, Chapter 13 ***/
541
542/* M-Bus Address Register */
543#define MCF5206E_MADR(mbar) MCF5206E_REG8(mbar, 0x1E0)
544
545/* M-Bus Frequency Divider Register */
546#define MCF5206E_MFDR(mbar) MCF5206E_REG8(mbar, 0x1E4)
547
548/* M-Bus Control Register */
549#define MCF5206E_MBCR(mbar) MCF5206E_REG8(mbar, 0x1E8)
550#define MCF5206E_MBCR_MEN (0x80) /* M-Bus Enable */
551#define MCF5206E_MBCR_MIEN (0x40) /* M-Bus Interrupt Enable */
552#define MCF5206E_MBCR_MSTA (0x20) /* Master Mode Selection */
553#define MCF5206E_MBCR_MTX (0x10) /* Transmit Mode Selection */
554#define MCF5206E_MBCR_TXAK (0x08) /* Transmit Acknowledge Enable */
555#define MCF5206E_MBCR_RSTA (0x04) /* Repeat Start */
556
557/* M-Bus Status Register */
558#define MCF5206E_MBSR(mbar) MCF5206E_REG8(mbar, 0x1EC)
559#define MCF5206E_MBSR_MCF (0x80) /* Data Transferring Bit */
560#define MCF5206E_MBSR_MAAS (0x40) /* Addressed as a Slave Bit */
561#define MCF5206E_MBSR_MBB (0x20) /* Bus Busy Bit */
562#define MCF5206E_MBSR_MAL (0x10) /* Arbitration Lost */
563#define MCF5206E_MBSR_SRW (0x04) /* Slave Read/Write */
564#define MCF5206E_MBSR_MIF (0x02) /* MBus Interrupt pending */
565#define MCF5206E_MBSR_RXAK (0x01) /* Received Acknowledge */
566
567/* M-Bus Data I/O Register */
568#define MCF5206E_MBDR(mbar) MCF5206E_REG8(mbar, 0x1F0)
569
570/*** Timer Module -- MCF5206e User's Manual, Chapter 14 ***/
571
572/* Timer Mode Register */
573#define MCF5206E_TMR(mbar,n) MCF5206E_REG16(mbar, 0x100 + (((n)-1)*0x20))
574#define MCF5206E_TMR_PS (0xFF00) /* Prescaler Value */
575#define MCF5206E_TMR_PS_S (8)
576#define MCF5206E_TMR_CE (0x00C0) /* Capture Edge and Enable
577 Interrupt */
578#define MCF5206E_TMR_CE_ANY (0x00C0) /* Capture on any edge */
579#define MCF5206E_TMR_CE_FALL (0x0080) /* Capture on falling edge only */
580#define MCF5206E_TMR_CE_RISE (0x0040) /* Capture on rising edge only */
581#define MCF5206E_TMR_CE_NONE (0x0000) /* Disable Interrupt on capture
582 event */
583#define MCF5206E_TMR_OM (0x0020) /* Output Mode - Toggle output */
584#define MCF5206E_TMR_ORI (0x0010) /* Output Reference Interrupt
585 Enable */
586#define MCF5206E_TMR_FRR (0x0008) /* Free Run/Restart */
587#define MCF5206E_TMR_ICLK (0x0006) /* Input Clock Source */
588#define MCF5206E_TMR_ICLK_TIN (0x0006) /* TIN pin (falling edge) */
589#define MCF5206E_TMR_ICLK_DIV16 (0x0004) /* Master system clock divided
590 by 16 */
591#define MCF5206E_TMR_ICLK_MSCLK (0x0002) /* Master System Clock */
592#define MCF5206E_TMR_ICLK_STOP (0x0000) /* Stops counter */
593#define MCF5206E_TMR_RST (0x0001) /* Reset/Enable Timer */
594
595/* Timer Reference Register */
596#define MCF5206E_TRR(mbar,n) MCF5206E_REG16(mbar, 0x104 + (((n)-1)*0x20))
597
598/* Timer Capture Register */
599#define MCF5206E_TCR(mbar,n) MCF5206E_REG16(mbar, 0x108 + (((n)-1)*0x20))
600
601/* Timer Counter Register */
602#define MCF5206E_TCN(mbar,n) MCF5206E_REG16(mbar, 0x10C + (((n)-1)*0x20))
603
604/* Timer Event Register */
605#define MCF5206E_TER(mbar,n) MCF5206E_REG8(mbar, 0x111 + (((n)-1)*0x20))
606#define MCF5206E_TER_REF (0x02) /* Output Reference Event */
607#define MCF5206E_TER_CAP (0x01) /* Capture Event */
608
609
610
611#endif
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