RTEMS
7.0-rc1
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bsps
powerpc
gen5200
nvram
m93cxx.h
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/*
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* RTEMS generic MPC5200 BSP
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*
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* This file contains definitions for the M93Cxx EEPROM devices.
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*
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* M93C46 is a serial microwire EEPROM which contains
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* 1Kbit (128 bytes/64 words) of non-volatile memory.
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* The device can be configured for byte- or word-
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* access. The driver provides a file-like interface
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* to this memory.
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*
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* MPC5x00 PIN settings:
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*
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* PSC3_6 (output) -> MC93C46 serial data in (D)
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* PSC3_7 (input) -> MC93C46 serial data out (Q)
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* PSC3_8 (output) -> MC93C46 chip select input (S)
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* PSC3_9 (output) -> MC93C46 serial clock (C)
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*/
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/*
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* Copyright (C) 2005 embedded brains GmbH & Co. KG
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* Copyright (C) 2003 IPR Engineering
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __M93CXX_H__
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#define __M93CXX_H__
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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static
void
m93cxx_enable_write(
void
);
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static
void
m93cxx_disable_write(
void
);
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static
void
m93cxx_write_byte(uint32_t, uint8_t);
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static
uint8_t m93cxx_read_byte(uint32_t);
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void
wait_usec(
unsigned
long
);
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#define M93CXX_MODE_WORD
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/*#define M93C46_MODE_BYTE*/
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#define M93C46
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#define M93C46_NVRAM_SIZE 128
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#define GPIO_PSC3_6 (1 << 12)
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#define GPIO_PSC3_7 (1 << 13)
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#define GPIO_PSC3_8 (1 << 26)
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#define GPIO_PSC3_9 (1 << 26)
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#define START_BIT 0x1
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#define EWDS_OPCODE 0x0
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#define WRAL_OPCODE 0x1
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#define ERAL_OPCODE 0x2
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#define EWEN_OPCODE 0x3
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#define WRITE_OPCODE 0x4
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#define READ_OPCODE 0x8
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#define ERASE_OPCODE 0xC
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#define WAIT(i) wait_usec(i)
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#define ENABLE_CHIP_SELECT mpc5200.gpiosido |= GPIO_PSC3_8
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#define DISABLE_CHIP_SELECT mpc5200.gpiosido &= ~GPIO_PSC3_8
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#define SET_DATA_BIT_HIGH mpc5200.gpiosdo |= GPIO_PSC3_6
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#define SET_DATA_BIT_LOW mpc5200.gpiosdo &= ~GPIO_PSC3_6
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#ifdef M93CXX_MODE_BYTE
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#define GET_DATA_BYTE_SHIFT(val) ((val) |= ((mpc5200.gpiosdi & GPIO_PSC3_7) >> 13)); \
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((val) <<= 1)
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#define SET_DATA_BYTE_SHIFT(val) (((val) & 0x80) ? (mpc5200.gpiosdo |= GPIO_PSC3_6) : (mpc5200.gpiosdo &= ~GPIO_PSC3_6)); \
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((val) <<= 1)
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#else
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#define GET_DATA_WORD_SHIFT(val) ((val) |= ((mpc5200.gpiosdi & GPIO_PSC3_7) >> 13)); \
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((val) <<= 1)
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#define SET_DATA_WORD_SHIFT(val) (((val) & 0x8000) ? (mpc5200.gpiosdo |= GPIO_PSC3_6) : (mpc5200.gpiosdo &= ~GPIO_PSC3_6)); \
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((val) <<= 1)
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#endif
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#define MASK_HEAD_SHIFT(head) ((((head) & 0x80000000) >> 31) ? (mpc5200.gpiosdo |= GPIO_PSC3_6) : (mpc5200.gpiosdo &= ~GPIO_PSC3_6)); \
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((head) <<= 1)
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#define DO_CLOCK_CYCLE mpc5200.gpiowdo |= GPIO_PSC3_9; \
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WAIT(1000); \
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mpc5200.gpiowdo &= ~GPIO_PSC3_9
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#define CHECK_WRITE_BUSY while(!(mpc5200.gpiosdi & GPIO_PSC3_7))
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#ifdef M93CXX_MODE_BYTE
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#ifdef M93C46
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#define M93C46_EWDS ((START_BIT << 31) | (EWDS_OPCODE << 27))
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#define M93C46_WRAL ((START_BIT << 31) | (WRAL_OPCODE << 27))
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#define M93C46_ERAL ((START_BIT << 31) | (ERAL_OPCODE << 27))
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#define M93C46_EWEN ((START_BIT << 31) | (EWEN_OPCODE << 27))
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#define M93C46_READ(addr) ((START_BIT << 31) | (READ_OPCODE << 27) | ((addr) << 22))
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#define M93C46_WRITE(addr) ((START_BIT << 31) | (WRITE_OPCODE << 27) | ((addr) << 22))
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#define M93C46_ERASE(addr) ((START_BIT << 31) | (ERASE_OPCODE << 27) | ((addr) << 22))
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#define M93C46_CLOCK_CYCLES 10
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#endif
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#else
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#ifdef M93C46
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#define M93C46_EWDS ((START_BIT << 31) | (EWDS_OPCODE << 27))
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#define M93C46_WRAL ((START_BIT << 31) | (WRAL_OPCODE << 27))
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#define M93C46_ERAL ((START_BIT << 31) | (ERAL_OPCODE << 27))
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#define M93C46_EWEN ((START_BIT << 31) | (EWEN_OPCODE << 27))
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#define M93C46_READ(addr) ((START_BIT << 31) | (READ_OPCODE << 27) | ((addr) << 23))
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#define M93C46_WRITE(addr) ((START_BIT << 31) | (WRITE_OPCODE << 27) | ((addr) << 23))
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#define M93C46_ERASE(addr) ((START_BIT << 31) | (ERASE_OPCODE << 27) | ((addr) << 23))
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#define M93C46_CLOCK_CYCLES 9
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#endif
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
/* __M93CXX_H__ */
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