RTEMS 7.0-rc1
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lpc32xx.h
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1
9/*
10 * Copyright (C) 2009, 2010 embedded brains GmbH & Co. KG
11 *
12 * The license and distribution terms for this file may be
13 * found in the file LICENSE in this distribution or at
14 * http:
15 */
16
17#ifndef LIBBSP_ARM_LPC32XX_LPC32XX_H
18#define LIBBSP_ARM_LPC32XX_LPC32XX_H
19
20#include <stdint.h>
21
22#include <bsp/utility.h>
23#include <bsp/lpc-timer.h>
24#include <bsp/lpc-dma.h>
25#include <bsp/lpc-i2s.h>
26#include <bsp/lpc-emc.h>
27
44#define LPC32XX_BASE_ADC 0x40048000
45#define LPC32XX_BASE_SYSCON 0x40004000
46#define LPC32XX_BASE_DEBUG_CTRL 0x40040000
47#define LPC32XX_BASE_DMA 0x31000000
48#define LPC32XX_BASE_EMC 0x31080000
49#define LPC32XX_BASE_EMC_CS_0 0xe0000000
50#define LPC32XX_BASE_EMC_CS_1 0xe1000000
51#define LPC32XX_BASE_EMC_CS_2 0xe2000000
52#define LPC32XX_BASE_EMC_CS_3 0xe3000000
53#define LPC32XX_BASE_EMC_DYCS_0 0x80000000
54#define LPC32XX_BASE_EMC_DYCS_1 0xa0000000
55#define LPC32XX_BASE_ETB_CFG 0x310c0000
56#define LPC32XX_BASE_ETB_DATA 0x310e0000
57#define LPC32XX_BASE_ETHERNET 0x31060000
58#define LPC32XX_BASE_GPIO 0x40028000
59#define LPC32XX_BASE_I2C_1 0x400a0000
60#define LPC32XX_BASE_I2C_2 0x400a8000
61#define LPC32XX_BASE_I2S_0 0x20094000
62#define LPC32XX_BASE_I2S_1 0x2009c000
63#define LPC32XX_BASE_IRAM 0x08000000
64#define LPC32XX_BASE_IROM 0x0c000000
65#define LPC32XX_BASE_KEYSCAN 0x40050000
66#define LPC32XX_BASE_LCD 0x31040000
67#define LPC32XX_BASE_MCPWM 0x400e8000
68#define LPC32XX_BASE_MIC 0x40008000
69#define LPC32XX_BASE_NAND_MLC 0x200a8000
70#define LPC32XX_BASE_NAND_SLC 0x20020000
71#define LPC32XX_BASE_PWM_1 0x4005c000
72#define LPC32XX_BASE_PWM_2 0x4005c004
73#define LPC32XX_BASE_PWM_3 0x4002c000
74#define LPC32XX_BASE_PWM_4 0x40030000
75#define LPC32XX_BASE_RTC 0x40024000
76#define LPC32XX_BASE_RTC_RAM 0x40024080
77#define LPC32XX_BASE_SDCARD 0x20098000
78#define LPC32XX_BASE_SIC_1 0x4000c000
79#define LPC32XX_BASE_SIC_2 0x40010000
80#define LPC32XX_BASE_SPI_1 0x20088000
81#define LPC32XX_BASE_SPI_2 0x20090000
82#define LPC32XX_BASE_SSP_0 0x20084000
83#define LPC32XX_BASE_SSP_1 0x2008c000
84#define LPC32XX_BASE_TIMER_0 0x40044000
85#define LPC32XX_BASE_TIMER_1 0x4004c000
86#define LPC32XX_BASE_TIMER_2 0x40058000
87#define LPC32XX_BASE_TIMER_3 0x40060000
88#define LPC32XX_BASE_TIMER_5 0x4002c000
89#define LPC32XX_BASE_TIMER_6 0x40030000
90#define LPC32XX_BASE_TIMER_HS 0x40038000
91#define LPC32XX_BASE_TIMER_MS 0x40034000
92#define LPC32XX_BASE_UART_1 0x40014000
93#define LPC32XX_BASE_UART_2 0x40018000
94#define LPC32XX_BASE_UART_3 0x40080000
95#define LPC32XX_BASE_UART_4 0x40088000
96#define LPC32XX_BASE_UART_5 0x40090000
97#define LPC32XX_BASE_UART_6 0x40098000
98#define LPC32XX_BASE_UART_7 0x4001c000
99#define LPC32XX_BASE_USB 0x31020000
100#define LPC32XX_BASE_USB_OTG_I2C 0x31020300
101#define LPC32XX_BASE_WDT 0x4003c000
102
111#define LPC32XX_U3CLK (*(volatile uint32_t *) 0x400040d0)
112#define LPC32XX_U4CLK (*(volatile uint32_t *) 0x400040d4)
113#define LPC32XX_U5CLK (*(volatile uint32_t *) 0x400040d8)
114#define LPC32XX_U6CLK (*(volatile uint32_t *) 0x400040dc)
115#define LPC32XX_IRDACLK (*(volatile uint32_t *) 0x400040e0)
116#define LPC32XX_UART_CTRL (*(volatile uint32_t *) 0x40054000)
117#define LPC32XX_UART_CLKMODE (*(volatile uint32_t *) 0x40054004)
118#define LPC32XX_UART_LOOP (*(volatile uint32_t *) 0x40054008)
119#define LPC32XX_SW_INT (*(volatile uint32_t *) 0x400040a8)
120#define LPC32XX_MAC_CLK_CTRL (*(volatile uint32_t *) 0x40004090)
121#define LPC32XX_USB_DIV (*(volatile uint32_t *) 0x4000401c)
122#define LPC32XX_OTG_CLK_CTRL (*(volatile uint32_t *) 0x31020ff4)
123#define LPC32XX_OTG_CLK_STAT (*(volatile uint32_t *) 0x31020ff8)
124#define LPC32XX_OTG_STAT_CTRL (*(volatile uint32_t *) 0x31020110)
125#define LPC32XX_I2C_RX (*(volatile uint32_t *) 0x31020300)
126#define LPC32XX_I2C_TX (*(volatile uint32_t *) 0x31020300)
127#define LPC32XX_I2C_STS (*(volatile uint32_t *) 0x31020304)
128#define LPC32XX_I2C_CTL (*(volatile uint32_t *) 0x31020308)
129#define LPC32XX_I2C_CLKHI (*(volatile uint32_t *) 0x3102030c)
130#define LPC32XX_I2C_CLKLO (*(volatile uint32_t *) 0x31020310)
131#define LPC32XX_PWR_CTRL (*(volatile uint32_t *) 0x40004044)
132#define LPC32XX_OSC_CTRL (*(volatile uint32_t *) 0x4000404c)
133#define LPC32XX_SYSCLK_CTRL (*(volatile uint32_t *) 0x40004050)
134#define LPC32XX_PLL397_CTRL (*(volatile uint32_t *) 0x40004048)
135#define LPC32XX_HCLKPLL_CTRL (*(volatile uint32_t *) 0x40004058)
136#define LPC32XX_HCLKDIV_CTRL (*(volatile uint32_t *) 0x40004040)
137#define LPC32XX_TEST_CLK (*(volatile uint32_t *) 0x400040a4)
138#define LPC32XX_AUTOCLK_CTRL (*(volatile uint32_t *) 0x400040ec)
139#define LPC32XX_START_ER_PIN (*(volatile uint32_t *) 0x40004030)
140#define LPC32XX_START_ER_INT (*(volatile uint32_t *) 0x40004020)
141#define LPC32XX_P0_INTR_ER (*(volatile uint32_t *) 0x40004018)
142#define LPC32XX_START_SR_PIN (*(volatile uint32_t *) 0x40004038)
143#define LPC32XX_START_SR_INT (*(volatile uint32_t *) 0x40004028)
144#define LPC32XX_START_RSR_PIN (*(volatile uint32_t *) 0x40004034)
145#define LPC32XX_START_RSR_INT (*(volatile uint32_t *) 0x40004024)
146#define LPC32XX_START_APR_PIN (*(volatile uint32_t *) 0x4000403c)
147#define LPC32XX_START_APR_INT (*(volatile uint32_t *) 0x4000402c)
148#define LPC32XX_USB_CTRL (*(volatile uint32_t *) 0x40004064)
149#define LPC32XX_USBDIV_CTRL (*(volatile uint32_t *) 0x4000401c)
150#define LPC32XX_MS_CTRL (*(volatile uint32_t *) 0x40004080)
151#define LPC32XX_DMACLK_CTRL (*(volatile uint32_t *) 0x400040e8)
152#define LPC32XX_FLASHCLK_CTRL (*(volatile uint32_t *) 0x400040c8)
153#define LPC32XX_MACCLK_CTRL (*(volatile uint32_t *) 0x40004090)
154#define LPC32XX_LCDCLK_CTRL (*(volatile uint32_t *) 0x40004054)
155#define LPC32XX_I2S_CTRL (*(volatile uint32_t *) 0x4000407c)
156#define LPC32XX_SSP_CTRL (*(volatile uint32_t *) 0x40004078)
157#define LPC32XX_SPI_CTRL (*(volatile uint32_t *) 0x400040c4)
158#define LPC32XX_I2CCLK_CTRL (*(volatile uint32_t *) 0x400040ac)
159#define LPC32XX_TIMCLK_CTRL1 (*(volatile uint32_t *) 0x400040c0)
160#define LPC32XX_TIMCLK_CTRL (*(volatile uint32_t *) 0x400040bc)
161#define LPC32XX_ADCLK_CTRL (*(volatile uint32_t *) 0x400040b4)
162#define LPC32XX_ADCLK_CTRL1 (*(volatile uint32_t *) 0x40004060)
163#define LPC32XX_KEYCLK_CTRL (*(volatile uint32_t *) 0x400040b0)
164#define LPC32XX_PWMCLK_CTRL (*(volatile uint32_t *) 0x400040b8)
165#define LPC32XX_UARTCLK_CTRL (*(volatile uint32_t *) 0x400040e4)
166#define LPC32XX_POS0_IRAM_CTRL (*(volatile uint32_t *) 0x40004110)
167#define LPC32XX_POS1_IRAM_CTRL (*(volatile uint32_t *) 0x40004114)
168#define LPC32XX_SDRAMCLK_CTRL (*(volatile uint32_t *) 0x40004068)
169
178#define PWR_STOP BSP_BIT32(0)
179#define PWR_HIGHCORE_ALWAYS BSP_BIT32(1)
180#define PWR_NORMAL_RUN_MODE BSP_BIT32(2)
181#define PWR_SYSCLKEN_ALWAYS BSP_BIT32(3)
182#define PWR_SYSCLKEN_HIGH BSP_BIT32(4)
183#define PWR_HIGHCORE_HIGH BSP_BIT32(5)
184#define PWR_SDRAM_AUTO_REFRESH BSP_BIT32(7)
185#define PWR_UPDATE_EMCSREFREQ BSP_BIT32(8)
186#define PWR_EMCSREFREQ BSP_BIT32(9)
187#define PWR_HCLK_USES_PERIPH_CLK BSP_BIT32(10)
188
197#define HCLK_PLL_LOCK BSP_BIT32(0)
198#define HCLK_PLL_M(val) BSP_FLD32(val, 1, 8)
199#define HCLK_PLL_M_GET(reg) BSP_FLD32GET(reg, 1, 8)
200#define HCLK_PLL_N(val) BSP_FLD32(val, 9, 10)
201#define HCLK_PLL_N_GET(reg) BSP_FLD32GET(reg, 9, 10)
202#define HCLK_PLL_P(val) BSP_FLD32(val, 11, 12)
203#define HCLK_PLL_P_GET(reg) BSP_FLD32GET(reg, 11, 12)
204#define HCLK_PLL_FBD_FCLKOUT BSP_BIT32(13)
205#define HCLK_PLL_DIRECT BSP_BIT32(14)
206#define HCLK_PLL_BYPASS BSP_BIT32(15)
207#define HCLK_PLL_POWER BSP_BIT32(16)
208
217#define HCLK_DIV_HCLK(val) BSP_FLD32(val, 0, 1)
218#define HCLK_DIV_HCLK_GET(reg) BSP_FLD32GET(reg, 0, 1)
219#define HCLK_DIV_PERIPH_CLK(val) BSP_FLD32(val, 2, 6)
220#define HCLK_DIV_PERIPH_CLK_GET(reg) BSP_FLD32GET(reg, 2, 6)
221#define HCLK_DIV_DDRAM_CLK(val) BSP_FLD32(val, 7, 8)
222#define HCLK_DIV_DDRAM_CLK_GET(reg) BSP_FLD32GET(reg, 7, 8)
223
232#define TIMCLK_CTRL_WDT BSP_BIT32(0)
233#define TIMCLK_CTRL_HST BSP_BIT32(1)
234
237#define LPC32XX_FILL(a, b, s) uint8_t reserved_ ## b [b - a - sizeof(s)]
238#define LPC32XX_RESERVE(a, b) uint8_t reserved_ ## b [b - a]
239
240typedef struct {
241 uint32_t unused;
242} lpc32xx_nand_slc;
243
244typedef struct {
245 uint32_t unused;
246} lpc32xx_ssp;
247
248typedef struct {
249 uint32_t unused;
250} lpc32xx_spi;
251
252typedef struct {
253 uint32_t unused;
254} lpc32xx_sd_card;
255
256typedef struct {
257 uint32_t unused;
258} lpc32xx_usb;
259
260typedef struct {
261 uint32_t unused;
262} lpc32xx_lcd;
263
264typedef struct {
265 uint32_t unused;
266} lpc32xx_etb;
267
268typedef struct {
269 uint32_t unused;
270} lpc32xx_syscon;
271
272typedef struct {
273 uint32_t unused;
274} lpc32xx_uart_ctrl;
275
276typedef struct {
277 uint32_t unused;
278} lpc32xx_uart;
279
280typedef struct {
281 uint32_t unused;
282} lpc32xx_ms_timer;
283
284typedef struct {
285 uint32_t unused;
286} lpc32xx_hs_timer;
287
294#define WDTTIM_INT_MATCH_INT BSP_BIT32(0)
295
304#define WDTTIM_CTRL_COUNT_ENAB BSP_BIT32(0)
305#define WDTTIM_CTRL_RESET_COUNT BSP_BIT32(1)
306#define WDTTIM_CTRL_PAUSE_EN BSP_BIT32(2)
307
316#define WDTTIM_MCTRL_MR0_INT BSP_BIT32(0)
317#define WDTTIM_MCTRL_RESET_COUNT0 BSP_BIT32(1)
318#define WDTTIM_MCTRL_STOP_COUNT0 BSP_BIT32(2)
319#define WDTTIM_MCTRL_M_RES1 BSP_BIT32(3)
320#define WDTTIM_MCTRL_M_RES2 BSP_BIT32(4)
321#define WDTTIM_MCTRL_RESFRC1 BSP_BIT32(5)
322#define WDTTIM_MCTRL_RESFRC2 BSP_BIT32(6)
323
332#define WDTTIM_EMR_EXT_MATCH0 BSP_BIT32(0)
333#define WDTTIM_EMR_MATCH_CTRL(val) BSP_FLD32(val, 4, 5)
334#define WDTTIM_EMR_MATCH_CTRL_SET(reg, val) BSP_FLD32SET(reg, val, 4, 5)
335
344#define WDTTIM_RES_WDT BSP_BIT32(0)
345
348typedef struct {
349 uint32_t intr;
350 uint32_t ctrl;
351 uint32_t counter;
352 uint32_t mctrl;
353 uint32_t match0;
354 uint32_t emr;
355 uint32_t pulse;
356 uint32_t res;
357} lpc32xx_wdt;
358
359typedef struct {
360 uint32_t unused;
361} lpc32xx_debug;
362
363typedef struct {
364 uint32_t unused;
365} lpc32xx_adc;
366
367typedef struct {
368 uint32_t unused;
369} lpc32xx_keyscan;
370
371typedef struct {
372 uint32_t unused;
373} lpc32xx_pwm;
374
375typedef struct {
376 uint32_t unused;
377} lpc32xx_mcpwm;
378
379typedef struct {
380 uint32_t mac1;
381 uint32_t mac2;
382 uint32_t ipgt;
383 uint32_t ipgr;
384 uint32_t clrt;
385 uint32_t maxf;
386 uint32_t supp;
387 uint32_t test;
388 uint32_t mcfg;
389 uint32_t mcmd;
390 uint32_t madr;
391 uint32_t mwtd;
392 uint32_t mrdd;
393 uint32_t mind;
394 uint32_t reserved_0 [2];
395 uint32_t sa0;
396 uint32_t sa1;
397 uint32_t sa2;
398 uint32_t reserved_1 [45];
399 uint32_t command;
400 uint32_t status;
401 uint32_t rxdescriptor;
402 uint32_t rxstatus;
403 uint32_t rxdescriptornum;
404 uint32_t rxproduceindex;
405 uint32_t rxconsumeindex;
406 uint32_t txdescriptor;
407 uint32_t txstatus;
408 uint32_t txdescriptornum;
409 uint32_t txproduceindex;
410 uint32_t txconsumeindex;
411 uint32_t reserved_2 [10];
412 uint32_t tsv0;
413 uint32_t tsv1;
414 uint32_t rsv;
415 uint32_t reserved_3 [3];
416 uint32_t flowcontrolcnt;
417 uint32_t flowcontrolsts;
418 uint32_t reserved_4 [34];
419 uint32_t rxfilterctrl;
420 uint32_t rxfilterwolsts;
421 uint32_t rxfilterwolclr;
422 uint32_t reserved_5 [1];
423 uint32_t hashfilterl;
424 uint32_t hashfilterh;
425 uint32_t reserved_6 [882];
426 uint32_t intstatus;
427 uint32_t intenable;
428 uint32_t intclear;
429 uint32_t intset;
430 uint32_t reserved_7 [1];
431 uint32_t powerdown;
432} lpc32xx_eth;
433
434typedef struct {
435 uint32_t er;
436 uint32_t rsr;
437 uint32_t sr;
438 uint32_t apr;
439 uint32_t atr;
440 uint32_t itr;
441} lpc32xx_irq;
442
443typedef struct {
444 uint32_t p3_inp_state;
445 uint32_t p3_outp_set;
446 uint32_t p3_outp_clr;
447 uint32_t p3_outp_state;
448 uint32_t p2_dir_set;
449 uint32_t p2_dir_clr;
450 uint32_t p2_dir_state;
451 uint32_t p2_inp_state;
452 uint32_t p2_outp_set;
453 uint32_t p2_outp_clr;
454 uint32_t p2_mux_set;
455 uint32_t p2_mux_clr;
456 uint32_t p2_mux_state;
457 LPC32XX_RESERVE(0x034, 0x040);
458 uint32_t p0_inp_state;
459 uint32_t p0_outp_set;
460 uint32_t p0_outp_clr;
461 uint32_t p0_outp_state;
462 uint32_t p0_dir_set;
463 uint32_t p0_dir_clr;
464 uint32_t p0_dir_state;
465 LPC32XX_RESERVE(0x05c, 0x060);
466 uint32_t p1_inp_state;
467 uint32_t p1_outp_set;
468 uint32_t p1_outp_clr;
469 uint32_t p1_outp_state;
470 uint32_t p1_dir_set;
471 uint32_t p1_dir_clr;
472 uint32_t p1_dir_state;
473 LPC32XX_RESERVE(0x07c, 0x110);
474 uint32_t p3_mux_set;
475 uint32_t p3_mux_clr;
476 uint32_t p3_mux_state;
477 LPC32XX_RESERVE(0x11c, 0x120);
478 uint32_t p0_mux_set;
479 uint32_t p0_mux_clr;
480 uint32_t p0_mux_state;
481 LPC32XX_RESERVE(0x12c, 0x130);
482 uint32_t p1_mux_set;
483 uint32_t p1_mux_clr;
484 uint32_t p1_mux_state;
485} lpc32xx_gpio;
486
487typedef struct {
488 uint32_t rx_or_tx;
489 uint32_t stat;
490 uint32_t ctrl;
491 uint32_t clk_hi;
492 uint32_t clk_lo;
493 uint32_t adr;
494 uint32_t rxfl;
495 uint32_t txfl;
496 uint32_t rxb;
497 uint32_t txb;
498 uint32_t s_tx;
499 uint32_t s_txfl;
500} lpc32xx_i2c;
501
502typedef struct {
503 uint32_t ucount;
504 uint32_t dcount;
505 uint32_t match0;
506 uint32_t match1;
507 uint32_t ctrl;
508 uint32_t intstat;
509 uint32_t key;
510 uint32_t sram [32];
511} lpc32xx_rtc;
512
513typedef struct {
514 uint32_t control;
515 uint32_t status;
516 uint32_t timeout;
517 uint32_t reserved_0 [5];
518} lpc32xx_emc_ahb;
519
520typedef struct {
521 union {
522 uint32_t w32;
523 uint16_t w16;
524 uint8_t w8;
525 } buff;
526 uint32_t reserved_0 [8191];
527 union {
528 uint32_t w32;
529 uint16_t w16;
530 uint8_t w8;
531 } data;
532 uint32_t reserved_1 [8191];
533 uint32_t cmd;
534 uint32_t addr;
535 uint32_t ecc_enc;
536 uint32_t ecc_dec;
537 uint32_t ecc_auto_enc;
538 uint32_t ecc_auto_dec;
539 uint32_t rpr;
540 uint32_t wpr;
541 uint32_t rubp;
542 uint32_t robp;
543 uint32_t sw_wp_add_low;
544 uint32_t sw_wp_add_hig;
545 uint32_t icr;
546 uint32_t time;
547 uint32_t irq_mr;
548 uint32_t irq_sr;
549 uint32_t reserved_2;
550 uint32_t lock_pr;
551 uint32_t isr;
552 uint32_t ceh;
553} lpc32xx_nand_mlc;
554
555typedef struct {
556 lpc32xx_nand_slc nand_slc;
557 LPC32XX_FILL(0x20020000, 0x20084000, lpc32xx_nand_slc);
558 lpc32xx_ssp ssp_0;
559 LPC32XX_FILL(0x20084000, 0x20088000, lpc32xx_ssp);
560 lpc32xx_spi spi_1;
561 LPC32XX_FILL(0x20088000, 0x2008c000, lpc32xx_spi);
562 lpc32xx_ssp ssp_1;
563 LPC32XX_FILL(0x2008c000, 0x20090000, lpc32xx_ssp);
564 lpc32xx_spi spi_2;
565 LPC32XX_FILL(0x20090000, 0x20094000, lpc32xx_spi);
566 lpc_i2s i2s_0;
567 LPC32XX_FILL(0x20094000, 0x20098000, lpc_i2s);
568 lpc32xx_sd_card sd_card;
569 LPC32XX_FILL(0x20098000, 0x2009c000, lpc32xx_sd_card);
570 lpc_i2s i2s_1;
571 LPC32XX_FILL(0x2009c000, 0x200a8000, lpc_i2s);
572 lpc32xx_nand_mlc nand_mlc;
573 LPC32XX_FILL(0x200a8000, 0x31000000, lpc32xx_nand_mlc);
574 lpc_dma dma;
575 LPC32XX_FILL(0x31000000, 0x31020000, lpc_dma);
576 lpc32xx_usb usb;
577 LPC32XX_FILL(0x31020000, 0x31040000, lpc32xx_usb);
578 lpc32xx_lcd lcd;
579 LPC32XX_FILL(0x31040000, 0x31060000, lpc32xx_lcd);
580 lpc32xx_eth eth;
581 LPC32XX_FILL(0x31060000, 0x31080000, lpc32xx_eth);
582 lpc_emc emc;
583 LPC32XX_FILL(0x31080000, 0x31080400, lpc_emc);
584 lpc32xx_emc_ahb emc_ahb [5];
585 LPC32XX_FILL(0x31080400, 0x310c0000, lpc32xx_emc_ahb [5]);
586 lpc32xx_etb etb;
587 LPC32XX_FILL(0x310c0000, 0x40004000, lpc32xx_etb);
588 lpc32xx_syscon syscon;
589 LPC32XX_FILL(0x40004000, 0x40008000, lpc32xx_syscon);
590 lpc32xx_irq mic;
591 LPC32XX_FILL(0x40008000, 0x4000c000, lpc32xx_irq);
592 lpc32xx_irq sic_1;
593 LPC32XX_FILL(0x4000c000, 0x40010000, lpc32xx_irq);
594 lpc32xx_irq sic_2;
595 LPC32XX_FILL(0x40010000, 0x40014000, lpc32xx_irq);
596 lpc32xx_uart uart_1;
597 LPC32XX_FILL(0x40014000, 0x40018000, lpc32xx_uart);
598 lpc32xx_uart uart_2;
599 LPC32XX_FILL(0x40018000, 0x4001c000, lpc32xx_uart);
600 lpc32xx_uart uart_7;
601 LPC32XX_FILL(0x4001c000, 0x40024000, lpc32xx_uart);
602 lpc32xx_rtc rtc;
603 LPC32XX_FILL(0x40024000, 0x40028000, lpc32xx_rtc);
604 lpc32xx_gpio gpio;
605 LPC32XX_FILL(0x40028000, 0x4002c000, lpc32xx_gpio);
606 lpc_timer timer_4;
607 LPC32XX_FILL(0x4002c000, 0x40030000, lpc_timer);
608 lpc_timer timer_5;
609 LPC32XX_FILL(0x40030000, 0x40034000, lpc_timer);
610 lpc32xx_ms_timer ms_timer;
611 LPC32XX_FILL(0x40034000, 0x40038000, lpc32xx_ms_timer);
612 lpc32xx_hs_timer hs_timer;
613 LPC32XX_FILL(0x40038000, 0x4003c000, lpc32xx_hs_timer);
614 lpc32xx_wdt wdt;
615 LPC32XX_FILL(0x4003c000, 0x40040000, lpc32xx_wdt);
616 lpc32xx_debug debug;
617 LPC32XX_FILL(0x40040000, 0x40044000, lpc32xx_debug);
618 lpc_timer timer_0;
619 LPC32XX_FILL(0x40044000, 0x40048000, lpc_timer);
620 lpc32xx_adc adc;
621 LPC32XX_FILL(0x40048000, 0x4004c000, lpc32xx_adc);
622 lpc_timer timer_1;
623 LPC32XX_FILL(0x4004c000, 0x40050000, lpc_timer);
624 lpc32xx_keyscan keyscan;
625 LPC32XX_FILL(0x40050000, 0x40054000, lpc32xx_keyscan);
626 lpc32xx_uart_ctrl uart_ctrl;
627 LPC32XX_FILL(0x40054000, 0x40058000, lpc32xx_uart_ctrl);
628 lpc_timer timer_2;
629 LPC32XX_FILL(0x40058000, 0x4005c000, lpc_timer);
630 lpc32xx_pwm pwm_1_and_pwm_2;
631 LPC32XX_FILL(0x4005c000, 0x40060000, lpc32xx_pwm);
632 lpc_timer timer3;
633 LPC32XX_FILL(0x40060000, 0x40080000, lpc_timer);
634 lpc32xx_uart uart_3;
635 LPC32XX_FILL(0x40080000, 0x40088000, lpc32xx_uart);
636 lpc32xx_uart uart_4;
637 LPC32XX_FILL(0x40088000, 0x40090000, lpc32xx_uart);
638 lpc32xx_uart uart_5;
639 LPC32XX_FILL(0x40090000, 0x40098000, lpc32xx_uart);
640 lpc32xx_uart uart_6;
641 LPC32XX_FILL(0x40098000, 0x400a0000, lpc32xx_uart);
642 lpc32xx_i2c i2c_1;
643 LPC32XX_FILL(0x400a0000, 0x400a8000, lpc32xx_i2c);
644 lpc32xx_i2c i2c_2;
645 LPC32XX_FILL(0x400a8000, 0x400e8000, lpc32xx_i2c);
646 lpc32xx_mcpwm mcpwm;
647} lpc32xx_registers;
648
649extern volatile lpc32xx_registers lpc32xx;
650
653#endif /* LIBBSP_ARM_LPC32XX_LPC32XX_H */
utility.h
This header file provides utility macros for BSPs.
lpc-dma.h
DMA support API.
lpc-emc.h
EMC support API.
lpc-i2s.h
I2S API.
lpc-timer.h
Timer API.
control
Definition: intercom.c:87
lcd
Definition: 8xx_immap.h:197
lpc32xx_adc
Definition: lpc32xx.h:363
lpc32xx_debug
Definition: lpc32xx.h:359
lpc32xx_emc_ahb
Definition: lpc32xx.h:513
lpc32xx_etb
Definition: lpc32xx.h:264
lpc32xx_eth
Definition: lpc32xx.h:379
lpc32xx_gpio
Definition: lpc32xx.h:443
lpc32xx_hs_timer
Definition: lpc32xx.h:284
lpc32xx_i2c
Definition: lpc32xx.h:487
lpc32xx_irq
Definition: lpc32xx.h:434
lpc32xx_keyscan
Definition: lpc32xx.h:367
lpc32xx_lcd
Definition: lpc32xx.h:260
lpc32xx_mcpwm
Definition: lpc32xx.h:375
lpc32xx_ms_timer
Definition: lpc32xx.h:280
lpc32xx_nand_mlc
Definition: lpc32xx.h:520
lpc32xx_nand_slc
Definition: lpc32xx.h:240
lpc32xx_pwm
Definition: lpc32xx.h:371
lpc32xx_registers
Definition: lpc32xx.h:555
lpc32xx_rtc
Definition: lpc32xx.h:502
lpc32xx_sd_card
Definition: lpc32xx.h:252
lpc32xx_spi
Definition: lpc32xx.h:248
lpc32xx_ssp
Definition: lpc32xx.h:244
lpc32xx_syscon
Definition: lpc32xx.h:268
lpc32xx_uart_ctrl
Definition: lpc32xx.h:272
lpc32xx_uart
Definition: lpc32xx.h:276
lpc32xx_usb
Definition: lpc32xx.h:256
lpc32xx_wdt
Definition: lpc32xx.h:348
lpc_dma
DMA control block.
Definition: lpc-dma.h:79
lpc_emc
Definition: lpc-emc.h:148
lpc_i2s
I2S control block.
Definition: lpc-i2s.h:59
lpc_timer
Timer control block.
Definition: lpc-timer.h:147
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