RTEMS 7.0-rc1
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lpc176x.h
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1/* SPDX-License-Identifier: GPL-2.0+-with-RTEMS-exception */
2
11/*
12 * Copyright (c) 2014 Taller Technologies.
13 *
14 * @author Boretto Martin (martin.boretto@tallertechnologies.com)
15 * @author Diaz Marcos (marcos.diaz@tallertechnologies.com)
16 * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com)
17 * @author Daniel Chicco (daniel.chicco@tallertechnologies.com)
18 *
19 * The license and distribution terms for this file may be
20 * found in the file LICENSE in this distribution or at
21 * http://www.rtems.org/license/LICENSE.
22 */
23
24#ifndef LIBBSP_ARM_LPC176X_H
25#define LIBBSP_ARM_LPC176X_H
26
27#include <bsp/lpc-i2s.h>
28
29#define LPC176X_PLL_CON_PLLE BSP_BIT32( 0 )
30#define LPC176X_PLL_CON_PLLC BSP_BIT32( 1 )
31#define LPC176X_PLL_SEL_MSEL( val ) BSP_FLD32( val, 0, 14 )
32#define LPC176X_PLL_SEL_MSEL_GET( reg ) BSP_FLD32GET( reg, 0, 14 )
33#define LPC176X_PLL_SEL_MSEL_SET( reg, val ) BSP_FLD32SET( reg, val, 0, 14 )
34#define LPC176X_PLL_SEL_PSEL( val ) BSP_FLD32( val, 16, 23 )
35#define LPC176X_PLL_SEL_PSEL_GET( reg ) BSP_FLD32GET( reg, 16, 23 )
36#define LPC176X_PLL_SEL_PSEL_SET( reg, val ) BSP_FLD32SET( reg, val, 16, 23 )
37#define LPC176X_PLL_STAT_PLLE BSP_BIT32( 24 )
38#define LPC176X_PLL_STAT_PLLC BSP_BIT32( 25 )
39#define LPC176X_PLL_STAT_PLOCK BSP_BIT32( 26 )
40
44typedef struct {
48 uint32_t con;
52 uint32_t cfg;
56 uint32_t stat;
60 uint32_t feed;
61} lpc176x_pll;
62
63#define LPC176X_SCB_BASE_ADDR 0x400FC000U
64#define LPC176X_SCB_FLASHCFG_FLASHTIM( val ) BSP_FLD32( val, 12, 15 )
65#define LPC176X_SCB_FLASHCFG_FLASHTIM_GET( reg ) BSP_FLD32GET( reg, 12, 15 )
66#define LPC176X_SCB_FLASHCFG_FLASHTIM_SET( reg, val ) BSP_FLD32SET( reg, val, \
67 12, 15 )
68#define LPC176X_SCB_MEMMAP_MAP BSP_BIT32( 0 )
69/* POWER MODE CONTROL REGISTER (PCON) */
70/* Power mode control bit 0 */
71#define LPC176X_SCB_PCON_PM0 BSP_BIT32( 0 )
72/* Power mode control bit 1 */
73#define LPC176X_SCB_PCON_PM1 BSP_BIT32( 1 )
74/* Brown-Out Reduced ower Down */
75#define LPC176X_SCB_PCON_BODRPM BSP_BIT32( 2 )
76/* Brown-Out Global Disable */
77#define LPC176X_SCB_PCON_BOGD BSP_BIT32( 3 )
78/* Brown-Out Reset Disable */
79#define LPC176X_SCB_PCON_BORD BSP_BIT32( 4 )
80/* Sleep Mode entry flag */
81#define LPC176X_SCB_PCON_SMFLAG BSP_BIT32( 8 )
82/* Deep Sleep entry flag */
83#define LPC176X_SCB_PCON_DSFLAG BSP_BIT32( 9 )
84/* Power-Down entry flag */
85#define LPC176X_SCB_PCON_PDFLAG BSP_BIT32( 10 )
86/* Deep Power-Down entry flag */
87#define LPC176X_SCB_PCON_DPDFLAG BSP_BIT32( 11 )
88/* POWER CONTROL for PERIPHERALS REGISTER (PCONP) */
89/* 0 - Reserved */
90/* Timer/Counter 0 power/clock control bit */
91#define LPC176X_SCB_PCONP_TIMER_0 BSP_BIT32( 1 )
92/* Timer/Counter 1 power/clock control bit */
93#define LPC176X_SCB_PCONP_TIMER_1 BSP_BIT32( 2 )
94/* UART 0 power/clock control bit */
95#define LPC176X_SCB_PCONP_UART_0 BSP_BIT32( 3 )
96/* UART 1 power/clock control bit */
97#define LPC176X_SCB_PCONP_UART_1 BSP_BIT32( 4 )
98/* 5 - Reserved */
99/* PWM 1 power/clock control bit */
100#define LPC176X_SCB_PCONP_PWM_0 BSP_BIT32( 6 )
101/* The I2C0 interface power/clock control bit */
102#define LPC176X_SCB_PCONP_I2C_0 BSP_BIT32( 7 )
103/* The SPI interface power/clock control bit */
104#define LPC176X_SCB_PCONP_SPI BSP_BIT32( 8 )
105/* The RTC power/clock control bit */
106#define LPC176X_SCB_PCONP_RTC BSP_BIT32( 9 )
107/* The SSP1 interface power/clock control bit */
108#define LPC176X_SCB_PCONP_SSP_1 BSP_BIT32( 10 )
109/* 11 - Reserved */
110/* A/D converter (ADC) power/clock control bit */
111#define LPC176X_SCB_PCONP_ADC BSP_BIT32( 12 )
112/* CAN Controller 1 power/clock control bit */
113#define LPC176X_SCB_PCONP_CAN_1 BSP_BIT32( 13 )
114/* CAN Controller 2 power/clock control bit */
115#define LPC176X_SCB_PCONP_CAN_2 BSP_BIT32( 14 )
116/* Power/clock control bit for IOCON, GPIO, and GPIO interrupts*/
117#define LPC176X_SCB_PCONP_GPIO BSP_BIT32( 15 )
118/* Repetitive Interrupt Timer power/clock control bit */
119#define LPC176X_SCB_PCONP_RIT BSP_BIT32( 16 )
120/* Motor Control PWM */
121#define LPC176X_SCB_PCONP_MCPWM BSP_BIT32( 17 )
122/* Quadrate Encoder Interface power/clock control bit */
123#define LPC176X_SCB_PCONP_QEI BSP_BIT32( 18 )
124/* The IC21 interface power/clock control bit */
125#define LPC176X_SCB_PCONP_I2C_1 BSP_BIT32( 19 )
126/* 20 - Reserved */
127/* The SSP0 interface power/clock control bit */
128#define LPC176X_SCB_PCONP_SSP_0 BSP_BIT32( 21 )
129/* Timer 2 power/clock control bit */
130#define LPC176X_SCB_PCONP_TIMER_2 BSP_BIT32( 22 )
131/* Timer 3 power/clock control bit */
132#define LPC176X_SCB_PCONP_TIMER_3 BSP_BIT32( 23 )
133/* UART 2 power/clock control bit */
134#define LPC176X_SCB_PCONP_UART_2 BSP_BIT32( 24 )
135/* UART 3 power/clock control bit */
136#define LPC176X_SCB_PCONP_UART_3 BSP_BIT32( 25 )
137/* I2C interface 2 power/clock control bit */
138#define LPC176X_SCB_PCONP_I2C_2 BSP_BIT32( 26 )
139/* I2S interface power/clock control bit */
140#define LPC176X_SCB_PCONP_I2S BSP_BIT32( 27 )
141/* 28 - Reserved */
142/* GPDMA function power/clock control bit */
143#define LPC176X_SCB_PCONP_GPDMA BSP_BIT32( 29 )
144/* Ethernet block power/clock control bit */
145#define LPC176X_SCB_PCONP_ENET BSP_BIT32( 30 )
146/* USB interface power/clock control bit */
147#define LPC176X_SCB_PCONP_USB BSP_BIT32( 31 )
148#define LPC176X_SCB_CCLKSEL_CCLKDIV( val ) BSP_FLD32( val, 0, 7 )
149#define LPC176X_SCB_CCLKSEL_CCLKDIV_GET( reg ) BSP_FLD32GET( reg, 0, 7 )
150#define LPC176X_SCB_CCLKSEL_CCLKDIV_SET( reg, val ) BSP_FLD32SET( reg, \
151 val, \
152 0, \
153 7 )
154#define LPC176X_SCB_CCLKSEL_CCLKSEL BSP_BIT32( 8 )
155#define LPC176X_SCB_USBCLKSEL_USBDIV( val ) BSP_FLD32( val, 0, 4 )
156#define LPC176X_SCB_USBCLKSEL_USBDIV_GET( reg ) BSP_FLD32GET( reg, 0, 4 )
157#define LPC176X_SCB_USBCLKSEL_USBDIV_SET( reg, val ) BSP_FLD32SET( reg, \
158 val, \
159 0, \
160 4 )
161#define LPC176X_SCB_USBCLKSEL_USBSEL( val ) BSP_FLD32( val, 8, 9 )
162#define LPC176X_SCB_USBCLKSEL_USBSEL_GET( reg ) BSP_FLD32GET( reg, 8, 9 )
163#define LPC176X_SCB_USBCLKSEL_USBSEL_SET( reg, val ) BSP_FLD32SET( reg, \
164 val, \
165 8, \
166 9 )
167#define LPC176X_SCB_CLKSRCSEL_CLKSRC BSP_BIT32( 0 )
168#define LPC176X_SCB_SCS_MCIPWR BSP_BIT32( 3 )
169#define LPC176X_SCB_SCS_OSC_RANGE_SEL BSP_BIT32( 4 )
170#define LPC176X_SCB_SCS_OSC_ENABLE BSP_BIT32( 5 )
171#define LPC176X_SCB_SCS_OSC_STATUS BSP_BIT32( 6 )
172#define LPC176X_SCB_PCLKSEL_PCLKDIV( val ) BSP_FLD32( val, 0, 4 )
173#define LPC176X_SCB_PCLKSEL_PCLKDIV_GET( reg ) BSP_FLD32GET( reg, 0, 4 )
174#define LPC176X_SCB_PCLKSEL_PCLKDIV_SET( reg, val ) BSP_FLD32SET( reg, \
175 val, \
176 0, \
177 4 )
178#define LPC176X_SCB_PBOOST_BOOST BSP_BIT32( 0 )
179#define LPC176X_SCB_CLKOUTCFG_CLKOUTSEL( val ) BSP_FLD32( val, 3, 0 )
180#define LPC176X_SCB_CLKOUTCFG_CLKOUTSEL_GET( reg ) BSP_FLD32GET( reg, 3, 0 )
181#define LPC176X_SCB_CLKOUTCFG_CLKOUTSEL_SET( reg, val ) BSP_FLD32SET( reg, \
182 val, 3, 0 )
183#define LPC176X_SCB_CLKOUTCFG_CLKOUTDIV( val ) BSP_FLD32( val, 7, 4 )
184#define LPC176X_SCB_CLKOUTCFG_CLKOUTDIV_GET( reg ) BSP_FLD32GET( reg, 7, 4 )
185#define LPC176X_SCB_CLKOUTCFG_CLKOUTDIV_SET( reg, val ) BSP_FLD32SET( reg, \
186 val, 7, 4 )
187#define LPC176X_SCB_CLKOUTCFG_CLKOUT_EN BSP_BIT32( 8 )
188#define LPC176X_SCB_CLKOUTCFG_CLKOUT_ACT BSP_BIT32( 9 )
189
193typedef struct {
197 uint32_t flashcfg;
198 uint32_t reserved_04[ 15 ];
202 uint32_t memmap;
203 uint32_t reserved_44[ 15 ];
207 lpc176x_pll pll_0;
208 uint32_t reserved_90[ 4 ];
212 lpc176x_pll pll_1;
213 uint32_t reserved_b0[ 4 ];
217 uint32_t pcon;
221 uint32_t pconp;
222 uint32_t reserved_c8[ 15 ];
227 uint32_t cclksel;
232 uint32_t usbclksel;
236 uint32_t clksrcsel;
237 uint32_t reserved_110[ 12 ];
241 uint32_t extint;
242 uint32_t reserved_144;
246 uint32_t extmode;
250 uint32_t extpolar;
251 uint32_t reserved_150[ 12 ];
255 uint32_t rsid;
256 uint32_t reserved_184[ 7 ];
260 uint32_t scs;
261 uint32_t reserved_1a4;
265 uint32_t pclksel[ 2 ];
269 uint32_t pboost;
270 uint32_t reserved_1b4[ 5 ];
274 uint32_t clkoutcfg;
278 uint32_t rstcon[ 2 ];
279 uint32_t reserved_1d4[ 4 ];
280} lpc176x_scb;
281
282#define LPC176X_BASE 0x00u
283#define LPC176X_SCB ( *(volatile lpc176x_scb *) ( LPC176X_SCB_BASE_ADDR ) )
284
285/* Fast I/O setup */
286#define LPC176X_FIO_BASE_ADDR 0x2009C000U
287#define LPC176X_FIO ( (volatile lpc176x_fio *) LPC176X_FIO_BASE_ADDR )
288
289#define FIO0DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x00U ) )
290#define FIO0MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x10U ) )
291#define FIO0PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x14U ) )
292#define FIO0SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x18U ) )
293#define FIO0CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x1CU ) )
294
295#define FIO1DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x20U ) )
296#define FIO1MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x30U ) )
297#define FIO1PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x34U ) )
298#define FIO1SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x38U ) )
299#define FIO1CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x3CU ) )
300
301#define FIO2DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x40U ) )
302#define FIO2MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x50U ) )
303#define FIO2PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x54U ) )
304#define FIO2SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x58U ) )
305#define FIO2CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x5CU ) )
306
307#define FIO3DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x60U ) )
308#define FIO3MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x70U ) )
309#define FIO3PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x74U ) )
310#define FIO3SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x78U ) )
311#define FIO3CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x7CU ) )
312
313#define FIO4DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x80U ) )
314#define FIO4MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x90U ) )
315#define FIO4PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x94U ) )
316#define FIO4SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x98U ) )
317#define FIO4CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x9CU ) )
318
319/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
320#define FIO0DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x00U ) )
321#define FIO1DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x20U ) )
322#define FIO2DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x40U ) )
323#define FIO3DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x60U ) )
324#define FIO4DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x80U ) )
325
326#define FIO0DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x01U ) )
327#define FIO1DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x21U ) )
328#define FIO2DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x41U ) )
329#define FIO3DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x61U ) )
330#define FIO4DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x81U ) )
331
332#define FIO0DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x02U ) )
333#define FIO1DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x22U ) )
334#define FIO2DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x42U ) )
335#define FIO3DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x62U ) )
336#define FIO4DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x82U ) )
337
338#define FIO0DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x03U ) )
339#define FIO1DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x23U ) )
340#define FIO2DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x43U ) )
341#define FIO3DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x63U ) )
342#define FIO4DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x83U ) )
343
344#define FIO0DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x00U ) )
345#define FIO1DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x20U ) )
346#define FIO2DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x40U ) )
347#define FIO3DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x60U ) )
348#define FIO4DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x80U ) )
349
350#define FIO0DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x02U ) )
351#define FIO1DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x22U ) )
352#define FIO2DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x42U ) )
353#define FIO3DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x62U ) )
354#define FIO4DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x82U ) )
355
356#define FIO0MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x10U ) )
357#define FIO1MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x30U ) )
358#define FIO2MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x50U ) )
359#define FIO3MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x70U ) )
360#define FIO4MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x90U ) )
361
362#define FIO0MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x11U ) )
363#define FIO1MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x21U ) )
364#define FIO2MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x51U ) )
365#define FIO3MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x71U ) )
366#define FIO4MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x91U ) )
367
368#define FIO0MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x12U ) )
369#define FIO1MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x32U ) )
370#define FIO2MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x52U ) )
371#define FIO3MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x72U ) )
372#define FIO4MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x92U ) )
373
374#define FIO0MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x13U ) )
375#define FIO1MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x33U ) )
376#define FIO2MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x53U ) )
377#define FIO3MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x73U ) )
378#define FIO4MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x93U ) )
379
380#define FIO0MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x10U ) )
381#define FIO1MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x30U ) )
382#define FIO2MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x50U ) )
383#define FIO3MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x70U ) )
384#define FIO4MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x90U ) )
385
386#define FIO0MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x12U ) )
387#define FIO1MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x32U ) )
388#define FIO2MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x52U ) )
389#define FIO3MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x72U ) )
390#define FIO4MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x92U ) )
391
392#define FIO0PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x14U ) )
393#define FIO1PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x34U ) )
394#define FIO2PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x54U ) )
395#define FIO3PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x74U ) )
396#define FIO4PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x94U ) )
397
398#define FIO0PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x15U ) )
399#define FIO1PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x25U ) )
400#define FIO2PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x55U ) )
401#define FIO3PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x75U ) )
402#define FIO4PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x95U ) )
403
404#define FIO0PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x16U ) )
405#define FIO1PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x36U ) )
406#define FIO2PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x56U ) )
407#define FIO3PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x76U ) )
408#define FIO4PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x96U ) )
409
410#define FIO0PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x17U ) )
411#define FIO1PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x37U ) )
412#define FIO2PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x57U ) )
413#define FIO3PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x77U ) )
414#define FIO4PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x97U ) )
415
416#define FIO0PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x14U ) )
417#define FIO1PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x34U ) )
418#define FIO2PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x54U ) )
419#define FIO3PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x74U ) )
420#define FIO4PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x94U ) )
421
422#define FIO0PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x16U ) )
423#define FIO1PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x36U ) )
424#define FIO2PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x56U ) )
425#define FIO3PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x76U ) )
426#define FIO4PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x96U ) )
427
428#define FIO0SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x18U ) )
429#define FIO1SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x38U ) )
430#define FIO2SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x58U ) )
431#define FIO3SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x78U ) )
432#define FIO4SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x98U ) )
433
434#define FIO0SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x19U ) )
435#define FIO1SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x29U ) )
436#define FIO2SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x59U ) )
437#define FIO3SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x79U ) )
438#define FIO4SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x99U ) )
439
440#define FIO0SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1AU ) )
441#define FIO1SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3AU ) )
442#define FIO2SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5AU ) )
443#define FIO3SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7AU ) )
444#define FIO4SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9AU ) )
445
446#define FIO0SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1BU ) )
447#define FIO1SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3BU ) )
448#define FIO2SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5BU ) )
449#define FIO3SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7BU ) )
450#define FIO4SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9BU ) )
451
452#define FIO0SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x18U ) )
453#define FIO1SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x38U ) )
454#define FIO2SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x58U ) )
455#define FIO3SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x78U ) )
456#define FIO4SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x98U ) )
457
458#define FIO0SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x1AU ) )
459#define FIO1SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x3AU ) )
460#define FIO2SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x5AU ) )
461#define FIO3SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x7AU ) )
462#define FIO4SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x9AU ) )
463
464#define FIO0CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1CU ) )
465#define FIO1CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3CU ) )
466#define FIO2CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5CU ) )
467#define FIO3CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7CU ) )
468#define FIO4CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9CU ) )
469
470#define FIO0CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1DU ) )
471#define FIO1CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x2DU ) )
472#define FIO2CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5DU ) )
473#define FIO3CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7DU ) )
474#define FIO4CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9DU ) )
475
476#define FIO0CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1EU ) )
477#define FIO1CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3EU ) )
478#define FIO2CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5EU ) )
479#define FIO3CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7EU ) )
480#define FIO4CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9EU ) )
481
482#define FIO0CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1FU ) )
483#define FIO1CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3FU ) )
484#define FIO2CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5FU ) )
485#define FIO3CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7FU ) )
486#define FIO4CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9FU ) )
487
488#define FIO0CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x1CU ) )
489#define FIO1CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x3CU ) )
490#define FIO2CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x5CU ) )
491#define FIO3CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x7CU ) )
492#define FIO4CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x9CU ) )
493
494#define FIO0CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x1EU ) )
495#define FIO1CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x3EU ) )
496#define FIO2CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x5EU ) )
497#define FIO3CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x7EU ) )
498#define FIO4CLRU ( *(volatile uint16_t *) ( FIO_BASE_ADDR + 0x9EU ) )
499
500#define LPC176X_USB_CLOCK 48000000U
501#define LPC176X_MODULE_CLOCK_MASK 0x3U
502
503/* Pin Connect Block */
504#define PINSEL_BASE_ADDR 0x4002C000U
505
506#define PINSEL0 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x00U ) )
507#define PINSEL1 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x04U ) )
508#define PINSEL2 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x08U ) )
509#define PINSEL3 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x0CU ) )
510#define PINSEL4 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x10U ) )
511#define PINSEL5 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x14U ) )
512#define PINSEL6 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x18U ) )
513#define PINSEL7 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x1CU ) )
514#define PINSEL8 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x20U ) )
515#define PINSEL9 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x24U ) )
516#define PINSEL10 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x28U ) )
517#define PINSEL11 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x2CU ) )
518
519#define PINMODE0 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x40U ) )
520#define PINMODE1 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x44U ) )
521#define PINMODE2 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x48U ) )
522#define PINMODE3 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x4CU ) )
523#define PINMODE4 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x50U ) )
524#define PINMODE5 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x54U ) )
525#define PINMODE6 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x58U ) )
526#define PINMODE7 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x5CU ) )
527#define PINMODE8 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x60U ) )
528#define PINMODE9 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x64U ) )
529
530/* Pulse Width Modulator (PWM) */
531#define PWM0_BASE_ADDR 0x40014000
532
533#define PWM0IR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x00 ) )
534#define PWM0TCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x04 ) )
535#define PWM0TC ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x08 ) )
536#define PWM0PR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x0C ) )
537#define PWM0PC ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x10 ) )
538#define PWM0MCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x14 ) )
539#define PWM0MR0 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x18 ) )
540#define PWM0MR1 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x1C ) )
541#define PWM0MR2 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x20 ) )
542#define PWM0MR3 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x24 ) )
543#define PWM0CCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x28 ) )
544#define PWM0CR0 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x2C ) )
545#define PWM0CR1 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x30 ) )
546#define PWM0CR2 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x34 ) )
547#define PWM0CR3 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x38 ) )
548#define PWM0EMR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x3C ) )
549#define PWM0MR4 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x40 ) )
550#define PWM0MR5 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x44 ) )
551#define PWM0MR6 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x48 ) )
552#define PWM0PCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x4C ) )
553#define PWM0LER ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x50 ) )
554#define PWM0CTCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x70 ) )
555
556#define PWM1_BASE_ADDR 0x40018000
557
558#define PWM1IR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x00 ) )
559#define PWM1TCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x04 ) )
560#define PWM1TC ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x08 ) )
561#define PWM1PR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x0C ) )
562#define PWM1PC ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x10 ) )
563#define PWM1MCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x14 ) )
564#define PWM1MR0 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x18 ) )
565#define PWM1MR1 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x1C ) )
566#define PWM1MR2 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x20 ) )
567#define PWM1MR3 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x24 ) )
568#define PWM1CCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x28 ) )
569#define PWM1CR0 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x2C ) )
570#define PWM1CR1 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x30 ) )
571#define PWM1CR2 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x34 ) )
572#define PWM1CR3 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x38 ) )
573#define PWM1EMR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x3C ) )
574#define PWM1MR4 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x40 ) )
575#define PWM1MR5 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x44 ) )
576#define PWM1MR6 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x48 ) )
577#define PWM1PCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x4C ) )
578#define PWM1LER ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x50 ) )
579#define PWM1CTCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x70 ) )
580
581/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
582#define UART0_BASE_ADDR 0x4000C000
583
584#define U0RBR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x00 ) )
585#define U0THR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x00 ) )
586#define U0DLL ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x00 ) )
587#define U0DLM ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x04 ) )
588#define U0IER ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x04 ) )
589#define U0IIR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x08 ) )
590#define U0FCR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x08 ) )
591#define U0LCR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x0C ) )
592#define U0LSR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x14 ) )
593#define U0SCR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x1C ) )
594#define U0ACR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x20 ) )
595#define U0ICR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x24 ) )
596#define U0FDR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x28 ) )
597#define U0TER ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x30 ) )
598
599/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
600#define UART1_BASE_ADDR 0x40010000
601
602#define U1RBR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x00 ) )
603#define U1THR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x00 ) )
604#define U1DLL ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x00 ) )
605#define U1DLM ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x04 ) )
606#define U1IER ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x04 ) )
607#define U1IIR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x08 ) )
608#define U1FCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x08 ) )
609#define U1LCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x0C ) )
610#define U1MCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x10 ) )
611#define U1LSR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x14 ) )
612#define U1MSR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x18 ) )
613#define U1SCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x1C ) )
614#define U1ACR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x20 ) )
615#define U1FDR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x28 ) )
616#define U1TER ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x30 ) )
617
618/* Universal Asynchronous Receiver Transmitter 2 (UART2) */
619#define UART2_BASE_ADDR 0x40098000
620
621#define U2RBR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x00 ) )
622#define U2THR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x00 ) )
623#define U2DLL ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x00 ) )
624#define U2DLM ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x04 ) )
625#define U2IER ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x04 ) )
626#define U2IIR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x08 ) )
627#define U2FCR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x08 ) )
628#define U2LCR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x0C ) )
629#define U2LSR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x14 ) )
630#define U2SCR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x1C ) )
631#define U2ACR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x20 ) )
632#define U2ICR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x24 ) )
633#define U2FDR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x28 ) )
634#define U2TER ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x30 ) )
635
636/* Universal Asynchronous Receiver Transmitter 3 (UART3) */
637#define UART3_BASE_ADDR 0x4009C000
638
639#define U3RBR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x00 ) )
640#define U3THR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x00 ) )
641#define U3DLL ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x00 ) )
642#define U3DLM ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x04 ) )
643#define U3IER ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x04 ) )
644#define U3IIR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x08 ) )
645#define U3FCR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x08 ) )
646#define U3LCR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x0C ) )
647#define U3LSR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x14 ) )
648#define U3SCR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x1C ) )
649#define U3ACR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x20 ) )
650#define U3ICR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x24 ) )
651#define U3FDR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x28 ) )
652#define U3TER ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x30 ) )
653
654/* SPI0 (Serial Peripheral Interface 0) */
655#define SPI0_BASE_ADDR 0xE0020000
656#define S0SPCR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x00 ) )
657#define S0SPSR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x04 ) )
658#define S0SPDR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x08 ) )
659#define S0SPCCR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x0C ) )
660#define S0SPINT ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x1C ) )
661
662/* Real Time Clock */
663#define RTC_BASE_ADDR 0x40024000
664
665#define RTC_ILR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x00 ) )
666#define RTC_CTC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x04 ) )
667#define RTC_CCR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x08 ) )
668#define RTC_CIIR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x0C ) )
669#define RTC_AMR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x10 ) )
670#define RTC_CTIME0 ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x14 ) )
671#define RTC_CTIME1 ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x18 ) )
672#define RTC_CTIME2 ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x1C ) )
673#define RTC_SEC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x20 ) )
674#define RTC_MIN ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x24 ) )
675#define RTC_HOUR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x28 ) )
676#define RTC_DOM ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x2C ) )
677#define RTC_DOW ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x30 ) )
678#define RTC_DOY ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x34 ) )
679#define RTC_MONTH ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x38 ) )
680#define RTC_YEAR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x3C ) )
681#define RTC_CISS ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x40 ) )
682#define RTC_ALSEC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x60 ) )
683#define RTC_ALMIN ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x64 ) )
684#define RTC_ALHOUR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x68 ) )
685#define RTC_ALDOM ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x6C ) )
686#define RTC_ALDOW ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x70 ) )
687#define RTC_ALDOY ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x74 ) )
688#define RTC_ALMON ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x78 ) )
689#define RTC_ALYEAR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x7C ) )
690#define RTC_PREINT ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x80 ) )
691#define RTC_PREFRAC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x84 ) )
692
693/* A/D Converter 0 (AD0) */
694#define AD0_BASE_ADDR 0x40034000
695
696#define AD0CR ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x00 ) )
697#define AD0GDR ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x04 ) )
698#define AD0INTEN ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x0C ) )
699#define AD0_DATA_START ( (volatile uint32_t *) ( AD0_BASE_ADDR + 0x10 ) )
700#define AD0DR0 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x10 ) )
701#define AD0DR1 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x14 ) )
702#define AD0DR2 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x18 ) )
703#define AD0DR3 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x1C ) )
704#define AD0DR4 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x20 ) )
705#define AD0DR5 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x24 ) )
706#define AD0DR6 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x28 ) )
707#define AD0DR7 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x2C ) )
708#define AD0STAT ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x30 ) )
709
710/* D/A Converter */
711#define DAC_BASE_ADDR 0x4008C000
712
713#define DACR ( *(volatile uint32_t *) ( DAC_BASE_ADDR + 0x00 ) )
714
715/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
716#define CAN_ACCEPT_BASE_ADDR 0x4003C000
717
718#define CAN_AFMR ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x00 ) )
719#define CAN_SFF_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x04 ) )
720#define CAN_SFF_GRP_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + \
721 0x08 ) )
722#define CAN_EFF_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x0C ) )
723#define CAN_EFF_GRP_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + \
724 0x10 ) )
725#define CAN_EOT ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x14 ) )
726#define CAN_LUT_ERR_ADR ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + \
727 0x18 ) )
728#define CAN_LUT_ERR ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x1C ) )
729
730#define CAN_CENTRAL_BASE_ADDR 0x40040000
731
732#define CAN_TX_SR ( *(volatile uint32_t *) ( CAN_CENTRAL_BASE_ADDR + 0x00 ) )
733#define CAN_RX_SR ( *(volatile uint32_t *) ( CAN_CENTRAL_BASE_ADDR + 0x04 ) )
734#define CAN_MSR ( *(volatile uint32_t *) ( CAN_CENTRAL_BASE_ADDR + 0x08 ) )
735
736#define CAN1_BASE_ADDR 0x40044000
737
738#define CAN1MOD ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x00 ) )
739#define CAN1CMR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x04 ) )
740#define CAN1GSR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x08 ) )
741#define CAN1ICR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x0C ) )
742#define CAN1IER ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x10 ) )
743#define CAN1BTR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x14 ) )
744#define CAN1EWL ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x18 ) )
745#define CAN1SR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x1C ) )
746#define CAN1RFS ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x20 ) )
747#define CAN1RID ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x24 ) )
748#define CAN1RDA ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x28 ) )
749#define CAN1RDB ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x2C ) )
750
751#define CAN1TFI1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x30 ) )
752#define CAN1TID1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x34 ) )
753#define CAN1TDA1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x38 ) )
754#define CAN1TDB1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x3C ) )
755#define CAN1TFI2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x40 ) )
756#define CAN1TID2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x44 ) )
757#define CAN1TDA2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x48 ) )
758#define CAN1TDB2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x4C ) )
759#define CAN1TFI3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x50 ) )
760#define CAN1TID3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x54 ) )
761#define CAN1TDA3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x58 ) )
762#define CAN1TDB3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x5C ) )
763
764#define CAN2_BASE_ADDR 0x40048000
765
766#define CAN2MOD ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x00 ) )
767#define CAN2CMR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x04 ) )
768#define CAN2GSR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x08 ) )
769#define CAN2ICR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x0C ) )
770#define CAN2IER ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x10 ) )
771#define CAN2BTR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x14 ) )
772#define CAN2EWL ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x18 ) )
773#define CAN2SR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x1C ) )
774#define CAN2RFS ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x20 ) )
775#define CAN2RID ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x24 ) )
776#define CAN2RDA ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x28 ) )
777#define CAN2RDB ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x2C ) )
778
779#define CAN2TFI1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x30 ) )
780#define CAN2TID1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x34 ) )
781#define CAN2TDA1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x38 ) )
782#define CAN2TDB1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x3C ) )
783#define CAN2TFI2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x40 ) )
784#define CAN2TID2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x44 ) )
785#define CAN2TDA2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x48 ) )
786#define CAN2TDB2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x4C ) )
787#define CAN2TFI3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x50 ) )
788#define CAN2TID3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x54 ) )
789#define CAN2TDA3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x58 ) )
790#define CAN2TDB3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x5C ) )
791
792/* MultiMedia Card Interface(MCI) Controller */
793#define MCI_BASE_ADDR 0x400c0000
794
795#define MCI_POWER ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x00 ) )
796#define MCI_CLOCK ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x04 ) )
797#define MCI_ARGUMENT ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x08 ) )
798#define MCI_COMMAND ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x0C ) )
799#define MCI_RESP_CMD ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x10 ) )
800#define MCI_RESP0 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x14 ) )
801#define MCI_RESP1 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x18 ) )
802#define MCI_RESP2 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x1C ) )
803#define MCI_RESP3 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x20 ) )
804#define MCI_DATA_TMR ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x24 ) )
805#define MCI_DATA_LEN ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x28 ) )
806#define MCI_DATA_CTRL ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x2C ) )
807#define MCI_DATA_CNT ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x30 ) )
808#define MCI_STATUS ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x34 ) )
809#define MCI_CLEAR ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x38 ) )
810#define MCI_MASK0 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x3C ) )
811#define MCI_MASK1 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x40 ) )
812#define MCI_FIFO_CNT ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x48 ) )
813#define MCI_FIFO ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x80 ) )
814
815/* I2S Interface Controller (I2S) */
816#define I2S_BASE_ADDR 0x400a8000
817
818#define I2S_DAO ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x00 ) )
819#define I2S_DAI ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x04 ) )
820#define I2S_TX_FIFO ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x08 ) )
821#define I2S_RX_FIFO ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x0C ) )
822#define I2S_STATE ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x10 ) )
823#define I2S_DMA1 ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x14 ) )
824#define I2S_DMA2 ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x18 ) )
825#define I2S_IRQ ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x1C ) )
826#define I2S_TXRATE ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x20 ) )
827#define I2S_RXRATE ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x24 ) )
828
829/* General-purpose DMA Controller */
830#define DMA_BASE_ADDR 0x50004000
831
832#define GPDMA_INT_STAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x000 ) )
833#define GPDMA_INT_TCSTAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x004 ) )
834#define GPDMA_INT_TCCLR ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x008 ) )
835#define GPDMA_INT_ERR_STAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x00C ) )
836#define GPDMA_INT_ERR_CLR ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x010 ) )
837#define GPDMA_RAW_INT_TCSTAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + \
838 0x014 ) )
839#define GPDMA_RAW_INT_ERR_STAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + \
840 0x018 ) )
841#define GPDMA_ENABLED_CHNS ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x01C ) )
842#define GPDMA_SOFT_BREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x020 ) )
843#define GPDMA_SOFT_SREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x024 ) )
844#define GPDMA_SOFT_LBREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x028 ) )
845#define GPDMA_SOFT_LSREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x02C ) )
846#define GPDMA_CONFIG ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x030 ) )
847#define GPDMA_SYNC ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x034 ) )
848
849/* DMA channel 0 registers */
850#define GPDMA_CH0_BASE_ADDR ( DMA_BASE_ADDR + 0x100 )
851#define GPDMA_CH0_SRC ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x100 ) )
852#define GPDMA_CH0_DEST ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x104 ) )
853#define GPDMA_CH0_LLI ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x108 ) )
854#define GPDMA_CH0_CTRL ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x10C ) )
855#define GPDMA_CH0_CFG ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x110 ) )
856
857/* DMA channel 1 registers */
858#define GPDMA_CH1_BASE_ADDR ( DMA_BASE_ADDR + 0x120 )
859#define GPDMA_CH1_SRC ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x120 ) )
860#define GPDMA_CH1_DEST ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x124 ) )
861#define GPDMA_CH1_LLI ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x128 ) )
862#define GPDMA_CH1_CTRL ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x12C ) )
863#define GPDMA_CH1_CFG ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x130 ) )
864
865/* USB Controller */
866#define USB_INT_BASE_ADDR 0x400fc1c0
867#define USB_BASE_ADDR 0x2008c200
868
869#define USB_INT_STAT ( *(volatile uint32_t *) ( USB_INT_BASE_ADDR + 0x00 ) )
870
871/* USB Device Interrupt Registers */
872#define DEV_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x00 ) )
873#define DEV_INT_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x04 ) )
874#define DEV_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x08 ) )
875#define DEV_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x0C ) )
876#define DEV_INT_PRIO ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x2C ) )
877
878/* USB Device Endpoint Interrupt Registers */
879#define EP_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x30 ) )
880#define EP_INT_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x34 ) )
881#define EP_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x38 ) )
882#define EP_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x3C ) )
883#define EP_INT_PRIO ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x40 ) )
884
885/* USB Device Endpoint Realization Registers */
886#define REALIZE_EP ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x44 ) )
887#define EP_INDEX ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x48 ) )
888#define MAXPACKET_SIZE ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x4C ) )
889
890/* USB Device Command Reagisters */
891#define CMD_CODE ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x10 ) )
892#define CMD_DATA ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x14 ) )
893
894/* USB Device Data Transfer Registers */
895#define RX_DATA ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x18 ) )
896#define TX_DATA ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x1C ) )
897#define RX_PLENGTH ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x20 ) )
898#define TX_PLENGTH ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x24 ) )
899#define USB_CTRL ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x28 ) )
900
901/* USB Device DMA Registers */
902#define DMA_REQ_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x50 ) )
903#define DMA_REQ_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x54 ) )
904#define DMA_REQ_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x58 ) )
905#define UDCA_HEAD ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x80 ) )
906#define EP_DMA_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x84 ) )
907#define EP_DMA_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x88 ) )
908#define EP_DMA_DIS ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x8C ) )
909#define DMA_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x90 ) )
910#define DMA_INT_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x94 ) )
911#define EOT_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xA0 ) )
912#define EOT_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xA4 ) )
913#define EOT_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xA8 ) )
914#define NDD_REQ_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xAC ) )
915#define NDD_REQ_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xB0 ) )
916#define NDD_REQ_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xB4 ) )
917#define SYS_ERR_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xB8 ) )
918#define SYS_ERR_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xBC ) )
919#define SYS_ERR_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xC0 ) )
920
921/* USB Host Controller */
922#define USBHC_BASE_ADDR 0x2008c000
923
924#define HC_REVISION ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x00 ) )
925#define HC_CONTROL ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x04 ) )
926#define HC_CMD_STAT ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x08 ) )
927#define HC_INT_STAT ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x0C ) )
928#define HC_INT_EN ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x10 ) )
929#define HC_INT_DIS ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x14 ) )
930#define HC_HCCA ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x18 ) )
931#define HC_PERIOD_CUR_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x1C ) )
932#define HC_CTRL_HEAD_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x20 ) )
933#define HC_CTRL_CUR_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x24 ) )
934#define HC_BULK_HEAD_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x28 ) )
935#define HC_BULK_CUR_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x2C ) )
936#define HC_DONE_HEAD ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x30 ) )
937#define HC_FM_INTERVAL ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x34 ) )
938#define HC_FM_REMAINING ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x38 ) )
939#define HC_FM_NUMBER ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x3C ) )
940#define HC_PERIOD_START ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x40 ) )
941#define HC_LS_THRHLD ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x44 ) )
942#define HC_RH_DESCA ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x48 ) )
943#define HC_RH_DESCB ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x4C ) )
944#define HC_RH_STAT ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x50 ) )
945#define HC_RH_PORT_STAT1 ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x54 ) )
946#define HC_RH_PORT_STAT2 ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x58 ) )
947
948/* USB OTG Controller */
949#define USBOTG_BASE_ADDR 0x2008c100
950
951#define OTG_INT_STAT ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x00 ) )
952#define OTG_INT_EN ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x04 ) )
953#define OTG_INT_SET ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x08 ) )
954#define OTG_INT_CLR ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x0C ) )
955#define OTG_STAT_CTRL ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x10 ) )
956#define OTG_TIMER ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x14 ) )
957
958#define USBOTG_I2C_BASE_ADDR 0x2008c300
959
960#define OTG_I2C_RX ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x00 ) )
961#define OTG_I2C_TX ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x00 ) )
962#define OTG_I2C_STS ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x04 ) )
963#define OTG_I2C_CTL ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x08 ) )
964#define OTG_I2C_CLKHI ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + \
965 0x0C ) )
966#define OTG_I2C_CLKLO ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + \
967 0x10 ) )
968
969#define USBOTG_CLK_BASE_ADDR 0x2008CFF0U
970
971#define OTG_CLK_CTRL ( *(volatile uint32_t *) ( USBOTG_CLK_BASE_ADDR + \
972 0x04U ) )
973#define OTG_CLK_STAT ( *(volatile uint32_t *) ( USBOTG_CLK_BASE_ADDR + \
974 0x08U ) )
975
976/* Register Fields */
977#define GET_FIELD( val, mask, shift ) \
978 ( ( ( val ) & ( mask ) ) >> ( shift ) )
979
980#define SET_FIELD( val, field, mask, shift ) \
981 ( ( ( val ) & ~( mask ) ) | ( ( ( field ) << ( shift ) ) & ( mask ) ) )
982
983/* CLKSRCSEL */
984#define CLKSRCSEL_CLKSRC_MASK 0x00000003U
985
986#define GET_CLKSRCSEL_CLKSRC( reg ) \
987 GET_FIELD( reg, CLKSRCSEL_CLKSRC_MASK, 0 )
988
989#define SET_CLKSRCSEL_CLKSRC( reg, val ) \
990 SET_FIELD( reg, val, CLKSRCSEL_CLKSRC_MASK, 0 )
991
992/* PLLCON */
993#define PLLCON_PLLE 0x00000001U
994
995#define PLLCON_PLLC 0x00000002U
996
997/* PLLCFG */
998#define PLLCFG_MSEL_MASK 0x00007fffU
999
1000#define GET_PLLCFG_MSEL( reg ) \
1001 GET_FIELD( reg, PLLCFG_MSEL_MASK, 0 )
1002
1003#define SET_PLLCFG_MSEL( reg, val ) \
1004 SET_FIELD( reg, val, PLLCFG_MSEL_MASK, 0 )
1005
1006#define PLLCFG_NSEL_MASK 0x00ff0000U
1007
1008#define GET_PLLCFG_NSEL( reg ) \
1009 GET_FIELD( reg, PLLCFG_NSEL_MASK, 16 )
1010
1011#define SET_PLLCFG_NSEL( reg, val ) \
1012 SET_FIELD( reg, val, PLLCFG_NSEL_MASK, 16 )
1013
1014/* PLLSTAT */
1015#define PLLSTAT_MSEL_MASK 0x00007fffU
1016
1017#define GET_PLLSTAT_MSEL( reg ) \
1018 GET_FIELD( reg, PLLSTAT_MSEL_MASK, 0 )
1019
1020#define SET_PLLSTAT_MSEL( reg, val ) \
1021 SET_FIELD( reg, val, PLLSTAT_MSEL_MASK, 0 )
1022
1023#define PLLSTAT_NSEL_MASK 0x00ff0000U
1024
1025#define GET_PLLSTAT_NSEL( reg ) \
1026 GET_FIELD( reg, PLLSTAT_NSEL_MASK, 16 )
1027
1028#define SET_PLLSTAT_NSEL( reg, val ) \
1029 SET_FIELD( reg, val, PLLSTAT_NSEL_MASK, 16 )
1030
1031#define PLLSTAT_PLLE 0x01000000U
1032
1033#define PLLSTAT_PLLC 0x02000000U
1034
1035#define PLLSTAT_PLOCK 0x04000000U
1036
1037/* CCLKCFG */
1038#define CCLKCFG_CCLKSEL_MASK 0x000000ffU
1039
1040#define GET_CCLKCFG_CCLKSEL( reg ) \
1041 GET_FIELD( reg, CCLKCFG_CCLKSEL_MASK, 0 )
1042
1043#define SET_CCLKCFG_CCLKSEL( reg, val ) \
1044 SET_FIELD( reg, val, CCLKCFG_CCLKSEL_MASK, 0 )
1045
1046/* MEMMAP */
1047#define MEMMAP_MAP_MASK 0x00000003U
1048
1049#define GET_MEMMAP_MAP( reg ) \
1050 GET_FIELD( reg, MEMMAP_MAP_MASK, 0 )
1051
1052#define SET_MEMMAP_MAP( reg, val ) \
1053 SET_FIELD( reg, val, MEMMAP_MAP_MASK, 0 )
1054
1055/* TIR */
1056#define TIR_MR0 0x00000001U
1057#define TIR_MR1 0x00000002U
1058#define TIR_MR2 0x00000004U
1059#define TIR_MR3 0x00000008U
1060#define TIR_CR0 0x00000010U
1061#define TIR_CR1 0x00000020U
1062#define TIR_CR2 0x00000040U
1063#define TIR_CR3 0x00000080U
1064
1065/* TCR */
1066#define TCR_EN 0x00000001U
1067#define TCR_RST 0x00000002U
1068
1069/* TMCR */
1070#define TMCR_MR0I 0x00000001U
1071#define TMCR_MR0R 0x00000002U
1072#define TMCR_MR0S 0x00000004U
1073#define TMCR_MR1I 0x00000008U
1074#define TMCR_MR1R 0x00000010U
1075#define TMCR_MR1S 0x00000020U
1076#define TMCR_MR2I 0x00000040U
1077#define TMCR_MR2R 0x00000080U
1078#define TMCR_MR2S 0x00000100U
1079#define TMCR_MR3I 0x00000200U
1080#define TMCR_MR3R 0x00000400U
1081#define TMCR_MR3S 0x00000800U
1082
1083/* PCLKSEL0 */
1084#define PCLKSEL0_PCLK_WDT_MASK 0x00000003U
1085
1086#define GET_PCLKSEL0_PCLK_WDT( reg ) \
1087 GET_FIELD( reg, PCLKSEL0_PCLK_WDT_MASK, 0 )
1088
1089#define SET_PCLKSEL0_PCLK_WDT( reg, val ) \
1090 SET_FIELD( reg, val, PCLKSEL0_PCLK_WDT_MASK, 0 )
1091
1092#define PCLKSEL0_PCLK_TIMER0_MASK 0x0000000cU
1093
1094#define GET_PCLKSEL0_PCLK_TIMER0( reg ) \
1095 GET_FIELD( reg, PCLKSEL0_PCLK_TIMER0_MASK, 2 )
1096
1097#define SET_PCLKSEL0_PCLK_TIMER0( reg, val ) \
1098 SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2 )
1099
1100#define PCLKSEL0_PCLK_TIMER1_MASK 0x00000030U
1101
1102#define GET_PCLKSEL0_PCLK_TIMER1( reg ) \
1103 GET_FIELD( reg, PCLKSEL0_PCLK_TIMER1_MASK, 4 )
1104
1105#define SET_PCLKSEL0_PCLK_TIMER1( reg, val ) \
1106 SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4 )
1107
1108#define PCLKSEL0_PCLK_UART0_MASK 0x000000c0U
1109
1110#define GET_PCLKSEL0_PCLK_UART0( reg ) \
1111 GET_FIELD( reg, PCLKSEL0_PCLK_UART0_MASK, 6 )
1112
1113#define SET_PCLKSEL0_PCLK_UART0( reg, val ) \
1114 SET_FIELD( reg, val, PCLKSEL0_PCLK_UART0_MASK, 6 )
1115
1116#define PCLKSEL0_PCLK_UART1_MASK 0x00000300U
1117
1118#define GET_PCLKSEL0_PCLK_UART1( reg ) \
1119 GET_FIELD( reg, PCLKSEL0_PCLK_UART1_MASK, 8 )
1120
1121#define SET_PCLKSEL0_PCLK_UART1( reg, val ) \
1122 SET_FIELD( reg, val, PCLKSEL0_PCLK_UART1_MASK, 8 )
1123
1124#define PCLKSEL0_PCLK_PWM0_MASK 0x00000c00U
1125
1126#define GET_PCLKSEL0_PCLK_PWM0( reg ) \
1127 GET_FIELD( reg, PCLKSEL0_PCLK_PWM0_MASK, 10 )
1128
1129#define SET_PCLKSEL0_PCLK_PWM0( reg, val ) \
1130 SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10 )
1131
1132#define PCLKSEL0_PCLK_PWM1_MASK 0x00003000U
1133
1134#define GET_PCLKSEL0_PCLK_PWM1( reg ) \
1135 GET_FIELD( reg, PCLKSEL0_PCLK_PWM1_MASK, 12 )
1136
1137#define SET_PCLKSEL0_PCLK_PWM1( reg, val ) \
1138 SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12 )
1139
1140#define PCLKSEL0_PCLK_I2C0_MASK 0x0000c000U
1141
1142#define GET_PCLKSEL0_PCLK_I2C0( reg ) \
1143 GET_FIELD( reg, PCLKSEL0_PCLK_I2C0_MASK, 14 )
1144
1145#define SET_PCLKSEL0_PCLK_I2C0( reg, val ) \
1146 SET_FIELD( reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14 )
1147
1148#define PCLKSEL0_PCLK_SPI_MASK 0x00030000U
1149
1150#define GET_PCLKSEL0_PCLK_SPI( reg ) \
1151 GET_FIELD( reg, PCLKSEL0_PCLK_SPI_MASK, 16 )
1152
1153#define SET_PCLKSEL0_PCLK_SPI( reg, val ) \
1154 SET_FIELD( reg, val, PCLKSEL0_PCLK_SPI_MASK, 16 )
1155
1156#define PCLKSEL0_PCLK_RTC_MASK 0x000c0000U
1157
1158#define GET_PCLKSEL0_PCLK_RTC( reg ) \
1159 GET_FIELD( reg, PCLKSEL0_PCLK_RTC_MASK, 18 )
1160
1161#define SET_PCLKSEL0_PCLK_RTC( reg, val ) \
1162 SET_FIELD( reg, val, PCLKSEL0_PCLK_RTC_MASK, 18 )
1163
1164#define PCLKSEL0_PCLK_SSP1_MASK 0x00300000U
1165
1166#define GET_PCLKSEL0_PCLK_SSP1( reg ) \
1167 GET_FIELD( reg, PCLKSEL0_PCLK_SSP1_MASK, 20 )
1168
1169#define SET_PCLKSEL0_PCLK_SSP1( reg, val ) \
1170 SET_FIELD( reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20 )
1171
1172#define PCLKSEL0_PCLK_DAC_MASK 0x00c00000U
1173
1174#define GET_PCLKSEL0_PCLK_DAC( reg ) \
1175 GET_FIELD( reg, PCLKSEL0_PCLK_DAC_MASK, 22 )
1176
1177#define SET_PCLKSEL0_PCLK_DAC( reg, val ) \
1178 SET_FIELD( reg, val, PCLKSEL0_PCLK_DAC_MASK, 22 )
1179
1180#define PCLKSEL0_PCLK_ADC_MASK 0x03000000U
1181
1182#define GET_PCLKSEL0_PCLK_ADC( reg ) \
1183 GET_FIELD( reg, PCLKSEL0_PCLK_ADC_MASK, 24 )
1184
1185#define SET_PCLKSEL0_PCLK_ADC( reg, val ) \
1186 SET_FIELD( reg, val, PCLKSEL0_PCLK_ADC_MASK, 24 )
1187
1188#define PCLKSEL0_PCLK_CAN1_MASK 0x0c000000U
1189
1190#define GET_PCLKSEL0_PCLK_CAN1( reg ) \
1191 GET_FIELD( reg, PCLKSEL0_PCLK_CAN1_MASK, 26 )
1192
1193#define SET_PCLKSEL0_PCLK_CAN1( reg, val ) \
1194 SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26 )
1195
1196#define PCLKSEL0_PCLK_CAN2_MASK 0x30000000U
1197
1198#define GET_PCLKSEL0_PCLK_CAN2( reg ) \
1199 GET_FIELD( reg, PCLKSEL0_PCLK_CAN2_MASK, 28 )
1200
1201#define SET_PCLKSEL0_PCLK_CAN2( reg, val ) \
1202 SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28 )
1203
1204/* PCLKSEL1 */
1205#define PCLKSEL1_PCLK_BAT_RAM_MASK 0x00000003U
1206
1207#define GET_PCLKSEL1_PCLK_BAT_RAM( reg ) \
1208 GET_FIELD( reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0 )
1209
1210#define SET_PCLKSEL1_PCLK_BAT_RAM( reg, val ) \
1211 SET_FIELD( reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0 )
1212
1213#define PCLKSEL1_PCLK_GPIO_MASK 0x0000000cU
1214
1215#define GET_PCLKSEL1_PCLK_GPIO( reg ) \
1216 GET_FIELD( reg, PCLKSEL1_PCLK_GPIO_MASK, 2 )
1217
1218#define SET_PCLKSEL1_PCLK_GPIO( reg, val ) \
1219 SET_FIELD( reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2 )
1220
1221#define PCLKSEL1_PCLK_PCB_MASK 0x00000030U
1222
1223#define GET_PCLKSEL1_PCLK_PCB( reg ) \
1224 GET_FIELD( reg, PCLKSEL1_PCLK_PCB_MASK, 4 )
1225
1226#define SET_PCLKSEL1_PCLK_PCB( reg, val ) \
1227 SET_FIELD( reg, val, PCLKSEL1_PCLK_PCB_MASK, 4 )
1228
1229#define PCLKSEL1_PCLK_I2C1_MASK 0x000000c0U
1230
1231#define GET_PCLKSEL1_PCLK_I2C1( reg ) \
1232 GET_FIELD( reg, PCLKSEL1_PCLK_I2C1_MASK, 6 )
1233
1234#define SET_PCLKSEL1_PCLK_I2C1( reg, val ) \
1235 SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6 )
1236
1237#define PCLKSEL1_PCLK_SSP0_MASK 0x00000c00U
1238
1239#define GET_PCLKSEL1_PCLK_SSP0( reg ) \
1240 GET_FIELD( reg, PCLKSEL1_PCLK_SSP0_MASK, 10 )
1241
1242#define SET_PCLKSEL1_PCLK_SSP0( reg, val ) \
1243 SET_FIELD( reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10 )
1244
1245#define PCLKSEL1_PCLK_TIMER2_MASK 0x00003000U
1246
1247#define GET_PCLKSEL1_PCLK_TIMER2( reg ) \
1248 GET_FIELD( reg, PCLKSEL1_PCLK_TIMER2_MASK, 12 )
1249
1250#define SET_PCLKSEL1_PCLK_TIMER2( reg, val ) \
1251 SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12 )
1252
1253#define PCLKSEL1_PCLK_TIMER3_MASK 0x0000c000U
1254
1255#define GET_PCLKSEL1_PCLK_TIMER3( reg ) \
1256 GET_FIELD( reg, PCLKSEL1_PCLK_TIMER3_MASK, 14 )
1257
1258#define SET_PCLKSEL1_PCLK_TIMER3( reg, val ) \
1259 SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14 )
1260
1261#define PCLKSEL1_PCLK_UART2_MASK 0x00030000U
1262
1263#define GET_PCLKSEL1_PCLK_UART2( reg ) \
1264 GET_FIELD( reg, PCLKSEL1_PCLK_UART2_MASK, 16 )
1265
1266#define SET_PCLKSEL1_PCLK_UART2( reg, val ) \
1267 SET_FIELD( reg, val, PCLKSEL1_PCLK_UART2_MASK, 16 )
1268
1269#define PCLKSEL1_PCLK_UART3_MASK 0x000c0000U
1270
1271#define GET_PCLKSEL1_PCLK_UART3( reg ) \
1272 GET_FIELD( reg, PCLKSEL1_PCLK_UART3_MASK, 18 )
1273
1274#define SET_PCLKSEL1_PCLK_UART3( reg, val ) \
1275 SET_FIELD( reg, val, PCLKSEL1_PCLK_UART3_MASK, 18 )
1276
1277#define PCLKSEL1_PCLK_I2C2_MASK 0x00300000U
1278
1279#define GET_PCLKSEL1_PCLK_I2C2( reg ) \
1280 GET_FIELD( reg, PCLKSEL1_PCLK_I2C2_MASK, 20 )
1281
1282#define SET_PCLKSEL1_PCLK_I2C2( reg, val ) \
1283 SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20 )
1284
1285#define PCLKSEL1_PCLK_I2S_MASK 0x00c00000U
1286
1287#define GET_PCLKSEL1_PCLK_I2S( reg ) \
1288 GET_FIELD( reg, PCLKSEL1_PCLK_I2S_MASK, 22 )
1289
1290#define SET_PCLKSEL1_PCLK_I2S( reg, val ) \
1291 SET_FIELD( reg, val, PCLKSEL1_PCLK_I2S_MASK, 22 )
1292
1293#define PCLKSEL1_PCLK_MCI_MASK 0x03000000U
1294
1295#define GET_PCLKSEL1_PCLK_MCI( reg ) \
1296 GET_FIELD( reg, PCLKSEL1_PCLK_MCI_MASK, 24 )
1297
1298#define SET_PCLKSEL1_PCLK_MCI( reg, val ) \
1299 SET_FIELD( reg, val, PCLKSEL1_PCLK_MCI_MASK, 24 )
1300
1301#define PCLKSEL1_PCLK_SYSCON_MASK 0x30000000U
1302
1303#define GET_PCLKSEL1_PCLK_SYSCON( reg ) \
1304 GET_FIELD( reg, PCLKSEL1_PCLK_SYSCON_MASK, 28 )
1305
1306#define SET_PCLKSEL1_PCLK_SYSCON( reg, val ) \
1307 SET_FIELD( reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28 )
1308
1309/* RTC_ILR */
1310#define RTC_ILR_RTCCIF 0x00000001U
1311#define RTC_ILR_RTCALF 0x00000002U
1312#define RTC_ILR_RTSSF 0x00000004U
1313
1314/* RTC_CCR */
1315#define RTC_CCR_CLKEN 0x00000001U
1316#define RTC_CCR_CTCRST 0x00000002U
1317#define RTC_CCR_CLKSRC 0x00000010U
1318
1319/* GPDMA */
1320typedef struct {
1321 uint32_t src;
1322 uint32_t dest;
1323 uint32_t lli;
1324 uint32_t ctrl;
1325} lpc176x_dma_descriptor;
1326
1327typedef struct {
1328 lpc176x_dma_descriptor desc;
1329 uint32_t cfg;
1330} lpc176x_dma_channel;
1331
1332#define GPDMA_CH_NUMBER 2
1333#define GPDMA_STATUS_CH_0 0x00000001U
1334#define GPDMA_STATUS_CH_1 0x00000002U
1335#define GPDMA_CH_BASE_ADDR( i ) \
1336 ( (volatile lpc176x_dma_channel *) \
1337 ( ( i ) ? GPDMA_CH1_BASE_ADDR : GPDMA_CH0_BASE_ADDR ) )
1338
1339/* GPDMA_CONFIG */
1340#define GPDMA_CONFIG_EN 0x00000001U
1341#define GPDMA_CONFIG_MODE 0x00000002U
1342
1343/* GPDMA_ENABLED_CHNS */
1344#define GPDMA_ENABLED_CHNS_CH0 0x00000001U
1345#define GPDMA_ENABLED_CHNS_CH1 0x00000002U
1346
1347/* GPDMA_CH_CTRL */
1348#define GPDMA_CH_CTRL_TSZ_MASK 0x00000fffU
1349
1350#define GET_GPDMA_CH_CTRL_TSZ( reg ) \
1351 GET_FIELD( reg, GPDMA_CH_CTRL_TSZ_MASK, 0 )
1352
1353#define SET_GPDMA_CH_CTRL_TSZ( reg, val ) \
1354 SET_FIELD( reg, val, GPDMA_CH_CTRL_TSZ_MASK, 0 )
1355
1356#define GPDMA_CH_CTRL_TSZ_MAX 0x00000fffU
1357
1358#define GPDMA_CH_CTRL_SBSZ_MASK 0x00007000U
1359
1360#define GET_GPDMA_CH_CTRL_SBSZ( reg ) \
1361 GET_FIELD( reg, GPDMA_CH_CTRL_SBSZ_MASK, 12 )
1362
1363#define SET_GPDMA_CH_CTRL_SBSZ( reg, val ) \
1364 SET_FIELD( reg, val, GPDMA_CH_CTRL_SBSZ_MASK, 12 )
1365
1366#define GPDMA_CH_CTRL_DBSZ_MASK 0x00038000U
1367
1368#define GET_GPDMA_CH_CTRL_DBSZ( reg ) \
1369 GET_FIELD( reg, GPDMA_CH_CTRL_DBSZ_MASK, 15 )
1370
1371#define SET_GPDMA_CH_CTRL_DBSZ( reg, val ) \
1372 SET_FIELD( reg, val, GPDMA_CH_CTRL_DBSZ_MASK, 15 )
1373
1374#define GPDMA_CH_CTRL_BSZ_1 0x00000000U
1375
1376#define GPDMA_CH_CTRL_BSZ_4 0x00000001U
1377
1378#define GPDMA_CH_CTRL_BSZ_8 0x00000002U
1379
1380#define GPDMA_CH_CTRL_BSZ_16 0x00000003U
1381
1382#define GPDMA_CH_CTRL_BSZ_32 0x00000004U
1383
1384#define GPDMA_CH_CTRL_BSZ_64 0x00000005U
1385
1386#define GPDMA_CH_CTRL_BSZ_128 0x00000006U
1387
1388#define GPDMA_CH_CTRL_BSZ_256 0x00000007U
1389
1390#define GPDMA_CH_CTRL_SW_MASK 0x001c0000U
1391
1392#define GET_GPDMA_CH_CTRL_SW( reg ) \
1393 GET_FIELD( reg, GPDMA_CH_CTRL_SW_MASK, 18 )
1394
1395#define SET_GPDMA_CH_CTRL_SW( reg, val ) \
1396 SET_FIELD( reg, val, GPDMA_CH_CTRL_SW_MASK, 18 )
1397
1398#define GPDMA_CH_CTRL_DW_MASK 0x00e00000U
1399
1400#define GET_GPDMA_CH_CTRL_DW( reg ) \
1401 GET_FIELD( reg, GPDMA_CH_CTRL_DW_MASK, 21 )
1402
1403#define SET_GPDMA_CH_CTRL_DW( reg, val ) \
1404 SET_FIELD( reg, val, GPDMA_CH_CTRL_DW_MASK, 21 )
1405
1406#define GPDMA_CH_CTRL_W_8 0x00000000U
1407
1408#define GPDMA_CH_CTRL_W_16 0x00000001U
1409
1410#define GPDMA_CH_CTRL_W_32 0x00000002U
1411
1412#define GPDMA_CH_CTRL_SI 0x04000000U
1413
1414#define GPDMA_CH_CTRL_DI 0x08000000U
1415
1416#define GPDMA_CH_CTRL_PROT_MASK 0x70000000U
1417
1418#define GET_GPDMA_CH_CTRL_PROT( reg ) \
1419 GET_FIELD( reg, GPDMA_CH_CTRL_PROT_MASK, 28 )
1420
1421#define SET_GPDMA_CH_CTRL_PROT( reg, val ) \
1422 SET_FIELD( reg, val, GPDMA_CH_CTRL_PROT_MASK, 28 )
1423
1424#define GPDMA_CH_CTRL_ITC 0x80000000U
1425
1426/* GPDMA_CH_CFG */
1427#define GPDMA_CH_CFG_EN 0x00000001U
1428
1429#define GPDMA_CH_CFG_SRCPER_MASK 0x0000001eU
1430
1431#define GET_GPDMA_CH_CFG_SRCPER( reg ) \
1432 GET_FIELD( reg, GPDMA_CH_CFG_SRCPER_MASK, 1 )
1433
1434#define SET_GPDMA_CH_CFG_SRCPER( reg, val ) \
1435 SET_FIELD( reg, val, GPDMA_CH_CFG_SRCPER_MASK, 1 )
1436
1437#define GPDMA_CH_CFG_DESTPER_MASK 0x000003c0U
1438
1439#define GET_GPDMA_CH_CFG_DESTPER( reg ) \
1440 GET_FIELD( reg, GPDMA_CH_CFG_DESTPER_MASK, 6 )
1441
1442#define SET_GPDMA_CH_CFG_DESTPER( reg, val ) \
1443 SET_FIELD( reg, val, GPDMA_CH_CFG_DESTPER_MASK, 6 )
1444
1445#define GPDMA_CH_CFG_PER_SSP0_TX 0x00000000U
1446
1447#define GPDMA_CH_CFG_PER_SSP0_RX 0x00000001U
1448
1449#define GPDMA_CH_CFG_PER_SSP1_TX 0x00000002U
1450
1451#define GPDMA_CH_CFG_PER_SSP1_RX 0x00000003U
1452
1453#define GPDMA_CH_CFG_PER_SD_MMC 0x00000004U
1454
1455#define GPDMA_CH_CFG_PER_I2S_CH0 0x00000005U
1456
1457#define GPDMA_CH_CFG_PER_I2S_CH1 0x00000006U
1458
1459#define GPDMA_CH_CFG_FLOW_MASK 0x00003800U
1460
1461#define GET_GPDMA_CH_CFG_FLOW( reg ) \
1462 GET_FIELD( reg, GPDMA_CH_CFG_FLOW_MASK, 11 )
1463
1464#define SET_GPDMA_CH_CFG_FLOW( reg, val ) \
1465 SET_FIELD( reg, val, GPDMA_CH_CFG_FLOW_MASK, 11 )
1466
1467#define GPDMA_CH_CFG_FLOW_MEM_TO_MEM_DMA 0x00000000U
1468
1469#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_DMA 0x00000001U
1470
1471#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_DMA 0x00000002U
1472
1473#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DMA 0x00000003U
1474
1475#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DEST 0x00000004U
1476
1477#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_PER 0x00000005U
1478
1479#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_PER 0x00000006U
1480
1481#define GPDMA_CH_CFG_FLOW_PER_TO_PER_SRC 0x00000007U
1482
1483#define GPDMA_CH_CFG_IE 0x00004000U
1484
1485#define GPDMA_CH_CFG_ITC 0x00008000U
1486
1487#define GPDMA_CH_CFG_LOCK 0x00010000U
1488
1489#define GPDMA_CH_CFG_ACTIVE 0x00020000U
1490
1491#define GPDMA_CH_CFG_HALT 0x00040000U
1492
1493/* AHBCFG */
1494#define AHBCFG_SCHEDULER_UNIFORM 0x00000001U
1495
1496#define AHBCFG_BREAK_BURST_MASK 0x00000006U
1497
1498#define GET_AHBCFG_BREAK_BURST( reg ) \
1499 GET_FIELD( reg, AHBCFG_BREAK_BURST_MASK, 1 )
1500
1501#define SET_AHBCFG_BREAK_BURST( reg, val ) \
1502 SET_FIELD( reg, val, AHBCFG_BREAK_BURST_MASK, 1 )
1503
1504#define AHBCFG_QUANTUM_BUS_CYCLE 0x00000008U
1505
1506#define AHBCFG_QUANTUM_SIZE_MASK 0x000000f0U
1507
1508#define GET_AHBCFG_QUANTUM_SIZE( reg ) \
1509 GET_FIELD( reg, AHBCFG_QUANTUM_SIZE_MASK, 4 )
1510
1511#define SET_AHBCFG_QUANTUM_SIZE( reg, val ) \
1512 SET_FIELD( reg, val, AHBCFG_QUANTUM_SIZE_MASK, 4 )
1513
1514#define AHBCFG_DEFAULT_MASTER_MASK 0x00000700U
1515
1516#define GET_AHBCFG_DEFAULT_MASTER( reg ) \
1517 GET_FIELD( reg, AHBCFG_DEFAULT_MASTER_MASK, 8 )
1518
1519#define SET_AHBCFG_DEFAULT_MASTER( reg, val ) \
1520 SET_FIELD( reg, val, AHBCFG_DEFAULT_MASTER_MASK, 8 )
1521
1522#define AHBCFG_EP1_MASK 0x00007000U
1523
1524#define GET_AHBCFG_EP1( reg ) \
1525 GET_FIELD( reg, AHBCFG_EP1_MASK, 12 )
1526
1527#define SET_AHBCFG_EP1( reg, val ) \
1528 SET_FIELD( reg, val, AHBCFG_EP1_MASK, 12 )
1529
1530#define AHBCFG_EP2_MASK 0x00070000U
1531
1532#define GET_AHBCFG_EP2( reg ) \
1533 GET_FIELD( reg, AHBCFG_EP2_MASK, 16 )
1534
1535#define SET_AHBCFG_EP2( reg, val ) \
1536 SET_FIELD( reg, val, AHBCFG_EP2_MASK, 16 )
1537
1538#define AHBCFG_EP3_MASK 0x00700000U
1539
1540#define GET_AHBCFG_EP3( reg ) \
1541 GET_FIELD( reg, AHBCFG_EP3_MASK, 20 )
1542
1543#define SET_AHBCFG_EP3( reg, val ) \
1544 SET_FIELD( reg, val, AHBCFG_EP3_MASK, 20 )
1545
1546#define AHBCFG_EP4_MASK 0x07000000U
1547
1548#define GET_AHBCFG_EP4( reg ) \
1549 GET_FIELD( reg, AHBCFG_EP4_MASK, 24 )
1550
1551#define SET_AHBCFG_EP4( reg, val ) \
1552 SET_FIELD( reg, val, AHBCFG_EP4_MASK, 24 )
1553
1554#define AHBCFG_EP5_MASK 0x70000000U
1555
1556#define GET_AHBCFG_EP5( reg ) \
1557 GET_FIELD( reg, AHBCFG_EP5_MASK, 28 )
1558
1559#define SET_AHBCFG_EP5( reg, val ) \
1560 SET_FIELD( reg, val, AHBCFG_EP5_MASK, 28 )
1561
1562/* I2S */
1563static volatile lpc_i2s * const lpc176x_i2s = (lpc_i2s *) I2S_BASE_ADDR;
1564
1565/* ADC */
1566#define ADC_CR_SEL( val ) BSP_FLD32( val, 0, 7 )
1567#define ADC_CR_SEL_GET( val ) BSP_FLD32GET( val, 0, 7 )
1568#define ADC_CR_SEL_SET( reg, val ) BSP_FLD32SET( reg, val, 0, 7 )
1569#define ADC_CR_CLKDIV( val ) BSP_FLD32( val, 8, 15 )
1570#define ADC_CR_CLKDIV_GET( reg ) BSP_FLD32GET( reg, 8, 15 )
1571#define ADC_CR_CLKDIV_SET( reg, val ) BSP_FLD32SET( reg, val, 8, 15 )
1572#define ADC_CR_BURST BSP_BIT32( 16 )
1573#define ADC_CR_CLKS( val ) BSP_FLD32( val, 17, 19 )
1574#define ADC_CR_PDN BSP_BIT32( 21 )
1575#define ADC_CR_START( val ) BSP_FLD32( val, 24, 26 )
1576#define ADC_CR_EDGE BSP_BIT32( 27 )
1577
1578#define ADC_DR_VALUE( reg ) BSP_FLD32GET( reg, 4, 15 )
1579#define ADC_DR_OVERRUN BSP_BIT32( 30 )
1580#define ADC_DR_DONE BSP_BIT32( 31 )
1581
1582/* DAC */
1583#define DAC_STEPS 1024
1584#define DAC_VALUE( val ) BSP_FLD32( val, 6, 15 )
1585#define DAC_BIAS BSP_BIT32( 16 )
1586
1587#endif /* LIBBSP_ARM_LPC176X_H */
lpc-i2s.h
I2S API.
lpc176x_dma_channel
Definition: lpc176x.h:1327
lpc176x_dma_descriptor
Definition: lpc176x.h:1320
lpc176x_pll
Phase-Locked Loop representation.
Definition: lpc176x.h:44
lpc176x_pll::stat
uint32_t stat
PLL Status Register.
Definition: lpc176x.h:56
lpc176x_pll::feed
uint32_t feed
PLL Feed Register.
Definition: lpc176x.h:60
lpc176x_pll::cfg
uint32_t cfg
PLL Configuration Register.
Definition: lpc176x.h:52
lpc176x_pll::con
uint32_t con
PLL Control Register.
Definition: lpc176x.h:48
lpc176x_scb
System Control Block representation.
Definition: lpc176x.h:193
lpc176x_scb::flashcfg
uint32_t flashcfg
Flash Accelerator Configuration Register.
Definition: lpc176x.h:197
lpc176x_scb::extint
uint32_t extint
External Interrupt flag register.
Definition: lpc176x.h:241
lpc176x_scb::pll_0
lpc176x_pll pll_0
Phase-Locked Loop 0.
Definition: lpc176x.h:207
lpc176x_scb::clksrcsel
uint32_t clksrcsel
Clock Source Select register.
Definition: lpc176x.h:236
lpc176x_scb::pll_1
lpc176x_pll pll_1
Phase-Locked Loop 1.
Definition: lpc176x.h:212
lpc176x_scb::usbclksel
uint32_t usbclksel
Selects the divide value for creating the USB clock from the PPL0 output.
Definition: lpc176x.h:232
lpc176x_scb::pboost
uint32_t pboost
Peripheral boost.
Definition: lpc176x.h:269
lpc176x_scb::extmode
uint32_t extmode
External Interrupt Mode register.
Definition: lpc176x.h:246
lpc176x_scb::pconp
uint32_t pconp
Power Control for Peripherals register.
Definition: lpc176x.h:221
lpc176x_scb::clkoutcfg
uint32_t clkoutcfg
Clock Output Configuration Register.
Definition: lpc176x.h:274
lpc176x_scb::rsid
uint32_t rsid
Reset Source Identification Register.
Definition: lpc176x.h:255
lpc176x_scb::memmap
uint32_t memmap
Memopry Map Control.
Definition: lpc176x.h:202
lpc176x_scb::cclksel
uint32_t cclksel
Selects the divide valuefor creating the CPU clock from the PPL0 output.
Definition: lpc176x.h:227
lpc176x_scb::pcon
uint32_t pcon
Power Mode Control register.
Definition: lpc176x.h:217
lpc176x_scb::scs
uint32_t scs
System Controls and Status Register.
Definition: lpc176x.h:260
lpc176x_scb::extpolar
uint32_t extpolar
External Interrupt Polarity register.
Definition: lpc176x.h:250
lpc_i2s
I2S control block.
Definition: lpc-i2s.h:59
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