RTEMS 7.0-rc1
Loading...
Searching...
No Matches
efm32gg11_gpio.h
Go to the documentation of this file.
1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2025 Allan N. Hessenflow
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#ifndef LIBBSP_ARM_EFM32GG11_GPIO_H
37#define LIBBSP_ARM_EFM32GG11_GPIO_H
38
39#include <bspopts.h>
40
41void efm32gg11_gpio_init_0(void);
42void efm32gg11_gpio_init(void);
43
44/* returns a non-negative number on success indicating the interrupt
45 number assigned, or a negative number on failure. */
46int efm32gg11_gpio_int_register(uint8_t port, uint8_t pin,
47 void (*cb)(void *), void *arg);
48
49/* which is the bit number from the em4 wakeup pin registers, range 16 - 31 */
50void efm32gg11_gpio_wake_pin_int_register(unsigned int which,
51 void (*cb)(void *), void *arg);
52
53/* which is the interrupt number provided by efm32gg11_gpio_int_register() */
54void efm32gg11_gpio_int_mode(unsigned int which, bool rising, bool falling);
55
56/* which is the bit number from the em4 wakeup pin registers, range 16 - 31 */
57void efm32gg11_gpio_wake_pin_level(unsigned int which, bool high);
58
59/* which is the interrupt number provided by efm32gg11_gpio_int_register() */
60void efm32gg11_gpio_int_enable(unsigned int which, bool enable);
61
62void efm32gg11_gpio_mode(uint8_t port, uint8_t pin, uint8_t mode);
63
64void efm32gg11_gpio_clear_set(uint8_t port, uint16_t clear, uint16_t set);
65
66#endif /* LIBBSP_ARM_EFM32GG11_GPIO_H */