RTEMS 7.0-rc1
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bestcomm_cntrl.h
1#ifndef __TASK_API_BESTCOMM_CNTRL_H
2#define __TASK_API_BESTCOMM_CNTRL_H 1
3
4/******************************************************************************
5*
6* Copyright (c) 2004 Freescale Semiconductor, Inc.
7*
8* Permission is hereby granted, free of charge, to any person obtaining a
9* copy of this software and associated documentation files (the "Software"),
10* to deal in the Software without restriction, including without limitation
11* the rights to use, copy, modify, merge, publish, distribute, sublicense,
12* and/or sell copies of the Software, and to permit persons to whom the
13* Software is furnished to do so, subject to the following conditions:
14*
15* The above copyright notice and this permission notice shall be included
16* in all copies or substantial portions of the Software.
17*
18* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24* OTHER DEALINGS IN THE SOFTWARE.
25*
26******************************************************************************/
27
28/*******************************************************************************
29 * Defines to control SmartDMA and its tasks. These defines are used for the
30 * task build process to minimize disconnects at the task/driver interface.
31 ******************************************************************************/
32
33#define SDMA_INT_BIT_DBG 31 /* debug interrupt bit */
34#define SDMA_INT_BIT_TEA 28 /* TEA interrupt bit */
35#define SDMA_INT_BIT_TEA_TASK 24 /* lsb for TEA task number */
36#define SDMA_INT_BIT_IMPL 0x9000FFFF
37
38#define SDMA_PTDCTRL_BIT_TEA 14 /* TEA detection enable bit */
39
40#define SDMA_TCR_BIT_AUTO 15 /* auto start bit */
41#define SDMA_TCR_BIT_HOLD 5 /* hold initiator bit */
42
43#define SDMA_STAT_BIT_ALARM 17
44#define SDMA_FIFO_ALARM_MASK 0x0020000
45
46#define SDMA_DRD_BIT_TFD 27 /* mark last buffer of frame */
47#define SDMA_DRD_BIT_INT 26 /* interrupt after buffer processed */
48#define SDMA_DRD_BIT_INIT 21 /* lsb position of initiator */
49#define SDMA_DRD_MASK_FLAGS 0x0C000000 /* BD_FLAGS flag bits */
50#define SDMA_DRD_MASK_LENGTH 0x03FFFFFF /* BD_FLAGS length mask */
51#define SDMA_BD_BIT_READY 30 /* Status BD ready bit */
52#ifdef SAS_COMPILE
53 #define SDMA_BD_MASK_READY constant(1<<SDMA_BD_BIT_READY)
54#else
55 #define SDMA_BD_MASK_READY (1<<SDMA_BD_BIT_READY)
56#endif
57#define SDMA_BD_MASK_SIGN 0x7FFFFFFF /* task code needs Status>0 */
58
59#define SDMA_PRAGMA_BIT_RSV 7 /* reserved pragma bit */
60#define SDMA_PRAGMA_BIT_PRECISE_INC 6 /* increment 0=when possible, 1=iter end */
61#define SDMA_PRAGMA_BIT_RST_ERROR_NO 5 /* don't reset errors on task enable */
62#define SDMA_PRAGMA_BIT_PACK 4 /* pack data enable */
63#define SDMA_PRAGMA_BIT_INTEGER 3 /* data alignment 0=frac(msb), 1=int(lsb) */
64#define SDMA_PRAGMA_BIT_SPECREAD 2 /* XLB speculative read enable */
65#define SDMA_PRAGMA_BIT_CW 1 /* write line buffer enable */
66#define SDMA_PRAGMA_BIT_RL 0 /* read line buffer enable */
67
68#define SDMA_TASK_ENTRY_BYTES 32 /* Bytes per task in entry table */
69#define SDMA_TASK_GROUP_NUM 16 /* Number of tasks per task group */
70#define SDMA_TASK_GROUP_BYTES (SDMA_TASK_ENTRY_BYTES*SDMA_TASK_GROUP_NUM)
71
72
73/*******************************************************************************
74 * Task group control macros, use when TaskNum > 15
75 ******************************************************************************/
76#define SDMA_TASKNUM_EXT(OldTaskNum) (OldTaskNum%16)
77
78#define SDMA_TASKBAR_CHANGE(sdma, OldTaskNum) { \
79 sdma->taskBar += (((int)(OldTaskNum/SDMA_TASK_GROUP_NUM))*SDMA_TASK_GROUP_BYTES); \
80}
81
82#define SDMA_TASKBAR_RESTORE(sdma, OldTaskNum) { \
83 sdma->taskBar -= (((int)(OldTaskNum/SDMA_TASK_GROUP_NUM))*SDMA_TASK_GROUP_BYTES); \
84}
85
86
87/*******************************************************************************
88 * Task control macros
89 ******************************************************************************/
90#define SDMA_TASK_CFG(RegAddr, TaskNum, AutoStart, AutoStartNum) { \
91 *(((volatile uint16 *)RegAddr)+TaskNum) = (uint16)(0x0000 | \
92 ((AutoStart!=0)<<7) | \
93 (AutoStartNum&0xF) ); \
94}
95
96#define SDMA_TASK_AUTO_START(RegAddr, TaskNum, AutoStart, AutoStartNum) { \
97 *(((volatile uint16 *)RegAddr)+TaskNum) = (uint16)((*(((volatile uint16 *)RegAddr)+TaskNum) & \
98 (uint16) 0xff30) | ((uint16)(0x0000 | \
99 ((AutoStart!=0)<<7) | \
100 (AutoStartNum&0xF)) )); \
101}
102
103#define SDMA_TASK_ENABLE(RegAddr, TaskNum) { \
104 *(((volatile uint16 *)RegAddr)+TaskNum) |= (uint16)0x8000; \
105}
106
107#define SDMA_TASK_DISABLE(RegAddr, TaskNum) { \
108 *(((volatile uint16 *)RegAddr)+TaskNum) &= ~(uint16)0x8000; \
109}
110
111#define SDMA_TASK_STATUS(RegAddr, TaskNum) \
112 *(((volatile uint16 *)RegAddr)+TaskNum)
113
114
115/*******************************************************************************
116 * Interrupt control macros
117 ******************************************************************************/
118#define SDMA_INT_ENABLE(RegAddr, Bit) \
119 do { \
120 rtems_interrupt_level level; \
121 volatile uint32 *reg = (volatile uint32 *) RegAddr; \
122 rtems_interrupt_disable(level); \
123 *reg &= ~((uint32) (1 << Bit)); \
124 rtems_interrupt_enable(level); \
125 } while (0)
126
127#define SDMA_INT_DISABLE(RegAddr, Bit) \
128 do { \
129 rtems_interrupt_level level; \
130 volatile uint32 *reg = (volatile uint32 *) RegAddr; \
131 rtems_interrupt_disable(level); \
132 *reg |= ((uint32)(1 << Bit)); \
133 rtems_interrupt_enable(level); \
134 } while (0)
135
136#define SDMA_INT_SOURCE(RegPend, RegMask) \
137 (*((volatile uint32 *)(RegPend)) & (~*((volatile uint32 *)(RegMask))) & (uint32)SDMA_INT_BIT_IMPL)
138
139#define SDMA_INT_PENDING(RegPend, RegMask) \
140 (*((volatile uint32 *)(RegPend)) & (~*((volatile uint32 *)(RegMask))))
141
142#define SDMA_INT_TEST(IntSource, Bit) \
143 (((uint32)IntSource) & ((uint32)(1<<Bit)))
144
145/*
146 * define SDMA_INT_FIND to get int bit rather than scan all bits use
147 * cntlzw
148 */
149
150/* Clear the IntPend bit */
151#define SDMA_CLEAR_IEVENT(RegAddr, Bit) { \
152 volatile uint32 *reg = (volatile uint32 *) RegAddr; \
153 *reg = ((uint32)(1<<Bit)); \
154}
155
156#define SDMA_GET_PENDINGBIT(sdma, Bit) \
157 (sdma->IntPend & (uint32)(1<<Bit))
158
159#define SDMA_GET_MASKBIT(sdma, Bit) \
160 (sdma->IntMask & (uint32)(1<<Bit))
161
162
163/*******************************************************************************
164 * SmartDMA FIFO control macros
165 ******************************************************************************/
166
167/*******************************************************************************
168 * SmartDMA TEA detection control macros
169 ******************************************************************************/
170/* Enable SmartDMA TEA detection and TEA interrupt */
171#define SDMA_TEA_ENABLE(sdma) { \
172 SDMA_INT_ENABLE(sdma, SDMA_INT_BIT_TEA); \
173 sdma->PtdCntrl &= ~((uint32)(1<<SDMA_PTDCTRL_BIT_TEA)); \
174}
175
176/* Disable SmartDMA TEA detection and TEA interrupt */
177#define SDMA_TEA_DISABLE(sdma) { \
178 SDMA_INT_DISABLE(sdma, SDMA_INT_BIT_TEA); \
179 sdma->PtdCntrl |= ((uint32)(1<<SDMA_PTDCTRL_BIT_TEA)); \
180}
181
182/* Clear the TEA interrupt */
183#define SDMA_TEA_CLEAR(sdma) { \
184 sdma->IntPend = ((uint32)(0x1F<<SDMA_INT_BIT_TEA_TASK)); \
185}
186
187/* Determine which task caused a TEA on the XLB */
188#define SDMA_TEA_SOURCE(RegPend) \
189 (uint32)(((*(volatile uint32 *)RegPend)>>SDMA_INT_BIT_TEA_TASK) & 0xF)
190
191
192/*******************************************************************************
193 * SmartDMA debug control macros
194 ******************************************************************************/
195/* Enable the SmartDMA debug unit and DBG interrupt */
196/* add sdma->dbg_regs setup? */
197#define SDMA_DBG_ENABLE(sdma) { \
198 SDMA_INT_ENABLE(sdma, SDMA_INT_BIT_DBG); \
199}
200
201#define SDMA_DBG_DISABLE(sdma) { \
202 SDMA_INT_DISABLE(sdma, SDMA_INT_BIT_DBG); \
203}
204
205/* Clear the debug interrupt */
206#define SDMA_DBG_CLEAR(sdma) { \
207 SDMA_CLEAR_IEVENT(sdma, SDMA_INT_BIT_DBG); \
208}
209
210#define SDMA_DBG_MDE(dst, sdma, addr) { \
211 sdma->MDEDebug = addr; \
212 dst = sdma->MDEDebug; \
213}
214
215#define SDMA_DBG_ADS(dst, sdma, addr) { \
216 sdma->ADSDebug = addr; \
217 dst = sdma->ADSDebug; \
218}
219
220#define SDMA_DBG_PTD(dst, sdma, addr) { \
221 sdma->PTDDebug = addr; \
222 dst = sdma->PTDDebug; \
223}
224
225
226/*******************************************************************************
227 * Initiator control macros
228 ******************************************************************************/
229
230/* This macro may not work, getting compile errors */
231/* Set the Transfer Size */
232/* Note that masking the size w/ 0x3 gives the desired value for uint32 */
233/* (expressed as 4), namely 0. */
234#define SDMA_SET_SIZE(RegAddr, TaskNum, SrcSize, DstSize) \
235 *(((volatile uint8 *)RegAddr)+((uint32)(TaskNum/2))) = \
236 (uint8)((*(((volatile uint8 *)RegAddr)+((uint32)(TaskNum/2))) & \
237 ((TaskNum%2) ? 0xf0 : 0x0f)) | \
238 ((uint8)(((SrcSize & 0x3)<<2) | \
239 ( DstSize & 0x3 ) ) <<(4*((int)(1-(TaskNum%2))))));
240
241/* This macro may not work */
242/* Set the Initiator in TCR */
243#define SDMA_SET_INIT(RegAddr, TaskNum, Initiator) \
244{ \
245 *(((volatile uint16 *)RegAddr)+TaskNum) &= (uint16)0xE0FF; \
246 *(((volatile uint16 *)RegAddr)+TaskNum) |= (((0x01F & Initiator)<<8) | \
247 (0<<SDMA_TCR_BIT_HOLD)); \
248}
249
250/* Change DRD initiator number */
251#define SDMA_INIT_CHANGE(task, oldInitiator, newInitiator) { \
252 int i; \
253 for (i=0; i<task->NumDRD; i++) { \
254 if (SDMA_INIT_READ(task->DRD[i]) == (uint32)oldInitiator) { \
255 SDMA_INIT_WRITE(task->DRD[i],newInitiator); \
256 } \
257 } \
258}
259
260/* Set the Initiator Priority */
261#define SDMA_SET_INITIATOR_PRIORITY(sdma, initiator, priority) \
262 *(((volatile uint8 *)&sdma->IPR0)+initiator) = priority;
263
264
265/* Read DRD initiator number */
266#define SDMA_INIT_READ(PtrDRD) \
267 (((*(volatile uint32 *)PtrDRD)>>SDMA_DRD_BIT_INIT) & (uint32)0x1F)
268
269/* Write DRD initiator number */
270#define SDMA_INIT_WRITE(PtrDRD, Initiator) { \
271 *(volatile uint32 *)PtrDRD = ((*(volatile uint32 *)PtrDRD) & 0xFC1FFFFF) | \
272 (Initiator<<SDMA_DRD_BIT_INIT); \
273}
274
275/* Change DRD initiator number */
276#define SDMA_INIT_CHANGE(task, oldInitiator, newInitiator) { \
277 int i; \
278 for (i=0; i<task->NumDRD; i++) { \
279 if (SDMA_INIT_READ(task->DRD[i]) == (uint32)oldInitiator) { \
280 SDMA_INIT_WRITE(task->DRD[i],newInitiator); \
281 } \
282 } \
283}
284
285#endif /* __TASK_API_BESTCOMM_CNTRL_H */
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