RTEMS 7.0-rc1
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at91rm9200_usart.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
13/*
14 * Copyright (C) 2003 Cogent Computer Systems
15 * Written by Mike Kelly <mike@cogcomp.com>
16 *
17 * Modified by Fernando Nicodemos <fgnicodemos@terra.com.br>
18 * from NCB - Sistemas Embarcados Ltda. (Brazil)
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 * 1. Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * 2. Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
33 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#ifndef __AT91RM9200_USART_H__
43#define __AT91RM9200_USART_H__
44
45#include <bits.h>
46
47/* Register Offsets */
48#define US_CR 0x00 /* Control Register */
49#define US_MR 0x04 /* Mode Register */
50#define US_IER 0x08 /* Interrupt Enable Register */
51#define US_IDR 0x0C /* Interrupt Disable Register */
52#define US_IMR 0x10 /* Interrupt Mask Register */
53#define US_SR 0x14 /* Channel Status Register */
54#define US_RHR 0x18 /* Receiver Holding Register */
55#define US_THR 0x1C /* Transmitter Holding Register */
56#define US_BRGR 0x20 /* Baud Rate Generator Register */
57#define US_RTOR 0x24 /* Receiver Time-out Register */
58#define US_TTGR 0x28 /* Transmitter Timeguard Register */
59#define US_C1R 0x40 /* Chip ID1 Register - FI DI Ratio Register */
60#define US_C2R 0x44 /* Chip ID2 Register - Number of Erros Register */
61#define US_FNTR 0x48 /* Force NTRST Register */
62#define US_IF 0x4C /* IrDA Filter Register */
63
64/* Bit Defines */
65/* Control Register, US_CR, Offset 0x00 */
66#define US_CR_RSTRX BIT2 /* 1 = Reset and disable receiver */
67#define US_CR_RSTTX BIT3 /* 1 = Reset and disable transmitter */
68#define US_CR_RXEN BIT4 /* 1 = Receiver enable */
69#define US_CR_RXDIS BIT5 /* 1 = Receiver disable */
70#define US_CR_TXEN BIT6 /* 1 = Transmitter enable */
71#define US_CR_TXDIS BIT7 /* 1 = Transmitter disable */
72#define US_CR_RSTSTA BIT8 /* 1 = Reset PARE, FRAME and OVRE in DBGU_SR. */
73#define US_CR_STTBRK BIT9 /* 1 = Start transmission of a Break */
74#define US_CR_STPBRK BIT10 /* 1 = Stop transmission of a Break */
75#define US_CR_STTTO BIT11 /* 1 = Start Time-out */
76#define US_CR_SENDA BIT12 /* 1 = Send Address - MDROP mode only */
77#define US_CR_RSTIT BIT13 /* 1 = Reset Iteration */
78#define US_CR_RSTNACK BIT14 /* 1 = Reset Non Acknowledge */
79#define US_CR_RETTO BIT15 /* 1 = Restart Time-out */
80#define US_CR_DTREN BIT16 /* 1 = Data Terminal Ready Enable - AT91RM9200 only */
81#define US_CR_DTRDIS BIT17 /* 1 = Data Terminal Ready Disable - AT91RM9200 only */
82#define US_CR_RTSEN BIT18 /* 1 = Request To Send Enable */
83#define US_CR_RTSDIS BIT19 /* 1 = Request To Send Disable */
84
85
86/* Mode Register. US_MR. Offset 0x04 */
87#define US_MR_USMODE (0xF << 0) /* Mode of the USART */
88#define US_MR_USMODE_NORMAL 0
89#define US_MR_USMODE_RS485 1
90#define US_MR_USMODE_HWHS 2
91#define US_MR_USMODE_MODEM 3
92#define US_MR_USMODE_ISO7816_T0 4
93#define US_MR_USMODE_ISO7816_T1 6
94#define US_MR_USMODE_IRDA 8
95#define US_MR_USCLKS (3 << 4) /* Clock Selection */
96#define US_MR_USCLKS_MCK (0 << 4)
97#define US_MR_USCLKS_MCK_DIV8 (1 << 4)
98#define US_MR_USCLKS_SCK (3 << 4)
99#define US_MR_CHRL (3 << 6) /* Character Length */
100#define US_MR_CHRL_5 (0 << 6)
101#define US_MR_CHRL_6 (1 << 6)
102#define US_MR_CHRL_7 (2 << 6)
103#define US_MR_CHRL_8 (3 << 6)
104#define US_MR_SYNC (1 << 8) /* Synchronous Mode Select */
105#define US_MR_PAR (7 << 9) /* Parity Type */
106#define US_MR_PAR_EVEN (0 << 9) /* Even Parity */
107#define US_MR_PAR_ODD (1 << 9) /* Odd Parity */
108#define US_MR_PAR_SPACE (2 << 9) /* Parity forced to 0 (Space) */
109#define US_MR_PAR_MARK (3 << 9) /* Parity forced to 1 (Mark) */
110#define US_MR_PAR_NONE (4 << 9) /* No Parity */
111#define US_MR_PAR_MDROP (6 << 9) /* Multi-drop mode */
112#define US_MR_NBSTOP (3 << 12) /* Number of Stop Bits */
113#define US_MR_NBSTOP_1 (0 << 12)
114#define US_MR_NBSTOP_1_5 (1 << 12)
115#define US_MR_NBSTOP_2 (2 << 12)
116#define US_MR_CHMODE (3 << 14) /* Channel Mode */
117#define US_MR_CHMODE_NORM (0 << 14) /* Normal Mode */
118#define US_MR_CHMODE_AUTO (1 << 14) /* Auto Echo: RXD drives TXD */
119#define US_MR_CHMODE_LOC (2 << 14) /* Local Loopback: TXD drives RXD */
120#define US_MR_CHMODE_REM (3 << 14) /* Remote Loopback: RXD pin connected to TXD pin. */
121#define US_MR_MSBF (1 << 16) /* Bit Order */
122#define US_MR_MODE9 (1 << 17) /* 9-bit Character Length */
123#define US_MR_CLKO (1 << 18) /* Clock Output Select */
124#define US_MR_OVER (1 << 19) /* Oversampling Mode */
125#define US_MR_INACK (1 << 20) /* Inhibit Non Acknowledge */
126#define US_MR_DSNACK (1 << 21) /* Disable Successive NACK */
127#define US_MR_MAX_ITER (7 << 24) /* Max Iterations */
128#define US_MR_FILTER (1 << 28) /* Infrared Receive Line Filter */
129
130/* Interrupt Enable Register, US_IER, Offset 0x08 */
131/* Interrupt Disable Register, US_IDR, Offset 0x0C */
132/* Interrupt Mask Register, US_IMR, Offset 0x10 */
133/* Channel Status Register, US_SR, Offset 0x14 */
134#define US_IER_RXRDY BIT0 /* RXRDY Interrupt */
135#define US_IER_TXRDY BIT1 /* TXRDY Interrupt */
136#define US_IER_RXBRK BIT2 /* End of Receive Transfer Interrupt */
137#define US_IER_ENDRX BIT3 /* End of Receiver Transfer */
138//#define US_IER_ENDTX BIT4 /* End of Transmit Interrupt */
139#define US_IER_OVRE BIT5 /* Overrun Interrupt */
140#define US_IER_FRAME BIT6 /* Framing Error Interrupt */
141#define US_IER_PARE BIT7 /* Parity Error */
142#define US_IER_TIMEOUT BIT8 /* Receiver Time-out */
143#define US_IER_TXEMPTY BIT9 /* Transmitter Empty */
144#define US_IER_ITERATION BIT10 /* Max number of Repetitions Reached */
145#define US_IER_TXBUFE BIT11 /* Transmission Buffer Empty */
146#define US_IER_RXBUFF BIT12 /* Reception Buffer Full */
147#define US_IER_NACK BIT13 /* Non Acknowledge */
148#define US_IER_RIIC BIT16 /* Ring Indicator Input Change [AT91RM9200 only] */
149#define US_IER_DSRIC BIT17 /* Data Set Ready Input Change [AT91RM9200 only] */
150#define US_IER_DCDIC BIT18 /* Data Carrier Detect Input Change [AT91RM9200 only] */
151#define US_IER_CTSIC BIT19 /* Clear to Send Input Change */
152#define US_IER_ALL 0xC0001AFB /* all assigned bits */
153
154/* FORCE_NTRST Register, US_FNTR, Offset 0x48 */
155#define US_FNTR_NTRST BIT0 /* 1 = Force NTRST low in JTAG */
156
157typedef struct {
158 volatile uint32_t cr;
159 volatile uint32_t mr;
160 volatile uint32_t ier;
161 volatile uint32_t idr;
162 volatile uint32_t imr;
163 volatile uint32_t sr;
164 volatile uint32_t rhr;
165 volatile uint32_t thr;
166 volatile uint32_t brgr;
167 volatile uint32_t _res0[7];
168 volatile uint32_t cidr;
169 volatile uint32_t exid;
170 volatile uint32_t fnr;
171} at91rm9200_usart_regs_t;
172
173#endif /* __AT91RM9200_USART_H__ */
bits.h
Contains bit position definitions.
at91rm9200_usart_regs_t
Definition: at91rm9200_usart.h:157
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