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at91rm9200.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
13/*
14 * Copyright (c) 2003 by Cogent Computer Systems
15 * Written by Mike Kelly <mike@cogcomp.com>
16 * Modified by Fernando Nicodemos <fgnicodemos@terra.com.br>
17 * from NCB - Sistemas Embarcados Ltda. (Brazil)
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
21 * are met:
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
32 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 */
40
41#ifndef __AT91RM9200_H__
42#define __AT91RM9200_H__
43
44#include "bits.h"
45
46typedef volatile unsigned long vulong;
47
48/* Source Mode Register - 32 of them */
49#define AIC_SMR_BASE 0xFFFFF000
50#define AIC_SMR_REG(_x_) *(vulong *)(AIC_SMR_BASE + (_x_ & 0x7c))
51
52/* Source Vector Register - 32 of them */
53#define AIC_SVR_BASE 0xFFFFF080
54#define AIC_SVR_REG(_x_) *(vulong *)(AIC_SVR_BASE + (_x_ & 0x7c))
55
56/* Control Register - 32 of them */
57#define AIC_CTL_BASE 0xFFFFF100
58#define AIC_CTL_REG(_x_) *(vulong *)(AIC_CTL_BASE + (_x_ & 0x7f))
59
60/* Register Offsets */
61/* offsets from AIC_SMR_BASE and AIC_SVR_BASE */
62#define AIC_SMR_FIQ 0x00 /* Advanced Interrupt Controller FIQ */
63#define AIC_SMR_SYSIRQ 0x04 /* Advanced Interrupt Controller SYSIRQ */
64#define AIC_SMR_PIOA 0x08 /* Parallel I/O Controller A */
65#define AIC_SMR_PIOB 0x0c /* Parallel I/O Controller B */
66#define AIC_SMR_PIOC 0x10 /* Parallel I/O Controller C */
67#define AIC_SMR_PIOD 0x14 /* Parallel I/O Controller D */
68#define AIC_SMR_US0 0x18 /* USART 0 */
69#define AIC_SMR_US1 0x1c /* USART 1 */
70#define AIC_SMR_US2 0x20 /* USART 2 */
71#define AIC_SMR_US3 0x24 /* USART 3 */
72#define AIC_SMR_MCI 0x28 /* Multimedia Card Interface */
73#define AIC_SMR_UDP 0x2c /* USB Device Port */
74#define AIC_SMR_TWI 0x30 /* Two-wire Interface */
75#define AIC_SMR_SPI 0x34 /* Serial Peripheral Interface */
76#define AIC_SMR_SSC0 0x38 /* Synchronous Serial Controller 0 */
77#define AIC_SMR_SSC1 0x3c /* Synchronous Serial Controller 1 */
78#define AIC_SMR_SSC2 0x40 /* Synchronous Serial Controller 2 */
79#define AIC_SMR_TC0 0x44 /* Timer/Counter 0 */
80#define AIC_SMR_TC1 0x48 /* Timer/Counter 1 */
81#define AIC_SMR_TC2 0x4c /* Timer/Counter 2 */
82#define AIC_SMR_TC3 0x50 /* Timer/Counter 3 */
83#define AIC_SMR_TC4 0x54 /* Timer/Counter 4 */
84#define AIC_SMR_TC5 0x58 /* Timer/Counter 5 */
85#define AIC_SMR_UHP 0x5c /* USB Host Port */
86#define AIC_SMR_EMAC 0x60 /* Ethernet MAC */
87#define AIC_SMR_IRQ0 0x64 /* Advanced Interrupt Controller IRQ0 */
88#define AIC_SMR_IRQ1 0x68 /* Advanced Interrupt Controller IRQ1 */
89#define AIC_SMR_IRQ2 0x6c /* Advanced Interrupt Controller IRQ2 */
90#define AIC_SMR_IRQ3 0x70 /* Advanced Interrupt Controller IRQ3 */
91#define AIC_SMR_IRQ4 0x74 /* Advanced Interrupt Controller IRQ4 */
92#define AIC_SMR_IRQ5 0x78 /* Advanced Interrupt Controller IRQ5 */
93#define AIC_SMR_IRQ6 0x7c /* Advanced Interrupt Controller IRQ6 */
94
95/* from AIC_CTL_BASE */
96#define AIC_IVR 0x00 /* IRQ Vector Register */
97#define AIC_FVR 0x04 /* FIQ Vector Register */
98#define AIC_ISR 0x08 /* Interrupt Status Register */
99#define AIC_IPR 0x0C /* Interrupt Pending Register */
100#define AIC_IMR 0x10 /* Interrupt Mask Register */
101#define AIC_CISR 0x14 /* Core Interrupt Status Register */
102#define AIC_IECR 0x20 /* Interrupt Enable Command Register */
103#define AIC_IDCR 0x24 /* Interrupt Disable Command Register */
104#define AIC_ICCR 0x28 /* Interrupt Clear Command Register */
105#define AIC_ISCR 0x2C /* Interrupt Set Command Register */
106#define AIC_EOICR 0x30 /* End of Interrupt Command Register */
107#define AIC_SPU 0x34 /* Spurious Vector Register */
108#define AIC_DCR 0x38 /* Debug Control Register (Protect) */
109#define AIC_FFER 0x40 /* Fast Forcing Enable Register */
110#define AIC_FFDR 0x44 /* Fast Forcing Disable Register */
111#define AIC_FFSR 0x48 /* Fast Forcing Status Register */
112
113/* Bit Defines */
114/* AIC_ISR - Interrupt Status Register */
115#define AIC_ISR_IRQID_MASK 0x1f /* current interrupt ID */
116
117/* AIC_CISR - Core Interrupt Status Register */
118#define AIC_CISR_IRQ BIT1 /* 1 = Core IRQ is active */
119#define AIC_CISR_FIQ BIT0 /* 1 = Core FIQ is active */
120
121/* AIC_DCR - Debug Control Register (Protect) */
122#define AIC_DCR_GMSK BIT1 /* 0 = AIC controls IRQ and FIQ */
123#define AIC_DCR_PROT BIT0 /* 1 = enable protection mode */
124
125/* AIC_SMR */
126#define AIC_SMR_PRIOR(_x_) ((_x_ & 0x07) << 0)
127#define AIC_SMR_SRC_LVL_LOW (0 << 5) /* Are these right? docs don't say which is high/low */
128#define AIC_SMR_SRC_EDGE_LOW (1 << 5)
129#define AIC_SMR_SRC_LVL_HI (2 << 5)
130#define AIC_SMR_SRC_EDGE_HI (3 << 5)
131
132/**************************************************************************/
133/* Debug Unit */
134/**************************************************************************/
135#define DBGU_BASE 0xFFFFF200
136#define DBGU_REG(_x_) *(vulong *)(DBGU_BASE + _x_)
137
138/* Register Offsets */
139#define DBGU_CR 0x00 /* Control Register */
140#define DBGU_MR 0x04 /* Mode Register */
141#define DBGU_IER 0x08 /* Interrupt Enable Register */
142#define DBGU_IDR 0x0C /* Interrupt Disable Register */
143#define DBGU_IMR 0x10 /* Interrupt Mask Register */
144#define DBGU_CSR 0x14 /* Channel Status Register */
145#define DBGU_RHR 0x18 /* Receiver Holding Register */
146#define DBGU_THR 0x1C /* Transmitter Holding Register */
147#define DBGU_BRGR 0x20 /* Baud Rate Generator Register */
148#define DBGU_C1R 0x40 /* Chip ID1 Register */
149#define DBGU_C2R 0x44 /* Chip ID2 Register */
150#define DBGU_FNTR 0x48 /* Force NTRST Register */
151
152/**************************************************************************/
153/* USART 0-3 */
154/**************************************************************************/
155#define USART0_BASE 0xFFFC0000
156#define USART1_BASE 0xFFFC4000
157#define USART2_BASE 0xFFFC8000
158#define USART3_BASE 0xFFFCC000
159/*
160 * WARNING: The USART3_BASE at the AT91RM9200 Manual is wrong!!!
161 * Manual revision: Rev. 1768H-ATARM-16-Jun-09
162 * USART3_BASE is NOT 0xFFECC000
163 */
164
165/****************/
166/* System Timer */
167/****************/
168#define ST_BASE 0xFFFFFD00
169#define ST_REG(_x_) *(vulong *)(ST_BASE + _x_)
170
171/* Register Offsets */
172#define ST_CR 0x00 /* Control Register */
173#define ST_PIMR 0x04 /* Period Interval Mode Register */
174#define ST_WDMR 0x08 /* Watchdog Mode Register */
175#define ST_RTMR 0x0C /* Real-time Mode Register */
176#define ST_SR 0x10 /* Status Register */
177#define ST_IER 0x14 /* Interrupt Enable Register */
178#define ST_IDR 0x18 /* Interrupt Disable Register */
179#define ST_IMR 0x1C /* Interrupt Mask Register */
180#define ST_RTAR 0x20 /* Real-time Alarm Register */
181#define ST_CRTR 0x24 /* Current Real-time Register */
182
183/* Bit Defines */
184/* ST_CR - Control Register */
185#define ST_CR_WDRST BIT0 /* write 1 to reload WD counter */
186
187/* ST_PIMR - Period Interval Mode Register */
188#define ST_PIMR_PIV_MASK 0x0000ffff
189
190/* ST_WDMR - Watchdog Mode Register */
191#define ST_WDMR_EXTEN BIT17 /* WDOVF is not implemented on AT91RM9200 */
192#define ST_WDMR_RSTEN BIT16 /* 1 = reset the AT91RM9200 when WD overflows */
193#define ST_WDMR_WDV_MASK 0x0000ffff /* WD counter is in the lower 16-bits */
194
195/* ST_RTMR - Real-time Mode Register */
196#define ST_RTMR_RTPRES_MASK 0x0000ffff /* Real-Time Prescaler */
197
198/* ST_SR - Status Register - Read Only */
199/* ST_IER - Interrupt Enable Register - Write Only */
200/* ST_IDR - Interrupt Disable Register - Write Only */
201/* ST_IMR - Interrupt Mask Register - Read Only */
202#define ST_SR_ALMS BIT3
203#define ST_SR_RTTINC BIT2
204#define ST_SR_WDOVF BIT1
205#define ST_SR_PITS BIT0
206
207/* ST_RTAR - Real-time Alarm Register */
208#define ST_RTAR_ALMV_MASK 0x000fffff
209
210/* ST_CRTR - Current Real-time Register */
211#define ST_CRTR_CRTV_MASK 0x000fffff
212
213
214/**************************************************************************
215 * Peripheral Data Control (DMA)
216 * Note that each of the following peripherals has it's own
217 * set of these registers starting at offset 0x100 from it's
218 * base address: DBGU, SPI, USART and SSC
219 * To access the DMA for a peripheral, use the macro for that
220 * peripheral but with these register offsets
221 **************************************************************************/
222/* Register Offsets */
223#define PDC_RPR 0x100 /* Receive Pointer Register */
224#define PDC_RCR 0x104 /* Receive Counter Register */
225#define PDC_TPR 0x108 /* Transmit Pointer Register */
226#define PDC_TCR 0x10c /* Transmit Counter Register */
227#define PDC_RNPR 0x110 /* Receive Next Pointer Register */
228#define PDC_RNCR 0x114 /* Receive Next Counter Register */
229#define PDC_TNPR 0x118 /* Transmit Next Pointer Register */
230#define PDC_TNCR 0x11c /* Transmit Next Counter Register */
231#define PDC_PTCR 0x120 /* PDC Transfer Control Register */
232#define PDC_PTSR 0x124 /* PDC Transfer Status Register */
233
234/**************************************************************************
235 * Parallel I/O Unit
236 * There are four PIO blocks - A, B, C and D. They all have the
237 * same register set, but different base addresses
238 **************************************************************************/
239/* Port A */
240#define PIOA_BASE 0xFFFFF400
241#define PIOA_REG(_x_) *(vulong *)(PIOA_BASE + _x_)
242
243/* Port B */
244#define PIOB_BASE 0xFFFFF600
245#define PIOB_REG(_x_) *(vulong *)(PIOB_BASE + _x_)
246
247/* Port C */
248#define PIOC_BASE 0xFFFFF800
249#define PIOC_REG(_x_) *(vulong *)(PIOC_BASE + _x_)
250
251/* Port D */
252#define PIOD_BASE 0xFFFFFA00
253#define PIOD_REG(_x_) *(vulong *)(PIOD_BASE + _x_)
254
255/**************************************************************************
256 * Power Management and Clock Control
257 *************************************************************************/
258#define PMC_BASE 0xFFFFFC00
259#define PMC_REG(_x_) *(vulong *)(PMC_BASE + _x_)
260
261/**************************************************************************
262 * MAC Unit
263 *************************************************************************/
264#define EMAC_BASE 0xFFFBC000
265#define EMAC_REG(_x_) *(vulong *)(EMAC_BASE + _x_)
266
267/**************************************************************************
268 * Timer/Counter Unit
269 **************************************************************************/
270#define TC_BASE 0xFFFA0000
271#define TC_REG(_x_) *(vulong *)(TC_BASE + 0x00 + _x_)
272#define TC_TC0_REG(_x_) *(vulong *)(TC_BASE + 0x00 + _x_)
273#define TC_TC1_REG(_x_) *(vulong *)(TC_BASE + 0x40 + _x_)
274#define TC_TC2_REG(_x_) *(vulong *)(TC_BASE + 0x80 + _x_)
275
276/* Offsets from TC_TC?_REG */
277#define TC_CCR 0x00 /* Channel Control Register */
278#define TC_CMR 0x04 /* Channel Mode Register */
279#define TC_CV 0x10 /* Counter Value */
280#define TC_RA 0x14 /* Register A */
281#define TC_RB 0x18 /* Register B */
282#define TC_RC 0x1C /* Register C */
283#define TC_SR 0x20 /* Status Register */
284#define TC_IER 0x24 /* Interrupt Enable Register */
285#define TC_IDR 0x28 /* Interrupt Disable Register */
286#define TC_IMR 0x2C /* Interrupt Mask Register */
287
288/* Offsets from TC_BASE */
289#define TC_BCR 0xc0 /* Channel Control Register */
290#define TC_BMR 0xc4 /* Channel Control Register */
291
292/* Block control register */
293#define TC_BCR_SYNC BIT1 /* Set to syncronize channels */
294
295/* Block mode register */
296#define TC_BMR_TC0(_x_) ((_x_ & 0x3) << 0) /* TC0 clock source */
297#define TC_BMR_TC1(_x_) ((_x_ & 0x3) << 2) /* TC1 clock source */
298#define TC_BMR_TC2(_x_) ((_x_ & 0x3) << 4) /* TC2 clock source */
299
300/* Channel Control register */
301#define TC_CCR_CLKEN BIT0 /* Enable clock */
302#define TC_CCR_CLKDIS BIT1 /* Disable clock */
303#define TC_CCR_SWTRG BIT2 /* Software trigger command */
304
305/* Channel mode register */
306#define TC_CMR_TCCLKS(_x_) ((_x_ & 0x7) << 0) /* Clock source */
307#define TC_CMR_CLKI BIT3 /* Clock invert */
308#define TC_BURST(_x_) ((_x_ & 0x3 << 4) /* Burst signal selection */
309#define TC_WAVE BIT15 /* 0 for catpure, 1 for wave */
310
311/* Channel mode register - capture mode (TC_WAVE = 0) */
312#define TC_CMR_LDBSTOP BIT6 /* Set to stop clock when RB loads */
313#define TC_CMR_LDBDIS BIT7 /* Set to disable clock when RB loads */
314#define TC_CMR_ETRGEDG(_x_) ((_x_ & 0x3) << 8) /* Select edge triggering mode */
315#define TC_CMR_ABETRG BIT10 /* Select ext trigger source */
316#define TC_CMR_CPCTRG BIT14 /* RC Compare trigger enable */
317#define TC_CMR_LDRA(_x_) ((_x_ & 0x3) << 16) /* RA loading selection */
318#define TC_CMR_LDRB(_x_) ((_x_ & 0x3) << 18) /* RB loading selection */
319
320/* Channel mode register - wave mode (TC_WAVE = 1) */
321#define TC_CMR_CPCSTOP BIT6 /* Clock stopped w/ RC compare */
322#define TC_CMR_CPCDIS BIT7 /* Clock disabled w/ RC compare */
323#define TC_CMR_EEVTEDG(_x_) ((_x_ & 0x3) << 8) /* Ext event edge selection */
324#define TC_CMR_EEVT(_x_) ((_x_ & 0x3) << 10) /* Ext event selection */
325#define TC_CMR_ENETRG BIT12 /* Ext event trigger enable */
326#define TC_CMR_WAVESEL(_x_) ((_x_ & 0x3) << 13) /* Waveform selection */
327#define TC_CMR_ACPA(_x_) ((_x_ & 0x3) << 16) /* RA compare effect on TIOA */
328#define TC_CMR_ACPC(_x_) ((_x_ & 0x3) << 18) /* RC compare effect on TIOA */
329#define TC_CMR_AEEVT(_x_) ((_x_ & 0x3) << 20) /* Ext event effect on TIOA */
330#define TC_CMR_ASWTRG(_x_) ((_x_ & 0x3) << 22) /* SW trigger effect on TIOA */
331#define TC_CMR_BCPB(_x_) ((_x_ & 0x3) << 24) /* RB compare effect on TIOB */
332#define TC_CMR_BCPC(_x_) ((_x_ & 0x3) << 26) /* RC compare effect on TIOB */
333#define TC_CMR_BEEVT(_x_) ((_x_ & 0x3) << 28) /* Ext event effect on TIOB */
334#define TC_CMR_BSWTRG(_x_) ((_x_ & 0x3) << 30) /* SW trigger effect on TIOB */
335
336/* Counter value */
337#define TC_CV_MASK 0xffff /* Timer counter mask */
338
339/* Status, Interrupt enable, Interrupt disable, and Interrupt mask registers */
340#define TC_SR_COVFS BIT0 /* Counter overflow status */
341#define TC_SR_LOVRS BIT1 /* Load overrun status */
342#define TC_SR_CPAS BIT2 /* RA compare status */
343#define TC_SR_CPBS BIT3 /* RB compare status */
344#define TC_SR_CPCS BIT4 /* RC compare status */
345#define TC_SR_LDRAS BIT5 /* RA loading status */
346#define TC_SR_LDRBS BIT6 /* RB loading status */
347#define TC_SR_ETRGS BIT7 /* External trigger status */
348#define TC_SR_CLKSTA BIT16 /* Clock enabling status */
349#define TC_SR_MTIOA BIT17 /* TIOA Mirror */
350#define TC_SR_MTIOB BIT18 /* TIOB Mirror */
351
352/***************************************************************************
353 * External Bus Interface Unit
354 **************************************************************************/
355#define EBI_BASE 0xFFFFFF60
356#define EBI_REG(_x_) *(vulong *)(EBI_BASE + _x_)
357
358/***************************************************************************
359 * Static Memory Interface Unit
360 ***************************************************************************/
361#define SMC_REG(_x_) *(vulong *)(EBI_BASE + 0x10 + _x_)
362
363/**************************************************************************
364 * SDRAM Memory Interface Unit
365 **************************************************************************/
366#define SDRC_REG(_x_) *(vulong *)(EBI_BASE + 0x30 + _x_)
367
368#endif /* __AT91RM9200_H__ */
369
bits.h
Contains bit position definitions.
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