RTEMS 7.0-rc1
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8xx_immap.h
1/* SPDX-License-Identifier: GPL-2.0+-with-RTEMS-exception */
2
3/*
4 * RTEMS BSP support for TQ modules
5 *
6 * This file contains definitions to interact with TQC's
7 * processor modules.
8 *
9 * derived from mbx8xx BSP
10 *
11 * MPC8xx Internal Memory Map
12 */
13
14/*
15 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
16 * Copyright (c) 2007 embedded brains GmbH & Co. KG
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23/*
24 * The I/O on the MPC860 is comprised of blocks of special registers
25 * and the dual port ram for the Communication Processor Module.
26 * Within this space are functional units such as the SIU, memory
27 * controller, system timers, and other control functions. It is
28 * a combination that I found difficult to separate into logical
29 * functional files.....but anyone else is welcome to try. -- Dan
30 */
31#ifndef __IMMAP_8XX__
32#define __IMMAP_8XX__
33
34/* System configuration registers.
35*/
36typedef struct sys_conf {
37 unsigned int sc_siumcr;
38 unsigned int sc_sypcr;
39 unsigned int sc_swt;
40 char res1[2];
41 unsigned short sc_swsr;
42 unsigned int sc_sipend;
43 unsigned int sc_simask;
44 unsigned int sc_siel;
45 unsigned int sc_sivec;
46 unsigned int sc_tesr;
47 char res2[0xc];
48 unsigned int sc_sdcr;
49 char res3[0x4c];
50} sysconf8xx_t;
51
52/* PCMCIA configuration registers.
53*/
54typedef struct pcmcia_conf {
55 unsigned int pcmc_pbr0;
56 unsigned int pcmc_por0;
57 unsigned int pcmc_pbr1;
58 unsigned int pcmc_por1;
59 unsigned int pcmc_pbr2;
60 unsigned int pcmc_por2;
61 unsigned int pcmc_pbr3;
62 unsigned int pcmc_por3;
63 unsigned int pcmc_pbr4;
64 unsigned int pcmc_por4;
65 unsigned int pcmc_pbr5;
66 unsigned int pcmc_por5;
67 unsigned int pcmc_pbr6;
68 unsigned int pcmc_por6;
69 unsigned int pcmc_pbr7;
70 unsigned int pcmc_por7;
71 char res1[0x20];
72 unsigned int pcmc_pgcra;
73 unsigned int pcmc_pgcrb;
74 unsigned int pcmc_pscr;
75 char res2[4];
76 unsigned int pcmc_pipr;
77 char res3[4];
78 unsigned int pcmc_per;
79 char res4[4];
80} pcmconf8xx_t;
81
82/* Memory controller registers.
83*/
84typedef struct mem_ctlr {
85 unsigned int memc_br0;
86 unsigned int memc_or0;
87 unsigned int memc_br1;
88 unsigned int memc_or1;
89 unsigned int memc_br2;
90 unsigned int memc_or2;
91 unsigned int memc_br3;
92 unsigned int memc_or3;
93 unsigned int memc_br4;
94 unsigned int memc_or4;
95 unsigned int memc_br5;
96 unsigned int memc_or5;
97 unsigned int memc_br6;
98 unsigned int memc_or6;
99 unsigned int memc_br7;
100 unsigned int memc_or7;
101 char res1[0x24];
102 unsigned int memc_mar;
103 unsigned int memc_mcr;
104 char res2[4];
105 unsigned int memc_mamr;
106 unsigned int memc_mbmr;
107 unsigned short memc_mstat;
108 unsigned short memc_mptpr;
109 unsigned int memc_mdr;
110 char res3[0x80];
111} memctl8xx_t;
112
113/* System Integration Timers.
114*/
115typedef struct sys_int_timers {
116 unsigned short sit_tbscr;
117 unsigned int sit_tbreff0;
118 unsigned int sit_tbreff1;
119 char res1[0x14];
120 unsigned short sit_rtcsc;
121 unsigned int sit_rtc;
122 unsigned int sit_rtsec;
123 unsigned int sit_rtcal;
124 char res2[0x10];
125 unsigned short sit_piscr;
126 char res3[2];
127 unsigned int sit_pitc;
128 unsigned int sit_pitr;
129 char res4[0x34];
130} sit8xx_t;
131
132#define TBSCR_TBIRQ_MASK ((unsigned short)0xff00)
133#define TBSCR_REFA ((unsigned short)0x0080)
134#define TBSCR_REFB ((unsigned short)0x0040)
135#define TBSCR_REFAE ((unsigned short)0x0008)
136#define TBSCR_REFBE ((unsigned short)0x0004)
137#define TBSCR_TBF ((unsigned short)0x0002)
138#define TBSCR_TBE ((unsigned short)0x0001)
139
140#define RTCSC_RTCIRQ_MASK ((unsigned short)0xff00)
141#define RTCSC_SEC ((unsigned short)0x0080)
142#define RTCSC_ALR ((unsigned short)0x0040)
143#define RTCSC_38K ((unsigned short)0x0010)
144#define RTCSC_SIE ((unsigned short)0x0008)
145#define RTCSC_ALE ((unsigned short)0x0004)
146#define RTCSC_RTF ((unsigned short)0x0002)
147#define RTCSC_RTE ((unsigned short)0x0001)
148
149#define PISCR_PIRQ_MASK ((unsigned short)0xff00)
150#define PISCR_PS ((unsigned short)0x0080)
151#define PISCR_PIE ((unsigned short)0x0004)
152#define PISCR_PTF ((unsigned short)0x0002)
153#define PISCR_PTE ((unsigned short)0x0001)
154
155/* Clocks and Reset.
156*/
157typedef struct clk_and_reset {
158 unsigned int car_sccr;
159 unsigned int car_plprcr;
160 unsigned int car_rsr;
161 char res[0x74]; /* Reserved area */
162} car8xx_t;
163
164/* System Integration Timers keys.
165*/
166typedef struct sitk {
167 unsigned int sitk_tbscrk;
168 unsigned int sitk_tbreff0k;
169 unsigned int sitk_tbreff1k;
170 unsigned int sitk_tbk;
171 char res1[0x10];
172 unsigned int sitk_rtcsck;
173 unsigned int sitk_rtck;
174 unsigned int sitk_rtseck;
175 unsigned int sitk_rtcalk;
176 char res2[0x10];
177 unsigned int sitk_piscrk;
178 unsigned int sitk_pitck;
179 char res3[0x38];
180} sitk8xx_t;
181
182/* Clocks and reset keys.
183*/
184typedef struct cark {
185 unsigned int cark_sccrk;
186 unsigned int cark_plprcrk;
187 unsigned int cark_rsrk;
188 char res[0x474];
189} cark8xx_t;
190
191/* The key to unlock registers maintained by keep-alive power.
192*/
193#define KAPWR_KEY ((unsigned int)0x55ccaa33)
194
195/* LCD interface. MPC821 Only.
196*/
197typedef struct lcd {
198 unsigned short lcd_lcolr[16];
199 char res[0x20];
200 unsigned int lcd_lccr;
201 unsigned int lcd_lchcr;
202 unsigned int lcd_lcvcr;
203 char res2[4];
204 unsigned int lcd_lcfaa;
205 unsigned int lcd_lcfba;
206 char lcd_lcsr;
207 char res3[0x7];
208} lcd8xx_t;
209
210/* I2C
211*/
212typedef struct i2c {
213 unsigned char i2c_i2mod;
214 char res1[3];
215 unsigned char i2c_i2add;
216 char res2[3];
217 unsigned char i2c_i2brg;
218 char res3[3];
219 unsigned char i2c_i2com;
220 char res4[3];
221 unsigned char i2c_i2cer;
222 char res5[3];
223 unsigned char i2c_i2cmr;
224 char res6[0x8b];
225} i2c8xx_t;
226
227/* DMA control/status registers.
228*/
229typedef struct sdma_csr {
230 char res1[4];
231 unsigned int sdma_sdar;
232 unsigned char sdma_sdsr;
233 char res3[3];
234 unsigned char sdma_sdmr;
235 char res4[3];
236 unsigned char sdma_idsr1;
237 char res5[3];
238 unsigned char sdma_idmr1;
239 char res6[3];
240 unsigned char sdma_idsr2;
241 char res7[3];
242 unsigned char sdma_idmr2;
243 char res8[0x13];
244} sdma8xx_t;
245
246/* Communication Processor Module Interrupt Controller.
247*/
248typedef struct cpm_ic {
249 unsigned short cpic_civr;
250 char res[0xe];
251 unsigned int cpic_cicr;
252 unsigned int cpic_cipr;
253 unsigned int cpic_cimr;
254 unsigned int cpic_cisr;
255} cpic8xx_t;
256
257/* Input/Output Port control/status registers.
258*/
259typedef struct io_port {
260 unsigned short iop_padir;
261 unsigned short iop_papar;
262 unsigned short iop_paodr;
263 unsigned short iop_padat;
264 char res1[8];
265 unsigned short iop_pcdir;
266 unsigned short iop_pcpar;
267 unsigned short iop_pcso;
268 unsigned short iop_pcdat;
269 unsigned short iop_pcint;
270 char res2[6];
271 unsigned short iop_pddir;
272 unsigned short iop_pdpar;
273 char res3[2];
274 unsigned short iop_pddat;
275 char res4[8];
276} iop8xx_t;
277
278/* Communication Processor Module Timers
279*/
280typedef struct cpm_timers {
281 unsigned short cpmt_tgcr;
282 char res1[0xe];
283 unsigned short cpmt_tmr1;
284 unsigned short cpmt_tmr2;
285 unsigned short cpmt_trr1;
286 unsigned short cpmt_trr2;
287 unsigned short cpmt_tcr1;
288 unsigned short cpmt_tcr2;
289 unsigned short cpmt_tcn1;
290 unsigned short cpmt_tcn2;
291 unsigned short cpmt_tmr3;
292 unsigned short cpmt_tmr4;
293 unsigned short cpmt_trr3;
294 unsigned short cpmt_trr4;
295 unsigned short cpmt_tcr3;
296 unsigned short cpmt_tcr4;
297 unsigned short cpmt_tcn3;
298 unsigned short cpmt_tcn4;
299 unsigned short cpmt_ter1;
300 unsigned short cpmt_ter2;
301 unsigned short cpmt_ter3;
302 unsigned short cpmt_ter4;
303 char res2[8];
304} cpmtimer8xx_t;
305
306/* Finally, the Communication Processor stuff.....
307*/
308typedef struct scc { /* Serial communication channels */
309 unsigned int scc_gsmrl;
310 unsigned int scc_gsmrh;
311 unsigned short scc_pmsr;
312 char res1[2];
313 unsigned short scc_todr;
314 unsigned short scc_dsr;
315 unsigned short scc_scce;
316 char res2[2];
317 unsigned short scc_sccm;
318 char res3;
319 unsigned char scc_sccs;
320 char res4[8];
321} scc_t;
322
323typedef struct smc { /* Serial management channels */
324 char res1[2];
325 unsigned short smc_smcmr;
326 char res2[2];
327 unsigned char smc_smce;
328 char res3[3];
329 unsigned char smc_smcm;
330 char res4[5];
331} smc_t;
332
333/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but
334 * it fits within the address space.
335 */
336typedef struct fec {
337 unsigned int fec_addr_low; /* LS 32 bits of station address */
338 unsigned short fec_addr_high; /* MS 16 bits of address */
339 unsigned short res1;
340 unsigned int fec_hash_table_high;
341 unsigned int fec_hash_table_low;
342 unsigned int fec_r_des_start;
343 unsigned int fec_x_des_start;
344 unsigned int fec_r_buff_size;
345 unsigned int res2[9];
346 unsigned int fec_ecntrl;
347 unsigned int fec_ievent;
348 unsigned int fec_imask;
349 unsigned int fec_ivec;
350 unsigned int fec_r_des_active;
351 unsigned int fec_x_des_active;
352 unsigned int res3[10];
353 unsigned int fec_mii_data;
354 unsigned int fec_mii_speed;
355 unsigned int res4[17];
356 unsigned int fec_r_bound;
357 unsigned int fec_r_fstart;
358 unsigned int res5[6];
359 unsigned int fec_x_fstart;
360 unsigned int res6[17];
361 unsigned int fec_fun_code;
362 unsigned int res7[3];
363 unsigned int fec_r_cntrl;
364 unsigned int fec_r_hash;
365 unsigned int res8[14];
366 unsigned int fec_x_cntrl;
367 unsigned int res9[0x1e];
368} fec_t;
369
370typedef struct comm_proc {
371 /* General control and status registers.
372 */
373 unsigned short cp_cpcr;
374 char res1[2];
375 unsigned short cp_rccr;
376 char res2[6];
377 unsigned short cp_cpmcr1;
378 unsigned short cp_cpmcr2;
379 unsigned short cp_cpmcr3;
380 unsigned short cp_cpmcr4;
381 char res3[2];
382 unsigned short cp_rter;
383 char res4[2];
384 unsigned short cp_rtmr;
385 char res5[0x14];
386
387 /* Baud rate generators.
388 */
389 unsigned int cp_brgc1;
390 unsigned int cp_brgc2;
391 unsigned int cp_brgc3;
392 unsigned int cp_brgc4;
393
394 /* Serial Communication Channels.
395 */
396 scc_t cp_scc[4];
397
398 /* Serial Management Channels.
399 */
400 smc_t cp_smc[2];
401
402 /* Serial Peripheral Interface.
403 */
404 unsigned short cp_spmode;
405 char res6[4];
406 unsigned char cp_spie;
407 char res7[3];
408 unsigned char cp_spim;
409 char res8[2];
410 unsigned char cp_spcom;
411 char res9[2];
412
413 /* Parallel Interface Port.
414 */
415 char res10[2];
416 unsigned short cp_pipc;
417 char res11[2];
418 unsigned short cp_ptpr;
419 unsigned int cp_pbdir;
420 unsigned int cp_pbpar;
421 char res12[2];
422 unsigned short cp_pbodr;
423 unsigned int cp_pbdat;
424 char res13[0x18];
425
426 /* Serial Interface and Time Slot Assignment.
427 */
428 unsigned int cp_simode;
429 unsigned char cp_sigmr;
430 char res14;
431 unsigned char cp_sistr;
432 unsigned char cp_sicmr;
433 char res15[4];
434 unsigned int cp_sicr;
435 unsigned int cp_sirp;
436 char res16[0x10c];
437 unsigned char cp_siram[0x200];
438
439 /* The fast ethernet controller is not really part of the CPM,
440 * but it resides in the address space.
441 */
442 fec_t cp_fec;
443 char res18[0x1000];
444
445 /* Dual Ported RAM follows.
446 * There are many different formats for this memory area
447 * depending upon the devices used and options chosen.
448 */
449 unsigned char cp_dpmem[0x1000]; /* BD / Data / ucode */
450 unsigned char res19[0xc00];
451 unsigned char cp_dparam[0x400]; /* Parameter RAM */
452} cpm8xx_t;
453
454/* Internal memory map.
455*/
456typedef struct immap {
457 sysconf8xx_t im_siu_conf; /* SIU Configuration */
458 pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */
459 memctl8xx_t im_memctl; /* Memory Controller */
460 sit8xx_t im_sit; /* System integration timers */
461 car8xx_t im_clkrst; /* Clocks and reset */
462 sitk8xx_t im_sitk; /* Sys int timer keys */
463 cark8xx_t im_clkrstk; /* Clocks and reset keys */
464 lcd8xx_t im_lcd; /* LCD (821 only) */
465 i2c8xx_t im_i2c; /* I2C control/status */
466 sdma8xx_t im_sdma; /* SDMA control/status */
467 cpic8xx_t im_cpic; /* CPM Interrupt Controller */
468 iop8xx_t im_ioport; /* IO Port control/status */
469 cpmtimer8xx_t im_cpmtimer; /* CPM timers */
470 cpm8xx_t im_cpm; /* Communication processor */
471} immap_t;
472
473#endif /* __IMMAP_8XX__ */
cark
Definition: 8xx_immap.h:184
clk_and_reset
Definition: 8xx_immap.h:157
comm_proc
Definition: 8xx_immap.h:370
cpm_ic
Definition: 8xx_immap.h:248
cpm_timers
Definition: 8xx_immap.h:280
fec
Definition: 8xx_immap.h:336
i2c
Definition: 8xx_immap.h:212
immap
Definition: 8xx_immap.h:456
io_port
Definition: 8xx_immap.h:259
lcd
Definition: 8xx_immap.h:197
mem_ctlr
Definition: 8xx_immap.h:84
pcmcia_conf
Definition: 8xx_immap.h:54
scc
Definition: 8xx_immap.h:308
sdma_csr
Definition: 8xx_immap.h:229
sitk
Definition: 8xx_immap.h:166
smc
Definition: 8xx_immap.h:323
sys_conf
Definition: 8xx_immap.h:36
sys_int_timers
Definition: 8xx_immap.h:115
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