51#ifndef _RTEMS_SCORE_CPU_H
52#define _RTEMS_SCORE_CPU_H
55#if defined(RTEMS_PARAVIRT)
56#include <rtems/score/paravirt.h>
66#if defined(ARM_MULTILIB_ARCH_V4)
68#if defined(__thumb__) && !defined(__thumb2__)
69 #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg
70 #define ARM_SWITCH_TO_ARM ".align 2\nbx pc\n.arm\n"
71 #define ARM_SWITCH_BACK "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n"
72 #define ARM_SWITCH_OUTPUT [arm_switch_reg] "=&r" (arm_switch_reg)
73 #define ARM_SWITCH_ADDITIONAL_OUTPUT , ARM_SWITCH_OUTPUT
75 #define ARM_SWITCH_REGISTERS
76 #define ARM_SWITCH_TO_ARM
77 #define ARM_SWITCH_BACK
78 #define ARM_SWITCH_OUTPUT
79 #define ARM_SWITCH_ADDITIONAL_OUTPUT
87#define ARM_PSR_N (1 << 31)
88#define ARM_PSR_Z (1 << 30)
89#define ARM_PSR_C (1 << 29)
90#define ARM_PSR_V (1 << 28)
91#define ARM_PSR_Q (1 << 27)
92#define ARM_PSR_J (1 << 24)
93#define ARM_PSR_GE_SHIFT 16
94#define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT)
95#define ARM_PSR_E (1 << 9)
96#define ARM_PSR_A (1 << 8)
97#define ARM_PSR_I (1 << 7)
98#define ARM_PSR_F (1 << 6)
99#define ARM_PSR_T (1 << 5)
100#define ARM_PSR_M_SHIFT 0
101#define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT)
102#define ARM_PSR_M_USR 0x10
103#define ARM_PSR_M_FIQ 0x11
104#define ARM_PSR_M_IRQ 0x12
105#define ARM_PSR_M_SVC 0x13
106#define ARM_PSR_M_ABT 0x17
107#define ARM_PSR_M_HYP 0x1a
108#define ARM_PSR_M_UND 0x1b
109#define ARM_PSR_M_SYS 0x1f
118#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
120#define CPU_ISR_PASSES_FRAME_POINTER FALSE
122#define CPU_HARDWARE_FP FALSE
124#define CPU_SOFTWARE_FP FALSE
126#define CPU_ALL_TASKS_ARE_FP FALSE
128#define CPU_IDLE_TASK_IS_FP FALSE
130#define CPU_USE_DEFERRED_FP_SWITCH FALSE
132#define CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE
134#define CPU_STACK_GROWS_UP FALSE
136#if defined(ARM_MULTILIB_CACHE_LINE_MAX_64)
137 #define CPU_CACHE_LINE_BYTES 64
139 #define CPU_CACHE_LINE_BYTES 32
142#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
144#define CPU_MODES_INTERRUPT_MASK 0x1
146#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
148#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
150#define CPU_STACK_MINIMUM_SIZE (1024 * 4)
153#define CPU_SIZEOF_POINTER 4
156#define CPU_ALIGNMENT 8
158#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
161#define CPU_STACK_ALIGNMENT 8
163#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
176#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
178#define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE
180#define CPU_MAXIMUM_PROCESSORS 32
182#define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44
184#ifdef ARM_MULTILIB_VFP
185 #define ARM_CONTEXT_CONTROL_D8_OFFSET 48
188#ifdef ARM_MULTILIB_ARCH_V4
189 #define ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 40
193 #if defined(ARM_MULTILIB_VFP)
194 #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112
196 #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48
200#define ARM_EXCEPTION_FRAME_SIZE 80
202#define ARM_EXCEPTION_FRAME_REGISTER_R8_OFFSET 32
204#define ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET 52
206#define ARM_EXCEPTION_FRAME_REGISTER_PC_OFFSET 60
208#if defined(ARM_MULTILIB_ARCH_V4)
209 #define ARM_EXCEPTION_FRAME_REGISTER_CPSR_OFFSET 64
210#elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M)
211 #define ARM_EXCEPTION_FRAME_REGISTER_XPSR_OFFSET 64
214#define ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET 72
216#define ARM_VFP_CONTEXT_SIZE 264
225#if defined(ARM_MULTILIB_ARCH_V4)
226 uint32_t register_r4;
227 uint32_t register_r5;
228 uint32_t register_r6;
229 uint32_t register_r7;
230 uint32_t register_r8;
231 uint32_t register_r9;
232 uint32_t register_r10;
233 uint32_t register_fp;
234 uint32_t register_sp;
235 uint32_t register_lr;
236 uint32_t isr_dispatch_disable;
237#elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M)
238 uint32_t register_r4;
239 uint32_t register_r5;
240 uint32_t register_r6;
241 uint32_t register_r7;
242 uint32_t register_r8;
243 uint32_t register_r9;
244 uint32_t register_r10;
245 uint32_t register_r11;
248 uint32_t isr_nest_level;
253#ifdef ARM_MULTILIB_VFP
254 uint64_t register_d8;
255 uint64_t register_d9;
256 uint64_t register_d10;
257 uint64_t register_d11;
258 uint64_t register_d12;
259 uint64_t register_d13;
260 uint64_t register_d14;
261 uint64_t register_d15;
264 volatile bool is_executing;
268static inline void _ARM_Data_memory_barrier(
void )
270#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS
271 __asm__
volatile (
"dmb" : : :
"memory" );
277static inline void _ARM_Data_synchronization_barrier(
void )
279#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS
280 __asm__
volatile (
"dsb" : : :
"memory" );
286static inline void _ARM_Instruction_synchronization_barrier(
void )
288#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS
289 __asm__
volatile (
"isb" : : :
"memory" );
295#if defined(ARM_DISABLE_INLINE_ISR_DISABLE_ENABLE)
296uint32_t arm_interrupt_disable(
void );
297void arm_interrupt_enable( uint32_t level );
298void arm_interrupt_flash( uint32_t level );
300static inline uint32_t arm_interrupt_disable(
void )
304#if defined(ARM_MULTILIB_ARCH_V4)
327 uint32_t arm_switch_reg;
331 "mrs %[level], cpsr\n"
332 "orr %[arm_switch_reg], %[level], #0x80\n"
333 "msr cpsr, %[arm_switch_reg]\n"
335 : [arm_switch_reg]
"=&r" (arm_switch_reg), [level]
"=&r" (level)
338#elif defined(ARM_MULTILIB_ARCH_V7M)
339 uint32_t basepri = 0x80;
342 "mrs %[level], basepri\n"
343 "msr basepri_max, %[basepri]\n"
344 : [level]
"=&r" (level)
345 : [basepri]
"r" (basepri)
352static inline void arm_interrupt_enable( uint32_t level )
354#if defined(ARM_MULTILIB_ARCH_V4)
355 ARM_SWITCH_REGISTERS;
359 "msr cpsr, %[level]\n"
362 : [level]
"r" (level)
364#elif defined(ARM_MULTILIB_ARCH_V7M)
366 "msr basepri, %[level]\n"
368 : [level]
"r" (level)
373static inline void arm_interrupt_flash( uint32_t level )
375#if defined(ARM_MULTILIB_ARCH_V4)
376 uint32_t arm_switch_reg;
380 "mrs %[arm_switch_reg], cpsr\n"
381 "msr cpsr, %[level]\n"
382 "msr cpsr, %[arm_switch_reg]\n"
384 : [arm_switch_reg]
"=&r" (arm_switch_reg)
385 : [level]
"r" (level)
387#elif defined(ARM_MULTILIB_ARCH_V7M)
391 "mrs %[basepri], basepri\n"
392 "msr basepri, %[level]\n"
393 "msr basepri, %[basepri]\n"
394 : [basepri]
"=&r" (basepri)
395 : [level]
"r" (level)
401#define _CPU_ISR_Disable( _isr_cookie ) \
403 _isr_cookie = arm_interrupt_disable(); \
406#define _CPU_ISR_Enable( _isr_cookie ) \
407 arm_interrupt_enable( _isr_cookie )
409#define _CPU_ISR_Flash( _isr_cookie ) \
410 arm_interrupt_flash( _isr_cookie )
412static inline bool _CPU_ISR_Is_enabled( uint32_t level )
414#if defined(ARM_MULTILIB_ARCH_V4)
415 return ( level & 0x80 ) == 0;
416#elif defined(ARM_MULTILIB_ARCH_V7M)
425void _CPU_Context_Initialize(
427 void *stack_area_begin,
428 size_t stack_area_size,
430 void (*entry_point)(
void ),
435#define _CPU_Context_Get_SP( _context ) \
436 (_context)->register_sp
439 static inline bool _CPU_Context_Get_is_executing(
446 static inline void _CPU_Context_Set_is_executing(
451 context->is_executing = is_executing;
456 #define _CPU_Start_multitasking( _heir ) _ARM_Start_multitasking( _heir )
459#define _CPU_Context_Restart_self( _the_context ) \
460 _CPU_Context_restore( (_the_context) );
462#define _CPU_Context_Initialize_fp( _destination ) \
464 *(*(_destination)) = _CPU_Null_fp_context; \
472typedef void ( *CPU_ISR_handler )( void );
476 CPU_ISR_handler new_handler,
477 CPU_ISR_handler *old_handler
492#if defined(ARM_MULTILIB_ARCH_V7M)
494 #define _CPU_Start_multitasking _ARMV7M_Start_multitasking
498 uint32_t _CPU_SMP_Initialize(
void );
500 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
502 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
504 void _CPU_SMP_Prepare_start_multitasking(
void );
506 static inline uint32_t _CPU_SMP_Get_current_processor(
void )
512 "mrc p15, 0, %[mpidr], c0, c0, 5\n"
513 : [mpidr]
"=&r" (mpidr)
516 return mpidr & 0xffU;
519 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
521 static inline void _ARM_Send_event(
void )
523 __asm__
volatile (
"sev" : : :
"memory" );
526 static inline void _ARM_Wait_for_event(
void )
528 __asm__
volatile (
"wfe" : : :
"memory" );
533static inline uint32_t CPU_swap_u32( uint32_t value )
535#if defined(__thumb2__)
542#elif defined(__thumb__)
543 uint32_t byte1, byte2, byte3, byte4, swapped;
545 byte4 = (value >> 24) & 0xff;
546 byte3 = (value >> 16) & 0xff;
547 byte2 = (value >> 8) & 0xff;
548 byte1 = value & 0xff;
550 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
553 uint32_t tmp = value;
554 __asm__
volatile (
"EOR %1, %0, %0, ROR #16\n"
555 "BIC %1, %1, #0xff0000\n"
556 "MOV %0, %0, ROR #8\n"
557 "EOR %0, %0, %1, LSR #8\n"
558 :
"=r" (value),
"=r" (tmp)
559 :
"0" (value),
"1" (tmp));
566#if defined(__thumb2__)
574 return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU));
578typedef uint32_t CPU_Counter_ticks;
586#if defined(ARM_MULTILIB_ARCH_V4)
589 ARM_EXCEPTION_RESET = 0,
590 ARM_EXCEPTION_UNDEF = 1,
591 ARM_EXCEPTION_SWI = 2,
592 ARM_EXCEPTION_PREF_ABORT = 3,
593 ARM_EXCEPTION_DATA_ABORT = 4,
594 ARM_EXCEPTION_RESERVED = 5,
595 ARM_EXCEPTION_IRQ = 6,
596 ARM_EXCEPTION_FIQ = 7,
598 ARM_EXCEPTION_MAKE_ENUM_32_BIT = 0x7fffffff
599} Arm_symbolic_exception_name;
604 uint32_t register_fpexc;
605 uint32_t register_fpscr;
606 uint64_t register_d0;
607 uint64_t register_d1;
608 uint64_t register_d2;
609 uint64_t register_d3;
610 uint64_t register_d4;
611 uint64_t register_d5;
612 uint64_t register_d6;
613 uint64_t register_d7;
614 uint64_t register_d8;
615 uint64_t register_d9;
616 uint64_t register_d10;
617 uint64_t register_d11;
618 uint64_t register_d12;
619 uint64_t register_d13;
620 uint64_t register_d14;
621 uint64_t register_d15;
622 uint64_t register_d16;
623 uint64_t register_d17;
624 uint64_t register_d18;
625 uint64_t register_d19;
626 uint64_t register_d20;
627 uint64_t register_d21;
628 uint64_t register_d22;
629 uint64_t register_d23;
630 uint64_t register_d24;
631 uint64_t register_d25;
632 uint64_t register_d26;
633 uint64_t register_d27;
634 uint64_t register_d28;
635 uint64_t register_d29;
636 uint64_t register_d30;
637 uint64_t register_d31;
643 uint32_t register_r0;
644 uint32_t register_r1;
645 uint32_t register_r2;
646 uint32_t register_r3;
647 uint32_t register_r4;
648 uint32_t register_r5;
649 uint32_t register_r6;
650 uint32_t register_r7;
651 uint32_t register_r8;
652 uint32_t register_r9;
653 uint32_t register_r10;
654 uint32_t register_r11;
655 uint32_t register_r12;
656 uint32_t register_sp;
661 uint32_t registers[ 16 ];
663#if defined(ARM_MULTILIB_ARCH_V4)
664 uint32_t register_cpsr;
665 Arm_symbolic_exception_name vector;
666#elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M)
667 uint32_t register_xpsr;
671 uint32_t reserved_for_stack_alignment;
This header file provides defines derived from ARM multilib defines.
This header file provides basic definitions used by the API and the implementation.
#define RTEMS_COMPILER_MEMORY_BARRIER()
This macro forbids the compiler to reorder read and write commands around it.
Definition: basedefs.h:258
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
#define CPU_swap_u16(value)
Definition: cpu.h:597
#define _CPU_ISR_Set_level(_new_level)
Definition: cpu.h:378
rtems_termios_device_context * context
Definition: console-config.c:62
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Thread register context.
Definition: cpu.h:173