47#define APIC_BASE_MSR 0x1B
49#define APIC_BASE_MSR_ENABLE 0x800
51#define xAPIC_MAX_APIC_ID 0xFE
57#define LAPIC_OFFSET(val) (val >> 2)
59#define LAPIC_REGISTER_ID LAPIC_OFFSET(0x20)
60#define LAPIC_REGISTER_EOI LAPIC_OFFSET(0x0B0)
61#define LAPIC_REGISTER_SPURIOUS LAPIC_OFFSET(0x0F0)
62#define LAPIC_REGISTER_ICR_LOW LAPIC_OFFSET(0x300)
63#define LAPIC_REGISTER_ICR_HIGH LAPIC_OFFSET(0x310)
64#define LAPIC_REGISTER_LVT_TIMER LAPIC_OFFSET(0x320)
65#define LAPIC_REGISTER_TIMER_INITCNT LAPIC_OFFSET(0x380)
66#define LAPIC_REGISTER_TIMER_CURRCNT LAPIC_OFFSET(0x390)
67#define LAPIC_REGISTER_TIMER_DIV LAPIC_OFFSET(0x3E0)
69#define LAPIC_LVT_MASK 0x10000
71#define LAPIC_ICR_HIGH_MASK 0x00FFFFFF
72#define LAPIC_ICR_LOW_MASK 0xFFF32000
73#define LAPIC_ICR_DELIV_INIT 0x500
74#define LAPIC_ICR_DELIV_START 0x600
75#define LAPIC_ICR_DELIV_STAT_PEND 0x1000
76#define LAPIC_ICR_ASSERT 0x4000
77#define LAPIC_ICR_TRIG_LEVEL 0x8000
79#define LAPIC_EOI_ACK 0
80#define LAPIC_SELECT_TMR_PERIODIC 0x20000
81#define LAPIC_SPURIOUS_ENABLE 0x100
84#define LAPIC_TIMER_NUM_CALIBRATIONS 5
86#define LAPIC_TIMER_DIVIDE_VALUE 16
88#define LAPIC_TIMER_SELECT_DIVIDER 3
91#define PIT_FREQUENCY 1193180
97#define PIT_CALIBRATE_DIVIDER 20
98#define PIT_CALIBRATE_TICKS (PIT_FREQUENCY/PIT_CALIBRATE_DIVIDER)
105 PIT_CALIBRATE_TICKS <= 0xffff,
106 PIT_CALIBRATE_DIVIDER
110#define PIT_PORT_CHAN0 0x40
111#define PIT_PORT_CHAN1 0x41
112#define PIT_PORT_CHAN2 0x42
117#define PIT_PORT_CHAN2_GATE 0x61
118#define PIT_CHAN2_TIMER_BIT 1
119#define PIT_CHAN2_SPEAKER_BIT 2
121#define PIT_PORT_MCR 0x43
124#define PIT_SELECT_CHAN0 0b00000000
125#define PIT_SELECT_CHAN1 0b01000000
126#define PIT_SELECT_CHAN2 0b10000000
131#define PIT_SELECT_ACCESS_LOHI 0b00110000
132#define PIT_SELECT_ONE_SHOT_MODE 0b00000010
133#define PIT_SELECT_BINARY_MODE 0
135#define PIT_CHAN2_ENABLE(chan2_value) \
137 chan2_value = (inport_byte(PIT_PORT_CHAN2_GATE) | PIT_CHAN2_TIMER_BIT) \
138 & ~PIT_CHAN2_SPEAKER_BIT; \
139 outport_byte(PIT_PORT_CHAN2_GATE, chan2_value); \
143 PIT_SELECT_CHAN2 | PIT_SELECT_ACCESS_LOHI | \
144 PIT_SELECT_ONE_SHOT_MODE | PIT_SELECT_BINARY_MODE \
147#define PIT_CHAN2_WRITE_TICKS(pit_ticks) \
149 outport_byte(PIT_PORT_CHAN2, pit_ticks & 0xff); \
151 outport_byte(PIT_PORT_CHAN2, (pit_ticks >> 8) & 0xff); \
153#define PIT_CHAN2_START_DELAY(chan2_value) \
155 chan2_value &= ~PIT_CHAN2_TIMER_BIT; \
156 outport_byte(PIT_PORT_CHAN2_GATE, chan2_value); \
157 chan2_value |= PIT_CHAN2_TIMER_BIT; \
158 outport_byte(PIT_PORT_CHAN2_GATE, chan2_value); \
160#define PIT_CHAN2_WAIT_DELAY(pit_ticks) \
162 uint32_t curr_ticks = pit_ticks; \
163 while ( curr_ticks <= pit_ticks ) { \
165 outport_byte(PIT_PORT_MCR, PIT_SELECT_CHAN2); \
166 curr_ticks = inport_byte(PIT_PORT_CHAN2); \
167 curr_ticks |= inport_byte(PIT_PORT_CHAN2) << 8; \
171extern volatile uint32_t* amd64_lapic_base;
172extern uint8_t amd64_lapic_to_cpu_map[xAPIC_MAX_APIC_ID + 1];
208uint32_t lapic_get_num_of_procesors(
void);
216void lapic_send_ipi(uint32_t target_cpu_index, uint8_t
isr_vector);
224void lapic_start_ap(uint32_t cpu_index, uint8_t page_vector);
234 return amd64_lapic_base[LAPIC_REGISTER_ID]>>24;
242 amd64_lapic_base[LAPIC_REGISTER_EOI] = LAPIC_EOI_ACK;
This header file provides basic definitions used by the API and the implementation.
lpc176x_can_isr_vector isr_vector
Vector of isr for the can_driver .
Definition: can.c:37
#define RTEMS_STATIC_ASSERT(_cond, _msg)
It is defined if a static analysis run is performed.
Definition: basedefs.h:841
void lapic_eoi(void)
Signals an end of interrupt to the Local APIC.
Definition: apic.h:240
uint8_t lapic_get_id(void)
Retrieves the Local APIC ID.
Definition: apic.h:231
bool lapic_initialize(void)
Initializes the Local APIC by hardware and software enabling it.
Definition: apic.c:228
void lapic_timer_enable(uint32_t reload_value)
Enables the Local APIC timer.
Definition: apic.c:305
uint32_t lapic_timer_calc_ticks(uint64_t desired_freq_hz)
Calculates the number of Local APIC timer ticks which can be used with lapic_timer_enable to set up a...
Definition: apic.c:283