RTEMS 6.1-rc7
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Data Fields

Data Fields

__IO uint32_t TIMxCR
 
__IO uint32_t TIMxISR
 
__IO uint32_t TIMxICR
 
__IO uint32_t TIMxDIER
 
__IO uint32_t CNTxR
 
__IO uint32_t PERxR
 
__IO uint32_t REPxR
 
__IO uint32_t CMP1xR
 
__IO uint32_t CMP1CxR
 
__IO uint32_t CMP2xR
 
__IO uint32_t CMP3xR
 
__IO uint32_t CMP4xR
 
__IO uint32_t CPT1xR
 
__IO uint32_t CPT2xR
 
__IO uint32_t DTxR
 
__IO uint32_t SETx1R
 
__IO uint32_t RSTx1R
 
__IO uint32_t SETx2R
 
__IO uint32_t RSTx2R
 
__IO uint32_t EEFxR1
 
__IO uint32_t EEFxR2
 
__IO uint32_t RSTxR
 
__IO uint32_t CHPxR
 
__IO uint32_t CPT1xCR
 
__IO uint32_t CPT2xCR
 
__IO uint32_t OUTxR
 
__IO uint32_t FLTxR
 
uint32_t RESERVED0 [5]
 

Field Documentation

◆ CHPxR

__IO uint32_t HRTIM_Timerx_TypeDef::CHPxR

HRTIM Timerx Chopper register, Address offset: 0x58

◆ CMP1CxR

__IO uint32_t HRTIM_Timerx_TypeDef::CMP1CxR

HRTIM Timerx compare 1 compound register, Address offset: 0x20

◆ CMP1xR

__IO uint32_t HRTIM_Timerx_TypeDef::CMP1xR

HRTIM Timerx compare 1 register, Address offset: 0x1C

◆ CMP2xR

__IO uint32_t HRTIM_Timerx_TypeDef::CMP2xR

HRTIM Timerx compare 2 register, Address offset: 0x24

◆ CMP3xR

__IO uint32_t HRTIM_Timerx_TypeDef::CMP3xR

HRTIM Timerx compare 3 register, Address offset: 0x28

◆ CMP4xR

__IO uint32_t HRTIM_Timerx_TypeDef::CMP4xR

HRTIM Timerx compare 4 register, Address offset: 0x2C

◆ CNTxR

__IO uint32_t HRTIM_Timerx_TypeDef::CNTxR

HRTIM Timerx counter register, Address offset: 0x10

◆ CPT1xCR

__IO uint32_t HRTIM_Timerx_TypeDef::CPT1xCR

HRTIM Timerx Capture 1 register, Address offset: 0x5C

◆ CPT1xR

__IO uint32_t HRTIM_Timerx_TypeDef::CPT1xR

HRTIM Timerx capture 1 register, Address offset: 0x30

◆ CPT2xCR

__IO uint32_t HRTIM_Timerx_TypeDef::CPT2xCR

HRTIM Timerx Capture 2 register, Address offset: 0x60

◆ CPT2xR

__IO uint32_t HRTIM_Timerx_TypeDef::CPT2xR

HRTIM Timerx capture 2 register, Address offset: 0x34

◆ DTxR

__IO uint32_t HRTIM_Timerx_TypeDef::DTxR

HRTIM Timerx dead time register, Address offset: 0x38

◆ EEFxR1

__IO uint32_t HRTIM_Timerx_TypeDef::EEFxR1

HRTIM Timerx external event filtering 1 register, Address offset: 0x4C

◆ EEFxR2

__IO uint32_t HRTIM_Timerx_TypeDef::EEFxR2

HRTIM Timerx external event filtering 2 register, Address offset: 0x50

◆ FLTxR

__IO uint32_t HRTIM_Timerx_TypeDef::FLTxR

HRTIM Timerx Fault register, Address offset: 0x68

◆ OUTxR

__IO uint32_t HRTIM_Timerx_TypeDef::OUTxR

HRTIM Timerx Output register, Address offset: 0x64

◆ PERxR

__IO uint32_t HRTIM_Timerx_TypeDef::PERxR

HRTIM Timerx period register, Address offset: 0x14

◆ REPxR

__IO uint32_t HRTIM_Timerx_TypeDef::REPxR

HRTIM Timerx repetition register, Address offset: 0x18

◆ RESERVED0

uint32_t HRTIM_Timerx_TypeDef::RESERVED0

Reserved, 0x6C..0x7C

◆ RSTx1R

__IO uint32_t HRTIM_Timerx_TypeDef::RSTx1R

HRTIM Timerx output 1 reset register, Address offset: 0x40

◆ RSTx2R

__IO uint32_t HRTIM_Timerx_TypeDef::RSTx2R

HRTIM Timerx output 2 reset register, Address offset: 0x48

◆ RSTxR

__IO uint32_t HRTIM_Timerx_TypeDef::RSTxR

HRTIM Timerx Reset register, Address offset: 0x54

◆ SETx1R

__IO uint32_t HRTIM_Timerx_TypeDef::SETx1R

HRTIM Timerx output 1 set register, Address offset: 0x3C

◆ SETx2R

__IO uint32_t HRTIM_Timerx_TypeDef::SETx2R

HRTIM Timerx output 2 set register, Address offset: 0x44

◆ TIMxCR

__IO uint32_t HRTIM_Timerx_TypeDef::TIMxCR

HRTIM Timerx control register, Address offset: 0x00

◆ TIMxDIER

__IO uint32_t HRTIM_Timerx_TypeDef::TIMxDIER

HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C

◆ TIMxICR

__IO uint32_t HRTIM_Timerx_TypeDef::TIMxICR

HRTIM Timerx interrupt clear register, Address offset: 0x08

◆ TIMxISR

__IO uint32_t HRTIM_Timerx_TypeDef::TIMxISR

HRTIM Timerx interrupt status register, Address offset: 0x04


The documentation for this struct was generated from the following files: