RTEMS 6.1-rc7
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fsl_dcdc.h
1/*
2 * Copyright 2020-2021 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef __FSL_DCDC_H__
10#define __FSL_DCDC_H__
11
12#include "fsl_common.h"
13
19/*******************************************************************************
20 * Definitions
21 ******************************************************************************/
23#define FSL_DCDC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
26#define STANDBY_MODE_VDD1P0_TARGET_VOLTAGE \
27 { \
28 625, 650, 675, 700, 725, 750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1075, 1100, 1125, \
29 1150, 1175, 1200, 1225, 1250, 1275, 1300, 1325, 1350, 1375, 1400 \
30 }
31
33#define STANDBY_MODE_VDD1P8_TARGET_VOLTAGE \
34 { \
35 1525, 1550, 1575, 1600, 1625, 1650, 1675, 1700, 1725, 1750, 1775, 1800, 1825, 1850, 1875, 1900, 1925, 1950, \
36 1975, 2000, 2025, 2050, 2075, 2100, 2125, 2150, 2175, 2200, 2225, 2250, 2275, 2300 \
37 }
38
40#define BUCK_MODE_VDD1P0_TARGET_VOLTAGE \
41 { \
42 600, 625, 650, 675, 700, 725, 750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1075, 1100, \
43 1125, 1150, 1175, 1200, 1225, 1250, 1275, 1300, 1325, 1350, 1375 \
44 }
45
47#define BUCK_MODE_VDD1P8_TARGET_VOLTAGE \
48 { \
49 1500, 1525, 1550, 1575, 1600, 1625, 1650, 1675, 1700, 1725, 1750, 1775, 1800, 1825, 1850, 1875, 1900, 1925, \
50 1950, 1975, 2000, 2025, 2050, 2075, 2100, 2125, 2150, 2175, 2200, 2225, 2250, 2275 \
51 }
52
57{
58 kDCDC_AlreadySettledStatusFlag = DCDC_REG0_STS_DC_OK_MASK,
61};
62
67{
68 kDCDC_SetPoint0 = 1UL << 0UL,
69 kDCDC_SetPoint1 = 1UL << 1UL,
70 kDCDC_SetPoint2 = 1UL << 2UL,
71 kDCDC_SetPoint3 = 1UL << 3UL,
72 kDCDC_SetPoint4 = 1UL << 4UL,
73 kDCDC_SetPoint5 = 1UL << 5UL,
74 kDCDC_SetPoint6 = 1UL << 6UL,
75 kDCDC_SetPoint7 = 1UL << 7UL,
76 kDCDC_SetPoint8 = 1UL << 8UL,
77 kDCDC_SetPoint9 = 1UL << 9UL,
78 kDCDC_SetPoint10 = 1UL << 10UL,
79 kDCDC_SetPoint11 = 1UL << 11UL,
80 kDCDC_SetPoint12 = 1UL << 12UL,
81 kDCDC_SetPoint13 = 1UL << 13UL,
82 kDCDC_SetPoint14 = 1UL << 14UL,
83 kDCDC_SetPoint15 = 1UL << 15UL
84};
85
90{
94
99{
103
108{
150
155{
197
202{
243
248{
289
294{
300
305{
315
320{
325
330{
334
338typedef struct _dcdc_config
339{
345
350{
353
358{
369
374{
398
403{
404 uint32_t feedbackPoint;
406
411{
414
419{
420 uint32_t enableDCDCMap;
424 uint32_t lowpowerMap;
426 uint32_t standbyMap;
447
448/*******************************************************************************
449 * API
450 ******************************************************************************/
462void DCDC_Init(DCDC_Type *base, const dcdc_config_t *config);
463
469void DCDC_Deinit(DCDC_Type *base);
470
485
500static inline void DCDC_EnterLowPowerModeViaStandbyRequest(DCDC_Type *base, bool enable)
501{
502 if (enable)
503 {
504 base->CTRL0 |= DCDC_CTRL0_STBY_LP_MODE_EN_MASK;
505 }
506 else
507 {
508 base->CTRL0 &= ~DCDC_CTRL0_STBY_LP_MODE_EN_MASK;
509 }
510}
511
520static inline void DCDC_EnterLowPowerMode(DCDC_Type *base, bool enable)
521{
522 if (enable)
523 {
524 base->REG3 |= DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK | DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
525 base->CTRL0 |= DCDC_CTRL0_LP_MODE_EN_MASK;
526 }
527 else
528 {
529 base->CTRL0 &= ~DCDC_CTRL0_LP_MODE_EN_MASK;
530 }
531}
532
540static inline void DCDC_EnterStandbyMode(DCDC_Type *base, bool enable)
541{
542 if (enable)
543 {
544 base->CTRL0 |= DCDC_CTRL0_STBY_EN_MASK;
545 }
546 else
547 {
548 base->CTRL0 &= ~DCDC_CTRL0_STBY_EN_MASK;
549 }
550}
551
565static inline void DCDC_SetVDD1P0StandbyModeTargetVoltage(DCDC_Type *base,
567{
568 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
569 base->CTRL1 =
570 ((base->CTRL1) & (~DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK)) | DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(targetVoltage);
571 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
572 {
573 }
574}
575
583static inline uint16_t DCDC_GetVDD1P0StandbyModeTargetVoltage(DCDC_Type *base)
584{
585 const uint16_t vdd1P0TargetVoltage[] = STANDBY_MODE_VDD1P0_TARGET_VOLTAGE;
586 uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK) >> DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT;
587
588 return vdd1P0TargetVoltage[voltageValue];
589}
590
597static inline void DCDC_SetVDD1P8StandbyModeTargetVoltage(DCDC_Type *base,
599{
600 base->REG3 &= ~DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK;
601 base->CTRL1 =
602 ((base->CTRL1) & (~DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK)) | DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(targetVoltage);
603 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
604 {
605 }
606}
607
615static inline uint16_t DCDC_GetVDD1P8StandbyModeTargetVoltage(DCDC_Type *base)
616{
617 const uint16_t vdd1P8TargetVoltage[] = STANDBY_MODE_VDD1P8_TARGET_VOLTAGE;
618 uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK) >> DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT;
619
620 return vdd1P8TargetVoltage[voltageValue];
621}
622
629static inline void DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC_Type *base, dcdc_buck_mode_1P0_target_vol_t targetVoltage)
630{
631 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
632 base->CTRL1 = ((base->CTRL1 & (~DCDC_CTRL1_VDD1P0CTRL_TRG_MASK)) | DCDC_CTRL1_VDD1P0CTRL_TRG(targetVoltage));
633 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
634 {
635 }
636}
637
645static inline uint16_t DCDC_GetVDD1P0BuckModeTargetVoltage(DCDC_Type *base)
646{
647 const uint16_t vdd1P0TargetVoltage[] = BUCK_MODE_VDD1P0_TARGET_VOLTAGE;
648 uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P0CTRL_TRG_MASK) >> DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT;
649
650 return vdd1P0TargetVoltage[voltageValue];
651}
652
659static inline void DCDC_SetVDD1P8BuckModeTargetVoltage(DCDC_Type *base, dcdc_buck_mode_1P8_target_vol_t targetVoltage)
660{
661 base->REG3 &= ~DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK;
662 base->CTRL1 = ((base->CTRL1 & (~DCDC_CTRL1_VDD1P8CTRL_TRG_MASK)) | DCDC_CTRL1_VDD1P8CTRL_TRG(targetVoltage));
663 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
664 {
665 }
666}
667
675static inline uint16_t DCDC_GetVDD1P8BuckModeTargetVoltage(DCDC_Type *base)
676{
677 const uint16_t vdd1P8TargetVoltage[] = BUCK_MODE_VDD1P8_TARGET_VOLTAGE;
678 uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P8CTRL_TRG_MASK) >> DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT;
679
680 return vdd1P8TargetVoltage[voltageValue];
681}
682
692static inline void DCDC_EnableVDD1P0TargetVoltageStepping(DCDC_Type *base, bool enable)
693{
694 if (enable)
695 {
696 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
697 }
698 else
699 {
700 base->REG3 |= DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
701 }
702}
703
713static inline void DCDC_EnableVDD1P8TargetVoltageStepping(DCDC_Type *base, bool enable)
714{
715 if (enable)
716 {
717 base->REG3 &= ~DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK;
718 }
719 else
720 {
721 base->REG3 |= DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK;
722 }
723}
724
752
760
778static inline void DCDC_EnableOutputRangeComparator(DCDC_Type *base, bool enable)
779{
780 if (enable)
781 {
782 base->REG0 &= ~DCDC_REG0_PWD_CMP_OFFSET_MASK;
783 }
784 else
785 {
786 base->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK;
787 }
788}
789
796void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource);
797
810
818
825static inline void DCDC_SetBandgapVoltageTrimValue(DCDC_Type *base, uint32_t trimValue)
826{
827 base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK;
828 base->REG1 |= DCDC_REG1_VBG_TRIM(trimValue);
829}
830
850
858
866
873static inline void DCDC_SetLPComparatorBiasValue(DCDC_Type *base, dcdc_comparator_current_bias_t biasValue)
874{
875 base->REG1 &= ~DCDC_REG1_LP_CMP_ISRC_SEL_MASK;
876 base->REG1 |= DCDC_REG1_LP_CMP_ISRC_SEL(biasValue);
877}
878
886
893static inline void DCDC_EnableAdjustDelay(DCDC_Type *base, bool enable)
894{
895 if (enable)
896 {
897 base->REG3 |= DCDC_REG3_MISC_DELAY_TIMING_MASK;
898 }
899 else
900 {
901 base->REG3 &= ~DCDC_REG3_MISC_DELAY_TIMING_MASK;
902 }
903}
904
914static inline void DCDC_EnableImproveTransition(DCDC_Type *base, bool enable)
915{
916 if (enable)
917 {
918 base->REG2 |= DCDC_REG2_DCM_SET_CTRL_MASK;
919 }
920 else
921 {
922 base->REG2 &= ~DCDC_REG2_DCM_SET_CTRL_MASK;
923 }
924}
941
949static inline void DCDC_SetPointDeinit(DCDC_Type *base, uint32_t setpointMap)
950{
951 base->REG4 &= ~setpointMap;
952}
953
967static inline uint32_t DCDC_GetStatusFlags(DCDC_Type *base)
968{
969 return (base->REG0 & DCDC_REG0_STS_DC_OK_MASK);
970}
971
972/* @} */
973
992void DCDC_BootIntoDCM(DCDC_Type *base);
993
1005void DCDC_BootIntoCCM(DCDC_Type *base);
1006
1013#endif /* __FSL_DCDC_H__ */
#define DCDC_REG1_LP_CMP_ISRC_SEL(x)
Definition: MIMXRT1052.h:12222
#define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(x)
Definition: MIMXRT1166_cm4.h:28377
#define DCDC_REG1_VBG_TRIM(x)
Definition: MIMXRT1052.h:12244
#define DCDC_CTRL1_VDD1P8CTRL_TRG(x)
Definition: MIMXRT1166_cm4.h:28350
#define DCDC_CTRL1_VDD1P0CTRL_TRG(x)
Definition: MIMXRT1166_cm4.h:28359
void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config)
Configures for the min power.
Definition: fsl_dcdc.c:404
#define STANDBY_MODE_VDD1P8_TARGET_VOLTAGE
The array of VDD1P8 target voltage in standby mode.
Definition: fsl_dcdc.h:33
void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config)
Gets the default setting for low power configuration.
Definition: fsl_dcdc.c:280
void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config)
Configures the DCDC low power.
Definition: fsl_dcdc.c:295
_dcdc_buck_mode_1P8_target_vol
The enumeration VDD1P8's target voltage value in buck mode.
Definition: fsl_dcdc.h:248
enum _dcdc_trim_input_mode dcdc_trim_input_mode_t
DCDC trim input mode, including sample trim input and hold trim input.
enum _dcdc_voltage_output_sel dcdc_voltage_output_sel_t
Voltage output option.
void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config)
Configures the DCDC internal regulator.
Definition: fsl_dcdc.c:424
struct _dcdc_min_power_config dcdc_min_power_config_t
Configuration for min power setting.
void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config)
Gets the default setting for loop control configuration.
Definition: fsl_dcdc.c:328
void DCDC_GetDefaultConfig(dcdc_config_t *config)
Gets the default setting for DCDC, such as control mode, etc.
Definition: fsl_dcdc.c:139
_dcdc_control_mode
DCDC control mode, including setpoint control mode and static control mode.
Definition: fsl_dcdc.h:90
struct _dcdc_internal_regulator_config dcdc_internal_regulator_config_t
Configuration for DCDC internal regulator.
void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource)
Configures the DCDC clock source.
Definition: fsl_dcdc.c:242
void DCDC_Init(DCDC_Type *base, const dcdc_config_t *config)
Initializes the basic resource of DCDC module, such as control mode, etc.
Definition: fsl_dcdc.c:88
enum _dcdc_buck_mode_1P8_target_vol dcdc_buck_mode_1P8_target_vol_t
The enumeration VDD1P8's target voltage value in buck mode.
_dcdc_status_flags
The enumeration of DCDC status flags.
Definition: fsl_dcdc.h:57
_dcdc_standby_mode_1P0_target_vol
The enumeration VDD1P0's target voltage value in standby mode.
Definition: fsl_dcdc.h:108
_dcdc_clock_source
Oscillator clock option.
Definition: fsl_dcdc.h:320
void DCDC_SetPointInit(DCDC_Type *base, const dcdc_setpoint_config_t *config)
Initializes DCDC module when the control mode selected as setpoint mode.
Definition: fsl_dcdc.c:444
_dcdc_peak_current_threshold
The threshold if peak current detection.
Definition: fsl_dcdc.h:305
enum _dcdc_clock_source dcdc_clock_source_t
Oscillator clock option.
enum _dcdc_buck_mode_1P0_target_vol dcdc_buck_mode_1P0_target_vol_t
The enumeration VDD1P0's target voltage value in buck mode.
_dcdc_standby_mode_1P8_target_vol
The enumeration VDD1P8's target voltage value in standby mode.
Definition: fsl_dcdc.h:155
void DCDC_Deinit(DCDC_Type *base)
De-initializes the DCDC module.
Definition: fsl_dcdc.c:116
struct _dcdc_config dcdc_config_t
Configuration for DCDC.
void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config)
Configures the DCDC detection.
Definition: fsl_dcdc.c:193
_dcdc_comparator_current_bias
The current bias of low power comparator.
Definition: fsl_dcdc.h:294
_dcdc_setpoint_map
System setpoints enumeration.
Definition: fsl_dcdc.h:67
#define STANDBY_MODE_VDD1P0_TARGET_VOLTAGE
The array of VDD1P0 target voltage in standby mode.
Definition: fsl_dcdc.h:26
enum _dcdc_control_mode dcdc_control_mode_t
DCDC control mode, including setpoint control mode and static control mode.
#define BUCK_MODE_VDD1P0_TARGET_VOLTAGE
The array of VDD1P0 target voltage in buck mode.
Definition: fsl_dcdc.h:40
void DCDC_BootIntoDCM(DCDC_Type *base)
Boots DCDC into DCM(discontinous conduction mode).
Definition: fsl_dcdc.c:495
void DCDC_BootIntoCCM(DCDC_Type *base)
Boots DCDC into CCM(continous conduction mode).
Definition: fsl_dcdc.c:514
void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config)
Gets the default setting for detection configuration.
Definition: fsl_dcdc.c:170
enum _dcdc_comparator_current_bias dcdc_comparator_current_bias_t
The current bias of low power comparator.
_dcdc_trim_input_mode
DCDC trim input mode, including sample trim input and hold trim input.
Definition: fsl_dcdc.h:99
struct _dcdc_loop_control_config dcdc_loop_control_config_t
Configuration for the loop control.
enum _dcdc_standby_mode_1P8_target_vol dcdc_standby_mode_1P8_target_vol_t
The enumeration VDD1P8's target voltage value in standby mode.
enum _dcdc_standby_mode_1P0_target_vol dcdc_standby_mode_1P0_target_vol_t
The enumeration VDD1P0's target voltage value in standby mode.
#define BUCK_MODE_VDD1P8_TARGET_VOLTAGE
The array of VDD1P8 target voltage in buck mode.
Definition: fsl_dcdc.h:47
struct _dcdc_setpoint_config dcdc_setpoint_config_t
DCDC configuration in set point mode.
struct _dcdc_detection_config dcdc_detection_config_t
Configuration for DCDC detection.
enum _dcdc_peak_current_threshold dcdc_peak_current_threshold_t
The threshold if peak current detection.
void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config)
Configures the DCDC loop control.
Definition: fsl_dcdc.c:351
_dcdc_voltage_output_sel
Voltage output option.
Definition: fsl_dcdc.h:330
_dcdc_buck_mode_1P0_target_vol
The enumeration VDD1P0's target voltage value in buck mode.
Definition: fsl_dcdc.h:202
struct _dcdc_low_power_config dcdc_low_power_config_t
Configuration for DCDC low power.
@ kDCDC_1P8BuckTarget1P725V
Definition: fsl_dcdc.h:260
@ kDCDC_1P8BuckTarget2P175V
Definition: fsl_dcdc.h:282
@ kDCDC_1P8BuckTarget1P7V
Definition: fsl_dcdc.h:259
@ kDCDC_1P8BuckTarget2P0V
Definition: fsl_dcdc.h:274
@ kDCDC_1P8BuckTarget1P925V
Definition: fsl_dcdc.h:270
@ kDCDC_1P8BuckTarget2P025V
Definition: fsl_dcdc.h:275
@ kDCDC_1P8BuckTarget1P5V
Definition: fsl_dcdc.h:249
@ kDCDC_1P8BuckTarget2P1V
Definition: fsl_dcdc.h:279
@ kDCDC_1P8BuckTarget1P95V
Definition: fsl_dcdc.h:271
@ kDCDC_1P8BuckTarget2P15V
Definition: fsl_dcdc.h:281
@ kDCDC_1P8BuckTarget1P775V
Definition: fsl_dcdc.h:262
@ kDCDC_1P8BuckTarget1P975V
Definition: fsl_dcdc.h:272
@ kDCDC_1P8BuckTarget1P55V
Definition: fsl_dcdc.h:251
@ kDCDC_1P8BuckTarget2P225V
Definition: fsl_dcdc.h:285
@ kDCDC_1P8BuckTarget1P825V
Definition: fsl_dcdc.h:265
@ kDCDC_1P8BuckTarget2P075V
Definition: fsl_dcdc.h:277
@ kDCDC_1P8BuckTarget2P05V
Definition: fsl_dcdc.h:276
@ kDCDC_1P8BuckTarget2P2V
Definition: fsl_dcdc.h:284
@ kDCDC_1P8BuckTarget2P125V
Definition: fsl_dcdc.h:280
@ kDCDC_1P8BuckTarget1P75V
Definition: fsl_dcdc.h:261
@ kDCDC_1P8BuckTarget1P85V
Definition: fsl_dcdc.h:266
@ kDCDC_1P8BuckTarget1P6V
Definition: fsl_dcdc.h:254
@ kDCDC_1P8BuckTarget1P575V
Definition: fsl_dcdc.h:252
@ kDCDC_1P8BuckTarget1P675V
Definition: fsl_dcdc.h:257
@ kDCDC_1P8BuckTarget2P275V
Definition: fsl_dcdc.h:287
@ kDCDC_1P8BuckTarget1P525V
Definition: fsl_dcdc.h:250
@ kDCDC_1P8BuckTarget1P8V
Definition: fsl_dcdc.h:264
@ kDCDC_1P8BuckTarget1P625V
Definition: fsl_dcdc.h:255
@ kDCDC_1P8BuckTarget2P25V
Definition: fsl_dcdc.h:286
@ kDCDC_1P8BuckTarget1P875V
Definition: fsl_dcdc.h:267
@ kDCDC_1P8BuckTarget1P65V
Definition: fsl_dcdc.h:256
@ kDCDC_1P8BuckTarget1P9V
Definition: fsl_dcdc.h:269
@ kDCDC_StaticControl
Definition: fsl_dcdc.h:91
@ kDCDC_SetPointControl
Definition: fsl_dcdc.h:92
@ kDCDC_AlreadySettledStatusFlag
Definition: fsl_dcdc.h:58
@ kDCDC_1P0StbyTarget1P175V
Definition: fsl_dcdc.h:136
@ kDCDC_1P0StbyTarget1P15V
Definition: fsl_dcdc.h:135
@ kDCDC_1P0StbyTarget1P075V
Definition: fsl_dcdc.h:131
@ kDCDC_1P0StbyTarget0P75V
Definition: fsl_dcdc.h:115
@ kDCDC_1P0StbyTarget0P725V
Definition: fsl_dcdc.h:114
@ kDCDC_1P0StbyTarget0P7V
Definition: fsl_dcdc.h:113
@ kDCDC_1P0StbyTarget0P675V
Definition: fsl_dcdc.h:111
@ kDCDC_1P0StbyTarget1P25V
Definition: fsl_dcdc.h:140
@ kDCDC_1P0StbyTarget1P025V
Definition: fsl_dcdc.h:129
@ kDCDC_1P0StbyTarget0P975V
Definition: fsl_dcdc.h:126
@ kDCDC_1P0StbyTarget0P9V
Definition: fsl_dcdc.h:123
@ kDCDC_1P0StbyTarget1P125V
Definition: fsl_dcdc.h:134
@ kDCDC_1P0StbyTarget0P925V
Definition: fsl_dcdc.h:124
@ kDCDC_1P0StbyTarget0P95V
Definition: fsl_dcdc.h:125
@ kDCDC_1P0StbyTarget1P1V
Definition: fsl_dcdc.h:133
@ kDCDC_1P0StbyTarget1P375V
Definition: fsl_dcdc.h:146
@ kDCDC_1P0StbyTarget0P825V
Definition: fsl_dcdc.h:119
@ kDCDC_1P0StbyTarget0P875V
Definition: fsl_dcdc.h:121
@ kDCDC_1P0StbyTarget1P05V
Definition: fsl_dcdc.h:130
@ kDCDC_1P0StbyTarget0P65V
Definition: fsl_dcdc.h:110
@ kDCDC_1P0StbyTarget1P4V
Definition: fsl_dcdc.h:148
@ kDCDC_1P0StbyTarget1P225V
Definition: fsl_dcdc.h:139
@ kDCDC_1P0StbyTarget1P275V
Definition: fsl_dcdc.h:141
@ kDCDC_1P0StbyTarget0P625V
Definition: fsl_dcdc.h:109
@ kDCDC_1P0StbyTarget0P775V
Definition: fsl_dcdc.h:116
@ kDCDC_1P0StbyTarget1P325V
Definition: fsl_dcdc.h:144
@ kDCDC_1P0StbyTarget1P3V
Definition: fsl_dcdc.h:143
@ kDCDC_1P0StbyTarget1P2V
Definition: fsl_dcdc.h:138
@ kDCDC_1P0StbyTarget1P0V
Definition: fsl_dcdc.h:128
@ kDCDC_1P0StbyTarget0P85V
Definition: fsl_dcdc.h:120
@ kDCDC_1P0StbyTarget0P8V
Definition: fsl_dcdc.h:118
@ kDCDC_1P0StbyTarget1P35V
Definition: fsl_dcdc.h:145
@ kDCDC_1P8StbyTarget1P9V
Definition: fsl_dcdc.h:175
@ kDCDC_1P8StbyTarget1P775V
Definition: fsl_dcdc.h:168
@ kDCDC_1P8StbyTarget1P7V
Definition: fsl_dcdc.h:165
@ kDCDC_1P8StbyTarget2P225V
Definition: fsl_dcdc.h:191
@ kDCDC_1P8StbyTarget2P025V
Definition: fsl_dcdc.h:181
@ kDCDC_1P8StbyTarget1P925V
Definition: fsl_dcdc.h:176
@ kDCDC_1P8StbyTarget1P525V
Definition: fsl_dcdc.h:156
@ kDCDC_1P8StbyTarget1P85V
Definition: fsl_dcdc.h:172
@ kDCDC_1P8StbyTarget1P675V
Definition: fsl_dcdc.h:163
@ kDCDC_1P8StbyTarget1P825V
Definition: fsl_dcdc.h:171
@ kDCDC_1P8StbyTarget2P0V
Definition: fsl_dcdc.h:180
@ kDCDC_1P8StbyTarget1P65V
Definition: fsl_dcdc.h:162
@ kDCDC_1P8StbyTarget1P725V
Definition: fsl_dcdc.h:166
@ kDCDC_1P8StbyTarget2P125V
Definition: fsl_dcdc.h:186
@ kDCDC_1P8StbyTarget1P875V
Definition: fsl_dcdc.h:173
@ kDCDC_1P8StbyTarget1P6V
Definition: fsl_dcdc.h:160
@ kDCDC_1P8StbyTarget1P625V
Definition: fsl_dcdc.h:161
@ kDCDC_1P8StbyTarget1P75V
Definition: fsl_dcdc.h:167
@ kDCDC_1P8StbyTarget1P55V
Definition: fsl_dcdc.h:157
@ kDCDC_1P8StbyTarget2P075V
Definition: fsl_dcdc.h:183
@ kDCDC_1P8StbyTarget1P95V
Definition: fsl_dcdc.h:177
@ kDCDC_1P8StbyTarget2P05V
Definition: fsl_dcdc.h:182
@ kDCDC_1P8StbyTarget1P575V
Definition: fsl_dcdc.h:158
@ kDCDC_1P8StbyTarget2P275V
Definition: fsl_dcdc.h:193
@ kDCDC_1P8StbyTarget2P2V
Definition: fsl_dcdc.h:190
@ kDCDC_1P8StbyTarget1P8V
Definition: fsl_dcdc.h:170
@ kDCDC_1P8StbyTarget2P15V
Definition: fsl_dcdc.h:187
@ kDCDC_1P8StbyTarget2P175V
Definition: fsl_dcdc.h:188
@ kDCDC_1P8StbyTarget2P25V
Definition: fsl_dcdc.h:192
@ kDCDC_1P8StbyTarget2P3V
Definition: fsl_dcdc.h:195
@ kDCDC_1P8StbyTarget2P1V
Definition: fsl_dcdc.h:185
@ kDCDC_1P8StbyTarget1P975V
Definition: fsl_dcdc.h:178
@ kDCDC_SetPoint11
Definition: fsl_dcdc.h:79
@ kDCDC_SetPoint2
Definition: fsl_dcdc.h:70
@ kDCDC_SetPoint14
Definition: fsl_dcdc.h:82
@ kDCDC_SetPoint10
Definition: fsl_dcdc.h:78
@ kDCDC_SetPoint3
Definition: fsl_dcdc.h:71
@ kDCDC_SetPoint4
Definition: fsl_dcdc.h:72
@ kDCDC_SetPoint7
Definition: fsl_dcdc.h:75
@ kDCDC_SetPoint6
Definition: fsl_dcdc.h:74
@ kDCDC_SetPoint15
Definition: fsl_dcdc.h:83
@ kDCDC_SetPoint1
Definition: fsl_dcdc.h:69
@ kDCDC_SetPoint9
Definition: fsl_dcdc.h:77
@ kDCDC_SetPoint12
Definition: fsl_dcdc.h:80
@ kDCDC_SetPoint8
Definition: fsl_dcdc.h:76
@ kDCDC_SetPoint0
Definition: fsl_dcdc.h:68
@ kDCDC_SetPoint5
Definition: fsl_dcdc.h:73
@ kDCDC_SetPoint13
Definition: fsl_dcdc.h:81
@ kDCDC_SampleTrimInput
Definition: fsl_dcdc.h:100
@ kDCDC_HoldTrimInput
Definition: fsl_dcdc.h:101
@ kDCDC_VoltageOutput1P8
Definition: fsl_dcdc.h:331
@ kDCDC_VoltageOutput1P0
Definition: fsl_dcdc.h:332
@ kDCDC_1P0BuckTarget1P25V
Definition: fsl_dcdc.h:235
@ kDCDC_1P0BuckTarget0P625V
Definition: fsl_dcdc.h:204
@ kDCDC_1P0BuckTarget0P825V
Definition: fsl_dcdc.h:214
@ kDCDC_1P0BuckTarget0P95V
Definition: fsl_dcdc.h:220
@ kDCDC_1P0BuckTarget1P025V
Definition: fsl_dcdc.h:224
@ kDCDC_1P0BuckTarget1P125V
Definition: fsl_dcdc.h:229
@ kDCDC_1P0BuckTarget1P2V
Definition: fsl_dcdc.h:233
@ kDCDC_1P0BuckTarget0P6V
Definition: fsl_dcdc.h:203
@ kDCDC_1P0BuckTarget1P225V
Definition: fsl_dcdc.h:234
@ kDCDC_1P0BuckTarget1P075V
Definition: fsl_dcdc.h:226
@ kDCDC_1P0BuckTarget0P775V
Definition: fsl_dcdc.h:211
@ kDCDC_1P0BuckTarget0P725V
Definition: fsl_dcdc.h:209
@ kDCDC_1P0BuckTarget1P375V
Definition: fsl_dcdc.h:241
@ kDCDC_1P0BuckTarget1P15V
Definition: fsl_dcdc.h:230
@ kDCDC_1P0BuckTarget1P1V
Definition: fsl_dcdc.h:228
@ kDCDC_1P0BuckTarget0P8V
Definition: fsl_dcdc.h:213
@ kDCDC_1P0BuckTarget1P0V
Definition: fsl_dcdc.h:223
@ kDCDC_1P0BuckTarget0P7V
Definition: fsl_dcdc.h:208
@ kDCDC_1P0BuckTarget1P3V
Definition: fsl_dcdc.h:238
@ kDCDC_1P0BuckTarget1P05V
Definition: fsl_dcdc.h:225
@ kDCDC_1P0BuckTarget0P65V
Definition: fsl_dcdc.h:205
@ kDCDC_1P0BuckTarget0P925V
Definition: fsl_dcdc.h:219
@ kDCDC_1P0BuckTarget0P75V
Definition: fsl_dcdc.h:210
@ kDCDC_1P0BuckTarget1P325V
Definition: fsl_dcdc.h:239
@ kDCDC_1P0BuckTarget0P875V
Definition: fsl_dcdc.h:216
@ kDCDC_1P0BuckTarget1P35V
Definition: fsl_dcdc.h:240
@ kDCDC_1P0BuckTarget0P85V
Definition: fsl_dcdc.h:215
@ kDCDC_1P0BuckTarget0P675V
Definition: fsl_dcdc.h:206
@ kDCDC_1P0BuckTarget0P975V
Definition: fsl_dcdc.h:221
@ kDCDC_1P0BuckTarget1P175V
Definition: fsl_dcdc.h:231
@ kDCDC_1P0BuckTarget0P9V
Definition: fsl_dcdc.h:218
@ kDCDC_1P0BuckTarget1P275V
Definition: fsl_dcdc.h:236
bool enableUseHalfFreqForContinuous
Definition: fsl_dcdc.h:351
dcdc_peak_current_threshold_t PeakCurrentThreshold
Definition: fsl_dcdc.h:367
bool enableRCThresholdDetection
Definition: fsl_dcdc.h:384
bool powerDownZeroCrossDetection
Definition: fsl_dcdc.h:365
bool powerDownOverCurrentDetection
Definition: fsl_dcdc.h:363
bool enableCommonThresholdDetection
Definition: fsl_dcdc.h:377
bool powerDownPeakCurrentDetection
Definition: fsl_dcdc.h:364
uint32_t feedbackPoint
Definition: fsl_dcdc.h:404
bool enableAdjustHystereticValue
Definition: fsl_dcdc.h:412
bool enableXtalokDetection
Definition: fsl_dcdc.h:359
bool enableCommonHysteresis
Definition: fsl_dcdc.h:375
uint32_t enableRCScaleCircuit
Definition: fsl_dcdc.h:385
bool enableInvertHysteresisSign
Definition: fsl_dcdc.h:383
enum _dcdc_peak_current_threshold dcdc_peak_current_threshold_t
The threshold if peak current detection.
uint32_t complementFeedForwardStep
Definition: fsl_dcdc.h:387
@ kDCDC_ClockAutoSwitch
Definition: fsl_dcdc.h:321
@ kDCDC_ClockInternalOsc
Definition: fsl_dcdc.h:322
@ kDCDC_ClockExternalOsc
Definition: fsl_dcdc.h:323
@ kDCDC_PeakCurrentRunMode250mALPMode2A
Definition: fsl_dcdc.h:310
@ kDCDC_PeakCurrentRunMode200mALPMode1P5A
Definition: fsl_dcdc.h:308
@ kDCDC_PeakCurrentRunMode250mALPMode1P5A
Definition: fsl_dcdc.h:306
@ kDCDC_PeakCurrentRunMode200mALPMode2A
Definition: fsl_dcdc.h:312
@ kDCDC_ComparatorCurrentBias400nA
Definition: fsl_dcdc.h:298
@ kDCDC_ComparatorCurrentBias50nA
Definition: fsl_dcdc.h:295
@ kDCDC_ComparatorCurrentBias200nA
Definition: fsl_dcdc.h:297
@ kDCDC_ComparatorCurrentBias100nA
Definition: fsl_dcdc.h:296
Definition: MIMXRT1052.h:12013
Configuration for DCDC.
Definition: fsl_dcdc.h:339
bool enableDcdcTimeout
Definition: fsl_dcdc.h:342
dcdc_control_mode_t controlMode
Definition: fsl_dcdc.h:340
bool enableSwitchingConverterOutput
Definition: fsl_dcdc.h:343
dcdc_trim_input_mode_t trimInputMode
Definition: fsl_dcdc.h:341
Configuration for DCDC detection.
Definition: fsl_dcdc.h:358
bool powerDownLowVoltageDetection
Definition: fsl_dcdc.h:362
bool powerDownOverVoltageVdd1P0Detection
Definition: fsl_dcdc.h:361
bool powerDownOverVoltageVdd1P8Detection
Definition: fsl_dcdc.h:360
Configuration for DCDC internal regulator.
Definition: fsl_dcdc.h:403
Configuration for the loop control.
Definition: fsl_dcdc.h:374
uint32_t integralProportionalRatio
Definition: fsl_dcdc.h:394
bool enableDifferentialThresholdDetection
Definition: fsl_dcdc.h:381
uint32_t controlParameterMagnitude
Definition: fsl_dcdc.h:392
bool enableDifferentialHysteresis
Definition: fsl_dcdc.h:378
Configuration for DCDC low power.
Definition: fsl_dcdc.h:411
Configuration for min power setting.
Definition: fsl_dcdc.h:350
DCDC configuration in set point mode.
Definition: fsl_dcdc.h:419
uint32_t standbyLowpowerMap
Definition: fsl_dcdc.h:428
uint32_t standbyMap
Definition: fsl_dcdc.h:426
uint32_t enableDigLogicMap
Definition: fsl_dcdc.h:422
dcdc_buck_mode_1P0_target_vol_t * buckVDD1P0TargetVoltage
Definition: fsl_dcdc.h:434
uint32_t lowpowerMap
Definition: fsl_dcdc.h:424
dcdc_buck_mode_1P8_target_vol_t * buckVDD1P8TargetVoltage
Definition: fsl_dcdc.h:430
dcdc_standby_mode_1P0_target_vol_t * standbyVDD1P0TargetVoltage
Definition: fsl_dcdc.h:442
dcdc_standby_mode_1P8_target_vol_t * standbyVDD1P8TargetVoltage
Definition: fsl_dcdc.h:438
uint32_t enableDCDCMap
Definition: fsl_dcdc.h:420
Definition: deflate.c:114