RTEMS 6.1-rc7
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cache.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2016 Pavel Pisa
13 * Copyright (C) 2014, 2024 embedded brains GmbH & Co. KG
14 * Copyright (C) 2000, 2008 On-Line Applications Research Corporation (OAR)
15 *
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions
18 * are met:
19 * 1. Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38/*
39 * This file is part of the RTEMS quality process and was automatically
40 * generated. If you find something that needs to be fixed or
41 * worded better please post a report or patch to an RTEMS mailing list
42 * or raise a bug report:
43 *
44 * https://www.rtems.org/bugs.html
45 *
46 * For information on updating and regenerating please refer to the How-To
47 * section in the Software Requirements Engineering chapter of the
48 * RTEMS Software Engineering manual. The manual is provided as a part of
49 * a release. For development sources please refer to the online
50 * documentation at:
51 *
52 * https://docs.rtems.org
53 */
54
55/* Generated from spec:/rtems/cache/if/header */
56
57#ifndef _RTEMS_RTEMS_CACHE_H
58#define _RTEMS_RTEMS_CACHE_H
59
60#include <stddef.h>
61#include <stdint.h>
62#include <rtems/rtems/status.h>
63
64#ifdef __cplusplus
65extern "C" {
66#endif
67
68/* Generated from spec:/rtems/cache/if/group */
69
84/* Generated from spec:/rtems/cache/if/coherent-add-area */
85
110rtems_status_code rtems_cache_coherent_add_area( void *begin, uintptr_t size );
111
112/* Generated from spec:/rtems/cache/if/coherent-allocate */
113
163 size_t size,
164 uintptr_t alignment,
165 uintptr_t boundary
166);
167
168/* Generated from spec:/rtems/cache/if/coherent-free */
169
188void rtems_cache_coherent_free( void *ptr );
189
190/* Generated from spec:/rtems/cache/if/freeze-data */
191
204void rtems_cache_freeze_data( void );
205
206/* Generated from spec:/rtems/cache/if/freeze-instruction */
207
221
222/* Generated from spec:/rtems/cache/if/unfreeze-data */
223
236void rtems_cache_unfreeze_data( void );
237
238/* Generated from spec:/rtems/cache/if/unfreeze-instruction */
239
253
254/* Generated from spec:/rtems/cache/if/flush-multiple-data-lines */
255
277void rtems_cache_flush_multiple_data_lines( const void *begin, size_t size );
278
279/* Generated from spec:/rtems/cache/if/invalidate-multiple-data-lines */
280
311 const void *begin,
312 size_t size
313);
314
315/* Generated from spec:/rtems/cache/if/invalidate-multiple-instruction-lines */
316
344 const void *begin,
345 size_t size
346);
347
348/* Generated from spec:/rtems/cache/if/instruction-sync-after-code-change */
349
376 const void *begin,
377 size_t size
378);
379
380/* Generated from spec:/rtems/cache/if/get-maximal-line-size */
381
403
404/* Generated from spec:/rtems/cache/if/get-data-line-size */
405
425size_t rtems_cache_get_data_line_size( void );
426
427/* Generated from spec:/rtems/cache/if/get-instruction-line-size */
428
449
450/* Generated from spec:/rtems/cache/if/get-data-size */
451
473size_t rtems_cache_get_data_cache_size( uint32_t level );
474
475/* Generated from spec:/rtems/cache/if/get-instruction-size */
476
500size_t rtems_cache_get_instruction_cache_size( uint32_t level );
501
502/* Generated from spec:/rtems/cache/if/flush-entire-data */
503
519
520/* Generated from spec:/rtems/cache/if/invalidate-entire-data */
521
537
538/* Generated from spec:/rtems/cache/if/invalidate-entire-instruction */
539
555
556/* Generated from spec:/rtems/cache/if/enable-data */
557
572void rtems_cache_enable_data( void );
573
574/* Generated from spec:/rtems/cache/if/disable-data */
575
598void rtems_cache_disable_data( void );
599
600/* Generated from spec:/rtems/cache/if/enable-instruction */
601
617
618/* Generated from spec:/rtems/cache/if/disable-instruction */
619
635
636/* Generated from spec:/rtems/cache/if/aligned-malloc */
637
665void *rtems_cache_aligned_malloc( size_t size );
666
667#ifdef __cplusplus
668}
669#endif
670
671#endif /* _RTEMS_RTEMS_CACHE_H */
rtems_status_code rtems_cache_coherent_add_area(void *begin, uintptr_t size)
Adds a cache coherent memory area to the cache coherent allocator.
Definition: cachecoherentalloc.c:122
void rtems_cache_unfreeze_instruction(void)
Unfreezes the instruction cache.
Definition: cacheimpl.h:450
void * rtems_cache_coherent_allocate(size_t size, uintptr_t alignment, uintptr_t boundary)
Allocates a memory area from cache coherent memory.
Definition: cachecoherentalloc.c:48
void rtems_cache_unfreeze_data(void)
Unfreezes the data cache.
Definition: cacheimpl.h:274
void rtems_cache_freeze_instruction(void)
Freezes the instruction caches.
Definition: cacheimpl.h:443
void rtems_cache_coherent_free(void *ptr)
Frees memory allocated by rtems_cache_coherent_allocate().
Definition: cachecoherentalloc.c:76
void rtems_cache_freeze_data(void)
Freezes the data caches.
Definition: cacheimpl.h:267
void rtems_cache_instruction_sync_after_code_change(const void *begin, size_t size)
Ensures necessary synchronization required after code changes.
Definition: cacheimpl.h:501
size_t rtems_cache_get_maximal_line_size(void)
Gets the maximal cache line size in bytes of all caches (data, instruction, or unified).
Definition: cacheimpl.h:474
void rtems_cache_invalidate_entire_instruction(void)
Invalidates the entire instruction cache.
Definition: cacheimpl.h:404
void rtems_cache_invalidate_entire_data(void)
Invalidates the entire data cache.
Definition: cacheimpl.h:228
void rtems_cache_invalidate_multiple_instruction_lines(const void *begin, size_t size)
Invalidates the instruction cache lines covering the memory area.
Definition: cacheimpl.h:383
size_t rtems_cache_get_data_cache_size(uint32_t level)
Gets the data cache size in bytes for the cache level.
Definition: cacheimpl.h:253
void rtems_cache_enable_data(void)
Enables the data cache.
Definition: cacheimpl.h:282
void rtems_cache_disable_instruction(void)
Disables the instruction cache.
Definition: cacheimpl.h:466
void rtems_cache_disable_data(void)
Disables the data cache.
Definition: cacheimpl.h:291
size_t rtems_cache_get_instruction_cache_size(uint32_t level)
Gets the instruction cache size in bytes for the cache level.
Definition: cacheimpl.h:429
void * rtems_cache_aligned_malloc(size_t size)
Allocates memory from the C Program Heap which begins at a cache line boundary.
Definition: cachealignedalloc.c:37
void rtems_cache_invalidate_multiple_data_lines(const void *begin, size_t size)
Invalidates the data cache lines covering the memory area.
Definition: cacheimpl.h:180
void rtems_cache_flush_entire_data(void)
Flushes the entire data cache.
Definition: cacheimpl.h:213
void rtems_cache_flush_multiple_data_lines(const void *begin, size_t size)
Flushes the data cache lines covering the memory area.
Definition: cacheimpl.h:146
size_t rtems_cache_get_instruction_line_size(void)
Gets the instruction cache line size in bytes.
Definition: cacheimpl.h:419
size_t rtems_cache_get_data_line_size(void)
Gets the data cache line size in bytes.
Definition: cacheimpl.h:243
void rtems_cache_enable_instruction(void)
Enables the instruction cache.
Definition: cacheimpl.h:458
rtems_status_code
This enumeration provides status codes for directives of the Classic API.
Definition: status.h:85
This header file provides the status codes of Classic API directives and support functions.