35#ifndef STM32H7xx_LL_CORTEX_H
36#define STM32H7xx_LL_CORTEX_H
72#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000UL
73#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk
82#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk
83#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk
84#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk
95#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000UL
96#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
97#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
98#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
107#define LL_MPU_REGION_NUMBER0 0x00UL
108#define LL_MPU_REGION_NUMBER1 0x01UL
109#define LL_MPU_REGION_NUMBER2 0x02UL
110#define LL_MPU_REGION_NUMBER3 0x03UL
111#define LL_MPU_REGION_NUMBER4 0x04UL
112#define LL_MPU_REGION_NUMBER5 0x05UL
113#define LL_MPU_REGION_NUMBER6 0x06UL
114#define LL_MPU_REGION_NUMBER7 0x07UL
115#if !defined(CORE_CM4)
116#define LL_MPU_REGION_NUMBER8 0x08UL
117#define LL_MPU_REGION_NUMBER9 0x09UL
118#define LL_MPU_REGION_NUMBER10 0x0AUL
119#define LL_MPU_REGION_NUMBER11 0x0BUL
120#define LL_MPU_REGION_NUMBER12 0x0CUL
121#define LL_MPU_REGION_NUMBER13 0x0DUL
122#define LL_MPU_REGION_NUMBER14 0x0EUL
123#define LL_MPU_REGION_NUMBER15 0x0FUL
133#define LL_MPU_REGION_SIZE_32B (0x04UL << MPU_RASR_SIZE_Pos)
134#define LL_MPU_REGION_SIZE_64B (0x05UL << MPU_RASR_SIZE_Pos)
135#define LL_MPU_REGION_SIZE_128B (0x06UL << MPU_RASR_SIZE_Pos)
136#define LL_MPU_REGION_SIZE_256B (0x07UL << MPU_RASR_SIZE_Pos)
137#define LL_MPU_REGION_SIZE_512B (0x08UL << MPU_RASR_SIZE_Pos)
138#define LL_MPU_REGION_SIZE_1KB (0x09UL << MPU_RASR_SIZE_Pos)
139#define LL_MPU_REGION_SIZE_2KB (0x0AUL << MPU_RASR_SIZE_Pos)
140#define LL_MPU_REGION_SIZE_4KB (0x0BUL << MPU_RASR_SIZE_Pos)
141#define LL_MPU_REGION_SIZE_8KB (0x0CUL << MPU_RASR_SIZE_Pos)
142#define LL_MPU_REGION_SIZE_16KB (0x0DUL << MPU_RASR_SIZE_Pos)
143#define LL_MPU_REGION_SIZE_32KB (0x0EUL << MPU_RASR_SIZE_Pos)
144#define LL_MPU_REGION_SIZE_64KB (0x0FUL << MPU_RASR_SIZE_Pos)
145#define LL_MPU_REGION_SIZE_128KB (0x10UL << MPU_RASR_SIZE_Pos)
146#define LL_MPU_REGION_SIZE_256KB (0x11UL << MPU_RASR_SIZE_Pos)
147#define LL_MPU_REGION_SIZE_512KB (0x12UL << MPU_RASR_SIZE_Pos)
148#define LL_MPU_REGION_SIZE_1MB (0x13UL << MPU_RASR_SIZE_Pos)
149#define LL_MPU_REGION_SIZE_2MB (0x14UL << MPU_RASR_SIZE_Pos)
150#define LL_MPU_REGION_SIZE_4MB (0x15UL << MPU_RASR_SIZE_Pos)
151#define LL_MPU_REGION_SIZE_8MB (0x16UL << MPU_RASR_SIZE_Pos)
152#define LL_MPU_REGION_SIZE_16MB (0x17UL << MPU_RASR_SIZE_Pos)
153#define LL_MPU_REGION_SIZE_32MB (0x18UL << MPU_RASR_SIZE_Pos)
154#define LL_MPU_REGION_SIZE_64MB (0x19UL << MPU_RASR_SIZE_Pos)
155#define LL_MPU_REGION_SIZE_128MB (0x1AUL << MPU_RASR_SIZE_Pos)
156#define LL_MPU_REGION_SIZE_256MB (0x1BUL << MPU_RASR_SIZE_Pos)
157#define LL_MPU_REGION_SIZE_512MB (0x1CUL << MPU_RASR_SIZE_Pos)
158#define LL_MPU_REGION_SIZE_1GB (0x1DUL << MPU_RASR_SIZE_Pos)
159#define LL_MPU_REGION_SIZE_2GB (0x1EUL << MPU_RASR_SIZE_Pos)
160#define LL_MPU_REGION_SIZE_4GB (0x1FUL << MPU_RASR_SIZE_Pos)
169#define LL_MPU_REGION_NO_ACCESS (0x00UL << MPU_RASR_AP_Pos)
170#define LL_MPU_REGION_PRIV_RW (0x01UL << MPU_RASR_AP_Pos)
171#define LL_MPU_REGION_PRIV_RW_URO (0x02UL << MPU_RASR_AP_Pos)
172#define LL_MPU_REGION_FULL_ACCESS (0x03UL << MPU_RASR_AP_Pos)
173#define LL_MPU_REGION_PRIV_RO (0x05UL << MPU_RASR_AP_Pos)
174#define LL_MPU_REGION_PRIV_RO_URO (0x06UL << MPU_RASR_AP_Pos)
183#define LL_MPU_TEX_LEVEL0 (0x00UL << MPU_RASR_TEX_Pos)
184#define LL_MPU_TEX_LEVEL1 (0x01UL << MPU_RASR_TEX_Pos)
185#define LL_MPU_TEX_LEVEL2 (0x02UL << MPU_RASR_TEX_Pos)
188#define LL_MPU_TEX_LEVEL4 (0x04UL << MPU_RASR_TEX_Pos)
197#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00UL
198#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk
207#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk
208#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00UL
217#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk
218#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00UL
227#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk
228#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00UL
416 SET_BIT(
SCB->SHCSR, Fault);
431 CLEAR_BIT(
SCB->SHCSR, Fault);
513__STATIC_INLINE
void LL_MPU_Enable(uint32_t Options)
516 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
528__STATIC_INLINE
void LL_MPU_Disable(
void)
533 WRITE_REG(MPU->CTRL, 0U);
541__STATIC_INLINE uint32_t LL_MPU_IsEnabled(
void)
543 return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
569__STATIC_INLINE
void LL_MPU_EnableRegion(uint32_t Region)
572 WRITE_REG(MPU->RNR, Region);
574 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
624__STATIC_INLINE
void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
627 WRITE_REG(MPU->RNR, Region);
629 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
631 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
658__STATIC_INLINE
void LL_MPU_DisableRegion(uint32_t Region)
661 WRITE_REG(MPU->RNR, Region);
663 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:286
__STATIC_FORCEINLINE void __DMB(void)
Data Memory Barrier.
Definition: cmsis_gcc.h:297
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:275
#define SCB_CPUID_IMPLEMENTER_Msk
Definition: core_cm4.h:484
#define SCB_CPUID_VARIANT_Pos
Definition: core_cm4.h:486
#define SCB_CPUID_REVISION_Msk
Definition: core_cm4.h:496
#define SCB_CPUID_REVISION_Pos
Definition: core_cm4.h:495
#define SCB_SCR_SLEEPONEXIT_Msk
Definition: core_cm4.h:563
#define SCB_CPUID_IMPLEMENTER_Pos
Definition: core_cm4.h:483
#define SCB_CPUID_PARTNO_Pos
Definition: core_cm4.h:492
#define SCB_SCR_SLEEPDEEP_Msk
Definition: core_cm4.h:560
#define SCB_CPUID_PARTNO_Msk
Definition: core_cm4.h:493
#define SCB_CPUID_VARIANT_Msk
Definition: core_cm4.h:487
#define SCB_CPUID_ARCHITECTURE_Pos
Definition: core_cm4.h:489
#define SCB_CPUID_ARCHITECTURE_Msk
Definition: core_cm4.h:490
#define SCB_SCR_SEVONPEND_Msk
Definition: core_cm4.h:557
#define SysTick_CTRL_COUNTFLAG_Msk
Definition: core_cm4.h:786
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm4.h:792
#define SCB
Definition: core_cm4.h:1572
#define SysTick
Definition: core_cm4.h:1573
#define LL_SYSTICK_CLKSOURCE_HCLK
Definition: stm32h7xx_ll_cortex.h:73
__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
Disable a fault in System handler control register (SHCSR) @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_D...
Definition: stm32h7xx_ll_cortex.h:428
__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
Enable a fault in System handler control register (SHCSR) @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_En...
Definition: stm32h7xx_ll_cortex.h:413
__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
Processor uses deep sleep as its low power mode @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep.
Definition: stm32h7xx_ll_cortex.h:341
__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
Do not sleep when returning to Thread mode. @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit.
Definition: stm32h7xx_ll_cortex.h:365
__STATIC_INLINE void LL_LPM_EnableSleep(void)
Processor uses sleep as its low power mode @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep.
Definition: stm32h7xx_ll_cortex.h:330
__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
Configures sleep-on-exit when returning from Handler mode to Thread mode.
Definition: stm32h7xx_ll_cortex.h:354
__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor....
Definition: stm32h7xx_ll_cortex.h:377
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded @rmtoll ...
Definition: stm32h7xx_ll_cortex.h:389
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
Get Variant number (The r value in the rnpn product revision identifier) @rmtoll SCB_CPUID VARIANT LL...
Definition: stm32h7xx_ll_cortex.h:458
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
Get Implementer code @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer.
Definition: stm32h7xx_ll_cortex.h:448
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) @r...
Definition: stm32h7xx_ll_cortex.h:488
__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
Get Constant number @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant.
Definition: stm32h7xx_ll_cortex.h:468
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
Get Part number @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo.
Definition: stm32h7xx_ll_cortex.h:478
__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
Disable SysTick exception request @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT.
Definition: stm32h7xx_ll_cortex.h:301
__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
Get the SysTick clock source @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource.
Definition: stm32h7xx_ll_cortex.h:281
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
Enable SysTick exception request @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT.
Definition: stm32h7xx_ll_cortex.h:291
__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
Configures the SysTick clock source @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource.
Definition: stm32h7xx_ll_cortex.h:269
__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
Checks if the SYSTICK interrupt is enabled or disabled. @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabled...
Definition: stm32h7xx_ll_cortex.h:311
__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
This function checks if the Systick counter flag is active or not.
Definition: stm32h7xx_ll_cortex.h:256
CMSIS STM32H7xx Device Peripheral Access Layer Header File.