35#ifndef KERN_sparc64_sun4u_MMU_H_
36#define KERN_sparc64_sun4u_MMU_H_
40#define ASI_LSU_CONTROL_REG 0x45
45#define ASI_IMMU_TSB_8KB_PTR_REG 0x51
46#define ASI_IMMU_TSB_64KB_PTR_REG 0x52
47#define ASI_ITLB_DATA_IN_REG 0x54
48#define ASI_ITLB_DATA_ACCESS_REG 0x55
49#define ASI_ITLB_TAG_READ_REG 0x56
50#define ASI_IMMU_DEMAP 0x57
53#define VA_IMMU_TSB_TAG_TARGET 0x0
54#define VA_IMMU_SFSR 0x18
55#define VA_IMMU_TSB_BASE 0x28
56#define VA_IMMU_TAG_ACCESS 0x30
58#define VA_IMMU_PRIMARY_EXTENSION 0x48
59#define VA_IMMU_NUCLEUS_EXTENSION 0x58
65#define ASI_DMMU_TSB_8KB_PTR_REG 0x59
66#define ASI_DMMU_TSB_64KB_PTR_REG 0x5a
67#define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b
68#define ASI_DTLB_DATA_IN_REG 0x5c
69#define ASI_DTLB_DATA_ACCESS_REG 0x5d
70#define ASI_DTLB_TAG_READ_REG 0x5e
71#define ASI_DMMU_DEMAP 0x5f
74#define VA_DMMU_TSB_TAG_TARGET 0x0
75#define VA_PRIMARY_CONTEXT_REG 0x8
76#define VA_SECONDARY_CONTEXT_REG 0x10
77#define VA_DMMU_SFSR 0x18
78#define VA_DMMU_SFAR 0x20
79#define VA_DMMU_TSB_BASE 0x28
80#define VA_DMMU_TAG_ACCESS 0x30
81#define VA_DMMU_VA_WATCHPOINT_REG 0x38
82#define VA_DMMU_PA_WATCHPOINT_REG 0x40
84#define VA_DMMU_PRIMARY_EXTENSION 0x48
85#define VA_DMMU_SECONDARY_EXTENSION 0x50
86#define VA_DMMU_NUCLEUS_EXTENSION 0x58
92#include <arch/barrier.h>
93#include <arch/types.h>
Definition: xnandpsu_onfi.h:185