RTEMS 6.1-rc7
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cpu.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
12/*
13 * COPYRIGHT (c) 1989-2012.
14 * On-Line Applications Research Corporation (OAR).
15 *
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions
18 * are met:
19 * 1. Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#ifndef _RTEMS_SCORE_CPU_H
39#define _RTEMS_SCORE_CPU_H
40
41#ifdef __cplusplus
42extern "C" {
43#endif
44
46#include <rtems/score/v850.h>
47
48/* conditional compilation parameters */
49
61#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
62
63#define CPU_HARDWARE_FP FALSE
64
65#define CPU_SOFTWARE_FP FALSE
66
67#define CPU_ALL_TASKS_ARE_FP FALSE
68
69#define CPU_IDLE_TASK_IS_FP FALSE
70
71#define CPU_USE_DEFERRED_FP_SWITCH FALSE
72
73#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
74
86#define CPU_STACK_GROWS_UP FALSE
87
88/* FIXME: Is this the right value? */
89#define CPU_CACHE_LINE_BYTES 32
90
91#define CPU_STRUCTURE_ALIGNMENT
92
103#define CPU_MODES_INTERRUPT_MASK 0x00000001
104
105#define CPU_MAXIMUM_PROCESSORS 32
106
158typedef struct {
159 uint32_t r1;
162 uint32_t r20;
163 uint32_t r21;
164 uint32_t r22;
165 uint32_t r23;
166 uint32_t r24;
167 uint32_t r25;
168 uint32_t r26;
169 uint32_t r27;
170 uint32_t r28;
171 uint32_t r29;
172 uint32_t r31;
173 uint32_t psw;
175
183#define _CPU_Context_Get_SP( _context ) \
184 (_context)->r3_stack_pointer
185
191typedef struct {
196 uint32_t special_interrupt_register;
198
218#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
219
224#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
225
237#define CPU_STACK_MINIMUM_SIZE (1024*4)
238
239#define CPU_SIZEOF_POINTER 4
240
249#define CPU_ALIGNMENT 8
250
274#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
275
280#define CPU_STACK_ALIGNMENT 8
281
282#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
283
284/*
285 * ISR handler macros
286 */
287
303#define _CPU_ISR_Disable( _isr_cookie ) \
304 do { \
305 unsigned int _psw; \
306 \
307 v850_get_psw( _psw ); \
308 __asm__ __volatile__( "di" ); \
309 _isr_cookie = _psw; \
310 } while (0)
311
323#define _CPU_ISR_Enable( _isr_cookie ) \
324 do { \
325 unsigned int _psw = (_isr_cookie); \
326 \
327 v850_set_psw( _psw ); \
328 } while (0)
329
342#define _CPU_ISR_Flash( _isr_cookie ) \
343 do { \
344 unsigned int _psw = (_isr_cookie); \
345 v850_set_psw( _psw ); \
346 __asm__ __volatile__( "di" ); \
347 } while (0)
348
349static inline bool _CPU_ISR_Is_enabled( uint32_t level )
350{
351 return ( level & V850_PSW_INTERRUPT_DISABLE_MASK )
352 != V850_PSW_INTERRUPT_DISABLE;
353}
354
370#define _CPU_ISR_Set_level( new_level ) \
371 do { \
372 if ( new_level ) \
373 __asm__ __volatile__( "di" ); \
374 else \
375 __asm__ __volatile__( "ei" ); \
376 } while (0)
377
388uint32_t _CPU_ISR_Get_level( void );
389
390/* end of ISR handler macros */
391
394/* Context handler macros */
395
428void _CPU_Context_Initialize(
429 Context_Control *the_context,
430 uint32_t *stack_base,
431 uint32_t size,
432 uint32_t new_level,
433 void *entry_point,
434 bool is_fp,
435 void *tls_area
436);
437
453#define _CPU_Context_Restart_self( _the_context ) \
454 _CPU_Context_restore( (_the_context) );
455
456/* XXX this should be possible to remove */
457#if 0
476#define _CPU_Context_Initialize_fp( _destination ) \
477 { \
478 }
479#endif
480
481/* end of Context handler macros */
482
483#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
484
485#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
486
487/* functions */
488
499void _CPU_Initialize(void);
500
501RTEMS_NO_RETURN void *_CPU_Thread_Idle_body( uintptr_t ignored );
502
519 Context_Control *run,
520 Context_Control *heir
521);
522
535RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context );
536
537/* XXX this should be possible to remove */
538#if 0
553 Context_Control_fp **fp_context_ptr
554);
555#endif
556
557/* XXX this should be possible to remove */
558#if 0
573 Context_Control_fp **fp_context_ptr
574);
575#endif
576
579/* FIXME */
581
583
620static inline uint32_t CPU_swap_u32(
621 uint32_t value
622)
623{
624 unsigned int swapped;
625
626 #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1)
627 unsigned int v;
628
629 v = value;
630 __asm__ __volatile__ ("bsw %0, %1" : "=r" (v), "=&r" (swapped) );
631 #else
632 uint32_t byte1, byte2, byte3, byte4;
633
634 byte4 = (value >> 24) & 0xff;
635 byte3 = (value >> 16) & 0xff;
636 byte2 = (value >> 8) & 0xff;
637 byte1 = value & 0xff;
638
639 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
640 #endif
641 return swapped;
642}
643
654static inline uint16_t CPU_swap_u16( uint16_t value )
655{
656 unsigned int swapped;
657
658 #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1)
659 unsigned int v;
660
661 v = value;
662 __asm__ __volatile__ ("bsh %0, %1" : "=r" (v), "=&r" (swapped) );
663 #else
664 swapped = ((value & 0xff) << 8) | ((value >> 8) & 0xff);
665 #endif
666 return swapped;
667}
668
671typedef uint32_t CPU_Counter_ticks;
672
673uint32_t _CPU_Counter_frequency( void );
674
675CPU_Counter_ticks _CPU_Counter_read( void );
676
678typedef uintptr_t CPU_Uint32ptr;
679
680#ifdef __cplusplus
681}
682#endif
683
684#endif
This header file provides basic definitions used by the API and the implementation.
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
#define CPU_swap_u16(value)
Definition: cpu.h:597
#define _CPU_Context_restore_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:901
#define _CPU_Context_save_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:895
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
SPARC basic context.
Definition: cpu.h:213
Thread register context.
Definition: cpu.h:173
uint32_t r3_stack_pointer
Definition: cpu.h:161
V850 Set up Basic CPU Dependency Settings Based on Compiler Settings.