RTEMS 6.1-rc7
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bsp.h
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1
9/*
10 * Copyright (c) 2012 Claas Ziemke. All rights reserved.
11 *
12 * Claas Ziemke
13 * Kernerstrasse 11
14 * 70182 Stuttgart
15 * Germany
16 * <claas.ziemke@gmx.net>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 *
22 * Modified by Ben Gras <beng@shrike-systems.com> to add lots
23 * of beagleboard/beaglebone definitions, delete lpc32xx specific
24 * ones, and merge with some other header files.
25 */
26
27#ifndef LIBBSP_ARM_BEAGLE_BSP_H
28#define LIBBSP_ARM_BEAGLE_BSP_H
29
40#include <bspopts.h>
41#include <stdint.h>
42#include <bsp/start.h>
44#include <bsp/beagleboneblack.h>
45
46#include <rtems.h>
47#include <rtems/irq-extension.h>
48
49#include <libcpu/omap3.h>
50#include <libcpu/am335x.h>
51
52#include <ofw/ofw.h>
53
54#define BSP_FEATURE_IRQ_EXTENSION
55
56/* UART base clock frequency */
57#define UART_CLOCK 48000000
58
59/* Access memory-mapped I/O devices */
60#define mmio_read(a) (*(volatile uint32_t *)(a))
61#define mmio_write(a,v) (*(volatile uint32_t *)(a) = (v))
62#define mmio_set(a,v) mmio_write((a), mmio_read((a)) | (v))
63#define mmio_clear(a,v) mmio_write((a), mmio_read((a)) & ~(v))
64
65#define REG16(x)(*((volatile uint16_t *)(x)))
66#define REG(x)(*((volatile uint32_t *)(x)))
67#define BIT(x)(0x1 << (x))
68// Start and End included
69#define BITS(Start, End) (((1 << (End+1)) - 1) & ~((1 << (Start)) - 1))
70
71#define udelay(u) rtems_task_wake_after(1 + ((u)/rtems_configuration_get_microseconds_per_tick()))
72
73int beagle_get_node_unit(phandle_t node);
74
75/* Write a uint32_t value to a memory address. */
76static inline void
77write32(uint32_t address, uint32_t value)
78{
79 REG(address) = value;
80}
81
82/* Read an uint32_t from a memory address */
83static inline uint32_t
84read32(uint32_t address)
85{
86 return REG(address);
87}
88
89/* Set a 32 bits value depending on a mask */
90static inline void
91set32(uint32_t address, uint32_t mask, uint32_t value)
92{
93 uint32_t val;
94 val = read32(address);
95 /* clear the bits */
96 val &= ~(mask);
97 /* apply the value using the mask */
98 val |= (value & mask);
99 write32(address, val);
100}
101
102/* Write a uint16_t value to a memory address. */
103static inline void
104write16(uint32_t address, uint16_t value)
105{
106 REG16(address) = value;
107}
108
109/* Read an uint16_t from a memory address */
110static inline uint16_t
111read16(uint32_t address)
112{
113 return REG16(address);
114}
115
116/* Data synchronization barrier */
117static inline void dsb(void)
118{
119 __asm__ volatile("dsb" : : : "memory");
120}
121
122/* Instruction synchronization barrier */
123static inline void isb(void)
124{
125 __asm__ volatile("isb" : : : "memory");
126}
127
128/* flush data cache */
129static inline void flush_data_cache(void)
130{
131 __asm__ volatile(
132 "mov r0, #0\n"
133 "mcr p15, #0, r0, c7, c10, #4\n"
134 : /* No outputs */
135 : /* No inputs */
136 : "r0","memory"
137 );
138}
139
140#define __arch_getb(a) (*(volatile unsigned char *)(a))
141#define __arch_getw(a) (*(volatile unsigned short *)(a))
142#define __arch_getl(a) (*(volatile unsigned int *)(a))
143
144#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
145#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
146#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
147
148#define writeb(v,c) ({ unsigned char __v = v; __arch_putb(__v,c); __v; })
149#define writew(v,c) ({ unsigned short __v = v; __arch_putw(__v,c); __v; })
150#define writel(v,c) ({ unsigned int __v = v; __arch_putl(__v,c); __v; })
151
152#define readb(c) ({ unsigned char __v = __arch_getb(c); __v; })
153#define readw(c) ({ unsigned short __v = __arch_getw(c); __v; })
154#define readl(c) ({ unsigned int __v = __arch_getl(c); __v; })
155
156#define SYSTEM_CLOCK_12 12000000
157#define SYSTEM_CLOCK_13 13000000
158#define SYSTEM_CLOCK_192 19200000
159#define SYSTEM_CLOCK_96 96000000
160
161#if !defined(IS_DM3730) && !defined(IS_AM335X)
162#error Unrecognized BSP configured.
163#endif
164
165#if IS_DM3730
166#define BSP_DEVICEMEM_START 0x48000000
167#define BSP_DEVICEMEM_END 0x5F000000
168#endif
169
170#if IS_AM335X
171#define BSP_DEVICEMEM_START 0x44000000
172#define BSP_DEVICEMEM_END 0x57000000
173#endif
174
175/* per-target uart config */
176#if IS_AM335X
177#define BSP_CONSOLE_UART 1
178#define BSP_CONSOLE_UART_BASE BEAGLE_BASE_UART_1
179#define BSP_CONSOLE_UART_IRQ OMAP3_UART1_IRQ
180#define BEAGLE_BASE_UART_1 0x44E09000
181#define BEAGLE_BASE_UART_2 0x48022000
182#define BEAGLE_BASE_UART_3 0x48024000
183#endif
184
185/* per-target uart config */
186#if IS_DM3730
187#define BSP_CONSOLE_UART 3
188#define BSP_CONSOLE_UART_BASE BEAGLE_BASE_UART_3
189#define BSP_CONSOLE_UART_IRQ OMAP3_UART3_IRQ
190#define BEAGLE_BASE_UART_1 0x4806A000
191#define BEAGLE_BASE_UART_2 0x4806C000
192#define BEAGLE_BASE_UART_3 0x49020000
193#endif
194
195/* GPIO pin config */
196#if IS_AM335X
197#define BSP_GPIO_PIN_COUNT 128
198#define BSP_GPIO_PINS_PER_BANK 32
199#endif
200
201#if IS_DM3730
202#define BSP_GPIO_PIN_COUNT 192
203#define BSP_GPIO_PINS_PER_BANK 32
204#endif
205
206#if BSP_START_COPY_FDT_FROM_U_BOOT
207#define BSP_FDT_IS_SUPPORTED
208#endif
209
210/* i2c stuff */
211typedef struct {
212 uint32_t rx_or_tx;
213 uint32_t stat;
214 uint32_t ctrl;
215 uint32_t clk_hi;
216 uint32_t clk_lo;
217 uint32_t adr;
218 uint32_t rxfl;
219 uint32_t txfl;
220 uint32_t rxb;
221 uint32_t txb;
222 uint32_t s_tx;
223 uint32_t s_txfl;
224} beagle_i2c;
225
226/* sctlr */
227/* Read System Control Register */
228static inline uint32_t read_sctlr(void)
229{
230 uint32_t ctl;
231
232 __asm__ volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t"
233 : [ctl] "=r" (ctl));
234 return ctl;
235}
236
237/* Write System Control Register */
238static inline void write_sctlr(uint32_t ctl)
239{
240 __asm__ volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t"
241 : : [ctl] "r" (ctl));
242 isb();
243}
244
245/* Read Auxiliary Control Register */
246static inline uint32_t read_actlr(void)
247{
248 uint32_t ctl;
249
250 __asm__ volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t"
251 : [ctl] "=r" (ctl));
252 return ctl;
253}
254
255/* Write Auxiliary Control Register */
256static inline void write_actlr(uint32_t ctl)
257{
258 __asm__ volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t"
259 : : [ctl] "r" (ctl));
260 isb();
261}
262
263/* Write Translation Table Base Control Register */
264static inline void write_ttbcr(uint32_t bcr)
265{
266 __asm__ volatile("mcr p15, 0, %[bcr], c2, c0, 2 @ Write TTBCR\n\t"
267 : : [bcr] "r" (bcr));
268
269 isb();
270}
271
272/* Read Domain Access Control Register */
273static inline uint32_t read_dacr(void)
274{
275 uint32_t dacr;
276
277 __asm__ volatile("mrc p15, 0, %[dacr], c3, c0, 0 @ Read DACR\n\t"
278 : [dacr] "=r" (dacr));
279
280 return dacr;
281}
282
283
284/* Write Domain Access Control Register */
285static inline void write_dacr(uint32_t dacr)
286{
287 __asm__ volatile("mcr p15, 0, %[dacr], c3, c0, 0 @ Write DACR\n\t"
288 : : [dacr] "r" (dacr));
289
290 isb();
291}
292
293static inline void refresh_tlb(void)
294{
295 dsb();
296
297 /* Invalidate entire unified TLB */
298 __asm__ volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t"
299 : : [zero] "r" (0));
300
301 /* Invalidate all instruction caches to PoU.
302 * Also flushes branch target cache. */
303 __asm__ volatile("mcr p15, 0, %[zero], c7, c5, 0"
304 : : [zero] "r" (0));
305
306 /* Invalidate entire branch predictor array */
307 __asm__ volatile("mcr p15, 0, %[zero], c7, c5, 6"
308 : : [zero] "r" (0)); /* flush BTB */
309
310 dsb();
311 isb();
312}
313
314/* Read Translation Table Base Register 0 */
315static inline uint32_t read_ttbr0(void)
316{
317 uint32_t bar;
318
319 __asm__ volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
320 : [bar] "=r" (bar));
321
322 return bar & ARM_TTBR_ADDR_MASK;
323}
324
325
326/* Read Translation Table Base Register 0 */
327static inline uint32_t read_ttbr0_unmasked(void)
328{
329 uint32_t bar;
330
331 __asm__ volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
332 : [bar] "=r" (bar));
333
334 return bar;
335}
336
337/* Write Translation Table Base Register 0 */
338static inline void write_ttbr0(uint32_t bar)
339{
340 dsb();
341 isb();
342 /* In our setup TTBR contains the base address *and* the flags
343 but other pieces of the kernel code expect ttbr to be the
344 base address of the l1 page table. We therefore add the
345 flags here and remove them in the read_ttbr0 */
346 uint32_t v = (bar & ARM_TTBR_ADDR_MASK ) | ARM_TTBR_FLAGS_CACHED;
347 __asm__ volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t"
348 : : [bar] "r" (v));
349
350 refresh_tlb();
351}
352
358BSP_START_TEXT_SECTION void beagle_setup_mmu_and_cache(void);
359
360/* @} */
361
362#endif /* LIBBSP_ARM_BEAGLE_BSP_H */
BeagleBone Black BSP definitions.
This header file provides the default definition of BSP_INITIAL_EXTENSION.
BSP_START_TEXT_SECTION void beagle_setup_mmu_and_cache(void)
Beagleboard specific set up of the MMU.
Definition: bspstartmmu.c:33
uint32_t phandle_t
Definition: ofw.h:56
This header file is provided for backward compatiblility.
This header file defines the RTEMS Classic API.
Definition: bsp.h:211