10#include "fsl_common.h"
24#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
27#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
28#ifndef FSL_SDK_DISBLE_L2CACHE_PRESENT
29#define FSL_SDK_DISBLE_L2CACHE_PRESENT 0
35#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
38typedef enum _l2cache_way_num
41#if defined(FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY) && FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY
47typedef enum _l2cache_way_size
49 kL2CACHE_16KBSize = 1,
50 kL2CACHE_32KBSize = 2,
51 kL2CACHE_64KBSize = 3,
52 kL2CACHE_128KBSize = 4,
53 kL2CACHE_256KBSize = 5,
54 kL2CACHE_512KBSize = 6
58typedef enum _l2cache_replacement
60 kL2CACHE_Pseudorandom = 0U,
62} l2cache_replacement_t;
65typedef enum _l2cache_writealloc
67 kL2CACHE_UseAwcache = 0,
68 kL2CACHE_NoWriteallocate,
69 kL2CACHE_forceWriteallocate
70} l2cache_writealloc_t;
73typedef enum _l2cache_latency
75 kL2CACHE_1CycleLate = 0,
86typedef struct _l2cache_latency_config
88 l2cache_latency_t tagWriteLate;
89 l2cache_latency_t tagReadLate;
90 l2cache_latency_t tagSetupLate;
91 l2cache_latency_t dataWriteLate;
92 l2cache_latency_t dataReadLate;
93 l2cache_latency_t dataSetupLate;
94} L2cache_latency_config_t;
97typedef struct _l2cache_config
100 l2cache_way_num_t wayNum;
101 l2cache_way_size waySize;
102 l2cache_replacement_t repacePolicy;
104 L2cache_latency_config_t *lateConfig;
106 bool istrPrefetchEnable;
107 bool dataPrefetchEnable;
109 bool nsLockdownEnable;
111 l2cache_writealloc_t writeAlloc;
118#if defined(__cplusplus)
131static inline void L1CACHE_EnableICache(
void)
140static inline void L1CACHE_DisableICache(
void)
152static inline void L1CACHE_InvalidateICache(
void)
173static inline void L1CACHE_EnableDCache(
void)
182static inline void L1CACHE_DisableDCache(
void)
194static inline void L1CACHE_InvalidateDCache(
void)
203static inline void L1CACHE_CleanDCache(
void)
212static inline void L1CACHE_CleanInvalidateDCache(
void)
227static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
242static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte)
257static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
263#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
274void L2CACHE_Init(l2cache_config_t *
config);
293void L2CACHE_GetDefaultConfig(l2cache_config_t *
config);
301void L2CACHE_Enable(
void);
309void L2CACHE_Disable(
void);
316void L2CACHE_Invalidate(
void);
329void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
336void L2CACHE_Clean(
void);
349void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte);
356void L2CACHE_CleanInvalidate(
void);
369void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte);
388void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask,
bool enable);
457#if defined(__cplusplus)
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr(volatile void *addr, int32_t dsize)
D-Cache Invalidate by address.
Definition: cachel1_armv7.h:358
__STATIC_FORCEINLINE void SCB_EnableDCache(void)
Enable D-Cache.
Definition: cachel1_armv7.h:141
__STATIC_FORCEINLINE void SCB_DisableICache(void)
Disable I-Cache.
Definition: cachel1_armv7.h:78
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache(void)
Clean & Invalidate D-Cache.
Definition: cachel1_armv7.h:319
__STATIC_FORCEINLINE void SCB_InvalidateICache(void)
Invalidate I-Cache.
Definition: cachel1_armv7.h:95
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr(volatile void *addr, int32_t dsize)
D-Cache Clean and Invalidate by address.
Definition: cachel1_armv7.h:418
__STATIC_FORCEINLINE void SCB_EnableICache(void)
Enable I-Cache.
Definition: cachel1_armv7.h:57
__STATIC_FORCEINLINE void SCB_InvalidateDCache(void)
Invalidate D-Cache.
Definition: cachel1_armv7.h:249
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr(volatile void *addr, int32_t dsize)
D-Cache Clean by address.
Definition: cachel1_armv7.h:388
__STATIC_FORCEINLINE void SCB_CleanDCache(void)
Clean D-Cache.
Definition: cachel1_armv7.h:284
__STATIC_FORCEINLINE void SCB_DisableDCache(void)
Disable D-Cache.
Definition: cachel1_armv7.h:181
#define SCB_CCR_DC_Msk
Definition: core_cm7.h:618
#define SCB_CCR_IC_Msk
Definition: core_cm7.h:615
#define SCB
Definition: core_cm4.h:1572
void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
Invalidates all instruction caches by range.
Definition: fsl_cache.c:527
void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
Cleans all data caches by range.
Definition: fsl_cache.c:572
void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
Invalidates all data caches by range.
Definition: fsl_cache.c:550
void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
Cleans and Invalidates all data caches by range.
Definition: fsl_cache.c:594
void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
Invalidate cortex-m7 L1 instruction cache by range.
Definition: fsl_cache.c:411
Definition: deflate.c:114