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#define | CPU_SIMPLE_VECTORED_INTERRUPTS TRUE |
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#define | CPU_ISR_PASSES_FRAME_POINTER FALSE |
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#define | CPU_HARDWARE_FP FALSE |
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#define | CPU_SOFTWARE_FP FALSE |
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#define | CPU_ALL_TASKS_ARE_FP FALSE |
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#define | CPU_IDLE_TASK_IS_FP FALSE |
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#define | CPU_USE_DEFERRED_FP_SWITCH FALSE |
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#define | CPU_STACK_GROWS_UP FALSE |
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#define | CPU_CACHE_LINE_BYTES 64 |
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#define | CPU_STRUCTURE_ALIGNMENT |
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#define | CPU_MODES_INTERRUPT_MASK 0x00000001 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R1 0 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R2 4 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R3 8 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R4 12 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R5 16 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R6 20 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R7 24 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R8 28 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R9 32 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R10 36 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R11 40 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R12 44 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R13 48 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R14 52 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R15 56 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R16 60 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R17 64 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R18 68 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R19 72 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R20 76 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R21 80 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R22 84 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R23 88 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R24 92 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R25 96 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R26 100 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R27 104 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R28 108 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R29 112 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R30 116 |
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#define | MICROBLAZE_EXCEPTION_FRAME_R31 120 |
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#define | MICROBLAZE_EXCEPTION_FRAME_MSR 124 |
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#define | MICROBLAZE_EXCEPTION_FRAME_EAR 128 |
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#define | MICROBLAZE_EXCEPTION_FRAME_ESR 132 |
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#define | MICROBLAZE_EXCEPTION_FRAME_BTR 136 |
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#define | CPU_EXCEPTION_FRAME_SIZE 140 |
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#define | _CPU_Context_Get_SP(_context) (_context)->r1 |
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#define | CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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#define | CPU_INTERRUPT_NUMBER_OF_VECTORS 32 |
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#define | CPU_USE_LIBC_INIT_FINI_ARRAY TRUE |
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#define | CPU_MAXIMUM_PROCESSORS 32 |
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#define | CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
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#define | CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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#define | CPU_STACK_MINIMUM_SIZE (1024*4) |
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#define | CPU_ALIGNMENT 4 |
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#define | CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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#define | CPU_STACK_ALIGNMENT CPU_ALIGNMENT |
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#define | CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES |
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#define | MICROBLAZE_MSR_VM ( 1 << 13 ) |
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#define | MICROBLAZE_MSR_UM ( 1 << 11 ) |
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#define | MICROBLAZE_MSR_PVR ( 1 << 10 ) |
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#define | MICROBLAZE_MSR_EIP ( 1 << 9 ) |
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#define | MICROBLAZE_MSR_EE ( 1 << 8 ) |
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#define | MICROBLAZE_MSR_DCE ( 1 << 7 ) |
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#define | MICROBLAZE_MSR_DZO ( 1 << 6 ) |
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#define | MICROBLAZE_MSR_ICE ( 1 << 5 ) |
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#define | MICROBLAZE_MSR_FSL ( 1 << 4 ) |
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#define | MICROBLAZE_MSR_BIP ( 1 << 3 ) |
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#define | MICROBLAZE_MSR_C ( 1 << 2 ) |
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#define | MICROBLAZE_MSR_IE ( 1 << 1 ) |
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#define | MICROBLAZE_ESR_DS ( 1 << 12 ) |
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#define | MICROBLAZE_ESR_EC_MASK 0x1f |
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#define | MICROBLAZE_ESR_ESS_MASK 0x7f |
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#define | MICROBLAZE_ESR_ESS_SHIFT 5 |
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#define | _CPU_MSR_GET(_msr_value) |
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#define | _CPU_MSR_SET(_msr_value) { __asm__ volatile ("mts rmsr, %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); } |
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#define | MICROBLAZE_PVR0_VERSION_GET(_pvr0_value) ( ( _pvr0_value >> 8 ) & 0xff ) |
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#define | _CPU_PVR0_GET(_pvr0_value) |
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#define | MICROBLAZE_PVR3_BP_GET(_pvr3_value) ( ( _pvr3_value >> 25 ) & 0xf ) |
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#define | MICROBLAZE_PVR3_RWP_GET(_pvr3_value) ( ( _pvr3_value >> 19 ) & 0x7 ) |
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#define | MICROBLAZE_PVR3_WWP_GET(_pvr3_value) ( ( _pvr3_value >> 13 ) & 0x7 ) |
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#define | _CPU_PVR3_GET(_pvr3_value) |
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#define | _CPU_ISR_Disable(_isr_cookie) |
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#define | _CPU_ISR_Enable(_isr_cookie) |
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#define | _CPU_ISR_Flash(_isr_cookie) |
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#define | _CPU_Context_Restart_self(_the_context) _CPU_Context_restore( (_the_context) ); |
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#define | _CPU_Context_Initialize_fp(_destination) |
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#define | CPU_USE_GENERIC_BITFIELD_CODE TRUE |
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#define | CPU_SIZEOF_POINTER 4 |
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#define | CPU_PER_CPU_CONTROL_SIZE 0 |
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#define | CPU_swap_u16(value) (((value&0xff) << 8) | ((value >> 8)&0xff)) |
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void | _CPU_ISR_Set_level (uint32_t level) |
| Sets the hardware interrupt level by the level value.
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uint32_t | _CPU_ISR_Get_level (void) |
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void | _CPU_Context_Initialize (Context_Control *context, void *stack_area_begin, size_t stack_area_size, uint32_t new_level, void(*entry_point)(void), bool is_fp, void *tls_area) |
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void | _CPU_Initialize (void) |
| CPU initialization.
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void | _CPU_ISR_install_vector (uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler) |
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void | _MicroBlaze_Exception_install_handler (MicroBlaze_Exception_handler new_handler, MicroBlaze_Exception_handler *old_handler) |
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void | _MicroBlaze_Exception_handle (CPU_Exception_frame *ef) |
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void | _MicroBlaze_Debug_install_handler (MicroBlaze_Exception_handler new_handler, MicroBlaze_Exception_handler *old_handler) |
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void | _MicroBlaze_Debug_handle (CPU_Exception_frame *ef) |
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void | _CPU_Context_switch (Context_Control *run, Context_Control *heir) |
| CPU switch context.
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RTEMS_NO_RETURN void | _CPU_Exception_resume (CPU_Exception_frame *frame) |
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RTEMS_NO_RETURN void | _MicroBlaze_Exception_resume_from_exception (CPU_Exception_frame *frame) |
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RTEMS_NO_RETURN void | _MicroBlaze_Exception_resume_from_break (CPU_Exception_frame *frame) |
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RTEMS_NO_RETURN void | _CPU_Exception_dispatch_and_resume (CPU_Exception_frame *frame) |
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void | _CPU_Exception_disable_thread_dispatch (void) |
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int | _CPU_Exception_frame_get_signal (CPU_Exception_frame *frame) |
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void | _CPU_Exception_frame_set_resume (CPU_Exception_frame *frame, void *address) |
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void | _CPU_Exception_frame_make_resume_next_instruction (CPU_Exception_frame *frame) |
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uint32_t * | _MicroBlaze_Get_return_address (CPU_Exception_frame *ef) |
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RTEMS_NO_RETURN void | _CPU_Context_restore (Context_Control *new_context) |
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void | _CPU_Exception_frame_print (const CPU_Exception_frame *frame) |
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uint32_t | _CPU_Counter_frequency (void) |
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CPU_Counter_ticks | _CPU_Counter_read (void) |
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RTEMS_NO_RETURN void * | _CPU_Thread_Idle_body (uintptr_t ignored) |
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void | bsp_interrupt_dispatch (uint32_t source) |
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MicroBlaze architecture support.