RTEMS 6.1-rc7
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core_cm7.h
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1/**************************************************************************/
7/*
8 * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25#if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27#elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29#endif
30
31#ifndef __CORE_CM7_H_GENERIC
32#define __CORE_CM7_H_GENERIC
33
34#include <stdint.h>
35
36#ifdef __cplusplus
37 extern "C" {
38#endif
39
55/*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
63#include "cmsis_version.h"
64
65/* CMSIS CM7 definitions */
66#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
67#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB)
68#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
69 __CM7_CMSIS_VERSION_SUB )
71#define __CORTEX_M (7U)
76#if defined ( __CC_ARM )
77 #if defined __TARGET_FPU_VFP
78 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
79 #define __FPU_USED 1U
80 #else
81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
82 #define __FPU_USED 0U
83 #endif
84 #else
85 #define __FPU_USED 0U
86 #endif
87
88#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
89 #if defined __ARM_FP
90 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
91 #define __FPU_USED 1U
92 #else
93 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
94 #define __FPU_USED 0U
95 #endif
96 #else
97 #define __FPU_USED 0U
98 #endif
99
100#elif defined (__ti__)
101 #if defined (__ARM_FP)
102 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
103 #define __FPU_USED 1U
104 #else
105 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #define __FPU_USED 0U
107 #endif
108 #else
109 #define __FPU_USED 0U
110 #endif
111
112#elif defined ( __GNUC__ )
113 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
114 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
115 #define __FPU_USED 1U
116 #else
117 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
118 #define __FPU_USED 0U
119 #endif
120 #else
121 #define __FPU_USED 0U
122 #endif
123
124#elif defined ( __ICCARM__ )
125 #if defined __ARMVFP__
126 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
127 #define __FPU_USED 1U
128 #else
129 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
130 #define __FPU_USED 0U
131 #endif
132 #else
133 #define __FPU_USED 0U
134 #endif
135
136#elif defined ( __TI_ARM__ )
137 #if defined __TI_VFP_SUPPORT__
138 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
139 #define __FPU_USED 1U
140 #else
141 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
142 #define __FPU_USED 0U
143 #endif
144 #else
145 #define __FPU_USED 0U
146 #endif
147
148#elif defined ( __TASKING__ )
149 #if defined __FPU_VFP__
150 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
151 #define __FPU_USED 1U
152 #else
153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154 #define __FPU_USED 0U
155 #endif
156 #else
157 #define __FPU_USED 0U
158 #endif
159
160#elif defined ( __CSMC__ )
161 #if ( __CSMC__ & 0x400U)
162 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
163 #define __FPU_USED 1U
164 #else
165 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
166 #define __FPU_USED 0U
167 #endif
168 #else
169 #define __FPU_USED 0U
170 #endif
171
172#endif
173
174#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
175
176
177#ifdef __cplusplus
178}
179#endif
180
181#endif /* __CORE_CM7_H_GENERIC */
182
183#ifndef __CMSIS_GENERIC
184
185#ifndef __CORE_CM7_H_DEPENDANT
186#define __CORE_CM7_H_DEPENDANT
187
188#ifdef __cplusplus
189 extern "C" {
190#endif
191
192/* check device defines and use defaults */
193#if defined __CHECK_DEVICE_DEFINES
194 #ifndef __CM7_REV
195 #define __CM7_REV 0x0000U
196 #warning "__CM7_REV not defined in device header file; using default!"
197 #endif
198
199 #ifndef __FPU_PRESENT
200 #define __FPU_PRESENT 0U
201 #warning "__FPU_PRESENT not defined in device header file; using default!"
202 #endif
203
204 #ifndef __MPU_PRESENT
205 #define __MPU_PRESENT 0U
206 #warning "__MPU_PRESENT not defined in device header file; using default!"
207 #endif
208
209 #ifndef __ICACHE_PRESENT
210 #define __ICACHE_PRESENT 0U
211 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
212 #endif
213
214 #ifndef __DCACHE_PRESENT
215 #define __DCACHE_PRESENT 0U
216 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
217 #endif
218
219 #ifndef __DTCM_PRESENT
220 #define __DTCM_PRESENT 0U
221 #warning "__DTCM_PRESENT not defined in device header file; using default!"
222 #endif
223
224 #ifndef __VTOR_PRESENT
225 #define __VTOR_PRESENT 1U
226 #warning "__VTOR_PRESENT not defined in device header file; using default!"
227 #endif
228
229 #ifndef __NVIC_PRIO_BITS
230 #define __NVIC_PRIO_BITS 3U
231 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
232 #endif
233
234 #ifndef __Vendor_SysTickConfig
235 #define __Vendor_SysTickConfig 0U
236 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
237 #endif
238#endif
239
240/* IO definitions (access restrictions to peripheral registers) */
248#ifdef __cplusplus
249 #define __I volatile
250#else
251 #define __I volatile const
252#endif
253#define __O volatile
254#define __IO volatile
256/* following defines should be used for structure members */
257#define __IM volatile const
258#define __OM volatile
259#define __IOM volatile
265/*******************************************************************************
266 * Register Abstraction
267 Core Register contain:
268 - Core Register
269 - Core NVIC Register
270 - Core SCB Register
271 - Core SysTick Register
272 - Core Debug Register
273 - Core MPU Register
274 - Core FPU Register
275 ******************************************************************************/
291typedef union
292{
293 struct
294 {
295 uint32_t _reserved0:16;
296 uint32_t GE:4;
297 uint32_t _reserved1:7;
298 uint32_t Q:1;
299 uint32_t V:1;
300 uint32_t C:1;
301 uint32_t Z:1;
302 uint32_t N:1;
303 } b;
304 uint32_t w;
305} APSR_Type;
306
307/* APSR Register Definitions */
308#define APSR_N_Pos 31U
309#define APSR_N_Msk (1UL << APSR_N_Pos)
311#define APSR_Z_Pos 30U
312#define APSR_Z_Msk (1UL << APSR_Z_Pos)
314#define APSR_C_Pos 29U
315#define APSR_C_Msk (1UL << APSR_C_Pos)
317#define APSR_V_Pos 28U
318#define APSR_V_Msk (1UL << APSR_V_Pos)
320#define APSR_Q_Pos 27U
321#define APSR_Q_Msk (1UL << APSR_Q_Pos)
323#define APSR_GE_Pos 16U
324#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)
330typedef union
331{
332 struct
333 {
334 uint32_t ISR:9;
335 uint32_t _reserved0:23;
336 } b;
337 uint32_t w;
338} IPSR_Type;
339
340/* IPSR Register Definitions */
341#define IPSR_ISR_Pos 0U
342#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
348typedef union
349{
350 struct
351 {
352 uint32_t ISR:9;
353 uint32_t _reserved0:1;
354 uint32_t ICI_IT_1:6;
355 uint32_t GE:4;
356 uint32_t _reserved1:4;
357 uint32_t T:1;
358 uint32_t ICI_IT_2:2;
359 uint32_t Q:1;
360 uint32_t V:1;
361 uint32_t C:1;
362 uint32_t Z:1;
363 uint32_t N:1;
364 } b;
365 uint32_t w;
366} xPSR_Type;
367
368/* xPSR Register Definitions */
369#define xPSR_N_Pos 31U
370#define xPSR_N_Msk (1UL << xPSR_N_Pos)
372#define xPSR_Z_Pos 30U
373#define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
375#define xPSR_C_Pos 29U
376#define xPSR_C_Msk (1UL << xPSR_C_Pos)
378#define xPSR_V_Pos 28U
379#define xPSR_V_Msk (1UL << xPSR_V_Pos)
381#define xPSR_Q_Pos 27U
382#define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
384#define xPSR_ICI_IT_2_Pos 25U
385#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)
387#define xPSR_T_Pos 24U
388#define xPSR_T_Msk (1UL << xPSR_T_Pos)
390#define xPSR_GE_Pos 16U
391#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
393#define xPSR_ICI_IT_1_Pos 10U
394#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)
396#define xPSR_ISR_Pos 0U
397#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
403typedef union
404{
405 struct
406 {
407 uint32_t nPRIV:1;
408 uint32_t SPSEL:1;
409 uint32_t FPCA:1;
410 uint32_t _reserved0:29;
411 } b;
412 uint32_t w;
414
415/* CONTROL Register Definitions */
416#define CONTROL_FPCA_Pos 2U
417#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
419#define CONTROL_SPSEL_Pos 1U
420#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
422#define CONTROL_nPRIV_Pos 0U
423#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
438typedef struct
439{
440 __IOM uint32_t ISER[8U];
441 uint32_t RESERVED0[24U];
442 __IOM uint32_t ICER[8U];
443 uint32_t RESERVED1[24U];
444 __IOM uint32_t ISPR[8U];
445 uint32_t RESERVED2[24U];
446 __IOM uint32_t ICPR[8U];
447 uint32_t RESERVED3[24U];
448 __IOM uint32_t IABR[8U];
449 uint32_t RESERVED4[56U];
450 __IOM uint8_t IP[240U];
451 uint32_t RESERVED5[644U];
452 __OM uint32_t STIR;
453} NVIC_Type;
454
455/* Software Triggered Interrupt Register Definitions */
456#define NVIC_STIR_INTID_Pos 0U
457#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
472typedef struct
473{
474 __IM uint32_t CPUID;
475 __IOM uint32_t ICSR;
476 __IOM uint32_t VTOR;
477 __IOM uint32_t AIRCR;
478 __IOM uint32_t SCR;
479 __IOM uint32_t CCR;
480 __IOM uint8_t SHPR[12U];
481 __IOM uint32_t SHCSR;
482 __IOM uint32_t CFSR;
483 __IOM uint32_t HFSR;
484 __IOM uint32_t DFSR;
485 __IOM uint32_t MMFAR;
486 __IOM uint32_t BFAR;
487 __IOM uint32_t AFSR;
488 __IM uint32_t ID_PFR[2U];
489 __IM uint32_t ID_DFR;
490 __IM uint32_t ID_AFR;
491 __IM uint32_t ID_MFR[4U];
492 __IM uint32_t ID_ISAR[5U];
493 uint32_t RESERVED0[1U];
494 __IM uint32_t CLIDR;
495 __IM uint32_t CTR;
496 __IM uint32_t CCSIDR;
497 __IOM uint32_t CSSELR;
498 __IOM uint32_t CPACR;
499 uint32_t RESERVED3[93U];
500 __OM uint32_t STIR;
501 uint32_t RESERVED4[15U];
502 __IM uint32_t MVFR0;
503 __IM uint32_t MVFR1;
504 __IM uint32_t MVFR2;
505 uint32_t RESERVED5[1U];
506 __OM uint32_t ICIALLU;
507 uint32_t RESERVED6[1U];
508 __OM uint32_t ICIMVAU;
509 __OM uint32_t DCIMVAC;
510 __OM uint32_t DCISW;
511 __OM uint32_t DCCMVAU;
512 __OM uint32_t DCCMVAC;
513 __OM uint32_t DCCSW;
514 __OM uint32_t DCCIMVAC;
515 __OM uint32_t DCCISW;
516 __OM uint32_t BPIALL;
517 uint32_t RESERVED7[5U];
518 __IOM uint32_t ITCMCR;
519 __IOM uint32_t DTCMCR;
520 __IOM uint32_t AHBPCR;
521 __IOM uint32_t CACR;
522 __IOM uint32_t AHBSCR;
523 uint32_t RESERVED8[1U];
524 __IOM uint32_t ABFSR;
525} SCB_Type;
526
527/* SCB CPUID Register Definitions */
528#define SCB_CPUID_IMPLEMENTER_Pos 24U
529#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
531#define SCB_CPUID_VARIANT_Pos 20U
532#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
534#define SCB_CPUID_ARCHITECTURE_Pos 16U
535#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
537#define SCB_CPUID_PARTNO_Pos 4U
538#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
540#define SCB_CPUID_REVISION_Pos 0U
541#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
543/* SCB Interrupt Control State Register Definitions */
544#define SCB_ICSR_NMIPENDSET_Pos 31U
545#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
547#define SCB_ICSR_PENDSVSET_Pos 28U
548#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
550#define SCB_ICSR_PENDSVCLR_Pos 27U
551#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
553#define SCB_ICSR_PENDSTSET_Pos 26U
554#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
556#define SCB_ICSR_PENDSTCLR_Pos 25U
557#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
559#define SCB_ICSR_ISRPREEMPT_Pos 23U
560#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
562#define SCB_ICSR_ISRPENDING_Pos 22U
563#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
565#define SCB_ICSR_VECTPENDING_Pos 12U
566#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
568#define SCB_ICSR_RETTOBASE_Pos 11U
569#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
571#define SCB_ICSR_VECTACTIVE_Pos 0U
572#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
574/* SCB Vector Table Offset Register Definitions */
575#define SCB_VTOR_TBLOFF_Pos 7U
576#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
578/* SCB Application Interrupt and Reset Control Register Definitions */
579#define SCB_AIRCR_VECTKEY_Pos 16U
580#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
582#define SCB_AIRCR_VECTKEYSTAT_Pos 16U
583#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
585#define SCB_AIRCR_ENDIANESS_Pos 15U
586#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
588#define SCB_AIRCR_PRIGROUP_Pos 8U
589#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
591#define SCB_AIRCR_SYSRESETREQ_Pos 2U
592#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
594#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
595#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
597#define SCB_AIRCR_VECTRESET_Pos 0U
598#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
600/* SCB System Control Register Definitions */
601#define SCB_SCR_SEVONPEND_Pos 4U
602#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
604#define SCB_SCR_SLEEPDEEP_Pos 2U
605#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
607#define SCB_SCR_SLEEPONEXIT_Pos 1U
608#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
610/* SCB Configuration Control Register Definitions */
611#define SCB_CCR_BP_Pos 18U
612#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
614#define SCB_CCR_IC_Pos 17U
615#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
617#define SCB_CCR_DC_Pos 16U
618#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
620#define SCB_CCR_STKALIGN_Pos 9U
621#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
623#define SCB_CCR_BFHFNMIGN_Pos 8U
624#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
626#define SCB_CCR_DIV_0_TRP_Pos 4U
627#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
629#define SCB_CCR_UNALIGN_TRP_Pos 3U
630#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
632#define SCB_CCR_USERSETMPEND_Pos 1U
633#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
635#define SCB_CCR_NONBASETHRDENA_Pos 0U
636#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
638/* SCB System Handler Control and State Register Definitions */
639#define SCB_SHCSR_USGFAULTENA_Pos 18U
640#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
642#define SCB_SHCSR_BUSFAULTENA_Pos 17U
643#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
645#define SCB_SHCSR_MEMFAULTENA_Pos 16U
646#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
648#define SCB_SHCSR_SVCALLPENDED_Pos 15U
649#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
651#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
652#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
654#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
655#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
657#define SCB_SHCSR_USGFAULTPENDED_Pos 12U
658#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
660#define SCB_SHCSR_SYSTICKACT_Pos 11U
661#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
663#define SCB_SHCSR_PENDSVACT_Pos 10U
664#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
666#define SCB_SHCSR_MONITORACT_Pos 8U
667#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
669#define SCB_SHCSR_SVCALLACT_Pos 7U
670#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
672#define SCB_SHCSR_USGFAULTACT_Pos 3U
673#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
675#define SCB_SHCSR_BUSFAULTACT_Pos 1U
676#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
678#define SCB_SHCSR_MEMFAULTACT_Pos 0U
679#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
681/* SCB Configurable Fault Status Register Definitions */
682#define SCB_CFSR_USGFAULTSR_Pos 16U
683#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
685#define SCB_CFSR_BUSFAULTSR_Pos 8U
686#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
688#define SCB_CFSR_MEMFAULTSR_Pos 0U
689#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
691/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
692#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U)
693#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
695#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U)
696#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)
698#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U)
699#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
701#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U)
702#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
704#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U)
705#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
707#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U)
708#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
710/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
711#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
712#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
714#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)
715#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)
717#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
718#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
720#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
721#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
723#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
724#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
726#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
727#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
729#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
730#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
732/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
733#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
734#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
736#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
737#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
739#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
740#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
742#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
743#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
745#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
746#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
748#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
749#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
751/* SCB Hard Fault Status Register Definitions */
752#define SCB_HFSR_DEBUGEVT_Pos 31U
753#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
755#define SCB_HFSR_FORCED_Pos 30U
756#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
758#define SCB_HFSR_VECTTBL_Pos 1U
759#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
761/* SCB Debug Fault Status Register Definitions */
762#define SCB_DFSR_EXTERNAL_Pos 4U
763#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
765#define SCB_DFSR_VCATCH_Pos 3U
766#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
768#define SCB_DFSR_DWTTRAP_Pos 2U
769#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
771#define SCB_DFSR_BKPT_Pos 1U
772#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
774#define SCB_DFSR_HALTED_Pos 0U
775#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
777/* SCB Cache Level ID Register Definitions */
778#define SCB_CLIDR_LOUU_Pos 27U
779#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
781#define SCB_CLIDR_LOC_Pos 24U
782#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)
784/* SCB Cache Type Register Definitions */
785#define SCB_CTR_FORMAT_Pos 29U
786#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
788#define SCB_CTR_CWG_Pos 24U
789#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
791#define SCB_CTR_ERG_Pos 20U
792#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
794#define SCB_CTR_DMINLINE_Pos 16U
795#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
797#define SCB_CTR_IMINLINE_Pos 0U
798#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
800/* SCB Cache Size ID Register Definitions */
801#define SCB_CCSIDR_WT_Pos 31U
802#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)
804#define SCB_CCSIDR_WB_Pos 30U
805#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)
807#define SCB_CCSIDR_RA_Pos 29U
808#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)
810#define SCB_CCSIDR_WA_Pos 28U
811#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)
813#define SCB_CCSIDR_NUMSETS_Pos 13U
814#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
816#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U
817#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
819#define SCB_CCSIDR_LINESIZE_Pos 0U
820#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
822/* SCB Cache Size Selection Register Definitions */
823#define SCB_CSSELR_LEVEL_Pos 1U
824#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)
826#define SCB_CSSELR_IND_Pos 0U
827#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)
829/* SCB Software Triggered Interrupt Register Definitions */
830#define SCB_STIR_INTID_Pos 0U
831#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
833/* SCB D-Cache Invalidate by Set-way Register Definitions */
834#define SCB_DCISW_WAY_Pos 30U
835#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)
837#define SCB_DCISW_SET_Pos 5U
838#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)
840/* SCB D-Cache Clean by Set-way Register Definitions */
841#define SCB_DCCSW_WAY_Pos 30U
842#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)
844#define SCB_DCCSW_SET_Pos 5U
845#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)
847/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
848#define SCB_DCCISW_WAY_Pos 30U
849#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)
851#define SCB_DCCISW_SET_Pos 5U
852#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)
854/* Instruction Tightly-Coupled Memory Control Register Definitions */
855#define SCB_ITCMCR_SZ_Pos 3U
856#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)
858#define SCB_ITCMCR_RETEN_Pos 2U
859#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)
861#define SCB_ITCMCR_RMW_Pos 1U
862#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)
864#define SCB_ITCMCR_EN_Pos 0U
865#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/)
867/* Data Tightly-Coupled Memory Control Register Definitions */
868#define SCB_DTCMCR_SZ_Pos 3U
869#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)
871#define SCB_DTCMCR_RETEN_Pos 2U
872#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)
874#define SCB_DTCMCR_RMW_Pos 1U
875#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)
877#define SCB_DTCMCR_EN_Pos 0U
878#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/)
880/* AHBP Control Register Definitions */
881#define SCB_AHBPCR_SZ_Pos 1U
882#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)
884#define SCB_AHBPCR_EN_Pos 0U
885#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/)
887/* L1 Cache Control Register Definitions */
888#define SCB_CACR_FORCEWT_Pos 2U
889#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)
891#define SCB_CACR_ECCEN_Pos 1U
892#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)
894#define SCB_CACR_ECCDIS_Pos 1U
895#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos)
897#define SCB_CACR_SIWT_Pos 0U
898#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/)
900/* AHBS Control Register Definitions */
901#define SCB_AHBSCR_INITCOUNT_Pos 11U
902#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos)
904#define SCB_AHBSCR_TPRI_Pos 2U
905#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos)
907#define SCB_AHBSCR_CTL_Pos 0U
908#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/)
910/* Auxiliary Bus Fault Status Register Definitions */
911#define SCB_ABFSR_AXIMTYPE_Pos 8U
912#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)
914#define SCB_ABFSR_EPPB_Pos 4U
915#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)
917#define SCB_ABFSR_AXIM_Pos 3U
918#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)
920#define SCB_ABFSR_AHBP_Pos 2U
921#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)
923#define SCB_ABFSR_DTCM_Pos 1U
924#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)
926#define SCB_ABFSR_ITCM_Pos 0U
927#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
942typedef struct
943{
944 uint32_t RESERVED0[1U];
945 __IM uint32_t ICTR;
946 __IOM uint32_t ACTLR;
948
949/* Interrupt Controller Type Register Definitions */
950#define SCnSCB_ICTR_INTLINESNUM_Pos 0U
951#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
953/* Auxiliary Control Register Definitions */
954#define SCnSCB_ACTLR_DISDYNADD_Pos 26U
955#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos)
957#define SCnSCB_ACTLR_DISISSCH1_Pos 21U
958#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos)
960#define SCnSCB_ACTLR_DISDI_Pos 16U
961#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos)
963#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U
964#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos)
966#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U
967#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos)
969#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U
970#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos)
972#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U
973#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)
975#define SCnSCB_ACTLR_DISRAMODE_Pos 11U
976#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)
978#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U
979#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)
981#define SCnSCB_ACTLR_DISFOLD_Pos 2U
982#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
984#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U
985#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)
1000typedef struct
1001{
1002 __IOM uint32_t CTRL;
1003 __IOM uint32_t LOAD;
1004 __IOM uint32_t VAL;
1005 __IM uint32_t CALIB;
1006} SysTick_Type;
1007
1008/* SysTick Control / Status Register Definitions */
1009#define SysTick_CTRL_COUNTFLAG_Pos 16U
1010#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
1012#define SysTick_CTRL_CLKSOURCE_Pos 2U
1013#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
1015#define SysTick_CTRL_TICKINT_Pos 1U
1016#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
1018#define SysTick_CTRL_ENABLE_Pos 0U
1019#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
1021/* SysTick Reload Register Definitions */
1022#define SysTick_LOAD_RELOAD_Pos 0U
1023#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
1025/* SysTick Current Register Definitions */
1026#define SysTick_VAL_CURRENT_Pos 0U
1027#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
1029/* SysTick Calibration Register Definitions */
1030#define SysTick_CALIB_NOREF_Pos 31U
1031#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
1033#define SysTick_CALIB_SKEW_Pos 30U
1034#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
1036#define SysTick_CALIB_TENMS_Pos 0U
1037#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
1052typedef struct
1053{
1054 __OM union
1055 {
1056 __OM uint8_t u8;
1057 __OM uint16_t u16;
1058 __OM uint32_t u32;
1059 } PORT [32U];
1060 uint32_t RESERVED0[864U];
1061 __IOM uint32_t TER;
1062 uint32_t RESERVED1[15U];
1063 __IOM uint32_t TPR;
1064 uint32_t RESERVED2[15U];
1065 __IOM uint32_t TCR;
1066 uint32_t RESERVED3[32U];
1067 uint32_t RESERVED4[43U];
1068 __OM uint32_t LAR;
1069 __IM uint32_t LSR;
1070 uint32_t RESERVED5[6U];
1071 __IM uint32_t PID4;
1072 __IM uint32_t PID5;
1073 __IM uint32_t PID6;
1074 __IM uint32_t PID7;
1075 __IM uint32_t PID0;
1076 __IM uint32_t PID1;
1077 __IM uint32_t PID2;
1078 __IM uint32_t PID3;
1079 __IM uint32_t CID0;
1080 __IM uint32_t CID1;
1081 __IM uint32_t CID2;
1082 __IM uint32_t CID3;
1083} ITM_Type;
1084
1085/* ITM Trace Privilege Register Definitions */
1086#define ITM_TPR_PRIVMASK_Pos 0U
1087#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
1089/* ITM Trace Control Register Definitions */
1090#define ITM_TCR_BUSY_Pos 23U
1091#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
1093#define ITM_TCR_TRACEBUSID_Pos 16U
1094#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
1096#define ITM_TCR_GTSFREQ_Pos 10U
1097#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
1099#define ITM_TCR_TSPRESCALE_Pos 8U
1100#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)
1102#define ITM_TCR_SWOENA_Pos 4U
1103#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
1105#define ITM_TCR_DWTENA_Pos 3U
1106#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
1108#define ITM_TCR_SYNCENA_Pos 2U
1109#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
1111#define ITM_TCR_TSENA_Pos 1U
1112#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
1114#define ITM_TCR_ITMENA_Pos 0U
1115#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
1117/* ITM Lock Status Register Definitions */
1118#define ITM_LSR_BYTEACC_Pos 2U
1119#define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos)
1121#define ITM_LSR_ACCESS_Pos 1U
1122#define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos)
1124#define ITM_LSR_PRESENT_Pos 0U
1125#define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) /* end of group CMSIS_ITM */
1128
1129
1140typedef struct
1141{
1142 __IOM uint32_t CTRL;
1143 __IOM uint32_t CYCCNT;
1144 __IOM uint32_t CPICNT;
1145 __IOM uint32_t EXCCNT;
1146 __IOM uint32_t SLEEPCNT;
1147 __IOM uint32_t LSUCNT;
1148 __IOM uint32_t FOLDCNT;
1149 __IM uint32_t PCSR;
1150 __IOM uint32_t COMP0;
1151 __IOM uint32_t MASK0;
1152 __IOM uint32_t FUNCTION0;
1153 uint32_t RESERVED0[1U];
1154 __IOM uint32_t COMP1;
1155 __IOM uint32_t MASK1;
1156 __IOM uint32_t FUNCTION1;
1157 uint32_t RESERVED1[1U];
1158 __IOM uint32_t COMP2;
1159 __IOM uint32_t MASK2;
1160 __IOM uint32_t FUNCTION2;
1161 uint32_t RESERVED2[1U];
1162 __IOM uint32_t COMP3;
1163 __IOM uint32_t MASK3;
1164 __IOM uint32_t FUNCTION3;
1165 uint32_t RESERVED3[981U];
1166 __OM uint32_t LAR;
1167 __IM uint32_t LSR;
1168} DWT_Type;
1169
1170/* DWT Control Register Definitions */
1171#define DWT_CTRL_NUMCOMP_Pos 28U
1172#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
1174#define DWT_CTRL_NOTRCPKT_Pos 27U
1175#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
1177#define DWT_CTRL_NOEXTTRIG_Pos 26U
1178#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
1180#define DWT_CTRL_NOCYCCNT_Pos 25U
1181#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
1183#define DWT_CTRL_NOPRFCNT_Pos 24U
1184#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
1186#define DWT_CTRL_CYCEVTENA_Pos 22U
1187#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
1189#define DWT_CTRL_FOLDEVTENA_Pos 21U
1190#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
1192#define DWT_CTRL_LSUEVTENA_Pos 20U
1193#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
1195#define DWT_CTRL_SLEEPEVTENA_Pos 19U
1196#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
1198#define DWT_CTRL_EXCEVTENA_Pos 18U
1199#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
1201#define DWT_CTRL_CPIEVTENA_Pos 17U
1202#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
1204#define DWT_CTRL_EXCTRCENA_Pos 16U
1205#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
1207#define DWT_CTRL_PCSAMPLENA_Pos 12U
1208#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
1210#define DWT_CTRL_SYNCTAP_Pos 10U
1211#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
1213#define DWT_CTRL_CYCTAP_Pos 9U
1214#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
1216#define DWT_CTRL_POSTINIT_Pos 5U
1217#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
1219#define DWT_CTRL_POSTPRESET_Pos 1U
1220#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
1222#define DWT_CTRL_CYCCNTENA_Pos 0U
1223#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
1225/* DWT CPI Count Register Definitions */
1226#define DWT_CPICNT_CPICNT_Pos 0U
1227#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
1229/* DWT Exception Overhead Count Register Definitions */
1230#define DWT_EXCCNT_EXCCNT_Pos 0U
1231#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
1233/* DWT Sleep Count Register Definitions */
1234#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
1235#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
1237/* DWT LSU Count Register Definitions */
1238#define DWT_LSUCNT_LSUCNT_Pos 0U
1239#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
1241/* DWT Folded-instruction Count Register Definitions */
1242#define DWT_FOLDCNT_FOLDCNT_Pos 0U
1243#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
1245/* DWT Comparator Mask Register Definitions */
1246#define DWT_MASK_MASK_Pos 0U
1247#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/)
1249/* DWT Comparator Function Register Definitions */
1250#define DWT_FUNCTION_MATCHED_Pos 24U
1251#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
1253#define DWT_FUNCTION_DATAVADDR1_Pos 16U
1254#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
1256#define DWT_FUNCTION_DATAVADDR0_Pos 12U
1257#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
1259#define DWT_FUNCTION_DATAVSIZE_Pos 10U
1260#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
1262#define DWT_FUNCTION_LNK1ENA_Pos 9U
1263#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
1265#define DWT_FUNCTION_DATAVMATCH_Pos 8U
1266#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
1268#define DWT_FUNCTION_CYCMATCH_Pos 7U
1269#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
1271#define DWT_FUNCTION_EMITRANGE_Pos 5U
1272#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
1274#define DWT_FUNCTION_FUNCTION_Pos 0U
1275#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /* end of group CMSIS_DWT */
1278
1279
1290typedef struct
1291{
1292 __IM uint32_t SSPSR;
1293 __IOM uint32_t CSPSR;
1294 uint32_t RESERVED0[2U];
1295 __IOM uint32_t ACPR;
1296 uint32_t RESERVED1[55U];
1297 __IOM uint32_t SPPR;
1298 uint32_t RESERVED2[131U];
1299 __IM uint32_t FFSR;
1300 __IOM uint32_t FFCR;
1301 __IM uint32_t FSCR;
1302 uint32_t RESERVED3[759U];
1303 __IM uint32_t TRIGGER;
1304 __IM uint32_t FIFO0;
1305 __IM uint32_t ITATBCTR2;
1306 uint32_t RESERVED4[1U];
1307 __IM uint32_t ITATBCTR0;
1308 __IM uint32_t FIFO1;
1309 __IOM uint32_t ITCTRL;
1310 uint32_t RESERVED5[39U];
1311 __IOM uint32_t CLAIMSET;
1312 __IOM uint32_t CLAIMCLR;
1313 uint32_t RESERVED7[8U];
1314 __IM uint32_t DEVID;
1315 __IM uint32_t DEVTYPE;
1316} TPI_Type;
1317
1318/* TPI Asynchronous Clock Prescaler Register Definitions */
1319#define TPI_ACPR_PRESCALER_Pos 0U
1320#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
1322/* TPI Selected Pin Protocol Register Definitions */
1323#define TPI_SPPR_TXMODE_Pos 0U
1324#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
1326/* TPI Formatter and Flush Status Register Definitions */
1327#define TPI_FFSR_FtNonStop_Pos 3U
1328#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1330#define TPI_FFSR_TCPresent_Pos 2U
1331#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1333#define TPI_FFSR_FtStopped_Pos 1U
1334#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1336#define TPI_FFSR_FlInProg_Pos 0U
1337#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
1339/* TPI Formatter and Flush Control Register Definitions */
1340#define TPI_FFCR_TrigIn_Pos 8U
1341#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1343#define TPI_FFCR_EnFCont_Pos 1U
1344#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1346/* TPI TRIGGER Register Definitions */
1347#define TPI_TRIGGER_TRIGGER_Pos 0U
1348#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
1350/* TPI Integration ETM Data Register Definitions (FIFO0) */
1351#define TPI_FIFO0_ITM_ATVALID_Pos 29U
1352#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)
1354#define TPI_FIFO0_ITM_bytecount_Pos 27U
1355#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
1357#define TPI_FIFO0_ETM_ATVALID_Pos 26U
1358#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)
1360#define TPI_FIFO0_ETM_bytecount_Pos 24U
1361#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
1363#define TPI_FIFO0_ETM2_Pos 16U
1364#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
1366#define TPI_FIFO0_ETM1_Pos 8U
1367#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
1369#define TPI_FIFO0_ETM0_Pos 0U
1370#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
1372/* TPI ITATBCTR2 Register Definitions */
1373#define TPI_ITATBCTR2_ATREADY2_Pos 0U
1374#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)
1376#define TPI_ITATBCTR2_ATREADY1_Pos 0U
1377#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)
1379/* TPI Integration ITM Data Register Definitions (FIFO1) */
1380#define TPI_FIFO1_ITM_ATVALID_Pos 29U
1381#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)
1383#define TPI_FIFO1_ITM_bytecount_Pos 27U
1384#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
1386#define TPI_FIFO1_ETM_ATVALID_Pos 26U
1387#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)
1389#define TPI_FIFO1_ETM_bytecount_Pos 24U
1390#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
1392#define TPI_FIFO1_ITM2_Pos 16U
1393#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
1395#define TPI_FIFO1_ITM1_Pos 8U
1396#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
1398#define TPI_FIFO1_ITM0_Pos 0U
1399#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
1401/* TPI ITATBCTR0 Register Definitions */
1402#define TPI_ITATBCTR0_ATREADY2_Pos 0U
1403#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)
1405#define TPI_ITATBCTR0_ATREADY1_Pos 0U
1406#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)
1408/* TPI Integration Mode Control Register Definitions */
1409#define TPI_ITCTRL_Mode_Pos 0U
1410#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
1412/* TPI DEVID Register Definitions */
1413#define TPI_DEVID_NRZVALID_Pos 11U
1414#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1416#define TPI_DEVID_MANCVALID_Pos 10U
1417#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1419#define TPI_DEVID_PTINVALID_Pos 9U
1420#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1422#define TPI_DEVID_MinBufSz_Pos 6U
1423#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
1425#define TPI_DEVID_AsynClkIn_Pos 5U
1426#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
1428#define TPI_DEVID_NrTraceInput_Pos 0U
1429#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
1431/* TPI DEVTYPE Register Definitions */
1432#define TPI_DEVTYPE_SubType_Pos 4U
1433#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
1435#define TPI_DEVTYPE_MajorType_Pos 0U
1436#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /* end of group CMSIS_TPI */
1439
1440
1441#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1452typedef struct
1453{
1454 __IM uint32_t TYPE;
1455 __IOM uint32_t CTRL;
1456 __IOM uint32_t RNR;
1457 __IOM uint32_t RBAR;
1458 __IOM uint32_t RASR;
1459 __IOM uint32_t RBAR_A1;
1460 __IOM uint32_t RASR_A1;
1461 __IOM uint32_t RBAR_A2;
1462 __IOM uint32_t RASR_A2;
1463 __IOM uint32_t RBAR_A3;
1464 __IOM uint32_t RASR_A3;
1465} MPU_Type;
1466
1467#define MPU_TYPE_RALIASES 4U
1468
1469/* MPU Type Register Definitions */
1470#define MPU_TYPE_IREGION_Pos 16U
1471#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1473#define MPU_TYPE_DREGION_Pos 8U
1474#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1476#define MPU_TYPE_SEPARATE_Pos 0U
1477#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
1479/* MPU Control Register Definitions */
1480#define MPU_CTRL_PRIVDEFENA_Pos 2U
1481#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1483#define MPU_CTRL_HFNMIENA_Pos 1U
1484#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1486#define MPU_CTRL_ENABLE_Pos 0U
1487#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
1489/* MPU Region Number Register Definitions */
1490#define MPU_RNR_REGION_Pos 0U
1491#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
1493/* MPU Region Base Address Register Definitions */
1494#define MPU_RBAR_ADDR_Pos 5U
1495#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
1497#define MPU_RBAR_VALID_Pos 4U
1498#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
1500#define MPU_RBAR_REGION_Pos 0U
1501#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
1503/* MPU Region Attribute and Size Register Definitions */
1504#define MPU_RASR_ATTRS_Pos 16U
1505#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
1507#define MPU_RASR_XN_Pos 28U
1508#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
1510#define MPU_RASR_AP_Pos 24U
1511#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
1513#define MPU_RASR_TEX_Pos 19U
1514#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
1516#define MPU_RASR_S_Pos 18U
1517#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
1519#define MPU_RASR_C_Pos 17U
1520#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
1522#define MPU_RASR_B_Pos 16U
1523#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
1525#define MPU_RASR_SRD_Pos 8U
1526#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
1528#define MPU_RASR_SIZE_Pos 1U
1529#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
1531#define MPU_RASR_ENABLE_Pos 0U
1532#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/)
1535#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
1536
1537
1548typedef struct
1549{
1550 uint32_t RESERVED0[1U];
1551 __IOM uint32_t FPCCR;
1552 __IOM uint32_t FPCAR;
1553 __IOM uint32_t FPDSCR;
1554 __IM uint32_t MVFR0;
1555 __IM uint32_t MVFR1;
1556 __IM uint32_t MVFR2;
1557} FPU_Type;
1558
1559/* Floating-Point Context Control Register Definitions */
1560#define FPU_FPCCR_ASPEN_Pos 31U
1561#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
1563#define FPU_FPCCR_LSPEN_Pos 30U
1564#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
1566#define FPU_FPCCR_MONRDY_Pos 8U
1567#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
1569#define FPU_FPCCR_BFRDY_Pos 6U
1570#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
1572#define FPU_FPCCR_MMRDY_Pos 5U
1573#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
1575#define FPU_FPCCR_HFRDY_Pos 4U
1576#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
1578#define FPU_FPCCR_THREAD_Pos 3U
1579#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
1581#define FPU_FPCCR_USER_Pos 1U
1582#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
1584#define FPU_FPCCR_LSPACT_Pos 0U
1585#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
1587/* Floating-Point Context Address Register Definitions */
1588#define FPU_FPCAR_ADDRESS_Pos 3U
1589#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
1591/* Floating-Point Default Status Control Register Definitions */
1592#define FPU_FPDSCR_AHP_Pos 26U
1593#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
1595#define FPU_FPDSCR_DN_Pos 25U
1596#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
1598#define FPU_FPDSCR_FZ_Pos 24U
1599#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
1601#define FPU_FPDSCR_RMode_Pos 22U
1602#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
1604/* Media and FP Feature Register 0 Definitions */
1605#define FPU_MVFR0_FP_rounding_modes_Pos 28U
1606#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
1608#define FPU_MVFR0_Short_vectors_Pos 24U
1609#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
1611#define FPU_MVFR0_Square_root_Pos 20U
1612#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
1614#define FPU_MVFR0_Divide_Pos 16U
1615#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
1617#define FPU_MVFR0_FP_excep_trapping_Pos 12U
1618#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
1620#define FPU_MVFR0_Double_precision_Pos 8U
1621#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
1623#define FPU_MVFR0_Single_precision_Pos 4U
1624#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
1626#define FPU_MVFR0_A_SIMD_registers_Pos 0U
1627#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
1629/* Media and FP Feature Register 1 Definitions */
1630#define FPU_MVFR1_FP_fused_MAC_Pos 28U
1631#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
1633#define FPU_MVFR1_FP_HPFP_Pos 24U
1634#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
1636#define FPU_MVFR1_D_NaN_mode_Pos 4U
1637#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
1639#define FPU_MVFR1_FtZ_mode_Pos 0U
1640#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
1642/* Media and FP Feature Register 2 Definitions */
1643
1644#define FPU_MVFR2_VFP_Misc_Pos 4U
1645#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos)
1660typedef struct
1661{
1662 __IOM uint32_t DHCSR;
1663 __OM uint32_t DCRSR;
1664 __IOM uint32_t DCRDR;
1665 __IOM uint32_t DEMCR;
1667
1668/* Debug Halting Control and Status Register Definitions */
1669#define CoreDebug_DHCSR_DBGKEY_Pos 16U
1670#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1672#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1673#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1675#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1676#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1678#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1679#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1681#define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1682#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1684#define CoreDebug_DHCSR_S_HALT_Pos 17U
1685#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1687#define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1688#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1690#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
1691#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1693#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1694#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1696#define CoreDebug_DHCSR_C_STEP_Pos 2U
1697#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1699#define CoreDebug_DHCSR_C_HALT_Pos 1U
1700#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1702#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1703#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
1705/* Debug Core Register Selector Register Definitions */
1706#define CoreDebug_DCRSR_REGWnR_Pos 16U
1707#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1709#define CoreDebug_DCRSR_REGSEL_Pos 0U
1710#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
1712/* Debug Exception and Monitor Control Register Definitions */
1713#define CoreDebug_DEMCR_TRCENA_Pos 24U
1714#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1716#define CoreDebug_DEMCR_MON_REQ_Pos 19U
1717#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1719#define CoreDebug_DEMCR_MON_STEP_Pos 18U
1720#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1722#define CoreDebug_DEMCR_MON_PEND_Pos 17U
1723#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1725#define CoreDebug_DEMCR_MON_EN_Pos 16U
1726#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1728#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1729#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1731#define CoreDebug_DEMCR_VC_INTERR_Pos 9U
1732#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1734#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
1735#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1737#define CoreDebug_DEMCR_VC_STATERR_Pos 7U
1738#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1740#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
1741#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1743#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
1744#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1746#define CoreDebug_DEMCR_VC_MMERR_Pos 4U
1747#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1749#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1750#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
1768#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1769
1776#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1777
1788/* Memory mapping of Core Hardware */
1789#define SCS_BASE (0xE000E000UL)
1790#define ITM_BASE (0xE0000000UL)
1791#define DWT_BASE (0xE0001000UL)
1792#define TPI_BASE (0xE0040000UL)
1793#define CoreDebug_BASE (0xE000EDF0UL)
1794#define SysTick_BASE (SCS_BASE + 0x0010UL)
1795#define NVIC_BASE (SCS_BASE + 0x0100UL)
1796#define SCB_BASE (SCS_BASE + 0x0D00UL)
1798#define SCnSCB ((SCnSCB_Type *) SCS_BASE )
1799#define SCB ((SCB_Type *) SCB_BASE )
1800#define SysTick ((SysTick_Type *) SysTick_BASE )
1801#define NVIC ((NVIC_Type *) NVIC_BASE )
1802#define ITM ((ITM_Type *) ITM_BASE )
1803#define DWT ((DWT_Type *) DWT_BASE )
1804#define TPI ((TPI_Type *) TPI_BASE )
1805#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
1807#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1808 #define MPU_BASE (SCS_BASE + 0x0D90UL)
1809 #define MPU ((MPU_Type *) MPU_BASE )
1810#endif
1811
1812#define FPU_BASE (SCS_BASE + 0x0F30UL)
1813#define FPU ((FPU_Type *) FPU_BASE )
1825/* Capitalize ITM_TCR Register Definitions */
1826
1827/* ITM Trace Control Register Definitions */
1828#define ITM_TCR_TraceBusID_Pos (ITM_TCR_TRACEBUSID_Pos)
1829#define ITM_TCR_TraceBusID_Msk (ITM_TCR_TRACEBUSID_Msk)
1831#define ITM_TCR_TSPrescale_Pos (ITM_TCR_TSPRESCALE_Pos)
1832#define ITM_TCR_TSPrescale_Msk (ITM_TCR_TSPRESCALE_Msk)
1834/* ITM Lock Status Register Definitions */
1835#define ITM_LSR_ByteAcc_Pos (ITM_LSR_BYTEACC_Pos)
1836#define ITM_LSR_ByteAcc_Msk (ITM_LSR_BYTEACC_Msk)
1838#define ITM_LSR_Access_Pos (ITM_LSR_ACCESS_Pos)
1839#define ITM_LSR_Access_Msk (ITM_LSR_ACCESS_Msk)
1841#define ITM_LSR_Present_Pos (ITM_LSR_PRESENT_Pos)
1842#define ITM_LSR_Present_Msk (ITM_LSR_PRESENT_Msk)
1848/*******************************************************************************
1849 * Hardware Abstraction Layer
1850 Core Function Interface contains:
1851 - Core NVIC Functions
1852 - Core SysTick Functions
1853 - Core Debug Functions
1854 - Core Register Access Functions
1855 ******************************************************************************/
1862/* ########################## NVIC functions #################################### */
1870#ifdef CMSIS_NVIC_VIRTUAL
1871 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1872 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1873 #endif
1874 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1875#else
1876 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1877 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1878 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1879 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1880 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1881 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1882 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1883 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1884 #define NVIC_GetActive __NVIC_GetActive
1885 #define NVIC_SetPriority __NVIC_SetPriority
1886 #define NVIC_GetPriority __NVIC_GetPriority
1887 #define NVIC_SystemReset __NVIC_SystemReset
1888#endif /* CMSIS_NVIC_VIRTUAL */
1889
1890#ifdef CMSIS_VECTAB_VIRTUAL
1891 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1892 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1893 #endif
1894 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1895#else
1896 #define NVIC_SetVector __NVIC_SetVector
1897 #define NVIC_GetVector __NVIC_GetVector
1898#endif /* (CMSIS_VECTAB_VIRTUAL) */
1899
1900#define NVIC_USER_IRQ_OFFSET 16
1901
1902
1903/* The following EXC_RETURN values are saved the LR on exception entry */
1904#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
1905#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
1906#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
1907#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
1908#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
1909#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
1910
1911
1921__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1922{
1923 uint32_t reg_value;
1924 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1925
1926 reg_value = SCB->AIRCR; /* read old register configuration */
1927 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1928 reg_value = (reg_value |
1929 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1930 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
1931 SCB->AIRCR = reg_value;
1932}
1933
1934
1940__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
1941{
1942 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1943}
1944
1945
1952__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1953{
1954 if ((int32_t)(IRQn) >= 0)
1955 {
1956 __COMPILER_BARRIER();
1957 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1958 __COMPILER_BARRIER();
1959 }
1960}
1961
1962
1971__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1972{
1973 if ((int32_t)(IRQn) >= 0)
1974 {
1975 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1976 }
1977 else
1978 {
1979 return(0U);
1980 }
1981}
1982
1983
1990__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1991{
1992 if ((int32_t)(IRQn) >= 0)
1993 {
1994 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1995 __DSB();
1996 __ISB();
1997 }
1998}
1999
2000
2009__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2010{
2011 if ((int32_t)(IRQn) >= 0)
2012 {
2013 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2014 }
2015 else
2016 {
2017 return(0U);
2018 }
2019}
2020
2021
2028__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2029{
2030 if ((int32_t)(IRQn) >= 0)
2031 {
2032 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2033 }
2034}
2035
2036
2043__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2044{
2045 if ((int32_t)(IRQn) >= 0)
2046 {
2047 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2048 }
2049}
2050
2051
2060__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2061{
2062 if ((int32_t)(IRQn) >= 0)
2063 {
2064 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2065 }
2066 else
2067 {
2068 return(0U);
2069 }
2070}
2071
2072
2082__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2083{
2084 if ((int32_t)(IRQn) >= 0)
2085 {
2086 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2087 }
2088 else
2089 {
2090 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2091 }
2092}
2093
2094
2104__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2105{
2106
2107 if ((int32_t)(IRQn) >= 0)
2108 {
2109 return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2110 }
2111 else
2112 {
2113 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2114 }
2115}
2116
2117
2129__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2130{
2131 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2132 uint32_t PreemptPriorityBits;
2133 uint32_t SubPriorityBits;
2134
2135 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2136 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2137
2138 return (
2139 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2140 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2141 );
2142}
2143
2144
2156__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2157{
2158 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2159 uint32_t PreemptPriorityBits;
2160 uint32_t SubPriorityBits;
2161
2162 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2163 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2164
2165 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2166 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2167}
2168
2169
2179__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2180{
2181 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2182 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2183 __DSB();
2184}
2185
2186
2195__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2196{
2197 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2198 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2199}
2200
2201
2206__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2207{
2208 __DSB(); /* Ensure all outstanding memory accesses included
2209 buffered write are completed before reset */
2210 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2211 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2212 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2213 __DSB(); /* Ensure completion of memory access */
2214
2215 for(;;) /* wait until reset */
2216 {
2217 __NOP();
2218 }
2219}
2220
2224/* ########################## MPU functions #################################### */
2225
2226#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2227
2228#include "mpu_armv7.h"
2229
2230#endif
2231
2232
2233/* ########################## FPU functions #################################### */
2249__STATIC_INLINE uint32_t SCB_GetFPUType(void)
2250{
2251 uint32_t mvfr0;
2252
2253 mvfr0 = SCB->MVFR0;
2255 {
2256 return 2U; /* Double + Single precision FPU */
2257 }
2258 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2259 {
2260 return 1U; /* Single precision FPU */
2261 }
2262 else
2263 {
2264 return 0U; /* No FPU */
2265 }
2266}
2267
2271/* ########################## Cache functions #################################### */
2272
2273#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
2274 (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
2275#include "cachel1_armv7.h"
2276#endif
2277
2278
2279/* ################################## SysTick function ############################################ */
2287#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2288
2300__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2301{
2302 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2303 {
2304 return (1UL); /* Reload value impossible */
2305 }
2306
2307 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2308 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2309 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2312 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2313 return (0UL); /* Function successful */
2314}
2315
2316#endif
2317
2322/* ##################################### Debug In/Output function ########################################### */
2330extern volatile int32_t ITM_RxBuffer;
2331#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
2342__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2343{
2344 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2345 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2346 {
2347 while (ITM->PORT[0U].u32 == 0UL)
2348 {
2349 __NOP();
2350 }
2351 ITM->PORT[0U].u8 = (uint8_t)ch;
2352 }
2353 return (ch);
2354}
2355
2356
2363__STATIC_INLINE int32_t ITM_ReceiveChar (void)
2364{
2365 int32_t ch = -1; /* no character available */
2366
2368 {
2369 ch = ITM_RxBuffer;
2370 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2371 }
2372
2373 return (ch);
2374}
2375
2376
2383__STATIC_INLINE int32_t ITM_CheckChar (void)
2384{
2385
2387 {
2388 return (0); /* no character available */
2389 }
2390 else
2391 {
2392 return (1); /* character available */
2393 }
2394}
2395
2401#ifdef __cplusplus
2402}
2403#endif
2404
2405#endif /* __CORE_CM7_H_DEPENDANT */
2406
2407#endif /* __CMSIS_GENERIC */
This header file provides CMSIS interfaces.
CMSIS compiler generic header file.
CMSIS Core(M) Version definitions.
#define __NOP()
No Operation.
Definition: cmsis_gcc.h:245
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:286
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:275
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: core_cm4.h:1979
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: core_cm4.h:1952
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_cm4.h:1929
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: core_cm4.h:1968
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm4.h:1855
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm4.h:1816
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm4.h:1782
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_cm4.h:2022
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: core_cm4.h:1725
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: core_cm4.h:1713
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_cm4.h:1833
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm4.h:1801
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: core_cm4.h:1744
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_cm4.h:1902
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: core_cm4.h:1763
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm4.h:1877
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: core_cm4.h:1694
#define FPU_MVFR0_Double_precision_Msk
Definition: core_cm7.h:1621
#define FPU_MVFR0_Single_precision_Msk
Definition: core_cm7.h:1624
#define ITM_TCR_ITMENA_Msk
Definition: core_cm7.h:1115
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_cm7.h:589
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_cm7.h:580
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm7.h:579
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm7.h:592
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_cm7.h:588
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm7.h:1019
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm7.h:1023
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm7.h:1016
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm7.h:1013
__OM uint32_t DCCMVAC
Definition: core_cm7.h:512
__IOM uint32_t AHBPCR
Definition: core_cm7.h:520
uint32_t _reserved1
Definition: core_cm7.h:356
uint32_t T
Definition: core_cm7.h:357
volatile int32_t ITM_RxBuffer
uint32_t nPRIV
Definition: core_cm7.h:407
uint32_t ICI_IT_1
Definition: core_cm7.h:354
uint32_t _reserved0
Definition: core_cm7.h:353
uint32_t FPCA
Definition: core_cm7.h:409
__OM uint32_t DCISW
Definition: core_cm7.h:510
__IM uint32_t MVFR2
Definition: core_cm7.h:504
__IOM uint32_t DTCMCR
Definition: core_cm7.h:519
__OM uint8_t u8
Definition: core_cm7.h:1056
__IOM uint32_t ABFSR
Definition: core_cm7.h:524
__IM uint32_t LSR
Definition: core_cm7.h:1167
__OM uint16_t u16
Definition: core_cm7.h:1057
uint32_t C
Definition: core_cm7.h:361
uint32_t C
Definition: core_cm7.h:300
__OM uint32_t LAR
Definition: core_cm7.h:1166
__OM uint32_t DCIMVAC
Definition: core_cm7.h:509
__OM uint32_t DCCIMVAC
Definition: core_cm7.h:514
__IOM uint32_t CACR
Definition: core_cm7.h:521
uint32_t V
Definition: core_cm7.h:299
__OM uint32_t ICIALLU
Definition: core_cm7.h:506
__OM uint32_t ICIMVAU
Definition: core_cm7.h:508
uint32_t GE
Definition: core_cm7.h:355
__IM uint32_t MVFR1
Definition: core_cm7.h:503
__IM uint32_t MVFR0
Definition: core_cm7.h:502
uint32_t SPSEL
Definition: core_cm7.h:408
uint32_t Q
Definition: core_cm7.h:359
__IOM uint32_t AHBSCR
Definition: core_cm7.h:522
uint32_t N
Definition: core_cm7.h:302
uint32_t _reserved0
Definition: core_cm7.h:410
__IM uint32_t ID_AFR
Definition: core_cm7.h:490
#define ITM_RXBUFFER_EMPTY
Definition: core_cm7.h:2331
uint32_t Z
Definition: core_cm7.h:362
__OM uint32_t DCCMVAU
Definition: core_cm7.h:511
__OM uint32_t BPIALL
Definition: core_cm7.h:516
uint32_t V
Definition: core_cm7.h:360
uint32_t _reserved0
Definition: core_cm7.h:295
__OM uint32_t DCCSW
Definition: core_cm7.h:513
__IOM uint32_t ITCMCR
Definition: core_cm7.h:518
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: core_cm4.h:2126
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
ITM Send Character.
Definition: core_cm4.h:2105
__OM uint32_t u32
Definition: core_cm7.h:1058
uint32_t _reserved0
Definition: core_cm7.h:335
__IOM uint32_t CSSELR
Definition: core_cm7.h:497
uint32_t Z
Definition: core_cm7.h:301
__OM uint32_t STIR
Definition: core_cm7.h:500
__IM uint32_t CLIDR
Definition: core_cm7.h:494
__IM uint32_t ID_DFR
Definition: core_cm7.h:489
uint32_t GE
Definition: core_cm7.h:296
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: core_cm4.h:2146
uint32_t N
Definition: core_cm7.h:363
uint32_t ISR
Definition: core_cm7.h:352
uint32_t _reserved1
Definition: core_cm7.h:297
__IM uint32_t CTR
Definition: core_cm7.h:495
uint32_t ICI_IT_2
Definition: core_cm7.h:358
__OM uint32_t DCCISW
Definition: core_cm7.h:515
uint32_t ISR
Definition: core_cm7.h:334
uint32_t Q
Definition: core_cm7.h:298
__IM uint32_t CCSIDR
Definition: core_cm7.h:496
#define SCB
Definition: core_cm7.h:1799
#define ITM
Definition: core_cm7.h:1802
#define NVIC
Definition: core_cm7.h:1801
#define SysTick
Definition: core_cm7.h:1800
@ SysTick_IRQn
Definition: same70j19.h:68
IRQn_Type
STM32H7XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32h723xx.h:49
#define SCR
Scratch register.
Definition: uart.h:94
This header file provides CMSIS interfaces.
Structure type to access the Core Debug Register (CoreDebug).
Definition: core_cm4.h:1434
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_cm4.h:917
Structure type to access the Floating Point Unit (FPU).
Definition: core_cm4.h:1322
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_cm4.h:829
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm4.h:424
Structure type to access the System Control Block (SCB).
Definition: core_cm4.h:458
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_cm4.h:737
Structure type to access the System Timer (SysTick).
Definition: core_cm4.h:777
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_cm4.h:1064
unsigned w
Definition: tlb.h:16
Union type to access the Application Program Status Register (APSR).
Definition: core_cm4.h:277
Union type to access the Control Registers (CONTROL).
Definition: core_cm4.h:389
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm4.h:316
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm4.h:334