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RTEMS 6.1-rc7
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DTS. More...
#include <stm32h723xx.h>
Data Fields | |
__IO uint32_t | CFGR1 |
uint32_t | RESERVED0 |
__IO uint32_t | T0VALR1 |
uint32_t | RESERVED1 |
__IO uint32_t | RAMPVALR |
__IO uint32_t | ITR1 |
uint32_t | RESERVED2 |
__IO uint32_t | DR |
__IO uint32_t | SR |
__IO uint32_t | ITENR |
__IO uint32_t | ICIFR |
__IO uint32_t | OR |
DTS.
__IO uint32_t DTS_TypeDef::CFGR1 |
DTS configuration register, Address offset: 0x00
__IO uint32_t DTS_TypeDef::DR |
DTS data register, Address offset: 0x1C
__IO uint32_t DTS_TypeDef::ICIFR |
DTS Clear Interrupt flag register, Address offset: 0x28
__IO uint32_t DTS_TypeDef::ITENR |
DTS Interrupt enable register, Address offset: 0x24
__IO uint32_t DTS_TypeDef::ITR1 |
DTS Interrupt threshold register, Address offset: 0x14
__IO uint32_t DTS_TypeDef::OR |
DTS option register 1, Address offset: 0x2C
__IO uint32_t DTS_TypeDef::RAMPVALR |
DTS Ramp value register, Address offset: 0x10
uint32_t DTS_TypeDef::RESERVED0 |
Reserved, Address offset: 0x04
uint32_t DTS_TypeDef::RESERVED1 |
Reserved, Address offset: 0x0C
uint32_t DTS_TypeDef::RESERVED2 |
Reserved, Address offset: 0x18
__IO uint32_t DTS_TypeDef::SR |
DTS status register Address offset: 0x20
__IO uint32_t DTS_TypeDef::T0VALR1 |
DTS T0 Value register, Address offset: 0x08