20#ifndef STM32H7xx_HAL_TIM_EX_H
21#define STM32H7xx_HAL_TIM_EX_H
62#if defined(TIM_BREAK_INPUT_SUPPORT)
76} TIMEx_BreakInputConfigTypeDef;
94#define TIM_TIM1_ETR_GPIO 0x00000000U
95#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0
96#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1
97#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
98#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2)
99#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)
100#define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)
101#define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
102#define TIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3
104#define TIM_TIM8_ETR_GPIO 0x00000000U
105#define TIM_TIM8_ETR_COMP1 TIM8_AF1_ETRSEL_0
106#define TIM_TIM8_ETR_COMP2 TIM8_AF1_ETRSEL_1
107#define TIM_TIM8_ETR_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)
108#define TIM_TIM8_ETR_ADC2_AWD2 (TIM8_AF1_ETRSEL_2)
109#define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)
110#define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1)
111#define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)
112#define TIM_TIM8_ETR_ADC3_AWD3 TIM8_AF1_ETRSEL_3
114#define TIM_TIM2_ETR_GPIO 0x00000000U
115#define TIM_TIM2_ETR_COMP1 (TIM2_AF1_ETRSEL_0)
116#define TIM_TIM2_ETR_COMP2 (TIM2_AF1_ETRSEL_1)
117#define TIM_TIM2_ETR_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)
118#define TIM_TIM2_ETR_SAI1_FSA TIM2_AF1_ETRSEL_2
119#define TIM_TIM2_ETR_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)
121#define TIM_TIM3_ETR_GPIO 0x00000000U
122#define TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0
124#define TIM_TIM5_ETR_GPIO 0x00000000U
125#define TIM_TIM5_ETR_SAI2_FSA TIM5_AF1_ETRSEL_0
126#define TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1
127#define TIM_TIM5_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0
128#define TIM_TIM5_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1
130#define TIM_TIM23_ETR_GPIO 0x00000000U
131#define TIM_TIM23_ETR_COMP1 (TIM2_AF1_ETRSEL_0)
132#define TIM_TIM23_ETR_COMP2 (TIM2_AF1_ETRSEL_1)
134#define TIM_TIM24_ETR_GPIO 0x00000000U
135#define TIM_TIM24_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0
136#define TIM_TIM24_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1
137#define TIM_TIM24_ETR_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)
138#define TIM_TIM24_ETR_SAI1_FSB TIM2_AF1_ETRSEL_2
142#if defined(TIM_BREAK_INPUT_SUPPORT)
148#define TIM_BREAKINPUT_BRK 0x00000001U
149#define TIM_BREAKINPUT_BRK2 0x00000002U
158#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U
159#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U
160#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U
161#define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U
170#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U
171#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U
180#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U
181#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U
191#define TIM_TIM1_TI1_GPIO 0x00000000U
192#define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0
194#define TIM_TIM8_TI1_GPIO 0x00000000U
195#define TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_0
197#define TIM_TIM2_TI4_GPIO 0x00000000U
198#define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0
199#define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1
200#define TIM_TIM2_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1)
202#define TIM_TIM3_TI1_GPIO 0x00000000U
203#define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0
204#define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1
205#define TIM_TIM3_TI1_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1)
207#define TIM_TIM5_TI1_GPIO 0x00000000U
208#define TIM_TIM5_TI1_CAN_TMP TIM_TISEL_TI1SEL_0
209#define TIM_TIM5_TI1_CAN_RTP TIM_TISEL_TI1SEL_1
211#define TIM_TIM12_TI1_GPIO 0x00000000U
212#define TIM_TIM12_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0
214#define TIM_TIM15_TI1_GPIO 0x00000000U
215#define TIM_TIM15_TI1_TIM2_CH1 TIM_TISEL_TI1SEL_0
216#define TIM_TIM15_TI1_TIM3_CH1 TIM_TISEL_TI1SEL_1
217#define TIM_TIM15_TI1_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1)
218#define TIM_TIM15_TI1_RCC_LSE (TIM_TISEL_TI1SEL_2)
219#define TIM_TIM15_TI1_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)
220#define TIM_TIM15_TI1_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)
222#define TIM_TIM15_TI2_GPIO 0x00000000U
223#define TIM_TIM15_TI2_TIM2_CH2 (TIM_TISEL_TI2SEL_0)
224#define TIM_TIM15_TI2_TIM3_CH2 (TIM_TISEL_TI2SEL_1)
225#define TIM_TIM15_TI2_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1)
227#define TIM_TIM16_TI1_GPIO 0x00000000U
228#define TIM_TIM16_TI1_RCC_LSI TIM_TISEL_TI1SEL_0
229#define TIM_TIM16_TI1_RCC_LSE TIM_TISEL_TI1SEL_1
230#define TIM_TIM16_TI1_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1)
232#define TIM_TIM17_TI1_GPIO 0x00000000U
233#define TIM_TIM17_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0
234#define TIM_TIM17_TI1_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1
235#define TIM_TIM17_TI1_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1)
237#define TIM_TIM23_TI4_GPIO 0x00000000U
238#define TIM_TIM23_TI4_COMP1 TIM_TISEL_TI4SEL_0
239#define TIM_TIM23_TI4_COMP2 TIM_TISEL_TI4SEL_1
240#define TIM_TIM23_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1)
242#define TIM_TIM24_TI1_GPIO 0x00000000U
243#define TIM_TIM24_TI1_CAN_TMP TIM_TISEL_TI1SEL_0
244#define TIM_TIM24_TI1_CAN_RTP TIM_TISEL_TI1SEL_1
245#define TIM_TIM24_TI1_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1)
271#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
272 ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
274#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
275 ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
276 ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
277 ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))
279#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
280 ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
282#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
283 ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
285#define IS_TIM_TISEL(__TISEL__) (((__TISEL__) == TIM_TIM1_TI1_GPIO) ||\
286 ((__TISEL__) == TIM_TIM1_TI1_COMP1) ||\
287 ((__TISEL__) == TIM_TIM8_TI1_GPIO) ||\
288 ((__TISEL__) == TIM_TIM8_TI1_COMP2) ||\
289 ((__TISEL__) == TIM_TIM2_TI4_GPIO) ||\
290 ((__TISEL__) == TIM_TIM2_TI4_COMP1) ||\
291 ((__TISEL__) == TIM_TIM2_TI4_COMP2) ||\
292 ((__TISEL__) == TIM_TIM2_TI4_COMP1_COMP2) ||\
293 ((__TISEL__) == TIM_TIM3_TI1_GPIO) ||\
294 ((__TISEL__) == TIM_TIM3_TI1_COMP1) ||\
295 ((__TISEL__) == TIM_TIM3_TI1_COMP2) ||\
296 ((__TISEL__) == TIM_TIM3_TI1_COMP1_COMP2) ||\
297 ((__TISEL__) == TIM_TIM5_TI1_GPIO) ||\
298 ((__TISEL__) == TIM_TIM5_TI1_CAN_TMP) ||\
299 ((__TISEL__) == TIM_TIM5_TI1_CAN_RTP) ||\
300 ((__TISEL__) == TIM_TIM12_TI1_SPDIF_FS) ||\
301 ((__TISEL__) == TIM_TIM12_TI1_GPIO) ||\
302 ((__TISEL__) == TIM_TIM15_TI1_GPIO) ||\
303 ((__TISEL__) == TIM_TIM15_TI1_TIM2_CH1) ||\
304 ((__TISEL__) == TIM_TIM15_TI1_TIM3_CH1) ||\
305 ((__TISEL__) == TIM_TIM15_TI1_TIM4_CH1) ||\
306 ((__TISEL__) == TIM_TIM15_TI1_RCC_LSE) ||\
307 ((__TISEL__) == TIM_TIM15_TI1_RCC_CSI) ||\
308 ((__TISEL__) == TIM_TIM15_TI1_RCC_MCO2) ||\
309 ((__TISEL__) == TIM_TIM15_TI2_GPIO) ||\
310 ((__TISEL__) == TIM_TIM15_TI2_TIM2_CH2) ||\
311 ((__TISEL__) == TIM_TIM15_TI2_TIM3_CH2) ||\
312 ((__TISEL__) == TIM_TIM15_TI2_TIM4_CH2) ||\
313 ((__TISEL__) == TIM_TIM16_TI1_GPIO) ||\
314 ((__TISEL__) == TIM_TIM16_TI1_RCC_LSI) ||\
315 ((__TISEL__) == TIM_TIM16_TI1_RCC_LSE) ||\
316 ((__TISEL__) == TIM_TIM16_TI1_WKUP_IT) ||\
317 ((__TISEL__) == TIM_TIM17_TI1_GPIO) ||\
318 ((__TISEL__) == TIM_TIM17_TI1_SPDIF_FS) ||\
319 ((__TISEL__) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\
320 ((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1) ||\
321 ((__TISEL__) == TIM_TIM23_TI4_GPIO) ||\
322 ((__TISEL__) == TIM_TIM23_TI4_COMP1) ||\
323 ((__TISEL__) == TIM_TIM23_TI4_COMP2) ||\
324 ((__TISEL__) == TIM_TIM23_TI4_COMP1_COMP2) ||\
325 ((__TISEL__) == TIM_TIM24_TI1_GPIO) ||\
326 ((__TISEL__) == TIM_TIM24_TI1_CAN_TMP) ||\
327 ((__TISEL__) == TIM_TIM24_TI1_CAN_RTP) ||\
328 ((__TISEL__) == TIM_TIM24_TI1_CAN_SOC))
330#define IS_TIM_REMAP(__RREMAP__) (((__RREMAP__) == TIM_TIM1_ETR_GPIO) ||\
331 ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD1) ||\
332 ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD2) ||\
333 ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD3) ||\
334 ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD1) ||\
335 ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD2) ||\
336 ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD3) ||\
337 ((__RREMAP__) == TIM_TIM1_ETR_COMP1) ||\
338 ((__RREMAP__) == TIM_TIM1_ETR_COMP2) ||\
339 ((__RREMAP__) == TIM_TIM8_ETR_GPIO) ||\
340 ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD1) ||\
341 ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD2) ||\
342 ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD3) ||\
343 ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD1) ||\
344 ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD2) ||\
345 ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD3) ||\
346 ((__RREMAP__) == TIM_TIM8_ETR_COMP1) ||\
347 ((__RREMAP__) == TIM_TIM8_ETR_COMP2) ||\
348 ((__RREMAP__) == TIM_TIM2_ETR_GPIO) ||\
349 ((__RREMAP__) == TIM_TIM2_ETR_COMP1) ||\
350 ((__RREMAP__) == TIM_TIM2_ETR_COMP2) ||\
351 ((__RREMAP__) == TIM_TIM2_ETR_RCC_LSE) ||\
352 ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSA) ||\
353 ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSB) ||\
354 ((__RREMAP__) == TIM_TIM3_ETR_GPIO) ||\
355 ((__RREMAP__) == TIM_TIM3_ETR_COMP1) ||\
356 ((__RREMAP__) == TIM_TIM5_ETR_GPIO) ||\
357 ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSA) ||\
358 ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB) ||\
359 ((__RREMAP__) == TIM_TIM23_ETR_GPIO) ||\
360 ((__RREMAP__) == TIM_TIM23_ETR_COMP1) ||\
361 ((__RREMAP__) == TIM_TIM23_ETR_COMP2) ||\
362 ((__RREMAP__) == TIM_TIM24_ETR_GPIO) ||\
363 ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSA) ||\
364 ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSB) ||\
365 ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSA) ||\
366 ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSB))
465 uint32_t CommutationSource);
467 uint32_t CommutationSource);
469 uint32_t CommutationSource);
474#if defined(TIM_BREAK_INPUT_SUPPORT)
476 const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
481#if defined(TIM_BDTR_BKBID)
HAL_TIM_ChannelStateTypeDef
TIM Channel States definition.
Definition: stm32h7xx_hal_tim.h:322
HAL_TIM_StateTypeDef
HAL State structures definition.
Definition: stm32h7xx_hal_tim.h:310
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
TIM Break input(s) and Dead time configuration Structure definition.
Definition: stm32h7xx_hal_tim.h:273
TIM Hall sensor Configuration Structure definition.
Definition: stm32h7xx_hal_tim_ex.h:49
uint32_t IC1Polarity
Definition: stm32h7xx_hal_tim_ex.h:50
uint32_t IC1Filter
Definition: stm32h7xx_hal_tim_ex.h:56
uint32_t Commutation_Delay
Definition: stm32h7xx_hal_tim_ex.h:59
uint32_t IC1Prescaler
Definition: stm32h7xx_hal_tim_ex.h:53
TIM Time Base Handle Structure definition.
Definition: stm32h7xx_hal_tim.h:360
TIM Master configuration Structure definition.
Definition: stm32h7xx_hal_tim.h:235
DMA handle Structure definition.
Definition: stm32h7xx_hal_dma.h:138