RTEMS 6.1-rc7
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cpu.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
12/*
13 * This include file contains information pertaining to the XXX
14 * processor.
15 *
16 * @note This file is part of a porting template that is intended
17 * to be used as the starting point when porting RTEMS to a new
18 * CPU family. The following needs to be done when using this as
19 * the starting point for a new port:
20 *
21 * + Anywhere there is an XXX, it should be replaced
22 * with information about the CPU family being ported to.
23 *
24 * + At the end of each comment section, there is a heading which
25 * says "Port Specific Information:". When porting to RTEMS,
26 * add CPU family specific information in this section
27 */
28
29/*
30 * COPYRIGHT (c) 1989-2008.
31 * On-Line Applications Research Corporation (OAR).
32 *
33 * Redistribution and use in source and binary forms, with or without
34 * modification, are permitted provided that the following conditions
35 * are met:
36 * 1. Redistributions of source code must retain the above copyright
37 * notice, this list of conditions and the following disclaimer.
38 * 2. Redistributions in binary form must reproduce the above copyright
39 * notice, this list of conditions and the following disclaimer in the
40 * documentation and/or other materials provided with the distribution.
41 *
42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
43 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
45 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
46 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
47 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
48 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
49 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
50 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
51 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
52 * POSSIBILITY OF SUCH DAMAGE.
53 */
54
55#ifndef _RTEMS_SCORE_CPU_H
56#define _RTEMS_SCORE_CPU_H
57
58#ifdef __cplusplus
59extern "C" {
60#endif
61
63#include <rtems/score/no_cpu.h>
64
65/* conditional compilation parameters */
66
78#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
79
89#define CPU_ISR_PASSES_FRAME_POINTER FALSE
90
126#if ( NO_CPU_HAS_FPU == 1 )
127#define CPU_HARDWARE_FP TRUE
128#else
129#define CPU_HARDWARE_FP FALSE
130#endif
131#define CPU_SOFTWARE_FP FALSE
132
157#define CPU_ALL_TASKS_ARE_FP TRUE
158
174#define CPU_IDLE_TASK_IS_FP FALSE
175
205#define CPU_USE_DEFERRED_FP_SWITCH TRUE
206
217#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
218
230#define CPU_STACK_GROWS_UP TRUE
231
237#define CPU_CACHE_LINE_BYTES 32
238
250#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
251
263#define CPU_MODES_INTERRUPT_MASK 0x00000001
264
269#define CPU_MAXIMUM_PROCESSORS 32
270
277#define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE
278
279/*
280 * Processor defined structures required for cpukit/score.
281 *
282 * Port Specific Information:
283 *
284 * XXX document implementation including references if appropriate
285 */
286
287/* may need to put some structures here. */
288
350typedef struct {
361
367
368#ifdef RTEMS_SMP
413 volatile bool is_executing;
414#endif
416
426#define _CPU_Context_Get_SP( _context ) \
427 (_context)->stack_pointer
428
435typedef struct {
439
447typedef struct {
453 uint32_t special_interrupt_register;
455
466extern Context_Control_fp _CPU_Null_fp_context;
467
486/*
487 * Nothing prevents the porter from declaring more CPU specific variables.
488 *
489 * Port Specific Information:
490 *
491 * XXX document implementation including references if appropriate
492 */
493
494/* XXX: if needed, put more variables here */
495
508#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
509
519#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
520
531#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
532
543#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
544
551#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
552
564#define CPU_STACK_MINIMUM_SIZE (1024*4)
565
573#define CPU_SIZEOF_POINTER 4
574
586#define CPU_ALIGNMENT 8
587
610#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
611
624#define CPU_STACK_ALIGNMENT CPU_HEAP_ALIGNMENT
625
632#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
633
634/*
635 * ISR handler macros
636 */
637
650#define _CPU_ISR_Disable( _isr_cookie ) \
651 { \
652 (_isr_cookie) = 0; /* do something to prevent warnings */ \
653 }
654
668#define _CPU_ISR_Enable( _isr_cookie ) \
669 { \
670 }
671
686#define _CPU_ISR_Flash( _isr_cookie ) \
687 { \
688 }
689
699static inline bool _CPU_ISR_Is_enabled( uint32_t level )
700{
701 return false;
702}
703
721#define _CPU_ISR_Set_level( new_level ) \
722 { \
723 }
724
737uint32_t _CPU_ISR_Get_level( void );
738
739/* end of ISR handler macros */
740
741/* Context handler macros */
742
758#define _CPU_Context_Destroy( _the_thread, _the_context ) \
759 { \
760 }
761
799#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
800 _isr, _entry_point, _is_fp, _tls_area ) \
801 { \
802 }
803
819#define _CPU_Context_Restart_self( _the_context ) \
820 _CPU_Context_restore( (_the_context) );
821
840#define _CPU_Context_Initialize_fp( _destination ) \
841 { \
842 *(*(_destination)) = _CPU_Null_fp_context; \
843 }
844
845/* end of Context handler macros */
846
847/* Bitfield handler macros */
848
864#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
865
930#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
931#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
932 { \
933 (_output) = 0; /* do something to prevent warnings */ \
934 }
935#endif
936
939/* end of Bitfield handler macros */
940
950#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
951
952#define _CPU_Priority_Mask( _bit_number ) \
953 ( 1 << (_bit_number) )
954
955#endif
956
971#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
972
973#define _CPU_Priority_bits_index( _priority ) \
974 (_priority)
975
976#endif
977
978/* end of Priority handler macros */
979
980/* functions */
981
989void _CPU_Initialize(void);
990
991typedef void ( *CPU_ISR_raw_handler )( void );
992
1010 uint32_t vector,
1011 CPU_ISR_raw_handler new_handler,
1012 CPU_ISR_raw_handler *old_handler
1013);
1014
1015typedef void ( *CPU_ISR_handler )( uint32_t );
1016
1034 uint32_t vector,
1035 CPU_ISR_handler new_handler,
1036 CPU_ISR_handler *old_handler
1037);
1038
1046RTEMS_NO_RETURN void *_CPU_Thread_Idle_body( uintptr_t ignored );
1047
1065 Context_Control *executing,
1066 Context_Control *heir
1067);
1068
1084RTEMS_NO_RETURN void _CPU_Context_switch_no_return(
1085 Context_Control *executing,
1086 Context_Control *heir
1087);
1088
1103RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context );
1104
1121 Context_Control_fp **fp_context_ptr
1122);
1123
1140 Context_Control_fp **fp_context_ptr
1141);
1142
1152typedef struct {
1153 uint32_t processor_state_register;
1154 uint32_t integer_registers [1];
1155 double float_registers [1];
1157
1164
1165#ifdef RTEMS_EXCEPTION_EXTENSIONS
1175 RTEMS_NO_RETURN void _CPU_Exception_resume( CPU_Exception_frame *frame );
1176
1189 RTEMS_NO_RETURN void _CPU_Exception_dispatch_and_resume(
1190 CPU_Exception_frame *frame
1191 );
1192
1199 void _CPU_Exception_disable_thread_dispatch( void );
1200
1208 int _CPU_Exception_frame_get_signal( CPU_Exception_frame *frame );
1209
1216 void _CPU_Exception_frame_set_resume( CPU_Exception_frame *frame, void *address );
1217
1225 void _CPU_Exception_frame_make_resume_next_instruction( CPU_Exception_frame *frame );
1226#endif
1227
1265static inline uint32_t CPU_swap_u32(
1266 uint32_t value
1267)
1268{
1269 uint32_t byte1, byte2, byte3, byte4, swapped;
1270
1271 byte4 = (value >> 24) & 0xff;
1272 byte3 = (value >> 16) & 0xff;
1273 byte2 = (value >> 8) & 0xff;
1274 byte1 = value & 0xff;
1275
1276 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1277 return swapped;
1278}
1279
1286#define CPU_swap_u16( value ) \
1287 (((value&0xff) << 8) | ((value >> 8)&0xff))
1288
1294typedef uint32_t CPU_Counter_ticks;
1295
1301uint32_t _CPU_Counter_frequency( void );
1302
1316CPU_Counter_ticks _CPU_Counter_read( void );
1317
1318#ifdef RTEMS_SMP
1332 uint32_t _CPU_SMP_Initialize( void );
1333
1347 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
1348
1363 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
1364
1375 void _CPU_SMP_Prepare_start_multitasking( void );
1376
1384 static inline uint32_t _CPU_SMP_Get_current_processor( void )
1385 {
1386 return 123;
1387 }
1388
1397 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1398
1404 static inline bool _CPU_Context_Get_is_executing(
1406 )
1407 {
1408 return context->is_executing;
1409 }
1410
1417 static inline void _CPU_Context_Set_is_executing(
1419 bool is_executing
1420 )
1421 {
1422 context->is_executing = is_executing;
1423 }
1424
1426typedef uintptr_t CPU_Uint32ptr;
1427
1428#endif
1429
1430#ifdef __cplusplus
1431}
1432#endif
1433
1434#endif
This header file provides basic definitions used by the API and the implementation.
void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.c:100
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
rtems_termios_device_context * context
Definition: console-config.c:62
#define _CPU_Context_restore_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:901
#define _CPU_Context_save_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:895
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
SPARC basic context.
Definition: cpu.h:213
double some_float_register
Definition: cpu.h:437
Thread register context.
Definition: cpu.h:173
uint32_t some_integer_register
Definition: cpu.h:355
uint32_t some_system_register
Definition: cpu.h:360
uint32_t stack_pointer
Definition: cpu.h:366