RTEMS 6.1-rc7
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stm32h7xx_hal_cortex.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_HAL_CORTEX_H
21#define STM32H7xx_HAL_CORTEX_H
22
23#ifdef __cplusplus
24 extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx_hal_def.h"
29
37/* Exported types ------------------------------------------------------------*/
43#if (__MPU_PRESENT == 1)
49typedef struct
50{
51 uint8_t Enable;
53 uint8_t Number;
55 uint32_t BaseAddress;
56 uint8_t Size;
58 uint8_t SubRegionDisable;
60 uint8_t TypeExtField;
62 uint8_t AccessPermission;
64 uint8_t DisableExec;
66 uint8_t IsShareable;
68 uint8_t IsCacheable;
70 uint8_t IsBufferable;
72}MPU_Region_InitTypeDef;
76#endif /* __MPU_PRESENT */
77
82/* Exported constants --------------------------------------------------------*/
83
93#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007)
95#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006)
97#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005)
99#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004)
101#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003)
111#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
112#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
113
118#if (__MPU_PRESENT == 1)
123#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
124#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
125#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
126#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
135#define MPU_REGION_ENABLE ((uint8_t)0x01)
136#define MPU_REGION_DISABLE ((uint8_t)0x00)
145#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
146#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
155#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
156#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
165#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
166#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
175#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
176#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
185#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
186#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
187#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
196#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
197#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
198#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
199#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
200#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
201#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
202#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
203#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
204#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
205#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
206#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
207#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
208#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
209#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
210#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
211#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
212#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
213#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
214#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
215#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
216#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
217#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
218#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
219#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
220#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
221#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
222#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
223#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
232#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
233#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
234#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
235#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
236#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
237#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
246#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
247#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
248#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
249#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
250#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
251#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
252#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
253#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
254#if !defined(CORE_CM4)
255#define MPU_REGION_NUMBER8 ((uint8_t)0x08)
256#define MPU_REGION_NUMBER9 ((uint8_t)0x09)
257#define MPU_REGION_NUMBER10 ((uint8_t)0x0A)
258#define MPU_REGION_NUMBER11 ((uint8_t)0x0B)
259#define MPU_REGION_NUMBER12 ((uint8_t)0x0C)
260#define MPU_REGION_NUMBER13 ((uint8_t)0x0D)
261#define MPU_REGION_NUMBER14 ((uint8_t)0x0E)
262#define MPU_REGION_NUMBER15 ((uint8_t)0x0F)
263#endif /* !defined(CORE_CM4) */
264
268#endif /* __MPU_PRESENT */
269
275/* Exported Macros -----------------------------------------------------------*/
291#define CM7_CPUID ((uint32_t)0x00000003)
292
293#if defined(DUAL_CORE)
294#define CM4_CPUID ((uint32_t)0x00000001)
295#endif /*DUAL_CORE*/
301/* Exported functions --------------------------------------------------------*/
309/* Initialization and de-initialization functions *****************************/
310void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
311void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
312void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
313void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
314void HAL_NVIC_SystemReset(void);
315uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
323/* Peripheral Control functions ***********************************************/
324#if (__MPU_PRESENT == 1)
325void HAL_MPU_Enable(uint32_t MPU_Control);
326void HAL_MPU_Disable(void);
327void HAL_MPU_EnableRegion(uint32_t RegionNumber);
328void HAL_MPU_DisableRegion(uint32_t RegionNumber);
329void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
330#endif /* __MPU_PRESENT */
331uint32_t HAL_NVIC_GetPriorityGrouping(void);
332void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
333uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
334void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
335void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
336uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
337void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
338void HAL_SYSTICK_IRQHandler(void);
339void HAL_SYSTICK_Callback(void);
340uint32_t HAL_GetCurrentCPUID(void);
341
342
351/* Private types -------------------------------------------------------------*/
352/* Private variables ---------------------------------------------------------*/
353/* Private constants ---------------------------------------------------------*/
354/* Private macros ------------------------------------------------------------*/
359#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
360 ((GROUP) == NVIC_PRIORITYGROUP_1) || \
361 ((GROUP) == NVIC_PRIORITYGROUP_2) || \
362 ((GROUP) == NVIC_PRIORITYGROUP_3) || \
363 ((GROUP) == NVIC_PRIORITYGROUP_4))
364
365#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL)
366
367#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL)
368
369#define IS_NVIC_DEVICE_IRQ(IRQ) (((int32_t)IRQ) >= 0x00)
370
371#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
372 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
373
374#if (__MPU_PRESENT == 1)
375#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
376 ((STATE) == MPU_REGION_DISABLE))
377
378#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
379 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
380
381#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
382 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
383
384#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
385 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
386
387#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
388 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
389
390#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
391 ((TYPE) == MPU_TEX_LEVEL1) || \
392 ((TYPE) == MPU_TEX_LEVEL2))
393
394#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
395 ((TYPE) == MPU_REGION_PRIV_RW) || \
396 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
397 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
398 ((TYPE) == MPU_REGION_PRIV_RO) || \
399 ((TYPE) == MPU_REGION_PRIV_RO_URO))
400
401#if !defined(CORE_CM4)
402#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
403 ((NUMBER) == MPU_REGION_NUMBER1) || \
404 ((NUMBER) == MPU_REGION_NUMBER2) || \
405 ((NUMBER) == MPU_REGION_NUMBER3) || \
406 ((NUMBER) == MPU_REGION_NUMBER4) || \
407 ((NUMBER) == MPU_REGION_NUMBER5) || \
408 ((NUMBER) == MPU_REGION_NUMBER6) || \
409 ((NUMBER) == MPU_REGION_NUMBER7) || \
410 ((NUMBER) == MPU_REGION_NUMBER8) || \
411 ((NUMBER) == MPU_REGION_NUMBER9) || \
412 ((NUMBER) == MPU_REGION_NUMBER10) || \
413 ((NUMBER) == MPU_REGION_NUMBER11) || \
414 ((NUMBER) == MPU_REGION_NUMBER12) || \
415 ((NUMBER) == MPU_REGION_NUMBER13) || \
416 ((NUMBER) == MPU_REGION_NUMBER14) || \
417 ((NUMBER) == MPU_REGION_NUMBER15))
418#else
419#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
420 ((NUMBER) == MPU_REGION_NUMBER1) || \
421 ((NUMBER) == MPU_REGION_NUMBER2) || \
422 ((NUMBER) == MPU_REGION_NUMBER3) || \
423 ((NUMBER) == MPU_REGION_NUMBER4) || \
424 ((NUMBER) == MPU_REGION_NUMBER5) || \
425 ((NUMBER) == MPU_REGION_NUMBER6) || \
426 ((NUMBER) == MPU_REGION_NUMBER7))
427#endif /* !defined(CORE_CM4) */
428
429#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
430 ((SIZE) == MPU_REGION_SIZE_64B) || \
431 ((SIZE) == MPU_REGION_SIZE_128B) || \
432 ((SIZE) == MPU_REGION_SIZE_256B) || \
433 ((SIZE) == MPU_REGION_SIZE_512B) || \
434 ((SIZE) == MPU_REGION_SIZE_1KB) || \
435 ((SIZE) == MPU_REGION_SIZE_2KB) || \
436 ((SIZE) == MPU_REGION_SIZE_4KB) || \
437 ((SIZE) == MPU_REGION_SIZE_8KB) || \
438 ((SIZE) == MPU_REGION_SIZE_16KB) || \
439 ((SIZE) == MPU_REGION_SIZE_32KB) || \
440 ((SIZE) == MPU_REGION_SIZE_64KB) || \
441 ((SIZE) == MPU_REGION_SIZE_128KB) || \
442 ((SIZE) == MPU_REGION_SIZE_256KB) || \
443 ((SIZE) == MPU_REGION_SIZE_512KB) || \
444 ((SIZE) == MPU_REGION_SIZE_1MB) || \
445 ((SIZE) == MPU_REGION_SIZE_2MB) || \
446 ((SIZE) == MPU_REGION_SIZE_4MB) || \
447 ((SIZE) == MPU_REGION_SIZE_8MB) || \
448 ((SIZE) == MPU_REGION_SIZE_16MB) || \
449 ((SIZE) == MPU_REGION_SIZE_32MB) || \
450 ((SIZE) == MPU_REGION_SIZE_64MB) || \
451 ((SIZE) == MPU_REGION_SIZE_128MB) || \
452 ((SIZE) == MPU_REGION_SIZE_256MB) || \
453 ((SIZE) == MPU_REGION_SIZE_512MB) || \
454 ((SIZE) == MPU_REGION_SIZE_1GB) || \
455 ((SIZE) == MPU_REGION_SIZE_2GB) || \
456 ((SIZE) == MPU_REGION_SIZE_4GB))
457
458#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
459#endif /* __MPU_PRESENT */
460
473#ifdef __cplusplus
474}
475#endif
476
477#endif /* STM32H7xx_HAL_CORTEX_H */
478
479
IRQn_Type
STM32H7XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32h723xx.h:49
This file contains HAL common defines, enumeration, macros and structures definitions.