RTEMS 6.1-rc7
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fsl_clock.h
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1/*
2 * Copyright 2017 - 2021 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_CLOCK_H_
9#define _FSL_CLOCK_H_
10
11#include "fsl_common.h"
12
18/*******************************************************************************
19 * Configurations
20 ******************************************************************************/
21
32#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
33#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
34#endif
35
36/*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
43#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 1))
44
45/* Definition for delay API in clock driver, users can redefine it to the real application. */
46#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
47#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (600000000UL)
48#endif
49
50/* analog pll definition */
51#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
52#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
53#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
54
60#define CCSR_OFFSET 0x0C
61#define CBCDR_OFFSET 0x14
62#define CBCMR_OFFSET 0x18
63#define CSCMR1_OFFSET 0x1C
64#define CSCMR2_OFFSET 0x20
65#define CSCDR1_OFFSET 0x24
66#define CDCDR_OFFSET 0x30
67#define CSCDR2_OFFSET 0x38
68#define CSCDR3_OFFSET 0x3C
69#define CACRR_OFFSET 0x10
70#define CS1CDR_OFFSET 0x28
71#define CS2CDR_OFFSET 0x2C
72
76#define PLL_ARM_OFFSET 0x00
77#define PLL_SYS_OFFSET 0x30
78#define PLL_USB1_OFFSET 0x10
79#define PLL_AUDIO_OFFSET 0x70
80#define PLL_VIDEO_OFFSET 0xA0
81#define PLL_ENET_OFFSET 0xE0
82#define PLL_USB2_OFFSET 0x20
83
84#define CCM_TUPLE(reg, shift, mask, busyShift) \
85 (int)(((reg)&0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
86#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFU))))
87#define CCM_TUPLE_SHIFT(tuple) ((((uint32_t)tuple) >> 8U) & 0x1FU)
88#define CCM_TUPLE_MASK(tuple) \
89 ((uint32_t)((((uint32_t)(tuple) >> 13U) & 0x1FFFU) << (((((uint32_t)tuple) >> 8U) & 0x1FU))))
90#define CCM_TUPLE_BUSY_SHIFT(tuple) ((((uint32_t)tuple) >> 26U) & 0x3FU)
91
92#define CCM_NO_BUSY_WAIT (0x20U)
93
97#define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFU) << 16U) | (shift))
98#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU)
99#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
100 (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFU) + (off))))
101#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
102
103/* Definition for ERRATA 50235 check */
104#if (defined(FSL_FEATURE_CCM_HAS_ERRATA_50235) && FSL_FEATURE_CCM_HAS_ERRATA_50235)
105#define CAN_CLOCK_CHECK_NO_AFFECTS \
106 ((CCM_CSCMR2_CAN_CLK_SEL(2U) != (CCM->CSCMR2 & CCM_CSCMR2_CAN_CLK_SEL_MASK)) || \
107 (CCM_CCGR5_CG12(0) != (CCM->CCGR5 & CCM_CCGR5_CG12_MASK)))
108#endif /* FSL_FEATURE_CCM_HAS_ERRATA_50235 */
109
113#define CLKPN_FREQ 0U
114
125extern volatile uint32_t g_xtalFreq;
126
132extern volatile uint32_t g_rtcXtalFreq;
133
134/* For compatible with other platforms */
135#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq
136#define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq
137
139#define ADC_CLOCKS \
140 { \
141 kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \
142 }
143
145#define AOI_CLOCKS \
146 { \
147 kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \
148 }
149
151#define BEE_CLOCKS \
152 { \
153 kCLOCK_Bee \
154 }
155
157#define CMP_CLOCKS \
158 { \
159 kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \
160 }
161
163#define CSI_CLOCKS \
164 { \
165 kCLOCK_Csi \
166 }
167
169#define DCDC_CLOCKS \
170 { \
171 kCLOCK_Dcdc \
172 }
173
175#define DCP_CLOCKS \
176 { \
177 kCLOCK_Dcp \
178 }
179
181#define DMAMUX_CLOCKS \
182 { \
183 kCLOCK_Dma \
184 }
185
187#define EDMA_CLOCKS \
188 { \
189 kCLOCK_Dma \
190 }
191
193#define ENC_CLOCKS \
194 { \
195 kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \
196 }
197
199#define ENET_CLOCKS \
200 { \
201 kCLOCK_Enet \
202 }
203
205#define EWM_CLOCKS \
206 { \
207 kCLOCK_Ewm0 \
208 }
209
211#define FLEXCAN_CLOCKS \
212 { \
213 kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 \
214 }
215
217#define FLEXCAN_PERIPH_CLOCKS \
218 { \
219 kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S \
220 }
221
223#define FLEXIO_CLOCKS \
224 { \
225 kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \
226 }
227
229#define FLEXRAM_CLOCKS \
230 { \
231 kCLOCK_FlexRam \
232 }
233
235#define FLEXSPI_CLOCKS \
236 { \
237 kCLOCK_FlexSpi \
238 }
239
241#define FLEXSPI_EXSC_CLOCKS \
242 { \
243 kCLOCK_FlexSpiExsc \
244 }
245
247#define GPIO_CLOCKS \
248 { \
249 kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
250 }
251
253#define GPT_CLOCKS \
254 { \
255 kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \
256 }
257
259#define KPP_CLOCKS \
260 { \
261 kCLOCK_Kpp \
262 }
263
265#define LCDIF_CLOCKS \
266 { \
267 kCLOCK_Lcd \
268 }
269
271#define LCDIF_PERIPH_CLOCKS \
272 { \
273 kCLOCK_LcdPixel \
274 }
275
277#define LPI2C_CLOCKS \
278 { \
279 kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \
280 }
281
283#define LPSPI_CLOCKS \
284 { \
285 kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 \
286 }
287
289#define LPUART_CLOCKS \
290 { \
291 kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \
292 kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \
293 }
294
296#define MQS_CLOCKS \
297 { \
298 kCLOCK_Mqs \
299 }
300
302#define OCRAM_EXSC_CLOCKS \
303 { \
304 kCLOCK_OcramExsc \
305 }
306
308#define PIT_CLOCKS \
309 { \
310 kCLOCK_Pit \
311 }
312
314#define PWM_CLOCKS \
315 { \
316 {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
317 {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, \
318 {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2}, \
319 {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3}, \
320 { \
321 kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4 \
322 } \
323 }
324
326#define PXP_CLOCKS \
327 { \
328 kCLOCK_Pxp \
329 }
330
332#define RTWDOG_CLOCKS \
333 { \
334 kCLOCK_Wdog3 \
335 }
336
338#define SAI_CLOCKS \
339 { \
340 kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \
341 }
342
344#define SEMC_CLOCKS \
345 { \
346 kCLOCK_Semc \
347 }
348
350#define SEMC_EXSC_CLOCKS \
351 { \
352 kCLOCK_SemcExsc \
353 }
354
356#define TMR_CLOCKS \
357 { \
358 kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \
359 }
360
362#define TRNG_CLOCKS \
363 { \
364 kCLOCK_Trng \
365 }
366
368#define TSC_CLOCKS \
369 { \
370 kCLOCK_Tsc \
371 }
372
374#define WDOG_CLOCKS \
375 { \
376 kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \
377 }
378
380#define USDHC_CLOCKS \
381 { \
382 kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
383 }
384
386#define SPDIF_CLOCKS \
387 { \
388 kCLOCK_Spdif \
389 }
390
392#define XBARA_CLOCKS \
393 { \
394 kCLOCK_IpInvalid, kCLOCK_Xbar1 \
395 }
396
398#define XBARB_CLOCKS \
399 { \
400 kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \
401 }
402
403#define CLOCK_SOURCE_NONE (0xFFU)
404
405#define CLOCK_ROOT_SOUCE \
406 { \
407 {kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, kCLOCK_NoneName, \
408 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* USDHC1 Clock Root. */ \
409 {kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, kCLOCK_NoneName, \
410 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* USDHC2 Clock Root. */ \
411 {kCLOCK_SemcClk, kCLOCK_Usb1SwClk, kCLOCK_SysPllPfd2Clk, \
412 kCLOCK_Usb1PllPfd0Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXSPI Clock Root. */ \
413 {kCLOCK_OscClk, kCLOCK_SysPllPfd2Clk, kCLOCK_Usb1Sw120MClk, \
414 kCLOCK_Usb1PllPfd1Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* CSI Clock Root. */ \
415 {kCLOCK_Usb1PllPfd1Clk, kCLOCK_Usb1PllPfd0Clk, kCLOCK_SysPllClk, \
416 kCLOCK_SysPllPfd2Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* LPSPI Clock Root. */ \
417 {kCLOCK_SysPllClk, kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, \
418 kCLOCK_SysPllPfd1Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* TRACE Clock Root */ \
419 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \
420 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI1 Clock Root */ \
421 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \
422 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI2 Clock Root */ \
423 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \
424 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI3 Clock Root */ \
425 {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_NoneName, \
426 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* LPI2C Clock Root */ \
427 {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_Usb1Sw80MClk, \
428 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* CAN Clock Root. */ \
429 {kCLOCK_Usb1Sw80MClk, kCLOCK_OscClk, kCLOCK_NoneName, \
430 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* UART Clock Root */ \
431 {kCLOCK_SysPllClk, kCLOCK_Usb1PllPfd3Clk, kCLOCK_VideoPllClk, \
432 kCLOCK_SysPllPfd0Clk, kCLOCK_SysPllPfd1Clk, kCLOCK_Usb1PllPfd1Clk}, /* LCDIF Clock Root */ \
433 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \
434 kCLOCK_Usb1SwClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* SPDIF0 Clock Root */ \
435 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \
436 kCLOCK_Usb1SwClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXIO1 Clock Root */ \
437 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \
438 kCLOCK_Usb1PllClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXIO2 Clock ROOT */ \
439 }
440
441#define CLOCK_ROOT_MUX_TUPLE \
442 { \
443 kCLOCK_Usdhc1Mux, kCLOCK_Usdhc2Mux, kCLOCK_FlexspiMux, kCLOCK_CsiMux, kCLOCK_LpspiMux, kCLOCK_TraceMux, \
444 kCLOCK_Sai1Mux, kCLOCK_Sai2Mux, kCLOCK_Sai3Mux, kCLOCK_Lpi2cMux, kCLOCK_CanMux, kCLOCK_UartMux, \
445 kCLOCK_LcdifPreMux, kCLOCK_SpdifMux, kCLOCK_Flexio1Mux, kCLOCK_Flexio2Mux, \
446 }
447
448#define CLOCK_ROOT_NONE_PRE_DIV 0UL
449
450#define CLOCK_ROOT_DIV_TUPLE \
451 { \
452 {kCLOCK_NonePreDiv, kCLOCK_Usdhc1Div}, {kCLOCK_NonePreDiv, kCLOCK_Usdhc2Div}, \
453 {kCLOCK_NonePreDiv, kCLOCK_FlexspiDiv}, {kCLOCK_NonePreDiv, kCLOCK_CsiDiv}, \
454 {kCLOCK_NonePreDiv, kCLOCK_LpspiDiv}, {kCLOCK_NonePreDiv, kCLOCK_TraceDiv}, \
455 {kCLOCK_Sai1PreDiv, kCLOCK_Sai1Div}, {kCLOCK_Sai2PreDiv, kCLOCK_Sai2Div}, \
456 {kCLOCK_Sai3PreDiv, kCLOCK_Sai3Div}, {kCLOCK_NonePreDiv, kCLOCK_Lpi2cDiv}, \
457 {kCLOCK_NonePreDiv, kCLOCK_CanDiv}, {kCLOCK_NonePreDiv, kCLOCK_UartDiv}, \
458 {kCLOCK_LcdifPreDiv, kCLOCK_LcdifDiv}, {kCLOCK_Spdif0PreDiv, kCLOCK_Spdif0Div}, \
459 {kCLOCK_Flexio1PreDiv, kCLOCK_Flexio1Div}, {kCLOCK_Flexio2PreDiv, kCLOCK_Flexio2Div}, \
460 }
461
463typedef enum _clock_name
464{
499 kCLOCK_NoneName = CLOCK_SOURCE_NONE,
501
502#define kCLOCK_CoreSysClk kCLOCK_CpuClk
503#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq
508typedef enum _clock_ip_name
509{
510 kCLOCK_IpInvalid = -1,
511
512 /* CCM CCGR0 */
513 kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT,
514 kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT,
515 kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT,
516 kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT,
517 kCLOCK_Sim_M_Main = (0U << 8U) | CCM_CCGR0_CG4_SHIFT,
518 kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT,
519 kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT,
520 kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT,
521 kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT,
522 kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT,
523 kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT,
524 kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT,
525 kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT,
526 kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT,
527 kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT,
528 kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT,
530 /* CCM CCGR1 */
531 kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT,
532 kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT,
533 kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT,
534 kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT,
535 kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT,
536 kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT,
537 kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT,
538 kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT,
539 kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT,
540 kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT,
541 kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT,
542 kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT,
543 kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT,
544 kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT,
545 kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT,
546 kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT,
548 /* CCM CCGR2 */
549 kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT,
550 kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT,
551 kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT,
552 kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT,
553 kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT,
554 kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT,
555 kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT,
556 kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT,
557 kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT,
558 kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT,
559 kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT,
560 kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT,
561 kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT,
562 kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT,
563 kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT,
564 kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT,
566 /* CCM CCGR3 */
567 kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT,
568 kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT,
569 kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT,
570 kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT,
571 kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT,
572 kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT,
573 kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT,
574 kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT,
575 kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT,
576 kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT,
577 kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT,
578 kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT,
579 kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT,
580 kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT,
581 kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT,
582 kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT,
584 /* CCM CCGR4 */
585 kCLOCK_Sim_m7_clk_r = (4U << 8U) | CCM_CCGR4_CG0_SHIFT,
586 kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT,
587 kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT,
588 kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT,
589 kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT,
590 kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT,
591 kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT,
592 kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT,
593 kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT,
594 kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT,
595 kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT,
596 kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT,
597 kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT,
598 kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT,
599 kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT,
600 kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT,
602 /* CCM CCGR5 */
603 kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT,
604 kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT,
605 kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT,
606 kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT,
607 kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT,
608 kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT,
609 kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT,
610 kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT,
611 kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT,
612 kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT,
613 kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT,
614 kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT,
615 kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT,
616 kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT,
617 kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT,
618 kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT,
620 /* CCM CCGR6 */
621 kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT,
622 kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT,
623 kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT,
624 kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT,
625 kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT,
626 kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT,
627 kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT,
628 kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT,
629 kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT,
630 kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT,
631 kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT,
632 kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT,
633 kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT,
634 kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT,
635 kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT,
636 kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT,
639
641typedef enum _clock_osc
642{
646
649{
654
656typedef enum _clock_mode_t
657{
662
671typedef enum _clock_mux
672{
673 kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET,
674 CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT,
675 CCM_CCSR_PLL3_SW_CLK_SEL_MASK,
676 CCM_NO_BUSY_WAIT),
678 kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET,
679 CCM_CBCDR_PERIPH_CLK_SEL_SHIFT,
680 CCM_CBCDR_PERIPH_CLK_SEL_MASK,
681 CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT),
682 kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR_OFFSET,
683 CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT,
684 CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK,
685 CCM_NO_BUSY_WAIT),
686 kCLOCK_SemcMux = CCM_TUPLE(CBCDR_OFFSET,
687 CCM_CBCDR_SEMC_CLK_SEL_SHIFT,
688 CCM_CBCDR_SEMC_CLK_SEL_MASK,
689 CCM_NO_BUSY_WAIT),
691 kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET,
692 CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT,
693 CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK,
694 CCM_NO_BUSY_WAIT),
695 kCLOCK_TraceMux = CCM_TUPLE(CBCMR_OFFSET,
696 CCM_CBCMR_TRACE_CLK_SEL_SHIFT,
697 CCM_CBCMR_TRACE_CLK_SEL_MASK,
698 CCM_NO_BUSY_WAIT),
699 kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET,
700 CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT,
701 CCM_CBCMR_PERIPH_CLK2_SEL_MASK,
702 CCM_NO_BUSY_WAIT),
703 kCLOCK_LpspiMux = CCM_TUPLE(CBCMR_OFFSET,
704 CCM_CBCMR_LPSPI_CLK_SEL_SHIFT,
705 CCM_CBCMR_LPSPI_CLK_SEL_MASK,
706 CCM_NO_BUSY_WAIT),
708 kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET,
709 CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT,
710 CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK,
711 CCM_NO_BUSY_WAIT),
712 kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1_OFFSET,
713 CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT,
714 CCM_CSCMR1_USDHC2_CLK_SEL_MASK,
715 CCM_NO_BUSY_WAIT),
716 kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1_OFFSET,
717 CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT,
718 CCM_CSCMR1_USDHC1_CLK_SEL_MASK,
719 CCM_NO_BUSY_WAIT),
720 kCLOCK_Sai3Mux = CCM_TUPLE(CSCMR1_OFFSET,
721 CCM_CSCMR1_SAI3_CLK_SEL_SHIFT,
722 CCM_CSCMR1_SAI3_CLK_SEL_MASK,
723 CCM_NO_BUSY_WAIT),
724 kCLOCK_Sai2Mux = CCM_TUPLE(CSCMR1_OFFSET,
725 CCM_CSCMR1_SAI2_CLK_SEL_SHIFT,
726 CCM_CSCMR1_SAI2_CLK_SEL_MASK,
727 CCM_NO_BUSY_WAIT),
728 kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR1_OFFSET,
729 CCM_CSCMR1_SAI1_CLK_SEL_SHIFT,
730 CCM_CSCMR1_SAI1_CLK_SEL_MASK,
731 CCM_NO_BUSY_WAIT),
732 kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1_OFFSET,
733 CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT,
734 CCM_CSCMR1_PERCLK_CLK_SEL_MASK,
735 CCM_NO_BUSY_WAIT),
737 kCLOCK_Flexio2Mux = CCM_TUPLE(CSCMR2_OFFSET,
738 CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT,
739 CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK,
740 CCM_NO_BUSY_WAIT),
741 kCLOCK_CanMux = CCM_TUPLE(CSCMR2_OFFSET,
742 CCM_CSCMR2_CAN_CLK_SEL_SHIFT,
743 CCM_CSCMR2_CAN_CLK_SEL_MASK,
744 CCM_NO_BUSY_WAIT),
746 kCLOCK_UartMux = CCM_TUPLE(CSCDR1_OFFSET,
747 CCM_CSCDR1_UART_CLK_SEL_SHIFT,
748 CCM_CSCDR1_UART_CLK_SEL_MASK,
749 CCM_NO_BUSY_WAIT),
751 kCLOCK_SpdifMux = CCM_TUPLE(CDCDR_OFFSET,
752 CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT,
753 CCM_CDCDR_SPDIF0_CLK_SEL_MASK,
754 CCM_NO_BUSY_WAIT),
755 kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR_OFFSET,
756 CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT,
757 CCM_CDCDR_FLEXIO1_CLK_SEL_MASK,
758 CCM_NO_BUSY_WAIT),
760 kCLOCK_Lpi2cMux = CCM_TUPLE(CSCDR2_OFFSET,
761 CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT,
762 CCM_CSCDR2_LPI2C_CLK_SEL_MASK,
763 CCM_NO_BUSY_WAIT),
764 kCLOCK_LcdifPreMux = CCM_TUPLE(CSCDR2_OFFSET,
765 CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT,
766 CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK,
767 CCM_NO_BUSY_WAIT),
769 kCLOCK_CsiMux = CCM_TUPLE(CSCDR3_OFFSET,
770 CCM_CSCDR3_CSI_CLK_SEL_SHIFT,
771 CCM_CSCDR3_CSI_CLK_SEL_MASK,
772 CCM_NO_BUSY_WAIT),
774
783typedef enum _clock_div
784{
785 kCLOCK_ArmDiv = CCM_TUPLE(CACRR_OFFSET,
786 CCM_CACRR_ARM_PODF_SHIFT,
787 CCM_CACRR_ARM_PODF_MASK,
788 CCM_CDHIPR_ARM_PODF_BUSY_SHIFT),
790 kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR_OFFSET,
791 CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT,
792 CCM_CBCDR_PERIPH_CLK2_PODF_MASK,
793 CCM_NO_BUSY_WAIT),
794 kCLOCK_SemcDiv = CCM_TUPLE(CBCDR_OFFSET,
795 CCM_CBCDR_SEMC_PODF_SHIFT,
796 CCM_CBCDR_SEMC_PODF_MASK,
797 CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT),
798 kCLOCK_AhbDiv = CCM_TUPLE(CBCDR_OFFSET,
799 CCM_CBCDR_AHB_PODF_SHIFT,
800 CCM_CBCDR_AHB_PODF_MASK,
801 CCM_CDHIPR_AHB_PODF_BUSY_SHIFT),
802 kCLOCK_IpgDiv = CCM_TUPLE(
803 CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT),
805 kCLOCK_LpspiDiv = CCM_TUPLE(
806 CBCMR_OFFSET, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT),
807 kCLOCK_LcdifDiv = CCM_TUPLE(
808 CBCMR_OFFSET, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT),
810 kCLOCK_FlexspiDiv = CCM_TUPLE(CSCMR1_OFFSET,
811 CCM_CSCMR1_FLEXSPI_PODF_SHIFT,
812 CCM_CSCMR1_FLEXSPI_PODF_MASK,
813 CCM_NO_BUSY_WAIT),
814 kCLOCK_PerclkDiv = CCM_TUPLE(CSCMR1_OFFSET,
815 CCM_CSCMR1_PERCLK_PODF_SHIFT,
816 CCM_CSCMR1_PERCLK_PODF_MASK,
817 CCM_NO_BUSY_WAIT),
819 kCLOCK_CanDiv = CCM_TUPLE(CSCMR2_OFFSET,
820 CCM_CSCMR2_CAN_CLK_PODF_SHIFT,
821 CCM_CSCMR2_CAN_CLK_PODF_MASK,
822 CCM_NO_BUSY_WAIT),
824 kCLOCK_TraceDiv = CCM_TUPLE(CSCDR1_OFFSET,
825 CCM_CSCDR1_TRACE_PODF_SHIFT,
826 CCM_CSCDR1_TRACE_PODF_MASK,
827 CCM_NO_BUSY_WAIT),
828 kCLOCK_Usdhc2Div = CCM_TUPLE(CSCDR1_OFFSET,
829 CCM_CSCDR1_USDHC2_PODF_SHIFT,
830 CCM_CSCDR1_USDHC2_PODF_MASK,
831 CCM_NO_BUSY_WAIT),
832 kCLOCK_Usdhc1Div = CCM_TUPLE(CSCDR1_OFFSET,
833 CCM_CSCDR1_USDHC1_PODF_SHIFT,
834 CCM_CSCDR1_USDHC1_PODF_MASK,
835 CCM_NO_BUSY_WAIT),
836 kCLOCK_UartDiv = CCM_TUPLE(CSCDR1_OFFSET,
837 CCM_CSCDR1_UART_CLK_PODF_SHIFT,
838 CCM_CSCDR1_UART_CLK_PODF_MASK,
839 CCM_NO_BUSY_WAIT),
841 kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR_OFFSET,
842 CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT,
843 CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK,
844 CCM_NO_BUSY_WAIT),
845 kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
846 CCM_CS1CDR_SAI3_CLK_PRED_SHIFT,
847 CCM_CS1CDR_SAI3_CLK_PRED_MASK,
848 CCM_NO_BUSY_WAIT),
849 kCLOCK_Sai3Div = CCM_TUPLE(CS1CDR_OFFSET,
850 CCM_CS1CDR_SAI3_CLK_PODF_SHIFT,
851 CCM_CS1CDR_SAI3_CLK_PODF_MASK,
852 CCM_NO_BUSY_WAIT),
853 kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
854 CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT,
855 CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK,
856 CCM_NO_BUSY_WAIT),
857 kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
858 CCM_CS1CDR_SAI1_CLK_PRED_SHIFT,
859 CCM_CS1CDR_SAI1_CLK_PRED_MASK,
860 CCM_NO_BUSY_WAIT),
861 kCLOCK_Sai1Div = CCM_TUPLE(CS1CDR_OFFSET,
862 CCM_CS1CDR_SAI1_CLK_PODF_SHIFT,
863 CCM_CS1CDR_SAI1_CLK_PODF_MASK,
864 CCM_NO_BUSY_WAIT),
866 kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR_OFFSET,
867 CCM_CS2CDR_SAI2_CLK_PRED_SHIFT,
868 CCM_CS2CDR_SAI2_CLK_PRED_MASK,
869 CCM_NO_BUSY_WAIT),
870 kCLOCK_Sai2Div = CCM_TUPLE(CS2CDR_OFFSET,
871 CCM_CS2CDR_SAI2_CLK_PODF_SHIFT,
872 CCM_CS2CDR_SAI2_CLK_PODF_MASK,
873 CCM_NO_BUSY_WAIT),
875 kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR_OFFSET,
876 CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT,
877 CCM_CDCDR_SPDIF0_CLK_PRED_MASK,
878 CCM_NO_BUSY_WAIT),
879 kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR_OFFSET,
880 CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT,
881 CCM_CDCDR_SPDIF0_CLK_PODF_MASK,
882 CCM_NO_BUSY_WAIT),
883 kCLOCK_Flexio1PreDiv = CCM_TUPLE(CDCDR_OFFSET,
884 CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT,
885 CCM_CDCDR_FLEXIO1_CLK_PRED_MASK,
886 CCM_NO_BUSY_WAIT),
887 kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR_OFFSET,
888 CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT,
889 CCM_CDCDR_FLEXIO1_CLK_PODF_MASK,
890 CCM_NO_BUSY_WAIT),
892 kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2_OFFSET,
893 CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT,
894 CCM_CSCDR2_LPI2C_CLK_PODF_MASK,
895 CCM_NO_BUSY_WAIT),
896 kCLOCK_LcdifPreDiv = CCM_TUPLE(CSCDR2_OFFSET,
897 CCM_CSCDR2_LCDIF_PRED_SHIFT,
898 CCM_CSCDR2_LCDIF_PRED_MASK,
899 CCM_NO_BUSY_WAIT),
901 kCLOCK_CsiDiv = CCM_TUPLE(
902 CSCDR3_OFFSET, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT),
904 kCLOCK_NonePreDiv = CLOCK_ROOT_NONE_PRE_DIV,
906
911{
1102 /* Only kCLOCK_Lpi2cDiv, kCLOCK_CanDiv, kCLOCK_UartDiv, kCLOCK_Sai1Div,
1103 * kCLOCK_Sai2Div, kCLOCK_Sai3Div, kCLOCK_PerclkDiv can use these.
1104 */
1170
1172typedef enum _clock_usb_src
1173{
1175 kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU,
1178
1181{
1184
1187{
1190};
1191
1194{
1195 uint32_t loopDivider;
1196 uint8_t src;
1198
1201{
1202 uint8_t loopDivider;
1205 uint8_t src;
1208
1211{
1212 uint8_t loopDivider;
1215 uint32_t numerator;
1216 uint32_t denominator;
1217 uint8_t src;
1218 uint16_t ss_stop;
1219 uint8_t ss_enable;
1220 uint16_t ss_step;
1223
1226{
1227 uint8_t loopDivider;
1228 uint8_t postDivider;
1229 uint32_t numerator;
1230 uint32_t denominator;
1231 uint8_t src;
1233
1236{
1237 uint8_t loopDivider;
1238 uint8_t postDivider;
1239 uint32_t numerator;
1240 uint32_t denominator;
1241 uint8_t src;
1244
1247{
1251 uint8_t loopDivider;
1256 uint8_t src;
1259
1261typedef enum _clock_pll
1262{
1263 kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT),
1264 kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT),
1265 kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT),
1266 kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT),
1267 kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO_OFFSET, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT),
1269 kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT),
1271 kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT),
1273 kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2_OFFSET, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT),
1276
1278typedef enum _clock_pfd
1279{
1285
1290{
1303
1309{
1324
1329{
1339
1343typedef enum _clock_root
1344{
1362
1363/*******************************************************************************
1364 * API
1365 ******************************************************************************/
1366
1367#if defined(__cplusplus)
1368extern "C" {
1369#endif /* __cplusplus */
1370
1377static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value)
1378{
1379 uint32_t busyShift;
1380
1381 busyShift = (uint32_t)CCM_TUPLE_BUSY_SHIFT(mux);
1382 CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) |
1383 (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux));
1384
1385 assert(busyShift <= CCM_NO_BUSY_WAIT);
1386
1387 /* Clock switch need Handshake? */
1388 if (CCM_NO_BUSY_WAIT != busyShift)
1389 {
1390 /* Wait until CCM internal handshake finish. */
1391 while ((CCM->CDHIPR & ((1UL << busyShift))) != 0UL)
1392 {
1393 }
1394 }
1395}
1396
1403static inline uint32_t CLOCK_GetMux(clock_mux_t mux)
1404{
1405 return (((uint32_t)(CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux))) >> CCM_TUPLE_SHIFT(mux));
1406}
1407
1429static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value)
1430{
1431 uint32_t busyShift;
1432
1433 busyShift = CCM_TUPLE_BUSY_SHIFT(divider);
1434 CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) |
1435 (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider));
1436
1437 assert(busyShift <= CCM_NO_BUSY_WAIT);
1438
1439 /* Clock switch need Handshake? */
1440 if (CCM_NO_BUSY_WAIT != busyShift)
1441 {
1442 /* Wait until CCM internal handshake finish. */
1443 while ((CCM->CDHIPR & ((uint32_t)(1UL << busyShift))) != 0UL)
1444 {
1445 }
1446 }
1447}
1448
1454static inline uint32_t CLOCK_GetDiv(clock_div_t divider)
1455{
1456 return ((uint32_t)(CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider));
1457}
1458
1465static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value)
1466{
1467 uint32_t index = ((uint32_t)name) >> 8U;
1468 uint32_t shift = ((uint32_t)name) & 0x1FU;
1469 volatile uint32_t *reg;
1470
1471 assert(index <= 6UL);
1472
1473 reg = (volatile uint32_t *)(&(((volatile uint32_t *)&CCM->CCGR0)[index]));
1474 SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, (3UL << shift), (((uint32_t)value) << shift));
1475}
1476
1482static inline void CLOCK_EnableClock(clock_ip_name_t name)
1483{
1484 CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait);
1485}
1486
1492static inline void CLOCK_DisableClock(clock_ip_name_t name)
1493{
1494 CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded);
1495}
1496
1502static inline void CLOCK_SetMode(clock_mode_t mode)
1503{
1504 CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode);
1505}
1506
1515static inline uint32_t CLOCK_GetOscFreq(void)
1516{
1517 return ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_xtalFreq;
1518}
1519
1525uint32_t CLOCK_GetAhbFreq(void);
1526
1532uint32_t CLOCK_GetSemcFreq(void);
1533
1539uint32_t CLOCK_GetIpgFreq(void);
1540
1546uint32_t CLOCK_GetPerClkFreq(void);
1547
1557uint32_t CLOCK_GetFreq(clock_name_t name);
1558
1564static inline uint32_t CLOCK_GetCpuClkFreq(void)
1565{
1567}
1568
1575uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot);
1576
1596void CLOCK_InitExternalClk(bool bypassXtalOsc);
1597
1606void CLOCK_DeinitExternalClk(void);
1607
1616
1622static inline uint32_t CLOCK_GetRtcFreq(void)
1623{
1624 return 32768U;
1625}
1626
1632static inline void CLOCK_SetXtalFreq(uint32_t freq)
1633{
1634 g_xtalFreq = freq;
1635}
1636
1642static inline void CLOCK_SetRtcXtalFreq(uint32_t freq)
1643{
1644 g_rtcXtalFreq = freq;
1645}
1646
1650void CLOCK_InitRcOsc24M(void);
1651
1655void CLOCK_DeinitRcOsc24M(void);
1656/* @} */
1657
1669bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
1670
1682bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq);
1683
1684/* @} */
1685
1699static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass)
1700{
1701 if (bypass)
1702 {
1703 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1704 }
1705 else
1706 {
1707 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1708 }
1709}
1710
1720static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll)
1721{
1722 return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_PLL_BYPASS_SHIFT));
1723}
1724
1734static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll)
1735{
1736 return ((CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pll))) != 0U);
1737}
1738
1747static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src)
1748{
1749 CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src;
1750}
1751
1760static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll)
1761{
1762 return (((CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK) >>
1763 CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == (uint32_t)kCLOCK_PllClkSrc24M) ?
1764 CLOCK_GetOscFreq() :
1765 CLKPN_FREQ;
1766}
1767
1776
1780void CLOCK_DeinitArmPll(void);
1781
1790
1794void CLOCK_DeinitSysPll(void);
1795
1804
1808void CLOCK_DeinitUsb1Pll(void);
1809
1818
1822void CLOCK_DeinitUsb2Pll(void);
1823
1832
1836void CLOCK_DeinitAudioPll(void);
1837
1846
1850void CLOCK_DeinitVideoPll(void);
1859
1865void CLOCK_DeinitEnetPll(void);
1866
1875uint32_t CLOCK_GetPllFreq(clock_pll_t pll);
1876
1887void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac);
1888
1897
1907
1918void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac);
1919
1928
1938
1947uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd);
1948
1957uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd);
1958
1968bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
1969
1975
1985bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
1986
1992
1993/* @} */
1994
2007
2015
2021uint32_t CLOCK_GetClockOutCLKO1Freq(void);
2022
2028uint32_t CLOCK_GetClockOutClkO2Freq(void);
2029
2032#if defined(__cplusplus)
2033}
2034#endif /* __cplusplus */
2035
2038#endif /* _FSL_CLOCK_H_ */
#define CCM
Definition: MIMXRT1052.h:7185
#define CCM_CLPCR_LPM(x)
Definition: MIMXRT1052.h:6298
#define XTALOSC24M
Definition: MIMXRT1052.h:53468
enum _clock_div clock_div_t
DIV control names for clock div setting.
enum _clock_ip_name clock_ip_name_t
CCM CCGR gate control for each module independently.
uint8_t loopDivider
Definition: fsl_clock.h:1251
void CLOCK_DeinitSysPfd(clock_pfd_t pfd)
De-initialize the System PLL PFD.
Definition: fsl_clock.c:1180
uint32_t denominator
Definition: fsl_clock.h:1230
_clock_ip_name
CCM CCGR gate control for each module independently.
Definition: fsl_clock.h:509
uint32_t loopDivider
Definition: fsl_clock.h:1195
uint32_t CLOCK_GetAhbFreq(void)
Gets the AHB clock frequency.
Definition: fsl_clock.c:258
struct _clock_video_pll_config clock_video_pll_config_t
PLL configuration for AUDIO and VIDEO.
enum _clock_mode_t clock_mode_t
System clock mode.
void CLOCK_DeinitEnetPll(void)
Deinitialize the ENET PLL.
Definition: fsl_clock.c:926
void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config)
Initialize the ENET PLL.
Definition: fsl_clock.c:891
#define PLL_ARM_OFFSET
CCM Analog registers offset.
Definition: fsl_clock.h:76
_clock_name
Clock name used to get clock frequency.
Definition: fsl_clock.h:464
bool CLOCK_IsUsb1PfdEnabled(clock_pfd_t pfd)
Check if Usb1 PFD is enabled.
Definition: fsl_clock.c:1244
void CLOCK_DeinitSysPll(void)
De-initialize the System PLL.
Definition: fsl_clock.c:640
_clock_div
DIV control names for clock div setting.
Definition: fsl_clock.h:784
enum _clock_output2_selection clock_output2_selection_t
The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on...
_clock_osc
OSC 24M sorce select.
Definition: fsl_clock.h:642
enum _clock_name clock_name_t
Clock name used to get clock frequency.
void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config)
Initialize the USB1 PLL.
Definition: fsl_clock.c:652
_clock_root
The enumerator of clock root.
Definition: fsl_clock.h:1344
enum _clock_gate_value clock_gate_value_t
Clock gate value.
uint32_t CLOCK_GetPerClkFreq(void)
Gets the PER clock frequency.
Definition: fsl_clock.c:312
enum _clock_mux clock_mux_t
MUX control names for clock mux setting.
void CLOCK_SetClockOutput1(clock_output1_selection_t selection, clock_output_divider_t divider)
Set the clock source and the divider of the clock output1.
Definition: fsl_clock.c:1366
void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd)
De-initialize the USB1 PLL PFD.
Definition: fsl_clock.c:1231
enum _clock_usb_src clock_usb_src_t
USB clock source definition.
bool enableClkOutput25M
Definition: fsl_clock.h:1250
_clock_pfd
PLL PFD name.
Definition: fsl_clock.h:1279
bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq)
Enable USB HS clock.
Definition: fsl_clock.c:515
uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd)
Get current System PLL PFD output frequency.
Definition: fsl_clock.c:1257
void CLOCK_InitExternalClk(bool bypassXtalOsc)
Initialize the external 24MHz clock.
Definition: fsl_clock.c:189
_clock_output2_selection
The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on...
Definition: fsl_clock.h:1309
uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot)
Gets the frequency of selected clock root.
Definition: fsl_clock.c:444
enum _clock_usb_phy_src clock_usb_phy_src_t
Source of the USB HS PHY.
void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config)
Initialize the USB2 PLL.
Definition: fsl_clock.c:685
enum _clock_root clock_root_t
The enumerator of clock root.
void CLOCK_InitVideoPll(const clock_video_pll_config_t *config)
Initialize the video PLL.
Definition: fsl_clock.c:805
bool CLOCK_IsSysPfdEnabled(clock_pfd_t pfd)
Check if Sys PFD is enabled.
Definition: fsl_clock.c:1193
volatile uint32_t g_rtcXtalFreq
External RTC XTAL (32K OSC) clock frequency.
Definition: fsl_clock.c:61
struct _clock_arm_pll_config clock_arm_pll_config_t
PLL configuration for ARM.
_clock_output_divider
The enumerator of clock output's divider.
Definition: fsl_clock.h:1329
uint32_t CLOCK_GetClockOutClkO2Freq(void)
Get the frequency of clock output2 clock signal.
Definition: fsl_clock.c:1475
void CLOCK_DeinitExternalClk(void)
Deinitialize the external 24MHz clock.
Definition: fsl_clock.c:213
enum _clock_pfd clock_pfd_t
PLL PFD name.
enum _clock_output1_selection clock_output1_selection_t
The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on.
void CLOCK_DeinitUsb2Pll(void)
Deinitialize the USB2 PLL.
Definition: fsl_clock.c:706
_clock_usb_phy_src
Source of the USB HS PHY.
Definition: fsl_clock.h:1181
struct _clock_sys_pll_config clock_sys_pll_config_t
PLL configuration for System.
void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac)
Initialize the USB1 PLL PFD.
Definition: fsl_clock.c:1208
bool enableClkOutput
Definition: fsl_clock.h:1248
struct _clock_enet_pll_config clock_enet_pll_config_t
PLL configuration for ENET.
void CLOCK_InitArmPll(const clock_arm_pll_config_t *config)
Initialize the ARM PLL.
Definition: fsl_clock.c:577
struct _clock_usb_pll_config clock_usb_pll_config_t
PLL configuration for USB.
_clock_pll
PLL name.
Definition: fsl_clock.h:1262
enum _clock_pll clock_pll_t
PLL name.
uint8_t src
Definition: fsl_clock.h:1205
#define CCSR_OFFSET
CCM registers offset.
Definition: fsl_clock.h:60
_clock_div_value
Clock divider value.
Definition: fsl_clock.h:911
void CLOCK_InitRcOsc24M(void)
Initialize the RC oscillator 24MHz clock.
Definition: fsl_clock.c:240
void CLOCK_DeinitUsb1Pll(void)
Deinitialize the USB1 PLL.
Definition: fsl_clock.c:673
uint8_t loopDivider
Definition: fsl_clock.h:1202
_clock_usb_src
USB clock source definition.
Definition: fsl_clock.h:1173
#define CLKPN_FREQ
clock1PN frequency.
Definition: fsl_clock.h:113
bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
Enable USB HS PHY PLL clock.
Definition: fsl_clock.c:1336
uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
Get current PLL output frequency.
Definition: fsl_clock.c:939
void CLOCK_SetClockOutput2(clock_output2_selection_t selection, clock_output_divider_t divider)
Set the clock source and the divider of the clock output2.
Definition: fsl_clock.c:1390
volatile uint32_t g_xtalFreq
External XTAL (24M OSC/SYSOSC) clock frequency.
Definition: fsl_clock.c:59
uint32_t CLOCK_GetClockOutCLKO1Freq(void)
Get the frequency of clock output1 clock signal.
Definition: fsl_clock.c:1414
void CLOCK_SwitchOsc(clock_osc_t osc)
Switch the OSC.
Definition: fsl_clock.c:225
struct _clock_audio_pll_config clock_audio_pll_config_t
PLL configuration for AUDIO and VIDEO.
bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
Enable USB HS PHY PLL clock.
Definition: fsl_clock.c:540
uint32_t CLOCK_GetSemcFreq(void)
Gets the SEMC clock frequency.
Definition: fsl_clock.c:268
uint32_t CLOCK_GetFreq(clock_name_t name)
Gets the clock frequency for a specific clock name.
Definition: fsl_clock.c:341
enum _clock_osc clock_osc_t
OSC 24M sorce select.
_clock_mode_t
System clock mode.
Definition: fsl_clock.h:657
enum _clock_output_divider clock_output_divider_t
The enumerator of clock output's divider.
uint32_t numerator
Definition: fsl_clock.h:1229
uint8_t postDivider
Definition: fsl_clock.h:1228
uint8_t loopDivider
Definition: fsl_clock.h:1227
_clock_output1_selection
The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on.
Definition: fsl_clock.h:1290
uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd)
Get current USB1 PLL PFD output frequency.
Definition: fsl_clock.c:1296
void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config)
Initializes the Audio PLL.
Definition: fsl_clock.c:718
_clock_pll_clk_src
PLL clock source, bypass cloco source also.
Definition: fsl_clock.h:1187
void CLOCK_InitSysPll(const clock_sys_pll_config_t *config)
Initialize the System PLL.
Definition: fsl_clock.c:610
void CLOCK_DeinitVideoPll(void)
De-initialize the Video PLL.
Definition: fsl_clock.c:879
#define CCM_ANALOG_TUPLE(reg, shift)
CCM ANALOG tuple macros to map corresponding registers and bit fields.
Definition: fsl_clock.h:97
enum _clock_div_value clock_div_value_t
Clock divider value.
_clock_mux
MUX control names for clock mux setting.
Definition: fsl_clock.h:672
void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac)
Initialize the System PLL PFD.
Definition: fsl_clock.c:1157
void CLOCK_DeinitArmPll(void)
De-initialize the ARM PLL.
Definition: fsl_clock.c:598
bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
Enable USB HS clock.
Definition: fsl_clock.c:488
_clock_gate_value
Clock gate value.
Definition: fsl_clock.h:649
void CLOCK_DeinitAudioPll(void)
De-initialize the Audio PLL.
Definition: fsl_clock.c:793
uint32_t CLOCK_GetIpgFreq(void)
Gets the IPG clock frequency.
Definition: fsl_clock.c:302
void CLOCK_DisableUsbhs0PhyPllClock(void)
Disable USB HS PHY PLL clock.
Definition: fsl_clock.c:564
uint8_t src
Definition: fsl_clock.h:1256
void CLOCK_DeinitRcOsc24M(void)
Power down the RCOSC 24M clock.
Definition: fsl_clock.c:248
void CLOCK_DisableUsbhs1PhyPllClock(void)
Disable USB HS PHY PLL clock.
Definition: fsl_clock.c:1354
@ kCLOCK_Lpi2c4
Definition: fsl_clock.h:633
@ kCLOCK_Pwm3
Definition: fsl_clock.h:595
@ kCLOCK_Lcd
Definition: fsl_clock.h:563
@ kCLOCK_Lpspi3
Definition: fsl_clock.h:533
@ kCLOCK_Csi
Definition: fsl_clock.h:550
@ kCLOCK_Aips_tz4
Definition: fsl_clock.h:609
@ kCLOCK_Lpuart3
Definition: fsl_clock.h:519
@ kCLOCK_Rom
Definition: fsl_clock.h:603
@ kCLOCK_Timer3
Definition: fsl_clock.h:636
@ kCLOCK_Ocram
Definition: fsl_clock.h:581
@ kCLOCK_Pwm2
Definition: fsl_clock.h:594
@ kCLOCK_Usdhc2
Definition: fsl_clock.h:623
@ kCLOCK_Trng
Definition: fsl_clock.h:627
@ kCLOCK_Lpi2c1
Definition: fsl_clock.h:552
@ kCLOCK_Lpi2c3
Definition: fsl_clock.h:554
@ kCLOCK_Gpio2
Definition: fsl_clock.h:528
@ kCLOCK_LcdPixel
Definition: fsl_clock.h:572
@ kCLOCK_Pwm4
Definition: fsl_clock.h:596
@ kCLOCK_Lpspi4
Definition: fsl_clock.h:534
@ kCLOCK_IomuxcSnvsGpr
Definition: fsl_clock.h:582
@ kCLOCK_Can2
Definition: fsl_clock.h:522
@ kCLOCK_Aips_tz1
Definition: fsl_clock.h:513
@ kCLOCK_Mqs
Definition: fsl_clock.h:515
@ kCLOCK_Can2S
Definition: fsl_clock.h:523
@ kCLOCK_Ewm0
Definition: fsl_clock.h:574
@ kCLOCK_Gpio4
Definition: fsl_clock.h:573
@ kCLOCK_Ipmux4
Definition: fsl_clock.h:625
@ kCLOCK_Iomuxc
Definition: fsl_clock.h:586
@ kCLOCK_IomuxcGpr
Definition: fsl_clock.h:587
@ kCLOCK_Lpuart2
Definition: fsl_clock.h:527
@ kCLOCK_Enc3
Definition: fsl_clock.h:599
@ kCLOCK_Flexio1
Definition: fsl_clock.h:604
@ kCLOCK_Bee
Definition: fsl_clock.h:588
@ kCLOCK_OcramExsc
Definition: fsl_clock.h:549
@ kCLOCK_Enet
Definition: fsl_clock.h:536
@ kCLOCK_Tsc
Definition: fsl_clock.h:590
@ kCLOCK_Usdhc1
Definition: fsl_clock.h:622
@ kCLOCK_Acmp3
Definition: fsl_clock.h:579
@ kCLOCK_Flexio2
Definition: fsl_clock.h:567
@ kCLOCK_Adc1
Definition: fsl_clock.h:539
@ kCLOCK_Anadig
Definition: fsl_clock.h:632
@ kCLOCK_Aoi2
Definition: fsl_clock.h:538
@ kCLOCK_Timer2
Definition: fsl_clock.h:635
@ kCLOCK_SimPer
Definition: fsl_clock.h:631
@ kCLOCK_Ipmux2
Definition: fsl_clock.h:558
@ kCLOCK_Acmp4
Definition: fsl_clock.h:580
@ kCLOCK_Gpio5
Definition: fsl_clock.h:546
@ kCLOCK_Lpuart7
Definition: fsl_clock.h:616
@ kCLOCK_Pwm1
Definition: fsl_clock.h:593
@ kCLOCK_Pit
Definition: fsl_clock.h:537
@ kCLOCK_Dcdc
Definition: fsl_clock.h:624
@ kCLOCK_Acmp2
Definition: fsl_clock.h:578
@ kCLOCK_Gpt1
Definition: fsl_clock.h:541
@ kCLOCK_SemcExsc
Definition: fsl_clock.h:540
@ kCLOCK_Gpio1
Definition: fsl_clock.h:544
@ kCLOCK_Gpio3
Definition: fsl_clock.h:562
@ kCLOCK_Enc2
Definition: fsl_clock.h:598
@ kCLOCK_Adc2
Definition: fsl_clock.h:535
@ kCLOCK_Gpt1S
Definition: fsl_clock.h:542
@ kCLOCK_Aips_tz3
Definition: fsl_clock.h:630
@ kCLOCK_Timer1
Definition: fsl_clock.h:634
@ kCLOCK_Dcp
Definition: fsl_clock.h:518
@ kCLOCK_FlexSpiExsc
Definition: fsl_clock.h:516
@ kCLOCK_Lpuart1
Definition: fsl_clock.h:615
@ kCLOCK_Sim_M_Main
Definition: fsl_clock.h:517
@ kCLOCK_SimM7
Definition: fsl_clock.h:589
@ kCLOCK_Acmp1
Definition: fsl_clock.h:577
@ kCLOCK_Pxp
Definition: fsl_clock.h:564
@ kCLOCK_Sai1
Definition: fsl_clock.h:612
@ kCLOCK_Timer4
Definition: fsl_clock.h:629
@ kCLOCK_FlexRam
Definition: fsl_clock.h:576
@ kCLOCK_Aoi1
Definition: fsl_clock.h:571
@ kCLOCK_Dma
Definition: fsl_clock.h:606
@ kCLOCK_Enc1
Definition: fsl_clock.h:597
@ kCLOCK_Kpp
Definition: fsl_clock.h:607
@ kCLOCK_Gpt2S
Definition: fsl_clock.h:526
@ kCLOCK_FlexSpi
Definition: fsl_clock.h:626
@ kCLOCK_SnvsHp
Definition: fsl_clock.h:617
@ kCLOCK_Xbar3
Definition: fsl_clock.h:556
@ kCLOCK_Gpt2
Definition: fsl_clock.h:525
@ kCLOCK_Lpi2c2
Definition: fsl_clock.h:553
@ kCLOCK_IomuxcSnvs
Definition: fsl_clock.h:551
@ kCLOCK_Ipmux1
Definition: fsl_clock.h:557
@ kCLOCK_Wdog2
Definition: fsl_clock.h:608
@ kCLOCK_Wdog3
Definition: fsl_clock.h:605
@ kCLOCK_Xbar1
Definition: fsl_clock.h:560
@ kCLOCK_Csu
Definition: fsl_clock.h:545
@ kCLOCK_Lpspi1
Definition: fsl_clock.h:531
@ kCLOCK_SimMain
Definition: fsl_clock.h:611
@ kCLOCK_Sai2
Definition: fsl_clock.h:613
@ kCLOCK_Aips_tz2
Definition: fsl_clock.h:514
@ kCLOCK_UsbOh3
Definition: fsl_clock.h:621
@ kCLOCK_Xbar2
Definition: fsl_clock.h:561
@ kCLOCK_Ipmux3
Definition: fsl_clock.h:559
@ kCLOCK_Spdif
Definition: fsl_clock.h:610
@ kCLOCK_SnvsLp
Definition: fsl_clock.h:618
@ kCLOCK_Lpspi2
Definition: fsl_clock.h:532
@ kCLOCK_Lpuart4
Definition: fsl_clock.h:543
@ kCLOCK_Sai3
Definition: fsl_clock.h:614
@ kCLOCK_Wdog1
Definition: fsl_clock.h:575
@ kCLOCK_SimEms
Definition: fsl_clock.h:592
@ kCLOCK_Sim_m7_clk_r
Definition: fsl_clock.h:585
@ kCLOCK_Lpuart6
Definition: fsl_clock.h:570
@ kCLOCK_Lpuart8
Definition: fsl_clock.h:628
@ kCLOCK_Semc
Definition: fsl_clock.h:569
@ kCLOCK_Trace
Definition: fsl_clock.h:524
@ kCLOCK_SimM
Definition: fsl_clock.h:591
@ kCLOCK_Can1S
Definition: fsl_clock.h:521
@ kCLOCK_Ocotp
Definition: fsl_clock.h:555
@ kCLOCK_Lpuart5
Definition: fsl_clock.h:568
@ kCLOCK_Can1
Definition: fsl_clock.h:520
@ kCLOCK_Enc4
Definition: fsl_clock.h:600
@ kCLOCK_OscClk
Definition: fsl_clock.h:471
@ kCLOCK_SysPllClk
Definition: fsl_clock.h:488
@ kCLOCK_ArmPllClk
Definition: fsl_clock.h:474
@ kCLOCK_CpuClk
Definition: fsl_clock.h:465
@ kCLOCK_Usb1Sw120MClk
Definition: fsl_clock.h:482
@ kCLOCK_IpgClk
Definition: fsl_clock.h:468
@ kCLOCK_Usb2PllClk
Definition: fsl_clock.h:486
@ kCLOCK_Usb1PllPfd1Clk
Definition: fsl_clock.h:478
@ kCLOCK_AudioPllClk
Definition: fsl_clock.h:497
@ kCLOCK_RtcClk
Definition: fsl_clock.h:472
@ kCLOCK_Usb1PllClk
Definition: fsl_clock.h:476
@ kCLOCK_Usb1PllPfd3Clk
Definition: fsl_clock.h:480
@ kCLOCK_EnetPll0Clk
Definition: fsl_clock.h:494
@ kCLOCK_Usb1Sw60MClk
Definition: fsl_clock.h:483
@ kCLOCK_Usb1Sw80MClk
Definition: fsl_clock.h:484
@ kCLOCK_Usb1PllPfd0Clk
Definition: fsl_clock.h:477
@ kCLOCK_SysPllPfd3Clk
Definition: fsl_clock.h:492
@ kCLOCK_SysPllPfd2Clk
Definition: fsl_clock.h:491
@ kCLOCK_PerClk
Definition: fsl_clock.h:469
@ kCLOCK_SysPllPfd0Clk
Definition: fsl_clock.h:489
@ kCLOCK_NoneName
Definition: fsl_clock.h:499
@ kCLOCK_VideoPllClk
Definition: fsl_clock.h:498
@ kCLOCK_SysPllPfd1Clk
Definition: fsl_clock.h:490
@ kCLOCK_Usb1PllPfd2Clk
Definition: fsl_clock.h:479
@ kCLOCK_Usb1SwClk
Definition: fsl_clock.h:481
@ kCLOCK_EnetPll1Clk
Definition: fsl_clock.h:495
@ kCLOCK_SemcClk
Definition: fsl_clock.h:467
@ kCLOCK_AhbClk
Definition: fsl_clock.h:466
@ kCLOCK_UartDiv
Definition: fsl_clock.h:836
@ kCLOCK_Flexio1Div
Definition: fsl_clock.h:887
@ kCLOCK_PerclkDiv
Definition: fsl_clock.h:814
@ kCLOCK_AhbDiv
Definition: fsl_clock.h:798
@ kCLOCK_Lpi2cDiv
Definition: fsl_clock.h:892
@ kCLOCK_LpspiDiv
Definition: fsl_clock.h:805
@ kCLOCK_Sai3PreDiv
Definition: fsl_clock.h:845
@ kCLOCK_Sai3Div
Definition: fsl_clock.h:849
@ kCLOCK_IpgDiv
Definition: fsl_clock.h:802
@ kCLOCK_TraceDiv
Definition: fsl_clock.h:824
@ kCLOCK_SemcDiv
Definition: fsl_clock.h:794
@ kCLOCK_Spdif0PreDiv
Definition: fsl_clock.h:875
@ kCLOCK_Sai2PreDiv
Definition: fsl_clock.h:866
@ kCLOCK_Sai1Div
Definition: fsl_clock.h:861
@ kCLOCK_LcdifDiv
Definition: fsl_clock.h:807
@ kCLOCK_Spdif0Div
Definition: fsl_clock.h:879
@ kCLOCK_LcdifPreDiv
Definition: fsl_clock.h:896
@ kCLOCK_ArmDiv
Definition: fsl_clock.h:785
@ kCLOCK_Sai2Div
Definition: fsl_clock.h:870
@ kCLOCK_Usdhc2Div
Definition: fsl_clock.h:828
@ kCLOCK_Flexio2PreDiv
Definition: fsl_clock.h:853
@ kCLOCK_Flexio1PreDiv
Definition: fsl_clock.h:883
@ kCLOCK_Usdhc1Div
Definition: fsl_clock.h:832
@ kCLOCK_NonePreDiv
Definition: fsl_clock.h:904
@ kCLOCK_PeriphClk2Div
Definition: fsl_clock.h:790
@ kCLOCK_Flexio2Div
Definition: fsl_clock.h:841
@ kCLOCK_CsiDiv
Definition: fsl_clock.h:901
@ kCLOCK_FlexspiDiv
Definition: fsl_clock.h:810
@ kCLOCK_Sai1PreDiv
Definition: fsl_clock.h:857
@ kCLOCK_CanDiv
Definition: fsl_clock.h:819
@ kCLOCK_XtalOsc
Definition: fsl_clock.h:644
@ kCLOCK_RcOsc
Definition: fsl_clock.h:643
@ kCLOCK_LpspiClkRoot
Definition: fsl_clock.h:1349
@ kCLOCK_Lpi2cClkRoot
Definition: fsl_clock.h:1354
@ kCLOCK_Usdhc2ClkRoot
Definition: fsl_clock.h:1346
@ kCLOCK_CanClkRoot
Definition: fsl_clock.h:1355
@ kCLOCK_Usdhc1ClkRoot
Definition: fsl_clock.h:1345
@ kCLOCK_Sai2ClkRoot
Definition: fsl_clock.h:1352
@ kCLOCK_Sai3ClkRoot
Definition: fsl_clock.h:1353
@ kCLOCK_TraceClkRoot
Definition: fsl_clock.h:1350
@ kCLOCK_Flexio2ClkRoot
Definition: fsl_clock.h:1360
@ kCLOCK_LcdifClkRoot
Definition: fsl_clock.h:1357
@ kCLOCK_SpdifClkRoot
Definition: fsl_clock.h:1358
@ kCLOCK_Sai1ClkRoot
Definition: fsl_clock.h:1351
@ kCLOCK_UartClkRoot
Definition: fsl_clock.h:1356
@ kCLOCK_FlexspiClkRoot
Definition: fsl_clock.h:1347
@ kCLOCK_Flexio1ClkRoot
Definition: fsl_clock.h:1359
@ kCLOCK_CsiClkRoot
Definition: fsl_clock.h:1348
@ kCLOCK_Pfd3
Definition: fsl_clock.h:1283
@ kCLOCK_Pfd2
Definition: fsl_clock.h:1282
@ kCLOCK_Pfd0
Definition: fsl_clock.h:1280
@ kCLOCK_Pfd1
Definition: fsl_clock.h:1281
@ kCLOCK_OutputLpi2cClk
Definition: fsl_clock.h:1311
@ kCLOCK_OutputSai3Clk
Definition: fsl_clock.h:1317
@ kCLOCK_OutputUsdhc1Clk
Definition: fsl_clock.h:1310
@ kCLOCK_DisableClockOutput2
Definition: fsl_clock.h:1322
@ kCLOCK_OutputCsiClk
Definition: fsl_clock.h:1312
@ kCLOCK_OutputUsdhc2Clk
Definition: fsl_clock.h:1314
@ kCLOCK_OutputSai1Clk
Definition: fsl_clock.h:1315
@ kCLOCK_OutputCanClk
Definition: fsl_clock.h:1318
@ kCLOCK_OutputUartClk
Definition: fsl_clock.h:1320
@ kCLOCK_OutputFlexspiClk
Definition: fsl_clock.h:1319
@ kCLOCK_OutputSai2Clk
Definition: fsl_clock.h:1316
@ kCLOCK_OutputSpdif0Clk
Definition: fsl_clock.h:1321
@ kCLOCK_OutputOscClk
Definition: fsl_clock.h:1313
@ kCLOCK_DivideBy5
Definition: fsl_clock.h:1334
@ kCLOCK_DivideBy3
Definition: fsl_clock.h:1332
@ kCLOCK_DivideBy1
Definition: fsl_clock.h:1330
@ kCLOCK_DivideBy4
Definition: fsl_clock.h:1333
@ kCLOCK_DivideBy8
Definition: fsl_clock.h:1337
@ kCLOCK_DivideBy7
Definition: fsl_clock.h:1336
@ kCLOCK_DivideBy6
Definition: fsl_clock.h:1335
@ kCLOCK_DivideBy2
Definition: fsl_clock.h:1331
@ kCLOCK_Usbphy480M
Definition: fsl_clock.h:1182
@ kCLOCK_PllVideo
Definition: fsl_clock.h:1267
@ kCLOCK_PllUsb1
Definition: fsl_clock.h:1265
@ kCLOCK_PllEnet
Definition: fsl_clock.h:1269
@ kCLOCK_PllAudio
Definition: fsl_clock.h:1266
@ kCLOCK_PllUsb2
Definition: fsl_clock.h:1273
@ kCLOCK_PllSys
Definition: fsl_clock.h:1264
@ kCLOCK_PllArm
Definition: fsl_clock.h:1263
@ kCLOCK_PllEnet25M
Definition: fsl_clock.h:1271
@ kCLOCK_MiscDivBy46
Definition: fsl_clock.h:1150
@ kCLOCK_TraceDivBy2
Definition: fsl_clock.h:981
@ kCLOCK_Spdif0PreDivBy1
Definition: fsl_clock.h:1048
@ kCLOCK_Sai3PreDivBy4
Definition: fsl_clock.h:1015
@ kCLOCK_Flexio1DivBy8
Definition: fsl_clock.h:1082
@ kCLOCK_SemcDivBy5
Definition: fsl_clock.h:934
@ kCLOCK_Flexio2DivBy2
Definition: fsl_clock.h:1004
@ kCLOCK_ArmDivBy7
Definition: fsl_clock.h:918
@ kCLOCK_Usdhc1DivBy1
Definition: fsl_clock.h:994
@ kCLOCK_CsiDivBy6
Definition: fsl_clock.h:1098
@ kCLOCK_Sai3PreDivBy3
Definition: fsl_clock.h:1014
@ kCLOCK_Sai1PreDivBy6
Definition: fsl_clock.h:1035
@ kCLOCK_AhbDivBy3
Definition: fsl_clock.h:941
@ kCLOCK_Sai2PreDivBy4
Definition: fsl_clock.h:1042
@ kCLOCK_LcdifPreDivBy7
Definition: fsl_clock.h:1090
@ kCLOCK_MiscDivBy18
Definition: fsl_clock.h:1122
@ kCLOCK_LpspiDivBy2
Definition: fsl_clock.h:954
@ kCLOCK_AhbDivBy4
Definition: fsl_clock.h:942
@ kCLOCK_FlexspiDivBy1
Definition: fsl_clock.h:971
@ kCLOCK_MiscDivBy30
Definition: fsl_clock.h:1134
@ kCLOCK_Usdhc2DivBy1
Definition: fsl_clock.h:985
@ kCLOCK_MiscDivBy24
Definition: fsl_clock.h:1128
@ kCLOCK_IpgDivBy3
Definition: fsl_clock.h:950
@ kCLOCK_PeriphClk2DivBy2
Definition: fsl_clock.h:922
@ kCLOCK_MiscDivBy33
Definition: fsl_clock.h:1137
@ kCLOCK_Flexio2PreDivBy4
Definition: fsl_clock.h:1024
@ kCLOCK_CsiDivBy7
Definition: fsl_clock.h:1099
@ kCLOCK_ArmDivBy6
Definition: fsl_clock.h:917
@ kCLOCK_LpspiDivBy4
Definition: fsl_clock.h:956
@ kCLOCK_PeriphClk2DivBy3
Definition: fsl_clock.h:923
@ kCLOCK_Usdhc2DivBy7
Definition: fsl_clock.h:991
@ kCLOCK_Usdhc2DivBy4
Definition: fsl_clock.h:988
@ kCLOCK_AhbDivBy5
Definition: fsl_clock.h:943
@ kCLOCK_Sai3PreDivBy2
Definition: fsl_clock.h:1013
@ kCLOCK_MiscDivBy48
Definition: fsl_clock.h:1152
@ kCLOCK_Spdif0PreDivBy7
Definition: fsl_clock.h:1054
@ kCLOCK_MiscDivBy16
Definition: fsl_clock.h:1120
@ kCLOCK_Spdif0DivBy2
Definition: fsl_clock.h:1058
@ kCLOCK_PeriphClk2DivBy1
Definition: fsl_clock.h:921
@ kCLOCK_Flexio1DivBy7
Definition: fsl_clock.h:1081
@ kCLOCK_PeriphClk2DivBy7
Definition: fsl_clock.h:927
@ kCLOCK_Flexio1PreDivBy2
Definition: fsl_clock.h:1067
@ kCLOCK_PeriphClk2DivBy8
Definition: fsl_clock.h:928
@ kCLOCK_MiscDivBy38
Definition: fsl_clock.h:1142
@ kCLOCK_MiscDivBy12
Definition: fsl_clock.h:1116
@ kCLOCK_MiscDivBy53
Definition: fsl_clock.h:1157
@ kCLOCK_Usdhc1DivBy8
Definition: fsl_clock.h:1001
@ kCLOCK_Flexio1PreDivBy1
Definition: fsl_clock.h:1066
@ kCLOCK_Spdif0DivBy5
Definition: fsl_clock.h:1061
@ kCLOCK_FlexspiDivBy8
Definition: fsl_clock.h:978
@ kCLOCK_MiscDivBy40
Definition: fsl_clock.h:1144
@ kCLOCK_LpspiDivBy5
Definition: fsl_clock.h:957
@ kCLOCK_SemcDivBy1
Definition: fsl_clock.h:930
@ kCLOCK_MiscDivBy20
Definition: fsl_clock.h:1124
@ kCLOCK_LcdifPreDivBy4
Definition: fsl_clock.h:1087
@ kCLOCK_MiscDivBy19
Definition: fsl_clock.h:1123
@ kCLOCK_CsiDivBy4
Definition: fsl_clock.h:1096
@ kCLOCK_Spdif0DivBy6
Definition: fsl_clock.h:1062
@ kCLOCK_Flexio1DivBy5
Definition: fsl_clock.h:1079
@ kCLOCK_MiscDivBy43
Definition: fsl_clock.h:1147
@ kCLOCK_Sai2PreDivBy6
Definition: fsl_clock.h:1044
@ kCLOCK_MiscDivBy57
Definition: fsl_clock.h:1161
@ kCLOCK_Flexio2DivBy1
Definition: fsl_clock.h:1003
@ kCLOCK_MiscDivBy5
Definition: fsl_clock.h:1109
@ kCLOCK_Sai1PreDivBy4
Definition: fsl_clock.h:1033
@ kCLOCK_MiscDivBy36
Definition: fsl_clock.h:1140
@ kCLOCK_PeriphClk2DivBy6
Definition: fsl_clock.h:926
@ kCLOCK_IpgDivBy2
Definition: fsl_clock.h:949
@ kCLOCK_FlexspiDivBy7
Definition: fsl_clock.h:977
@ kCLOCK_LpspiDivBy3
Definition: fsl_clock.h:955
@ kCLOCK_Flexio2DivBy6
Definition: fsl_clock.h:1008
@ kCLOCK_MiscDivBy47
Definition: fsl_clock.h:1151
@ kCLOCK_FlexspiDivBy2
Definition: fsl_clock.h:972
@ kCLOCK_MiscDivBy29
Definition: fsl_clock.h:1133
@ kCLOCK_CsiDivBy2
Definition: fsl_clock.h:1094
@ kCLOCK_MiscDivBy54
Definition: fsl_clock.h:1158
@ kCLOCK_Sai2PreDivBy1
Definition: fsl_clock.h:1039
@ kCLOCK_Sai3PreDivBy1
Definition: fsl_clock.h:1012
@ kCLOCK_LcdifDivBy2
Definition: fsl_clock.h:963
@ kCLOCK_TraceDivBy3
Definition: fsl_clock.h:982
@ kCLOCK_Usdhc1DivBy7
Definition: fsl_clock.h:1000
@ kCLOCK_SemcDivBy8
Definition: fsl_clock.h:937
@ kCLOCK_MiscDivBy27
Definition: fsl_clock.h:1131
@ kCLOCK_ArmDivBy5
Definition: fsl_clock.h:916
@ kCLOCK_Flexio1PreDivBy6
Definition: fsl_clock.h:1071
@ kCLOCK_Usdhc2DivBy8
Definition: fsl_clock.h:992
@ kCLOCK_MiscDivBy51
Definition: fsl_clock.h:1155
@ kCLOCK_Flexio2PreDivBy2
Definition: fsl_clock.h:1022
@ kCLOCK_PeriphClk2DivBy4
Definition: fsl_clock.h:924
@ kCLOCK_AhbDivBy8
Definition: fsl_clock.h:946
@ kCLOCK_Flexio1PreDivBy5
Definition: fsl_clock.h:1070
@ kCLOCK_Usdhc1DivBy5
Definition: fsl_clock.h:998
@ kCLOCK_Spdif0DivBy1
Definition: fsl_clock.h:1057
@ kCLOCK_MiscDivBy14
Definition: fsl_clock.h:1118
@ kCLOCK_Flexio2PreDivBy1
Definition: fsl_clock.h:1021
@ kCLOCK_Usdhc2DivBy5
Definition: fsl_clock.h:989
@ kCLOCK_Flexio1DivBy1
Definition: fsl_clock.h:1075
@ kCLOCK_MiscDivBy3
Definition: fsl_clock.h:1107
@ kCLOCK_AhbDivBy7
Definition: fsl_clock.h:945
@ kCLOCK_MiscDivBy49
Definition: fsl_clock.h:1153
@ kCLOCK_Usdhc1DivBy4
Definition: fsl_clock.h:997
@ kCLOCK_Spdif0DivBy3
Definition: fsl_clock.h:1059
@ kCLOCK_MiscDivBy32
Definition: fsl_clock.h:1136
@ kCLOCK_FlexspiDivBy4
Definition: fsl_clock.h:974
@ kCLOCK_LcdifPreDivBy5
Definition: fsl_clock.h:1088
@ kCLOCK_Flexio1DivBy2
Definition: fsl_clock.h:1076
@ kCLOCK_SemcDivBy2
Definition: fsl_clock.h:931
@ kCLOCK_MiscDivBy60
Definition: fsl_clock.h:1164
@ kCLOCK_Flexio2DivBy4
Definition: fsl_clock.h:1006
@ kCLOCK_MiscDivBy41
Definition: fsl_clock.h:1145
@ kCLOCK_FlexspiDivBy5
Definition: fsl_clock.h:975
@ kCLOCK_MiscDivBy34
Definition: fsl_clock.h:1138
@ kCLOCK_MiscDivBy58
Definition: fsl_clock.h:1162
@ kCLOCK_Sai1PreDivBy8
Definition: fsl_clock.h:1037
@ kCLOCK_Sai3PreDivBy5
Definition: fsl_clock.h:1016
@ kCLOCK_LcdifPreDivBy6
Definition: fsl_clock.h:1089
@ kCLOCK_LcdifDivBy8
Definition: fsl_clock.h:969
@ kCLOCK_MiscDivBy63
Definition: fsl_clock.h:1167
@ kCLOCK_Flexio1DivBy6
Definition: fsl_clock.h:1080
@ kCLOCK_Flexio1PreDivBy7
Definition: fsl_clock.h:1072
@ kCLOCK_LcdifDivBy3
Definition: fsl_clock.h:964
@ kCLOCK_Spdif0DivBy8
Definition: fsl_clock.h:1064
@ kCLOCK_MiscDivBy52
Definition: fsl_clock.h:1156
@ kCLOCK_Sai3PreDivBy7
Definition: fsl_clock.h:1018
@ kCLOCK_MiscDivBy17
Definition: fsl_clock.h:1121
@ kCLOCK_MiscDivBy50
Definition: fsl_clock.h:1154
@ kCLOCK_MiscDivBy7
Definition: fsl_clock.h:1111
@ kCLOCK_LcdifPreDivBy2
Definition: fsl_clock.h:1085
@ kCLOCK_ArmDivBy4
Definition: fsl_clock.h:915
@ kCLOCK_Spdif0PreDivBy8
Definition: fsl_clock.h:1055
@ kCLOCK_Usdhc1DivBy2
Definition: fsl_clock.h:995
@ kCLOCK_MiscDivBy35
Definition: fsl_clock.h:1139
@ kCLOCK_LpspiDivBy1
Definition: fsl_clock.h:953
@ kCLOCK_MiscDivBy39
Definition: fsl_clock.h:1143
@ kCLOCK_LcdifPreDivBy3
Definition: fsl_clock.h:1086
@ kCLOCK_SemcDivBy7
Definition: fsl_clock.h:936
@ kCLOCK_MiscDivBy6
Definition: fsl_clock.h:1110
@ kCLOCK_Spdif0DivBy4
Definition: fsl_clock.h:1060
@ kCLOCK_LcdifDivBy6
Definition: fsl_clock.h:967
@ kCLOCK_Usdhc2DivBy3
Definition: fsl_clock.h:987
@ kCLOCK_SemcDivBy4
Definition: fsl_clock.h:933
@ kCLOCK_Sai1PreDivBy7
Definition: fsl_clock.h:1036
@ kCLOCK_MiscDivBy61
Definition: fsl_clock.h:1165
@ kCLOCK_Flexio2DivBy5
Definition: fsl_clock.h:1007
@ kCLOCK_Flexio1DivBy3
Definition: fsl_clock.h:1077
@ kCLOCK_TraceDivBy1
Definition: fsl_clock.h:980
@ kCLOCK_Usdhc2DivBy6
Definition: fsl_clock.h:990
@ kCLOCK_FlexspiDivBy6
Definition: fsl_clock.h:976
@ kCLOCK_Sai3PreDivBy6
Definition: fsl_clock.h:1017
@ kCLOCK_Flexio1PreDivBy8
Definition: fsl_clock.h:1073
@ kCLOCK_MiscDivBy15
Definition: fsl_clock.h:1119
@ kCLOCK_Sai1PreDivBy5
Definition: fsl_clock.h:1034
@ kCLOCK_Flexio2PreDivBy5
Definition: fsl_clock.h:1025
@ kCLOCK_MiscDivBy62
Definition: fsl_clock.h:1166
@ kCLOCK_FlexspiDivBy3
Definition: fsl_clock.h:973
@ kCLOCK_Spdif0PreDivBy6
Definition: fsl_clock.h:1053
@ kCLOCK_MiscDivBy31
Definition: fsl_clock.h:1135
@ kCLOCK_Flexio2PreDivBy3
Definition: fsl_clock.h:1023
@ kCLOCK_CsiDivBy3
Definition: fsl_clock.h:1095
@ kCLOCK_MiscDivBy55
Definition: fsl_clock.h:1159
@ kCLOCK_Spdif0DivBy7
Definition: fsl_clock.h:1063
@ kCLOCK_Flexio2DivBy3
Definition: fsl_clock.h:1005
@ kCLOCK_CsiDivBy8
Definition: fsl_clock.h:1100
@ kCLOCK_MiscDivBy11
Definition: fsl_clock.h:1115
@ kCLOCK_Usdhc2DivBy2
Definition: fsl_clock.h:986
@ kCLOCK_Sai3PreDivBy8
Definition: fsl_clock.h:1019
@ kCLOCK_MiscDivBy2
Definition: fsl_clock.h:1106
@ kCLOCK_Sai2PreDivBy7
Definition: fsl_clock.h:1045
@ kCLOCK_MiscDivBy28
Definition: fsl_clock.h:1132
@ kCLOCK_Flexio2PreDivBy7
Definition: fsl_clock.h:1027
@ kCLOCK_MiscDivBy25
Definition: fsl_clock.h:1129
@ kCLOCK_IpgDivBy4
Definition: fsl_clock.h:951
@ kCLOCK_ArmDivBy8
Definition: fsl_clock.h:919
@ kCLOCK_Spdif0PreDivBy5
Definition: fsl_clock.h:1052
@ kCLOCK_LpspiDivBy7
Definition: fsl_clock.h:959
@ kCLOCK_SemcDivBy3
Definition: fsl_clock.h:932
@ kCLOCK_Flexio2PreDivBy6
Definition: fsl_clock.h:1026
@ kCLOCK_AhbDivBy2
Definition: fsl_clock.h:940
@ kCLOCK_Spdif0PreDivBy3
Definition: fsl_clock.h:1050
@ kCLOCK_MiscDivBy44
Definition: fsl_clock.h:1148
@ kCLOCK_PeriphClk2DivBy5
Definition: fsl_clock.h:925
@ kCLOCK_MiscDivBy8
Definition: fsl_clock.h:1112
@ kCLOCK_Flexio1PreDivBy3
Definition: fsl_clock.h:1068
@ kCLOCK_MiscDivBy22
Definition: fsl_clock.h:1126
@ kCLOCK_Sai1PreDivBy1
Definition: fsl_clock.h:1030
@ kCLOCK_Sai2PreDivBy5
Definition: fsl_clock.h:1043
@ kCLOCK_IpgDivBy1
Definition: fsl_clock.h:948
@ kCLOCK_CsiDivBy1
Definition: fsl_clock.h:1093
@ kCLOCK_Spdif0PreDivBy4
Definition: fsl_clock.h:1051
@ kCLOCK_ArmDivBy1
Definition: fsl_clock.h:912
@ kCLOCK_MiscDivBy45
Definition: fsl_clock.h:1149
@ kCLOCK_MiscDivBy23
Definition: fsl_clock.h:1127
@ kCLOCK_Flexio1DivBy4
Definition: fsl_clock.h:1078
@ kCLOCK_Usdhc1DivBy3
Definition: fsl_clock.h:996
@ kCLOCK_LcdifDivBy1
Definition: fsl_clock.h:962
@ kCLOCK_MiscDivBy10
Definition: fsl_clock.h:1114
@ kCLOCK_ArmDivBy2
Definition: fsl_clock.h:913
@ kCLOCK_MiscDivBy21
Definition: fsl_clock.h:1125
@ kCLOCK_Usdhc1DivBy6
Definition: fsl_clock.h:999
@ kCLOCK_Flexio1PreDivBy4
Definition: fsl_clock.h:1069
@ kCLOCK_AhbDivBy6
Definition: fsl_clock.h:944
@ kCLOCK_MiscDivBy42
Definition: fsl_clock.h:1146
@ kCLOCK_AhbDivBy1
Definition: fsl_clock.h:939
@ kCLOCK_Flexio2DivBy7
Definition: fsl_clock.h:1009
@ kCLOCK_MiscDivBy64
Definition: fsl_clock.h:1168
@ kCLOCK_MiscDivBy13
Definition: fsl_clock.h:1117
@ kCLOCK_CsiDivBy5
Definition: fsl_clock.h:1097
@ kCLOCK_TraceDivBy4
Definition: fsl_clock.h:983
@ kCLOCK_LpspiDivBy8
Definition: fsl_clock.h:960
@ kCLOCK_MiscDivBy9
Definition: fsl_clock.h:1113
@ kCLOCK_LcdifPreDivBy1
Definition: fsl_clock.h:1084
@ kCLOCK_LcdifDivBy5
Definition: fsl_clock.h:966
@ kCLOCK_Spdif0PreDivBy2
Definition: fsl_clock.h:1049
@ kCLOCK_Sai1PreDivBy2
Definition: fsl_clock.h:1031
@ kCLOCK_Sai2PreDivBy2
Definition: fsl_clock.h:1040
@ kCLOCK_LcdifPreDivBy8
Definition: fsl_clock.h:1091
@ kCLOCK_MiscDivBy59
Definition: fsl_clock.h:1163
@ kCLOCK_ArmDivBy3
Definition: fsl_clock.h:914
@ kCLOCK_MiscDivBy4
Definition: fsl_clock.h:1108
@ kCLOCK_Sai2PreDivBy3
Definition: fsl_clock.h:1041
@ kCLOCK_Sai1PreDivBy3
Definition: fsl_clock.h:1032
@ kCLOCK_Flexio2DivBy8
Definition: fsl_clock.h:1010
@ kCLOCK_MiscDivBy56
Definition: fsl_clock.h:1160
@ kCLOCK_Sai2PreDivBy8
Definition: fsl_clock.h:1046
@ kCLOCK_SemcDivBy6
Definition: fsl_clock.h:935
@ kCLOCK_LcdifDivBy7
Definition: fsl_clock.h:968
@ kCLOCK_Flexio2PreDivBy8
Definition: fsl_clock.h:1028
@ kCLOCK_LcdifDivBy4
Definition: fsl_clock.h:965
@ kCLOCK_MiscDivBy37
Definition: fsl_clock.h:1141
@ kCLOCK_MiscDivBy26
Definition: fsl_clock.h:1130
@ kCLOCK_LpspiDivBy6
Definition: fsl_clock.h:958
@ kCLOCK_MiscDivBy1
Definition: fsl_clock.h:1105
@ kCLOCK_UsbSrcUnused
Definition: fsl_clock.h:1175
@ kCLOCK_Usb480M
Definition: fsl_clock.h:1174
@ kCLOCK_ModeWait
Definition: fsl_clock.h:659
@ kCLOCK_ModeStop
Definition: fsl_clock.h:660
@ kCLOCK_ModeRun
Definition: fsl_clock.h:658
@ kCLOCK_OutputPerClk
Definition: fsl_clock.h:1298
@ kCLOCK_OutputCkilSyncClk
Definition: fsl_clock.h:1299
@ kCLOCK_OutputPll4MainClk
Definition: fsl_clock.h:1300
@ kCLOCK_OutputPllVideo
Definition: fsl_clock.h:1293
@ kCLOCK_OutputLcdifPixClk
Definition: fsl_clock.h:1295
@ kCLOCK_OutputSemcClk
Definition: fsl_clock.h:1294
@ kCLOCK_OutputPllSys
Definition: fsl_clock.h:1292
@ kCLOCK_OutputIpgClk
Definition: fsl_clock.h:1297
@ kCLOCK_OutputAhbClk
Definition: fsl_clock.h:1296
@ kCLOCK_OutputPllUsb1
Definition: fsl_clock.h:1291
@ kCLOCK_DisableClockOutput1
Definition: fsl_clock.h:1301
@ kCLOCK_PllClkSrc24M
Definition: fsl_clock.h:1188
@ kCLOCK_PllSrcClkPN
Definition: fsl_clock.h:1189
@ kCLOCK_Lpi2cMux
Definition: fsl_clock.h:760
@ kCLOCK_Flexio1Mux
Definition: fsl_clock.h:755
@ kCLOCK_CsiMux
Definition: fsl_clock.h:769
@ kCLOCK_Usdhc2Mux
Definition: fsl_clock.h:712
@ kCLOCK_CanMux
Definition: fsl_clock.h:741
@ kCLOCK_Sai3Mux
Definition: fsl_clock.h:720
@ kCLOCK_PeriphClk2Mux
Definition: fsl_clock.h:699
@ kCLOCK_SemcMux
Definition: fsl_clock.h:686
@ kCLOCK_TraceMux
Definition: fsl_clock.h:695
@ kCLOCK_PrePeriphMux
Definition: fsl_clock.h:691
@ kCLOCK_UartMux
Definition: fsl_clock.h:746
@ kCLOCK_Pll3SwMux
Definition: fsl_clock.h:673
@ kCLOCK_SemcAltMux
Definition: fsl_clock.h:682
@ kCLOCK_Usdhc1Mux
Definition: fsl_clock.h:716
@ kCLOCK_PeriphMux
Definition: fsl_clock.h:678
@ kCLOCK_SpdifMux
Definition: fsl_clock.h:751
@ kCLOCK_PerclkMux
Definition: fsl_clock.h:732
@ kCLOCK_FlexspiMux
Definition: fsl_clock.h:708
@ kCLOCK_LcdifPreMux
Definition: fsl_clock.h:764
@ kCLOCK_Sai2Mux
Definition: fsl_clock.h:724
@ kCLOCK_Sai1Mux
Definition: fsl_clock.h:728
@ kCLOCK_Flexio2Mux
Definition: fsl_clock.h:737
@ kCLOCK_LpspiMux
Definition: fsl_clock.h:703
@ kCLOCK_ClockNeededRun
Definition: fsl_clock.h:651
@ kCLOCK_ClockNeededRunWait
Definition: fsl_clock.h:652
@ kCLOCK_ClockNotNeeded
Definition: fsl_clock.h:650
Definition: MIMXRT1052.h:7208
PLL configuration for ARM.
Definition: fsl_clock.h:1194
uint8_t src
Definition: fsl_clock.h:1196
PLL configuration for AUDIO and VIDEO.
Definition: fsl_clock.h:1226
uint8_t src
Definition: fsl_clock.h:1231
PLL configuration for ENET.
Definition: fsl_clock.h:1247
PLL configuration for System.
Definition: fsl_clock.h:1211
uint16_t ss_stop
Definition: fsl_clock.h:1218
uint32_t numerator
Definition: fsl_clock.h:1215
uint8_t ss_enable
Definition: fsl_clock.h:1219
uint8_t loopDivider
Definition: fsl_clock.h:1212
uint8_t src
Definition: fsl_clock.h:1217
uint32_t denominator
Definition: fsl_clock.h:1216
uint16_t ss_step
Definition: fsl_clock.h:1220
PLL configuration for USB.
Definition: fsl_clock.h:1201
PLL configuration for AUDIO and VIDEO.
Definition: fsl_clock.h:1236
uint32_t numerator
Definition: fsl_clock.h:1239
uint32_t denominator
Definition: fsl_clock.h:1240
uint8_t src
Definition: fsl_clock.h:1241
uint8_t loopDivider
Definition: fsl_clock.h:1237
uint8_t postDivider
Definition: fsl_clock.h:1238
Definition: deflate.c:114