RTEMS 6.1-rc7
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Data Fields

Power Control. More...

#include <stm32h723xx.h>

Data Fields

__IO uint32_t CR1
 
__IO uint32_t CSR1
 
__IO uint32_t CR2
 
__IO uint32_t CR3
 
__IO uint32_t CPUCR
 
uint32_t RESERVED0
 
__IO uint32_t D3CR
 
uint32_t RESERVED1
 
__IO uint32_t WKUPCR
 
__IO uint32_t WKUPFR
 
__IO uint32_t WKUPEPR
 
__IO uint32_t CPU2CR
 
__IO uint32_t SRDCR
 

Detailed Description

Power Control.

Field Documentation

◆ CPU2CR

__IO uint32_t PWR_TypeDef::CPU2CR

PWR CPU2 control register, Address offset: 0x14

◆ CPUCR

__IO uint32_t PWR_TypeDef::CPUCR

PWR CPU control register, Address offset: 0x10

◆ CR1

__IO uint32_t PWR_TypeDef::CR1

PWR power control register 1, Address offset: 0x00

◆ CR2

__IO uint32_t PWR_TypeDef::CR2

PWR power control register 2, Address offset: 0x08

◆ CR3

__IO uint32_t PWR_TypeDef::CR3

PWR power control register 3, Address offset: 0x0C

◆ CSR1

__IO uint32_t PWR_TypeDef::CSR1

PWR power control status register 1, Address offset: 0x04

◆ D3CR

__IO uint32_t PWR_TypeDef::D3CR

PWR D3 domain control register, Address offset: 0x18

◆ RESERVED0

uint32_t PWR_TypeDef::RESERVED0

Reserved, Address offset: 0x14

◆ RESERVED1

uint32_t PWR_TypeDef::RESERVED1

Reserved, Address offset: 0x1C

◆ SRDCR

__IO uint32_t PWR_TypeDef::SRDCR

PWR SRD domain control register, Address offset: 0x18

◆ WKUPCR

__IO uint32_t PWR_TypeDef::WKUPCR

PWR wakeup clear register, Address offset: 0x20

◆ WKUPEPR

__IO uint32_t PWR_TypeDef::WKUPEPR

PWR wakeup enable and polarity register, Address offset: 0x28

◆ WKUPFR

__IO uint32_t PWR_TypeDef::WKUPFR

PWR wakeup flag register, Address offset: 0x24


The documentation for this struct was generated from the following files: