◆ CCR
__IO uint32_t BDMA_Channel_TypeDef::CCR |
DMA channel x configuration register
◆ CM0AR
__IO uint32_t BDMA_Channel_TypeDef::CM0AR |
DMA channel x memory 0 address register
◆ CM1AR
__IO uint32_t BDMA_Channel_TypeDef::CM1AR |
DMA channel x memory 1 address register
◆ CNDTR
__IO uint32_t BDMA_Channel_TypeDef::CNDTR |
DMA channel x number of data register
◆ CPAR
__IO uint32_t BDMA_Channel_TypeDef::CPAR |
DMA channel x peripheral address register
The documentation for this struct was generated from the following files: