37#ifndef _RTEMS_SCORE_CPU_H
38#define _RTEMS_SCORE_CPU_H
45#include <rtems/score/cpu_asm.h>
46#include <rtems/score/x86_64.h>
48#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
49#define CPU_ISR_PASSES_FRAME_POINTER FALSE
50#define CPU_HARDWARE_FP TRUE
51#define CPU_SOFTWARE_FP FALSE
52#define CPU_ALL_TASKS_ARE_FP TRUE
53#define CPU_IDLE_TASK_IS_FP FALSE
54#define CPU_USE_DEFERRED_FP_SWITCH FALSE
55#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
56#define CPU_STACK_GROWS_UP FALSE
58#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED(64)
59#define CPU_CACHE_LINE_BYTES 64
60#define CPU_MODES_INTERRUPT_MASK 0x00000001
61#define CPU_MAXIMUM_PROCESSORS 32
63#define CPU_EFLAGS_INTERRUPTS_ON 0x00003202
64#define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002
66#define CPU_CONTEXT_CONTROL_EFLAGS 0
68#define CPU_CONTEXT_CONTROL_RBX CPU_CONTEXT_CONTROL_EFLAGS + 8
69#define CPU_CONTEXT_CONTROL_RSP CPU_CONTEXT_CONTROL_RBX + 8
70#define CPU_CONTEXT_CONTROL_RBP CPU_CONTEXT_CONTROL_RSP + 8
71#define CPU_CONTEXT_CONTROL_R12 CPU_CONTEXT_CONTROL_RBP + 8
72#define CPU_CONTEXT_CONTROL_R13 CPU_CONTEXT_CONTROL_R12 + 8
73#define CPU_CONTEXT_CONTROL_R14 CPU_CONTEXT_CONTROL_R13 + 8
74#define CPU_CONTEXT_CONTROL_R15 CPU_CONTEXT_CONTROL_R14 + 8
76#define CPU_CONTEXT_CONTROL_FS CPU_CONTEXT_CONTROL_R15 + 8
78#define CPU_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE CPU_CONTEXT_CONTROL_FS + 8
80#define CPU_CONTEXT_CONTROL_IS_EXECUTING CPU_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE + 4
102 uint32_t isr_dispatch_disable;
105 volatile uint16_t is_executing;
118#define _CPU_Context_Get_SP( _context ) \
123#define CPU_INTERRUPT_FRAME_SSE_STATE 0
125#define CPU_INTERRUPT_FRAME_RAX CPU_INTERRUPT_FRAME_SSE_STATE + 512
126#define CPU_INTERRUPT_FRAME_RCX CPU_INTERRUPT_FRAME_RAX + 8
127#define CPU_INTERRUPT_FRAME_RDX CPU_INTERRUPT_FRAME_RCX + 8
128#define CPU_INTERRUPT_FRAME_RSI CPU_INTERRUPT_FRAME_RDX + 8
129#define CPU_INTERRUPT_FRAME_R8 CPU_INTERRUPT_FRAME_RSI + 8
130#define CPU_INTERRUPT_FRAME_R9 CPU_INTERRUPT_FRAME_R8 + 8
131#define CPU_INTERRUPT_FRAME_R10 CPU_INTERRUPT_FRAME_R9 + 8
132#define CPU_INTERRUPT_FRAME_R11 CPU_INTERRUPT_FRAME_R10 + 8
133#define CPU_INTERRUPT_FRAME_RSP CPU_INTERRUPT_FRAME_R11 + 8
155 uint8_t sse_state[512];
184#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
188#define CPU_INTERRUPT_FRAME_X86_64_SIZE 48
189#define CPU_INTERRUPT_FRAME_PROLOGUE_SIZE 24
190#define CPU_INTERRUPT_FRAME_CALLER_SAVED_SIZE (512 + 72)
191#define CPU_INTERRUPT_FRAME_PADDING_SIZE 8
193#define CPU_INTERRUPT_FRAME_SIZE \
194 (CPU_INTERRUPT_FRAME_X86_64_SIZE + \
195 CPU_INTERRUPT_FRAME_PROLOGUE_SIZE + \
196 CPU_INTERRUPT_FRAME_CALLER_SAVED_SIZE + \
197 CPU_INTERRUPT_FRAME_PADDING_SIZE)
206 CPU_INTERRUPT_FRAME_SIZE
210#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
211#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
212#define CPU_STACK_MINIMUM_SIZE (1024*8)
213#define CPU_SIZEOF_POINTER 8
214#define CPU_ALIGNMENT 16
215#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
216#define CPU_STACK_ALIGNMENT 16
217#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
224#define CPU_ISR_LEVEL_ENABLED 0
228#define _CPU_ISR_Enable(_level) \
231 amd64_enable_interrupts(); \
235#define _CPU_ISR_Disable(_level) \
237 _level = _CPU_ISR_Get_level(); \
238 amd64_disable_interrupts(); \
241#define _CPU_ISR_Flash(_level) \
244 amd64_enable_interrupts(); \
246 amd64_disable_interrupts(); \
249static inline bool _CPU_ISR_Is_enabled(uint32_t level)
257 amd64_disable_interrupts();
260 amd64_enable_interrupts();
268 __asm__
volatile (
"pushf; \
273 uint32_t level = (rflags & EFLAGS_INTR_ENABLE) ? 0 : 1;
280#define _CPU_Context_Destroy( _the_thread, _the_context ) \
284void _CPU_Context_Initialize(
286 void *stack_area_begin,
287 size_t stack_area_size,
289 void (*entry_point)(
void ),
294#define _CPU_Context_Restart_self( _the_context ) \
295 _CPU_Context_restore( (_the_context) );
297#define _CPU_Context_Initialize_fp( _destination ) \
299 *(*(_destination)) = _CPU_Null_fp_context; \
304#define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE
308#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
310#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
311#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
319#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
320#define _CPU_Priority_Mask( _bit_number ) \
321 ( 1 << (_bit_number) )
324#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
325#define _CPU_Priority_bits_index( _priority ) \
350 uint32_t processor_state_register;
351 uint32_t integer_registers [1];
352 double float_registers [1];
365static inline uint32_t CPU_swap_u32(
369 uint32_t byte1, byte2, byte3, byte4, swapped;
371 byte4 = (value >> 24) & 0xff;
372 byte3 = (value >> 16) & 0xff;
373 byte2 = (value >> 8) & 0xff;
374 byte1 = value & 0xff;
376 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
380#define _CPU_Context_save_fp(fp_context_pp) \
382 __asm__ __volatile__( \
384 :"=m"((*(fp_context_pp))->fpucw) \
386 __asm__ __volatile__( \
388 :"=m"((*(fp_context_pp))->mxcsr) \
392#define _CPU_Context_restore_fp(fp_context_pp) \
394 __asm__ __volatile__( \
396 :"=m"((*(fp_context_pp))->fpucw) \
398 __asm__ __volatile__( \
400 :"=m"((*(fp_context_pp))->mxcsr) \
404#define CPU_swap_u16( value ) \
405 (((value&0xff) << 8) | ((value >> 8)&0xff))
407typedef uint32_t CPU_Counter_ticks;
415 uint32_t _CPU_SMP_Initialize(
void );
417 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
419 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
421 void _CPU_SMP_Prepare_start_multitasking(
void );
423 uint32_t _CPU_SMP_Get_current_processor(
void );
425 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
427 static inline bool _CPU_Context_Get_is_executing(
434 static inline void _CPU_Context_Set_is_executing(
439 context->is_executing = is_executing;
This header file provides basic definitions used by the API and the implementation.
#define RTEMS_STATIC_ASSERT(_cond, _msg)
It is defined if a static analysis run is performed.
Definition: basedefs.h:841
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
#define _CPU_ISR_Set_level(_new_level)
Definition: cpu.h:378
rtems_termios_device_context * context
Definition: console-config.c:62
#define _CPU_Context_restore_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:901
#define _CPU_Context_save_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:895
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
SPARC basic context.
Definition: cpu.h:213
uint32_t mxcsr
Definition: cpu.h:114
Thread register context.
Definition: cpu.h:173
uint64_t rbx
Definition: cpu.h:91