RTEMS 6.1-rc7
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Data Fields
FMC_NAND_PCC_TimingTypeDef Struct Reference

FMC NAND Timing parameters structure definition. More...

#include <stm32h7xx_ll_fmc.h>

Data Fields

uint32_t SetupTime
 
uint32_t WaitSetupTime
 
uint32_t HoldSetupTime
 
uint32_t HiZSetupTime
 

Detailed Description

FMC NAND Timing parameters structure definition.

Field Documentation

◆ HiZSetupTime

uint32_t FMC_NAND_PCC_TimingTypeDef::HiZSetupTime

Defines the number of HCLK clock cycles during which the data bus is kept in HiZ after the start of a NAND-Flash write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between Min_Data = 0 and Max_Data = 254

◆ HoldSetupTime

uint32_t FMC_NAND_PCC_TimingTypeDef::HoldSetupTime

Defines the number of HCLK clock cycles to hold address (and data for write access) after the command de-assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between Min_Data = 0 and Max_Data = 254

◆ SetupTime

uint32_t FMC_NAND_PCC_TimingTypeDef::SetupTime

Defines the number of HCLK cycles to setup address before the command assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a value between Min_Data = 0 and Max_Data = 254

◆ WaitSetupTime

uint32_t FMC_NAND_PCC_TimingTypeDef::WaitSetupTime

Defines the minimum number of HCLK cycles to assert the command for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between Min_Data = 0 and Max_Data = 254


The documentation for this struct was generated from the following file: