37#ifndef LIBBSP_ARM_XILINX_ZYNQMP_RPU_IRQ_H
38#define LIBBSP_ARM_XILINX_ZYNQMP_RPU_IRQ_H
52#ifndef ZYNQMP_RPU_LOCK_STEP_MODE
53#define BSP_IRQ_HAVE_GET_SET_AFFINITY
56#define BSP_INTERRUPT_VECTOR_COUNT 188
This header file provides interfaces of the ARM Generic Interrupt Controller (GIC) support.
This header file defines the RTEMS Classic API.
Xilinx Zynq Ultrascale+ MPSoC Peripheral memory map.