36#ifndef LIBCPU_POWERPC_MPC55XX_EDMA_H
37#define LIBCPU_POWERPC_MPC55XX_EDMA_H
48#if MPC55XX_CHIP_FAMILY == 551
49 #define EDMA_CHANNEL_COUNT 16U
50#elif MPC55XX_CHIP_FAMILY == 564
51 #define EDMA_CHANNEL_COUNT 16U
52#elif MPC55XX_CHIP_FAMILY == 567
53 #define EDMA_CHANNEL_COUNT 96U
55 #define EDMA_CHANNEL_COUNT 64U
58#define EDMA_MODULE_COUNT ((EDMA_CHANNEL_COUNT + 63U) / 64U)
60#define EDMA_CHANNELS_PER_MODULE 64U
62#if EDMA_MODULE_COUNT == 1
63 #define EDMA_TCD_BY_CHANNEL_INDEX(channel_index) \
64 (&EDMA.TCD[(channel_index)])
65#elif EDMA_MODULE_COUNT == 2
66 #define EDMA_TCD_BY_CHANNEL_INDEX(channel_index) \
67 ((channel_index) < EDMA_CHANNELS_PER_MODULE ? \
68 &EDMA_A.TCD[(channel_index)] \
69 : &EDMA_B.TCD[(channel_index) - EDMA_CHANNELS_PER_MODULE])
71 #error "unsupported module count"
76 EDMA_EQADC_A_FISR0_CFFF0 = 0,
77 EDMA_EQADC_A_FISR0_RFDF0 = 1,
78 EDMA_EQADC_A_FISR1_CFFF1 = 2,
79 EDMA_EQADC_A_FISR1_RFDF1 = 3,
80 EDMA_EQADC_A_FISR2_CFFF2 = 4,
81 EDMA_EQADC_A_FISR2_RFDF2 = 5,
82 EDMA_EQADC_A_FISR3_CFFF3 = 6,
83 EDMA_EQADC_A_FISR3_RFDF3 = 7,
84 EDMA_EQADC_A_FISR4_CFFF4 = 8,
85 EDMA_EQADC_A_FISR4_RFDF4 = 9,
86 EDMA_EQADC_A_FISR5_CFFF5 = 10,
87 EDMA_EQADC_A_FISR5_RFDF5 = 11,
88 EDMA_DSPI_B_SR_TFFF = 12,
89 EDMA_DSPI_B_SR_RFDF = 13,
90 EDMA_DSPI_C_SR_TFFF = 14,
91 EDMA_DSPI_C_SR_RFDF = 15,
92 EDMA_DSPI_D_SR_TFFF = 16,
93 EDMA_DSPI_D_SR_RFDF = 17,
94 EDMA_ESCI_A_COMBTX = 18,
95 EDMA_ESCI_A_COMBRX = 19,
96 EDMA_EMIOS_GFR_F0 = 20,
97 EDMA_EMIOS_GFR_F1 = 21,
98 EDMA_EMIOS_GFR_F2 = 22,
99 EDMA_EMIOS_GFR_F3 = 23,
100 EDMA_EMIOS_GFR_F4 = 24,
101 EDMA_EMIOS_GFR_F8 = 25,
102 EDMA_EMIOS_GFR_F9 = 26,
103 EDMA_ETPU_CDTRSR_A_DTRS0 = 27,
104 EDMA_ETPU_CDTRSR_A_DTRS1 = 28,
105 EDMA_ETPU_CDTRSR_A_DTRS2 = 29,
106 EDMA_ETPU_CDTRSR_A_DTRS14 = 30,
107 EDMA_ETPU_CDTRSR_A_DTRS15 = 31,
108 EDMA_DSPI_A_SR_TFFF = 32,
109 EDMA_DSPI_A_SR_RFDF = 33,
110 EDMA_ESCI_B_COMBTX = 34,
111 EDMA_ESCI_B_COMBRX = 35,
112 EDMA_EMIOS_GFR_F6 = 36,
113 EDMA_EMIOS_GFR_F7 = 37,
114 EDMA_EMIOS_GFR_F10 = 38,
115 EDMA_EMIOS_GFR_F11 = 39,
116 EDMA_EMIOS_GFR_F16 = 40,
117 EDMA_EMIOS_GFR_F17 = 41,
118 EDMA_EMIOS_GFR_F18 = 42,
119 EDMA_EMIOS_GFR_F19 = 43,
120 EDMA_ETPU_CDTRSR_A_DTRS12 = 44,
121 EDMA_ETPU_CDTRSR_A_DTRS13 = 45,
122 EDMA_ETPU_CDTRSR_A_DTRS28 = 46,
123 EDMA_ETPU_CDTRSR_A_DTRS29 = 47,
124 EDMA_SIU_EISR_EIF0 = 48,
125 EDMA_SIU_EISR_EIF1 = 49,
126 EDMA_SIU_EISR_EIF2 = 50,
127 EDMA_SIU_EISR_EIF3 = 51,
128 EDMA_ETPU_CDTRSR_B_DTRS0 = 52,
129 EDMA_ETPU_CDTRSR_B_DTRS1 = 53,
130 EDMA_ETPU_CDTRSR_B_DTRS2 = 54,
131 EDMA_ETPU_CDTRSR_B_DTRS3 = 55,
132 EDMA_ETPU_CDTRSR_B_DTRS12 = 56,
133 EDMA_ETPU_CDTRSR_B_DTRS13 = 57,
134 EDMA_ETPU_CDTRSR_B_DTRS14 = 58,
135 EDMA_ETPU_CDTRSR_B_DTRS15 = 59,
136 EDMA_ETPU_CDTRSR_B_DTRS28 = 60,
137 EDMA_ETPU_CDTRSR_B_DTRS29 = 61,
138 EDMA_ETPU_CDTRSR_B_DTRS30 = 62,
139 EDMA_ETPU_CDTRSR_B_DTRS31 = 63
140 #if MPC55XX_CHIP_FAMILY == 567
142 EDMA_EQADC_B_FISR0_CFFF0 = 64 + 0,
143 EDMA_EQADC_B_FISR0_RFDF0 = 64 + 1,
144 EDMA_EQADC_B_FISR1_CFFF1 = 64 + 2,
145 EDMA_EQADC_B_FISR1_RFDF1 = 64 + 3,
146 EDMA_EQADC_B_FISR2_CFFF2 = 64 + 4,
147 EDMA_EQADC_B_FISR2_RFDF2 = 64 + 5,
148 EDMA_EQADC_B_FISR3_CFFF3 = 64 + 6,
149 EDMA_EQADC_B_FISR3_RFDF3 = 64 + 7,
150 EDMA_EQADC_B_FISR4_CFFF4 = 64 + 8,
151 EDMA_EQADC_B_FISR4_RFDF4 = 64 + 9,
152 EDMA_EQADC_B_FISR5_CFFF5 = 64 + 10,
153 EDMA_EQADC_B_FISR5_RFDF5 = 64 + 11,
154 EDMA_DECFILTER_A_IB = 64 + 12,
155 EDMA_DECFILTER_A_OB = 64 + 13,
156 EDMA_DECFILTER_B_IB = 64 + 14,
157 EDMA_DECFILTER_B_OB = 64 + 15,
158 EDMA_DECFILTER_C_IB = 64 + 16,
159 EDMA_DECFILTER_C_OB = 64 + 17,
160 EDMA_DECFILTER_D_IB = 64 + 18,
161 EDMA_DECFILTER_D_OB = 64 + 19,
162 EDMA_DECFILTER_E_IB = 64 + 20,
163 EDMA_DECFILTER_E_OB = 64 + 21,
164 EDMA_DECFILTER_F_IB = 64 + 22,
165 EDMA_DECFILTER_F_OB = 64 + 23,
166 EDMA_DECFILTER_G_IB = 64 + 24,
167 EDMA_DECFILTER_G_OB = 64 + 25,
168 EDMA_DECFILTER_H_IB = 64 + 26,
169 EDMA_DECFILTER_H_OB = 64 + 27
175 volatile struct tcd_t *edma_tcd;
179void mpc55xx_edma_init(
void);
188 volatile struct tcd_t *edma_tcd
191void mpc55xx_edma_release_channel_by_tcd(
volatile struct tcd_t *edma_tcd);
209 unsigned irq_priority
224 volatile struct tcd_t *edma_tcd,
225 const struct tcd_t *source_tcd
235 volatile struct tcd_t *edma_tcd,
236 const struct tcd_t *source_tcd
239void mpc55xx_edma_sg_link(
240 volatile struct tcd_t *edma_tcd,
241 const struct tcd_t *source_tcd
244static inline volatile struct EDMA_tag *mpc55xx_edma_by_tcd(
245 volatile struct tcd_t *edma_tcd
249 ((uintptr_t) edma_tcd & ~(uintptr_t) 0x1fff);
252static inline unsigned mpc55xx_edma_channel_by_tcd(
253 volatile struct tcd_t *edma_tcd
256 volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd);
258 return edma_tcd - &edma->TCD[0];
261static inline void mpc55xx_edma_enable_hardware_requests(
262 volatile struct tcd_t *edma_tcd
265 volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd);
266 unsigned channel = edma_tcd - &edma->TCD[0];
268 edma->SERQR.R = (uint8_t) channel;
271static inline void mpc55xx_edma_disable_hardware_requests(
272 volatile struct tcd_t *edma_tcd
275 volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd);
276 unsigned channel = edma_tcd - &edma->TCD[0];
278 edma->CERQR.R = (uint8_t) channel;
281static inline void mpc55xx_edma_enable_error_interrupts(
282 volatile struct tcd_t *edma_tcd
285 volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd);
286 unsigned channel = edma_tcd - &edma->TCD[0];
288 edma->SEEIR.R = (uint8_t) channel;
291static inline void mpc55xx_edma_disable_error_interrupts(
292 volatile struct tcd_t *edma_tcd
295 volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd);
296 unsigned channel = edma_tcd - &edma->TCD[0];
298 edma->CEEIR.R = (uint8_t) channel;
301static inline void mpc55xx_edma_set_start(
302 volatile struct tcd_t *edma_tcd
305 volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd);
306 unsigned channel = edma_tcd - &edma->TCD[0];
308 edma->SSBR.R = (uint8_t) channel;
311static inline void mpc55xx_edma_clear_done(
312 volatile struct tcd_t *edma_tcd
315 volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd);
316 unsigned channel = edma_tcd - &edma->TCD[0];
318 edma->CDSBR.R = (uint8_t) channel;
321static inline void mpc55xx_edma_clear_interrupts(
322 volatile struct tcd_t *edma_tcd
325 volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd);
326 unsigned channel = edma_tcd - &edma->TCD[0];
328 edma->CIRQR.R = (uint8_t) channel;
331static inline bool mpc55xx_edma_is_done(
332 volatile struct tcd_t *edma_tcd
335 return edma_tcd->BMF.B.DONE;
This header file provides the Chains API.
rtems_status_code
This enumeration provides status codes for directives of the Classic API.
Definition: status.h:85
void mpc55xx_edma_copy(volatile struct tcd_t *edma_tcd, const struct tcd_t *source_tcd)
Copies a source TCD to an eDMA TCD.
Definition: edma.c:304
rtems_status_code mpc55xx_edma_obtain_channel_by_tcd(volatile struct tcd_t *edma_tcd)
Obtains an eDMA channel.
Definition: edma.c:221
void mpc55xx_edma_copy_and_enable_hardware_requests(volatile struct tcd_t *edma_tcd, const struct tcd_t *source_tcd)
Copies a source TCD to an eDMA TCD and enables hardware requests.
Definition: edma.c:322
rtems_status_code mpc55xx_edma_obtain_channel(edma_channel_context *ctx, unsigned irq_priority)
Obtains an eDMA channel and registers the channel context.
Definition: edma.c:257
Register definitions for the MPC55xx and MPC56xx microcontroller family.
This header file defines the RTEMS Classic API.
This structure represents a chain node.
Definition: chain.h:78
Definition: regs-edma.h:60