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RTEMS 6.1-rc7
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GPR0 - GPR0 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK (0xFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK) |
#define | IOMUXC_LPSR_GPR_GPR0_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR0_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR0_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK) |
GPR1 - GPR1 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK (0xFFFFU) |
#define | IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK) |
#define | IOMUXC_LPSR_GPR_GPR1_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR1_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR1_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK) |
GPR2 - GPR2 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR2_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK) |
GPR3 - GPR3 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR3_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK) |
GPR4 - GPR4 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR4_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR4_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK) |
GPR5 - GPR5 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR5_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR5_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK) |
GPR6 - GPR6 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR6_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR6_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR6_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR6_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR6_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_MASK) |
GPR7 - GPR7 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR7_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR7_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK) |
GPR8 - GPR8 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR8_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR8_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK) |
GPR9 - GPR9 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR9_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR9_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK) |
GPR10 - GPR10 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR10_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR10_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK) |
GPR11 - GPR11 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR11_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR11_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK) |
GPR12 - GPR12 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR12_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR12_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK) |
GPR13 - GPR13 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR13_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR13_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK) |
GPR14 - GPR14 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR14_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR14_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK) |
GPR15 - GPR15 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR15_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR15_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK) |
GPR16 - GPR16 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR16_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR16_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK) |
GPR17 - GPR17 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR17_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR17_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK) |
GPR18 - GPR18 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR18_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR18_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_LOCK_MASK) |
GPR19 - GPR19 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR19_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR19_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR19_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR19_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR19_LOCK_MASK) |
GPR20 - GPR20 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR20_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR20_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_LOCK_MASK) |
GPR21 - GPR21 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR21_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR21_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_LOCK_MASK) |
GPR22 - GPR22 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR22_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR22_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_LOCK_MASK) |
GPR23 - GPR23 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR23_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR23_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_LOCK_MASK) |
GPR24 - GPR24 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR24_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR24_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_LOCK_MASK) |
GPR25 - GPR25 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR25_APC_VALID(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK) |
#define | IOMUXC_LPSR_GPR_GPR25_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR25_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_LOCK_MASK) |
GPR26 - GPR26 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK (0x1FFFFFFU) |
#define | IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK) |
#define | IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK (0xE000000U) |
#define | IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT (25U) |
#define | IOMUXC_LPSR_GPR_GPR26_FIELD_0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK) |
#define | IOMUXC_LPSR_GPR_GPR26_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR26_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR26_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK) |
GPR33 - GPR33 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK) |
#define | IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK) |
#define | IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK) |
#define | IOMUXC_LPSR_GPR_GPR33_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR33_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR33_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK) |
GPR34 - GPR34 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK) |
#define | IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR34_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR34_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR34_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK) |
GPR35 - GPR35 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK (0x40U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT (6U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK (0x80U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT (7U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK (0x400U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT (10U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK (0x1000U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT (12U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK (0x2000U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT (13U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK (0x8000U) |
#define | IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT (15U) |
#define | IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK (0x10000U) |
#define | IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK (0x20000U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT (17U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK (0x40000U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT (18U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK (0x80000U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT (19U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK (0x100000U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT (20U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK (0x200000U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT (21U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK (0x400000U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT (22U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK (0x800000U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT (23U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK (0x1000000U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT (24U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK (0x2000000U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT (25U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK (0x4000000U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT (26U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR35_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR35_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK) |
GPR36 - GPR36 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK (0x40U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT (6U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK (0x80U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT (7U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK (0x400U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT (10U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK (0x1000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT (12U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK (0x2000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT (13U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK (0x4000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT (14U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK (0x8000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT (15U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK (0x10000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK (0x20000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT (17U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK (0x40000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT (18U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK (0x80000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT (19U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK (0x100000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT (20U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK (0x200000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT (21U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK (0x400000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT (22U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK (0x800000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT (23U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK (0x1000000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT (24U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK (0x2000000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT (25U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK (0x4000000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT (26U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR36_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR36_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK) |
GPR37 - GPR37 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK (0x40U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT (6U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK (0x80U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT (7U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK (0x400U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT (10U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK (0x1000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT (12U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK (0x2000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT (13U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK (0x4000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT (14U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK (0x8000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT (15U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK (0x10000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK (0x20000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT (17U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK (0x40000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT (18U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK (0x80000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT (19U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK (0x100000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT (20U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK (0x200000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT (21U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK (0x400000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT (22U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK (0x800000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT (23U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK (0x1000000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT (24U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK (0x2000000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT (25U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK (0x4000000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT (26U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR37_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR37_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK) |
GPR38 - GPR38 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK (0x40U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT (6U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK (0x80U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT (7U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK (0x400U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT (10U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK (0x1000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT (12U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK (0x2000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT (13U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK (0x4000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT (14U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK (0x8000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT (15U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK (0x10000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK (0x20000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT (17U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK (0x40000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT (18U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK (0x80000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT (19U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK (0x100000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT (20U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK (0x200000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT (21U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK (0x400000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT (22U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK (0x800000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT (23U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK (0x1000000U) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT (24U) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK (0x2000000U) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT (25U) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK (0x4000000U) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT (26U) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR38_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR38_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK) |
GPR39 - GPR39 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK (0x40U) |
#define | IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT (6U) |
#define | IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK (0x80U) |
#define | IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT (7U) |
#define | IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK (0x400U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT (10U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK (0x1000U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT (12U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK (0x2000U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT (13U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK (0x4000U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT (14U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK (0x8000U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT (15U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK (0x10000U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK (0x20000U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT (17U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR39_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR39_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK) |
GPR40 - GPR40 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK (0x40U) |
#define | IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT (6U) |
#define | IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK (0x80U) |
#define | IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT (7U) |
#define | IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK (0x400U) |
#define | IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT (10U) |
#define | IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK (0x1000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT (12U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK (0x2000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT (13U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK (0x4000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT (14U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK (0x8000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT (15U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK (0x10000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK (0x20000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT (17U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK (0x40000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT (18U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK (0x80000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT (19U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK (0x100000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT (20U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK (0x200000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT (21U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK (0x400000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT (22U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK (0x800000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT (23U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK (0x1000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT (24U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK (0x2000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT (25U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK (0x4000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT (26U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK (0x8000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT (27U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK (0x10000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK (0x20000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT (29U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK (0x40000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK (0x80000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT (31U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK) |
GPR41 - GPR41 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK (0x40U) |
#define | IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT (6U) |
#define | IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK (0x80U) |
#define | IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT (7U) |
#define | IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK (0x400U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT (10U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK (0x1000U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT (12U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK (0x2000U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT (13U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK (0x4000U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT (14U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK (0x8000U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT (15U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK (0x10000U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK (0x1000000U) |
#define | IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT (24U) |
#define | IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK) |
GPR0 - GPR0 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK (0xFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK) |
#define | IOMUXC_LPSR_GPR_GPR0_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR0_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR0_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK) |
GPR1 - GPR1 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK (0xFFFFU) |
#define | IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK) |
#define | IOMUXC_LPSR_GPR_GPR1_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR1_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR1_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK) |
GPR2 - GPR2 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR2_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK) |
GPR3 - GPR3 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR3_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK) |
GPR4 - GPR4 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR4_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR4_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK) |
GPR5 - GPR5 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR5_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR5_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK) |
GPR6 - GPR6 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR6_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR6_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR6_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR6_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR6_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_MASK) |
GPR7 - GPR7 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR7_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR7_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK) |
GPR8 - GPR8 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR8_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR8_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK) |
GPR9 - GPR9 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR9_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR9_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK) |
GPR10 - GPR10 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR10_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR10_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK) |
GPR11 - GPR11 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR11_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR11_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK) |
GPR12 - GPR12 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR12_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR12_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK) |
GPR13 - GPR13 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR13_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR13_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK) |
GPR14 - GPR14 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR14_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR14_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK) |
GPR15 - GPR15 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR15_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR15_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK) |
GPR16 - GPR16 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR16_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR16_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK) |
GPR17 - GPR17 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR17_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR17_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK) |
GPR18 - GPR18 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR18_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR18_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_LOCK_MASK) |
GPR19 - GPR19 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR19_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR19_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR19_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR19_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR19_LOCK_MASK) |
GPR20 - GPR20 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR20_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR20_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_LOCK_MASK) |
GPR21 - GPR21 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR21_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR21_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_LOCK_MASK) |
GPR22 - GPR22 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR22_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR22_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_LOCK_MASK) |
GPR23 - GPR23 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR23_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR23_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_LOCK_MASK) |
GPR24 - GPR24 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR24_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR24_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_LOCK_MASK) |
GPR25 - GPR25 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR25_APC_VALID(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK) |
#define | IOMUXC_LPSR_GPR_GPR25_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR25_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_LOCK_MASK) |
GPR26 - GPR26 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK (0x1FFFFFFU) |
#define | IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK) |
#define | IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK (0xE000000U) |
#define | IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT (25U) |
#define | IOMUXC_LPSR_GPR_GPR26_FIELD_0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK) |
#define | IOMUXC_LPSR_GPR_GPR26_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR26_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR26_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK) |
GPR33 - GPR33 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK) |
#define | IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK) |
#define | IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK) |
#define | IOMUXC_LPSR_GPR_GPR33_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR33_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR33_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK) |
GPR34 - GPR34 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK) |
#define | IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR34_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR34_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR34_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK) |
GPR35 - GPR35 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK (0x40U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT (6U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK (0x80U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT (7U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK (0x400U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT (10U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK (0x1000U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT (12U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK (0x2000U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT (13U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK (0x8000U) |
#define | IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT (15U) |
#define | IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK (0x10000U) |
#define | IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK (0x20000U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT (17U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK (0x40000U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT (18U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK (0x80000U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT (19U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK (0x100000U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT (20U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK (0x200000U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT (21U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK (0x400000U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT (22U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK (0x800000U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT (23U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK (0x1000000U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT (24U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK (0x2000000U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT (25U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK (0x4000000U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT (26U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR35_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR35_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK) |
GPR36 - GPR36 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK (0x40U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT (6U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK (0x80U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT (7U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK (0x400U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT (10U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK (0x1000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT (12U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK (0x2000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT (13U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK (0x4000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT (14U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK (0x8000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT (15U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK (0x10000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK (0x20000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT (17U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK (0x40000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT (18U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK (0x80000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT (19U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK (0x100000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT (20U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK (0x200000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT (21U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK (0x400000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT (22U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK (0x800000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT (23U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK (0x1000000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT (24U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK (0x2000000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT (25U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK (0x4000000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT (26U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR36_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR36_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK) |
GPR37 - GPR37 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK (0x40U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT (6U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK (0x80U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT (7U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK (0x400U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT (10U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK (0x1000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT (12U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK (0x2000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT (13U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK (0x4000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT (14U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK (0x8000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT (15U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK (0x10000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK (0x20000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT (17U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK (0x40000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT (18U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK (0x80000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT (19U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK (0x100000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT (20U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK (0x200000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT (21U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK (0x400000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT (22U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK (0x800000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT (23U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK (0x1000000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT (24U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK (0x2000000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT (25U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK (0x4000000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT (26U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR37_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR37_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK) |
GPR38 - GPR38 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK (0x40U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT (6U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK (0x80U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT (7U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK (0x400U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT (10U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK (0x1000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT (12U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK (0x2000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT (13U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK (0x4000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT (14U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK (0x8000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT (15U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK (0x10000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK (0x20000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT (17U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK (0x40000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT (18U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK (0x80000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT (19U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK (0x100000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT (20U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK (0x200000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT (21U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK (0x400000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT (22U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK (0x800000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT (23U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK (0x1000000U) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT (24U) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK (0x2000000U) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT (25U) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK (0x4000000U) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT (26U) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR38_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR38_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK) |
GPR39 - GPR39 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK (0x40U) |
#define | IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT (6U) |
#define | IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK (0x80U) |
#define | IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT (7U) |
#define | IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK (0x400U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT (10U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK (0x1000U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT (12U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK (0x2000U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT (13U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK (0x4000U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT (14U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK (0x8000U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT (15U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK (0x10000U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK (0x20000U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT (17U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR39_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR39_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK) |
GPR40 - GPR40 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK (0x40U) |
#define | IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT (6U) |
#define | IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK (0x80U) |
#define | IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT (7U) |
#define | IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK (0x400U) |
#define | IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT (10U) |
#define | IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK (0x1000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT (12U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK (0x2000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT (13U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK (0x4000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT (14U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK (0x8000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT (15U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK (0x10000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK (0x20000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT (17U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK (0x40000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT (18U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK (0x80000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT (19U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK (0x100000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT (20U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK (0x200000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT (21U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK (0x400000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT (22U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK (0x800000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT (23U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK (0x1000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT (24U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK (0x2000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT (25U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK (0x4000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT (26U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK (0x8000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT (27U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK (0x10000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK (0x20000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT (29U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK (0x40000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK (0x80000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT (31U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK) |
GPR41 - GPR41 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK (0x40U) |
#define | IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT (6U) |
#define | IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK (0x80U) |
#define | IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT (7U) |
#define | IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK (0x400U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT (10U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK (0x1000U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT (12U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK (0x2000U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT (13U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK (0x4000U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT (14U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK (0x8000U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT (15U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK (0x10000U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK (0x1000000U) |
#define | IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT (24U) |
#define | IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK) |
#define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK) |
CM4_INIT_VTOR_LOW - CM4 Vector table offset value lower bits out of reset
#define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK) |
CM4_INIT_VTOR_LOW - CM4 Vector table offset value lower bits out of reset
#define IOMUXC_LPSR_GPR_GPR0_DWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_MASK) |
DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden
#define IOMUXC_LPSR_GPR_GPR0_DWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_MASK) |
DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden
#define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK) |
DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked
#define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK) |
DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked
#define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK) |
APC_AC_R4_BOT - APC start address of memory region-4
#define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK) |
APC_AC_R4_BOT - APC start address of memory region-4
#define IOMUXC_LPSR_GPR_GPR10_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR10_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK) |
APC_AC_R4_TOP - APC end address of memory region-4
#define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK) |
APC_AC_R4_TOP - APC end address of memory region-4
#define IOMUXC_LPSR_GPR_GPR11_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR11_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK) |
APC_AC_R5_BOT - APC start address of memory region-5
#define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK) |
APC_AC_R5_BOT - APC start address of memory region-5
#define IOMUXC_LPSR_GPR_GPR12_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR12_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK) |
APC_AC_R5_TOP - APC end address of memory region-5
#define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK) |
APC_AC_R5_TOP - APC end address of memory region-5
#define IOMUXC_LPSR_GPR_GPR13_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR13_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK) |
APC_AC_R6_BOT - APC start address of memory region-6
#define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK) |
APC_AC_R6_BOT - APC start address of memory region-6
#define IOMUXC_LPSR_GPR_GPR14_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR14_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK) |
APC_AC_R6_TOP - APC end address of memory region-6
#define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK) |
APC_AC_R6_TOP - APC end address of memory region-6
#define IOMUXC_LPSR_GPR_GPR15_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR15_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK) |
APC_AC_R7_BOT - APC start address of memory region-7
#define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK) |
APC_AC_R7_BOT - APC start address of memory region-7
#define IOMUXC_LPSR_GPR_GPR16_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR16_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK) |
APC_AC_R7_TOP - APC end address of memory region-7
#define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK) |
APC_AC_R7_TOP - APC end address of memory region-7
#define IOMUXC_LPSR_GPR_GPR17_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR17_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK) |
APC_R0_ENCRYPT_ENABLE - APC memory region-0 encryption enable 0b1..Encryption enabled 0b0..No effect
#define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK) |
APC_R0_ENCRYPT_ENABLE - APC memory region-0 encryption enable 0b1..Encryption enabled 0b0..No effect
#define IOMUXC_LPSR_GPR_GPR18_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_LOCK_MASK) |
LOCK - Lock the write to bit 15:0
#define IOMUXC_LPSR_GPR_GPR18_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_LOCK_MASK) |
LOCK - Lock the write to bit 15:0
#define IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_MASK) |
APC_R1_ENCRYPT_ENABLE - APC memory region-1 encryption enable 0b1..Encryption enabled 0b0..No effect
#define IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_MASK) |
APC_R1_ENCRYPT_ENABLE - APC memory region-1 encryption enable 0b1..Encryption enabled 0b0..No effect
#define IOMUXC_LPSR_GPR_GPR19_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR19_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR19_LOCK_MASK) |
LOCK - Lock the write to bit 15:0
#define IOMUXC_LPSR_GPR_GPR19_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR19_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR19_LOCK_MASK) |
LOCK - Lock the write to bit 15:0
#define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK) |
CM4_INIT_VTOR_HIGH - CM4 Vector table offset value higher bits out of reset
#define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK) |
CM4_INIT_VTOR_HIGH - CM4 Vector table offset value higher bits out of reset
#define IOMUXC_LPSR_GPR_GPR1_DWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_MASK) |
DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden
#define IOMUXC_LPSR_GPR_GPR1_DWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_MASK) |
DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden
#define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK) |
DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked
#define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK) |
DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked
#define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK) |
APC_R2_ENCRYPT_ENABLE - APC memory region-2 encryption enable 0b1..Encryption enabled 0b0..No effect
#define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK) |
APC_R2_ENCRYPT_ENABLE - APC memory region-2 encryption enable 0b1..Encryption enabled 0b0..No effect
#define IOMUXC_LPSR_GPR_GPR20_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_LOCK_MASK) |
LOCK - Lock the write to bit 15:0
#define IOMUXC_LPSR_GPR_GPR20_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_LOCK_MASK) |
LOCK - Lock the write to bit 15:0
#define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK) |
APC_R3_ENCRYPT_ENABLE - APC memory region-3 encryption enable 0b1..Encryption enabled 0b0..No effect
#define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK) |
APC_R3_ENCRYPT_ENABLE - APC memory region-3 encryption enable 0b1..Encryption enabled 0b0..No effect
#define IOMUXC_LPSR_GPR_GPR21_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_LOCK_MASK) |
LOCK - Lock the write to bit 15:0
#define IOMUXC_LPSR_GPR_GPR21_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_LOCK_MASK) |
LOCK - Lock the write to bit 15:0
#define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK) |
APC_R4_ENCRYPT_ENABLE - APC memory region-4 encryption enable 0b1..Encryption enabled 0b0..No effect
#define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK) |
APC_R4_ENCRYPT_ENABLE - APC memory region-4 encryption enable 0b1..Encryption enabled 0b0..No effect
#define IOMUXC_LPSR_GPR_GPR22_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_LOCK_MASK) |
LOCK - Lock the write to bit 15:0
#define IOMUXC_LPSR_GPR_GPR22_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_LOCK_MASK) |
LOCK - Lock the write to bit 15:0
#define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK) |
APC_R5_ENCRYPT_ENABLE - APC memory region-5 encryption enable 0b1..Encryption enabled 0b0..No effect
#define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK) |
APC_R5_ENCRYPT_ENABLE - APC memory region-5 encryption enable 0b1..Encryption enabled 0b0..No effect
#define IOMUXC_LPSR_GPR_GPR23_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_LOCK_MASK) |
LOCK - Lock the write to bit 15:0
#define IOMUXC_LPSR_GPR_GPR23_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_LOCK_MASK) |
LOCK - Lock the write to bit 15:0
#define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK) |
APC_R6_ENCRYPT_ENABLE - APC memory region-6 encryption enable 0b1..Encryption enabled 0b0..No effect
#define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK) |
APC_R6_ENCRYPT_ENABLE - APC memory region-6 encryption enable 0b1..Encryption enabled 0b0..No effect
#define IOMUXC_LPSR_GPR_GPR24_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_LOCK_MASK) |
LOCK - Lock the write to bit 15:0
#define IOMUXC_LPSR_GPR_GPR24_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_LOCK_MASK) |
LOCK - Lock the write to bit 15:0
#define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK) |
APC_R7_ENCRYPT_ENABLE - APC memory region-7 encryption enable 0b1..Encryption enabled 0b0..No effect
#define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK) |
APC_R7_ENCRYPT_ENABLE - APC memory region-7 encryption enable 0b1..Encryption enabled 0b0..No effect
#define IOMUXC_LPSR_GPR_GPR25_APC_VALID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK) |
APC_VALID - APC global enable bit 0b1..Enable encryption for GPRx[APC_x_ENCRYPT_ENABLE] (valid for GPR2-GPR25) 0b0..No effect
#define IOMUXC_LPSR_GPR_GPR25_APC_VALID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK) |
APC_VALID - APC global enable bit 0b1..Enable encryption for GPRx[APC_x_ENCRYPT_ENABLE] (valid for GPR2-GPR25) 0b0..No effect
#define IOMUXC_LPSR_GPR_GPR25_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_LOCK_MASK) |
LOCK - Lock the write to bit 15:0
#define IOMUXC_LPSR_GPR_GPR25_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_LOCK_MASK) |
LOCK - Lock the write to bit 15:0
#define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK) |
CM7_INIT_VTOR - Vector table offset register out of reset. See the ARM v7-M Architecture Reference Manual for more information about the vector table offset register (VTOR).
#define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK) |
CM7_INIT_VTOR - Vector table offset register out of reset. See the ARM v7-M Architecture Reference Manual for more information about the vector table offset register (VTOR).
#define IOMUXC_LPSR_GPR_GPR26_DWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_MASK) |
DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden
#define IOMUXC_LPSR_GPR_GPR26_DWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_MASK) |
DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden
#define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK) |
DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked
#define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK) |
DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked
#define IOMUXC_LPSR_GPR_GPR26_FIELD_0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK) |
FIELD_0 - General purpose bits
#define IOMUXC_LPSR_GPR_GPR26_FIELD_0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK) |
FIELD_0 - General purpose bits
#define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK) |
APC_AC_R0_BOT - APC start address of memory region-0
#define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK) |
APC_AC_R0_BOT - APC start address of memory region-0
#define IOMUXC_LPSR_GPR_GPR2_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR2_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR33_DWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_MASK) |
DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden
#define IOMUXC_LPSR_GPR_GPR33_DWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_MASK) |
DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden
#define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK) |
DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked
#define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK) |
DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked
#define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK) |
M4_NMI_CLEAR - Clear CM4 NMI holding register
#define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK) |
M4_NMI_CLEAR - Clear CM4 NMI holding register
#define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK) |
USBPHY1_WAKEUP_IRQ_CLEAR - Clear USBPHY1 wakeup interrupt holding register
#define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK) |
USBPHY1_WAKEUP_IRQ_CLEAR - Clear USBPHY1 wakeup interrupt holding register
#define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK) |
USBPHY2_WAKEUP_IRQ_CLEAR - Clear USBPHY1 wakeup interrupt holding register
#define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK) |
USBPHY2_WAKEUP_IRQ_CLEAR - Clear USBPHY1 wakeup interrupt holding register
#define IOMUXC_LPSR_GPR_GPR34_DWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_MASK) |
DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden
#define IOMUXC_LPSR_GPR_GPR34_DWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_MASK) |
DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden
#define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK) |
DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked
#define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK) |
DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked
#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK) |
GPIO_LPSR_HIGH_RANGE - GPIO_LPSR IO bank supply voltage range selection
#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK) |
GPIO_LPSR_HIGH_RANGE - GPIO_LPSR IO bank supply voltage range selection
#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK) |
GPIO_LPSR_LOW_RANGE - GPIO_LPSR IO bank supply voltage range selection
#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK) |
GPIO_LPSR_LOW_RANGE - GPIO_LPSR IO bank supply voltage range selection
#define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK) |
M4_GPC_SLEEP_SEL - CM4 sleep request selection 0b0..CM4 SLEEPDEEP is sent to GPC 0b1..CM4 SLEEPING is sent to GPC
#define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK) |
M4_GPC_SLEEP_SEL - CM4 sleep request selection 0b0..CM4 SLEEPDEEP is sent to GPC 0b1..CM4 SLEEPING is sent to GPC
#define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK) |
M4_NMI_MASK - Mask CM4 NMI pin input 0b0..NMI input from IO to CM4 is not blocked 0b1..NMI input from IO to CM4 is blocked
#define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK) |
M4_NMI_MASK - Mask CM4 NMI pin input 0b0..NMI input from IO to CM4 is not blocked 0b1..NMI input from IO to CM4 is blocked
#define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK) |
M7_NMI_MASK - Mask CM7 NMI pin input 0b0..NMI input from IO to CM7 is not blocked 0b1..NMI input from IO to CM7 is blocked
#define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK) |
M7_NMI_MASK - Mask CM7 NMI pin input 0b0..NMI input from IO to CM7 is not blocked 0b1..NMI input from IO to CM7 is blocked
#define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK) |
SEC_ERR_RESP - Security error response enable 0b0..OKEY response 0b1..SLVError (default)
#define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK) |
SEC_ERR_RESP - Security error response enable 0b0..OKEY response 0b1..SLVError (default)
#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK) |
ADC1_IPG_DOZE - ADC1 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK) |
ADC1_IPG_DOZE - ADC1 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK) |
ADC1_IPG_STOP_MODE - ADC1 stop mode selection. This bitfield cannot change when ADC1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK) |
ADC1_IPG_STOP_MODE - ADC1 stop mode selection. This bitfield cannot change when ADC1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK) |
ADC1_STOP_REQ - ADC1 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK) |
ADC1_STOP_REQ - ADC1 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK) |
ADC2_IPG_DOZE - ADC2 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK) |
ADC2_IPG_DOZE - ADC2 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK) |
ADC2_IPG_STOP_MODE - ADC2 stop mode selection. This bitfield cannot change when ADC2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK) |
ADC2_IPG_STOP_MODE - ADC2 stop mode selection. This bitfield cannot change when ADC2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK) |
ADC2_STOP_REQ - ADC2 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK) |
ADC2_STOP_REQ - ADC2 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK) |
CAAM_IPG_DOZE - CAN3 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK) |
CAAM_IPG_DOZE - CAN3 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK) |
CAAM_STOP_REQ - CAAM stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK) |
CAAM_STOP_REQ - CAAM stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK) |
CAN1_IPG_DOZE - CAN1 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK) |
CAN1_IPG_DOZE - CAN1 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK) |
CAN1_STOP_REQ - CAN1 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK) |
CAN1_STOP_REQ - CAN1 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK) |
CAN2_IPG_DOZE - CAN2 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK) |
CAN2_IPG_DOZE - CAN2 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK) |
CAN2_STOP_REQ - CAN2 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK) |
CAN2_STOP_REQ - CAN2 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK) |
CAN3_IPG_DOZE - CAN3 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK) |
CAN3_IPG_DOZE - CAN3 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK) |
CAN3_STOP_REQ - CAN3 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK) |
CAN3_STOP_REQ - CAN3 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_DWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_MASK) |
DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden
#define IOMUXC_LPSR_GPR_GPR35_DWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_MASK) |
DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden
#define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK) |
DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked
#define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK) |
DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked
#define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK) |
EDMA_LPSR_STOP_REQ - EDMA_LPSR stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK) |
EDMA_LPSR_STOP_REQ - EDMA_LPSR stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK) |
EDMA_STOP_REQ - EDMA stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK) |
EDMA_STOP_REQ - EDMA stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK) |
ENET1G_IPG_DOZE - ENET1G doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK) |
ENET1G_IPG_DOZE - ENET1G doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK) |
ENET1G_STOP_REQ - ENET1G stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK) |
ENET1G_STOP_REQ - ENET1G stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK) |
ENET_IPG_DOZE - ENET doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK) |
ENET_IPG_DOZE - ENET doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK) |
ENET_STOP_REQ - ENET stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK) |
ENET_STOP_REQ - ENET stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK) |
FLEXIO1_IPG_DOZE - FLEXIO2 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK) |
FLEXIO1_IPG_DOZE - FLEXIO2 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK) |
FLEXIO2_IPG_DOZE - FLEXIO2 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK) |
FLEXIO2_IPG_DOZE - FLEXIO2 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK) |
FLEXSPI1_IPG_DOZE - FLEXSPI1 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK) |
FLEXSPI1_IPG_DOZE - FLEXSPI1 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK) |
FLEXSPI1_STOP_REQ - FLEXSPI1 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK) |
FLEXSPI1_STOP_REQ - FLEXSPI1 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK) |
FLEXSPI2_IPG_DOZE - FLEXSPI2 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK) |
FLEXSPI2_IPG_DOZE - FLEXSPI2 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK) |
FLEXSPI2_STOP_REQ - FLEXSPI2 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK) |
FLEXSPI2_STOP_REQ - FLEXSPI2 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR36_DWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_MASK) |
DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden
#define IOMUXC_LPSR_GPR_GPR36_DWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_MASK) |
DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden
#define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK) |
DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked
#define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK) |
DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked
#define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK) |
GPT1_IPG_DOZE - GPT1 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK) |
GPT1_IPG_DOZE - GPT1 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK) |
GPT2_IPG_DOZE - GPT2 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK) |
GPT2_IPG_DOZE - GPT2 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK) |
GPT3_IPG_DOZE - GPT3 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK) |
GPT3_IPG_DOZE - GPT3 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK) |
GPT4_IPG_DOZE - GPT4 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK) |
GPT4_IPG_DOZE - GPT4 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK) |
GPT5_IPG_DOZE - GPT5 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK) |
GPT5_IPG_DOZE - GPT5 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK) |
GPT6_IPG_DOZE - GPT6 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK) |
GPT6_IPG_DOZE - GPT6 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK) |
LPI2C1_IPG_DOZE - LPI2C1 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK) |
LPI2C1_IPG_DOZE - LPI2C1 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK) |
LPI2C1_IPG_STOP_MODE - LPI2C1 stop mode selection. This bitfield cannot change when LPI2C1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK) |
LPI2C1_IPG_STOP_MODE - LPI2C1 stop mode selection. This bitfield cannot change when LPI2C1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK) |
LPI2C1_STOP_REQ - LPI2C1 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK) |
LPI2C1_STOP_REQ - LPI2C1 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK) |
LPI2C2_IPG_DOZE - LPI2C2 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK) |
LPI2C2_IPG_DOZE - LPI2C2 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK) |
LPI2C2_IPG_STOP_MODE - LPI2C2 stop mode selection. This bitfield cannot change when LPI2C2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK) |
LPI2C2_IPG_STOP_MODE - LPI2C2 stop mode selection. This bitfield cannot change when LPI2C2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK) |
LPI2C2_STOP_REQ - LPI2C2 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK) |
LPI2C2_STOP_REQ - LPI2C2 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK) |
LPI2C3_IPG_DOZE - LPI2C3 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK) |
LPI2C3_IPG_DOZE - LPI2C3 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK) |
LPI2C3_IPG_STOP_MODE - LPI2C3 stop mode selection. This bitfield cannot change when LPI2C3_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK) |
LPI2C3_IPG_STOP_MODE - LPI2C3 stop mode selection. This bitfield cannot change when LPI2C3_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK) |
LPI2C3_STOP_REQ - LPI2C3 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK) |
LPI2C3_STOP_REQ - LPI2C3 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK) |
LPI2C4_IPG_DOZE - LPI2C4 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK) |
LPI2C4_IPG_DOZE - LPI2C4 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK) |
LPI2C4_IPG_STOP_MODE - LPI2C4 stop mode selection. This bitfield cannot change when LPI2C4_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK) |
LPI2C4_IPG_STOP_MODE - LPI2C4 stop mode selection. This bitfield cannot change when LPI2C4_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK) |
LPI2C4_STOP_REQ - LPI2C4 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK) |
LPI2C4_STOP_REQ - LPI2C4 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK) |
LPI2C5_IPG_DOZE - LPI2C5 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK) |
LPI2C5_IPG_DOZE - LPI2C5 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK) |
LPI2C5_IPG_STOP_MODE - LPI2C5 stop mode selection. This bitfield cannot change when LPI2C5_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK) |
LPI2C5_IPG_STOP_MODE - LPI2C5 stop mode selection. This bitfield cannot change when LPI2C5_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK) |
LPI2C5_STOP_REQ - LPI2C5 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK) |
LPI2C5_STOP_REQ - LPI2C5 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK) |
LPI2C6_IPG_DOZE - LPI2C6 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK) |
LPI2C6_IPG_DOZE - LPI2C6 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK) |
LPI2C6_IPG_STOP_MODE - LPI2C6 stop mode selection. This bitfield cannot change when LPI2C6_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK) |
LPI2C6_IPG_STOP_MODE - LPI2C6 stop mode selection. This bitfield cannot change when LPI2C6_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK) |
LPI2C6_STOP_REQ - LPI2C6 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK) |
LPI2C6_STOP_REQ - LPI2C6 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK) |
LPSPI1_IPG_DOZE - LPSPI1 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK) |
LPSPI1_IPG_DOZE - LPSPI1 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK) |
LPSPI1_IPG_STOP_MODE - LPSPI1 stop mode selection. This bitfield cannot change when LPSPI1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK) |
LPSPI1_IPG_STOP_MODE - LPSPI1 stop mode selection. This bitfield cannot change when LPSPI1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK) |
LPSPI1_STOP_REQ - LPSPI1 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK) |
LPSPI1_STOP_REQ - LPSPI1 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR37_DWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_MASK) |
DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden
#define IOMUXC_LPSR_GPR_GPR37_DWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_MASK) |
DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden
#define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK) |
DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked
#define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK) |
DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK) |
LPSPI2_IPG_DOZE - LPSPI2 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK) |
LPSPI2_IPG_DOZE - LPSPI2 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK) |
LPSPI2_IPG_STOP_MODE - LPSPI2 stop mode selection. This bitfield cannot change when LPSPI2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK) |
LPSPI2_IPG_STOP_MODE - LPSPI2 stop mode selection. This bitfield cannot change when LPSPI2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK) |
LPSPI2_STOP_REQ - LPSPI2 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK) |
LPSPI2_STOP_REQ - LPSPI2 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK) |
LPSPI3_IPG_DOZE - LPSPI3 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK) |
LPSPI3_IPG_DOZE - LPSPI3 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK) |
LPSPI3_IPG_STOP_MODE - LPSPI3 stop mode selection. This bitfield cannot change when LPSPI3_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK) |
LPSPI3_IPG_STOP_MODE - LPSPI3 stop mode selection. This bitfield cannot change when LPSPI3_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK) |
LPSPI3_STOP_REQ - LPSPI3 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK) |
LPSPI3_STOP_REQ - LPSPI3 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK) |
LPSPI4_IPG_DOZE - LPSPI4 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK) |
LPSPI4_IPG_DOZE - LPSPI4 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK) |
LPSPI4_IPG_STOP_MODE - LPSPI4 stop mode selection. This bitfield cannot change when LPSPI4_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK) |
LPSPI4_IPG_STOP_MODE - LPSPI4 stop mode selection. This bitfield cannot change when LPSPI4_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK) |
LPSPI4_STOP_REQ - LPSPI4 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK) |
LPSPI4_STOP_REQ - LPSPI4 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK) |
LPSPI5_IPG_DOZE - LPSPI5 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK) |
LPSPI5_IPG_DOZE - LPSPI5 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK) |
LPSPI5_IPG_STOP_MODE - LPSPI5 stop mode selection. This bitfield cannot change when LPSPI5_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK) |
LPSPI5_IPG_STOP_MODE - LPSPI5 stop mode selection. This bitfield cannot change when LPSPI5_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK) |
LPSPI5_STOP_REQ - LPSPI5 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK) |
LPSPI5_STOP_REQ - LPSPI5 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK) |
LPSPI6_IPG_DOZE - LPSPI6 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK) |
LPSPI6_IPG_DOZE - LPSPI6 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK) |
LPSPI6_IPG_STOP_MODE - LPSPI6 stop mode selection. This bitfield cannot change when LPSPI6_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK) |
LPSPI6_IPG_STOP_MODE - LPSPI6 stop mode selection. This bitfield cannot change when LPSPI6_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK) |
LPSPI6_STOP_REQ - LPSPI6 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK) |
LPSPI6_STOP_REQ - LPSPI6 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK) |
LPUART1_IPG_DOZE - LPUART1 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK) |
LPUART1_IPG_DOZE - LPUART1 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK) |
LPUART1_IPG_STOP_MODE - LPUART1 stop mode selection. This bitfield cannot change when LPUART1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK) |
LPUART1_IPG_STOP_MODE - LPUART1 stop mode selection. This bitfield cannot change when LPUART1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK) |
LPUART1_STOP_REQ - LPUART1 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK) |
LPUART1_STOP_REQ - LPUART1 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK) |
LPUART2_IPG_DOZE - LPUART2 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK) |
LPUART2_IPG_DOZE - LPUART2 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK) |
LPUART2_IPG_STOP_MODE - LPUART2 stop mode selection. This bitfield cannot change when LPUART2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK) |
LPUART2_IPG_STOP_MODE - LPUART2 stop mode selection. This bitfield cannot change when LPUART2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK) |
LPUART2_STOP_REQ - LPUART2 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK) |
LPUART2_STOP_REQ - LPUART2 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK) |
LPUART3_IPG_DOZE - LPUART3 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK) |
LPUART3_IPG_DOZE - LPUART3 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK) |
LPUART3_IPG_STOP_MODE - LPUART3 stop mode selection. This bitfield cannot change when LPUART3_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK) |
LPUART3_IPG_STOP_MODE - LPUART3 stop mode selection. This bitfield cannot change when LPUART3_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK) |
LPUART3_STOP_REQ - LPUART3 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK) |
LPUART3_STOP_REQ - LPUART3 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK) |
LPUART4_IPG_DOZE - LPUART4 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK) |
LPUART4_IPG_DOZE - LPUART4 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK) |
LPUART4_IPG_STOP_MODE - LPUART4 stop mode selection. This bitfield cannot change when LPUART4_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK) |
LPUART4_IPG_STOP_MODE - LPUART4 stop mode selection. This bitfield cannot change when LPUART4_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK) |
LPUART4_STOP_REQ - LPUART4 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK) |
LPUART4_STOP_REQ - LPUART4 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR38_DWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_MASK) |
DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden
#define IOMUXC_LPSR_GPR_GPR38_DWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_MASK) |
DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden
#define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK) |
DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked
#define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK) |
DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK) |
LPUART10_IPG_DOZE - LPUART10 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK) |
LPUART10_IPG_DOZE - LPUART10 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK) |
LPUART10_IPG_STOP_MODE - LPUART10 stop mode selection. This bitfield cannot change when LPUART10_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK) |
LPUART10_IPG_STOP_MODE - LPUART10 stop mode selection. This bitfield cannot change when LPUART10_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK) |
LPUART10_STOP_REQ - LPUART10 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK) |
LPUART10_STOP_REQ - LPUART10 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK) |
LPUART11_IPG_DOZE - LPUART11 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK) |
LPUART11_IPG_DOZE - LPUART11 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK) |
LPUART11_IPG_STOP_MODE - LPUART11 stop mode selection. This bitfield cannot change when LPUART11_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK) |
LPUART11_IPG_STOP_MODE - LPUART11 stop mode selection. This bitfield cannot change when LPUART11_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK) |
LPUART11_STOP_REQ - LPUART11 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK) |
LPUART11_STOP_REQ - LPUART11 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK) |
LPUART12_IPG_DOZE - LPUART12 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK) |
LPUART12_IPG_DOZE - LPUART12 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK) |
LPUART12_IPG_STOP_MODE - LPUART12 stop mode selection. This bitfield cannot change when LPUART12_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK) |
LPUART12_IPG_STOP_MODE - LPUART12 stop mode selection. This bitfield cannot change when LPUART12_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK) |
LPUART12_STOP_REQ - LPUART12 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK) |
LPUART12_STOP_REQ - LPUART12 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK) |
LPUART5_IPG_DOZE - LPUART5 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK) |
LPUART5_IPG_DOZE - LPUART5 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK) |
LPUART5_IPG_STOP_MODE - LPUART5 stop mode selection. This bitfield cannot change when LPUART5_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK) |
LPUART5_IPG_STOP_MODE - LPUART5 stop mode selection. This bitfield cannot change when LPUART5_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK) |
LPUART5_STOP_REQ - LPUART5 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK) |
LPUART5_STOP_REQ - LPUART5 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK) |
LPUART6_IPG_DOZE - LPUART6 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK) |
LPUART6_IPG_DOZE - LPUART6 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK) |
LPUART6_IPG_STOP_MODE - LPUART6 stop mode selection. This bitfield cannot change when LPUART6_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK) |
LPUART6_IPG_STOP_MODE - LPUART6 stop mode selection. This bitfield cannot change when LPUART6_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK) |
LPUART6_STOP_REQ - LPUART6 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK) |
LPUART6_STOP_REQ - LPUART6 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK) |
LPUART7_IPG_DOZE - LPUART7 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK) |
LPUART7_IPG_DOZE - LPUART7 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK) |
LPUART7_IPG_STOP_MODE - LPUART7 stop mode selection. This bitfield cannot change when LPUART7_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK) |
LPUART7_IPG_STOP_MODE - LPUART7 stop mode selection. This bitfield cannot change when LPUART7_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK) |
LPUART7_STOP_REQ - LPUART7 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK) |
LPUART7_STOP_REQ - LPUART7 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK) |
LPUART8_IPG_DOZE - LPUART8 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK) |
LPUART8_IPG_DOZE - LPUART8 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK) |
LPUART8_IPG_STOP_MODE - LPUART8 stop mode selection. This bitfield cannot change when LPUART8_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK) |
LPUART8_IPG_STOP_MODE - LPUART8 stop mode selection. This bitfield cannot change when LPUART8_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK) |
LPUART8_STOP_REQ - LPUART8 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK) |
LPUART8_STOP_REQ - LPUART8 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK) |
LPUART9_IPG_DOZE - LPUART9 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK) |
LPUART9_IPG_DOZE - LPUART9 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK) |
LPUART9_IPG_STOP_MODE - LPUART9 stop mode selection. This bitfield cannot change when LPUART9_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK) |
LPUART9_IPG_STOP_MODE - LPUART9 stop mode selection. This bitfield cannot change when LPUART9_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK) |
LPUART9_STOP_REQ - LPUART9 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK) |
LPUART9_STOP_REQ - LPUART9 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK) |
MIC_IPG_DOZE - MIC doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK) |
MIC_IPG_DOZE - MIC doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK) |
MIC_IPG_STOP_MODE - MIC stop mode selection. This bitfield cannot change when MIC_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK) |
MIC_IPG_STOP_MODE - MIC stop mode selection. This bitfield cannot change when MIC_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
#define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK) |
MIC_STOP_REQ - MIC stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK) |
MIC_STOP_REQ - MIC stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_DWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_MASK) |
DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden
#define IOMUXC_LPSR_GPR_GPR39_DWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_MASK) |
DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden
#define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK) |
DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked
#define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK) |
DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK) |
FLEXIO1_STOP_REQ_BUS - FLEXIO1 bus clock domain stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK) |
FLEXIO1_STOP_REQ_BUS - FLEXIO1 bus clock domain stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK) |
FLEXIO1_STOP_REQ_PER - FLEXIO1 peripheral clock domain stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK) |
FLEXIO1_STOP_REQ_PER - FLEXIO1 peripheral clock domain stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK) |
FLEXIO2_STOP_REQ_BUS - FLEXIO2 bus clock domain stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK) |
FLEXIO2_STOP_REQ_BUS - FLEXIO2 bus clock domain stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK) |
FLEXIO2_STOP_REQ_PER - FLEXIO2 peripheral clock domain stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK) |
FLEXIO2_STOP_REQ_PER - FLEXIO2 peripheral clock domain stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK) |
PIT1_STOP_REQ - PIT1 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK) |
PIT1_STOP_REQ - PIT1 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK) |
PIT2_STOP_REQ - PIT2 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK) |
PIT2_STOP_REQ - PIT2 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK) |
SAI1_STOP_REQ - SAI1 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK) |
SAI1_STOP_REQ - SAI1 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK) |
SAI2_STOP_REQ - SAI2 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK) |
SAI2_STOP_REQ - SAI2 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK) |
SAI3_STOP_REQ - SAI3 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK) |
SAI3_STOP_REQ - SAI3 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK) |
SAI4_STOP_REQ - SAI4 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK) |
SAI4_STOP_REQ - SAI4 stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK) |
SEMC_STOP_REQ - SEMC stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK) |
SEMC_STOP_REQ - SEMC stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK) |
SIM1_IPG_DOZE - SIM1 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK) |
SIM1_IPG_DOZE - SIM1 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK) |
SIM2_IPG_DOZE - SIM2 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK) |
SIM2_IPG_DOZE - SIM2 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK) |
SNVS_HP_IPG_DOZE - SNVS_HP doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK) |
SNVS_HP_IPG_DOZE - SNVS_HP doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK) |
SNVS_HP_STOP_REQ - SNVS_HP stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK) |
SNVS_HP_STOP_REQ - SNVS_HP stop request 0b0..Stop request off 0b1..Stop request on
#define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK) |
WDOG1_IPG_DOZE - WDOG1 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK) |
WDOG1_IPG_DOZE - WDOG1 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK) |
WDOG2_IPG_DOZE - WDOG2 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK) |
WDOG2_IPG_DOZE - WDOG2 doze mode 0b0..Not in doze mode 0b1..In doze mode
#define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK) |
APC_AC_R0_TOP - APC end address of memory region-0
#define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK) |
APC_AC_R0_TOP - APC end address of memory region-0
#define IOMUXC_LPSR_GPR_GPR3_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR3_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK) |
ADC1_STOP_ACK - ADC1 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK) |
ADC1_STOP_ACK - ADC1 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK) |
ADC2_STOP_ACK - ADC2 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK) |
ADC2_STOP_ACK - ADC2 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK) |
CAAM_STOP_ACK - CAAM stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK) |
CAAM_STOP_ACK - CAAM stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK) |
CAN1_STOP_ACK - CAN1 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK) |
CAN1_STOP_ACK - CAN1 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK) |
CAN2_STOP_ACK - CAN2 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK) |
CAN2_STOP_ACK - CAN2 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK) |
CAN3_STOP_ACK - CAN3 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK) |
CAN3_STOP_ACK - CAN3 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK) |
EDMA_LPSR_STOP_ACK - EDMA_LPSR stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK) |
EDMA_LPSR_STOP_ACK - EDMA_LPSR stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK) |
EDMA_STOP_ACK - EDMA stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK) |
EDMA_STOP_ACK - EDMA stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK) |
ENET1G_STOP_ACK - ENET1G stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK) |
ENET1G_STOP_ACK - ENET1G stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK) |
ENET_STOP_ACK - ENET stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK) |
ENET_STOP_ACK - ENET stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK) |
FLEXSPI1_STOP_ACK - FLEXSPI1 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK) |
FLEXSPI1_STOP_ACK - FLEXSPI1 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK) |
FLEXSPI2_STOP_ACK - FLEXSPI2 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK) |
FLEXSPI2_STOP_ACK - FLEXSPI2 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK) |
LPI2C1_STOP_ACK - LPI2C1 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK) |
LPI2C1_STOP_ACK - LPI2C1 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK) |
LPI2C2_STOP_ACK - LPI2C2 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK) |
LPI2C2_STOP_ACK - LPI2C2 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK) |
LPI2C3_STOP_ACK - LPI2C3 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK) |
LPI2C3_STOP_ACK - LPI2C3 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK) |
LPI2C4_STOP_ACK - LPI2C4 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK) |
LPI2C4_STOP_ACK - LPI2C4 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK) |
LPI2C5_STOP_ACK - LPI2C5 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK) |
LPI2C5_STOP_ACK - LPI2C5 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK) |
LPI2C6_STOP_ACK - LPI2C6 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK) |
LPI2C6_STOP_ACK - LPI2C6 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK) |
LPSPI1_STOP_ACK - LPSPI1 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK) |
LPSPI1_STOP_ACK - LPSPI1 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK) |
LPSPI2_STOP_ACK - LPSPI2 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK) |
LPSPI2_STOP_ACK - LPSPI2 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK) |
LPSPI3_STOP_ACK - LPSPI3 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK) |
LPSPI3_STOP_ACK - LPSPI3 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK) |
LPSPI4_STOP_ACK - LPSPI4 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK) |
LPSPI4_STOP_ACK - LPSPI4 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK) |
LPSPI5_STOP_ACK - LPSPI5 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK) |
LPSPI5_STOP_ACK - LPSPI5 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK) |
LPSPI6_STOP_ACK - LPSPI6 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK) |
LPSPI6_STOP_ACK - LPSPI6 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK) |
LPUART1_STOP_ACK - LPUART1 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK) |
LPUART1_STOP_ACK - LPUART1 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK) |
LPUART2_STOP_ACK - LPUART2 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK) |
LPUART2_STOP_ACK - LPUART2 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK) |
LPUART3_STOP_ACK - LPUART3 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK) |
LPUART3_STOP_ACK - LPUART3 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK) |
LPUART4_STOP_ACK - LPUART4 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK) |
LPUART4_STOP_ACK - LPUART4 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK) |
LPUART5_STOP_ACK - LPUART5 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK) |
LPUART5_STOP_ACK - LPUART5 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK) |
LPUART6_STOP_ACK - LPUART6 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK) |
LPUART6_STOP_ACK - LPUART6 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK) |
LPUART7_STOP_ACK - LPUART7 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK) |
LPUART7_STOP_ACK - LPUART7 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK) |
LPUART8_STOP_ACK - LPUART8 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK) |
LPUART8_STOP_ACK - LPUART8 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK) |
FLEXIO1_STOP_ACK_BUS - FLEXIO1 stop acknowledge of bus clock domain
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK) |
FLEXIO1_STOP_ACK_BUS - FLEXIO1 stop acknowledge of bus clock domain
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK) |
FLEXIO1_STOP_ACK_PER - FLEXIO1 stop acknowledge of peripheral clock domain
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK) |
FLEXIO1_STOP_ACK_PER - FLEXIO1 stop acknowledge of peripheral clock domain
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK) |
FLEXIO2_STOP_ACK_BUS - FLEXIO2 stop acknowledge of bus clock domain
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK) |
FLEXIO2_STOP_ACK_BUS - FLEXIO2 stop acknowledge of bus clock domain
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK) |
FLEXIO2_STOP_ACK_PER - FLEXIO2 stop acknowledge of peripheral clock domain
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK) |
FLEXIO2_STOP_ACK_PER - FLEXIO2 stop acknowledge of peripheral clock domain
#define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK) |
LPUART10_STOP_ACK - LPUART10 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK) |
LPUART10_STOP_ACK - LPUART10 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK) |
LPUART11_STOP_ACK - LPUART11 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK) |
LPUART11_STOP_ACK - LPUART11 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK) |
LPUART12_STOP_ACK - LPUART12 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK) |
LPUART12_STOP_ACK - LPUART12 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK) |
LPUART9_STOP_ACK - LPUART9 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK) |
LPUART9_STOP_ACK - LPUART9 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK) |
MIC_STOP_ACK - MIC stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK) |
MIC_STOP_ACK - MIC stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK) |
PIT1_STOP_ACK - PIT1 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK) |
PIT1_STOP_ACK - PIT1 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK) |
PIT2_STOP_ACK - PIT2 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK) |
PIT2_STOP_ACK - PIT2 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK) |
ROM_READ_LOCKED - ROM read lock status bit
#define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK) |
ROM_READ_LOCKED - ROM read lock status bit
#define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK) |
SAI1_STOP_ACK - SAI1 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK) |
SAI1_STOP_ACK - SAI1 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK) |
SAI2_STOP_ACK - SAI2 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK) |
SAI2_STOP_ACK - SAI2 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK) |
SAI3_STOP_ACK - SAI3 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK) |
SAI3_STOP_ACK - SAI3 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK) |
SAI4_STOP_ACK - SAI4 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK) |
SAI4_STOP_ACK - SAI4 stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK) |
SEMC_STOP_ACK - SEMC stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK) |
SEMC_STOP_ACK - SEMC stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK) |
SNVS_HP_STOP_ACK - SNVS_HP stop acknowledge
#define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK) |
SNVS_HP_STOP_ACK - SNVS_HP stop acknowledge
#define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK) |
APC_AC_R1_BOT - APC start address of memory region-1
#define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK) |
APC_AC_R1_BOT - APC start address of memory region-1
#define IOMUXC_LPSR_GPR_GPR4_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR4_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK) |
APC_AC_R1_TOP - APC end address of memory region-1
#define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK) |
APC_AC_R1_TOP - APC end address of memory region-1
#define IOMUXC_LPSR_GPR_GPR5_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR5_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_MASK) |
APC_AC_R2_BOT - APC start address of memory region-2
#define IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_MASK) |
APC_AC_R2_BOT - APC start address of memory region-2
#define IOMUXC_LPSR_GPR_GPR6_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR6_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR6_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR6_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR6_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR6_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK) |
APC_AC_R2_TOP - APC end address of memory region-2
#define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK) |
APC_AC_R2_TOP - APC end address of memory region-2
#define IOMUXC_LPSR_GPR_GPR7_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR7_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK) |
APC_AC_R3_BOT - APC start address of memory region-3
#define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK) |
APC_AC_R3_BOT - APC start address of memory region-3
#define IOMUXC_LPSR_GPR_GPR8_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR8_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK) |
APC_AC_R3_TOP - APC end address of memory region-3
#define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK) |
APC_AC_R3_TOP - APC end address of memory region-3
#define IOMUXC_LPSR_GPR_GPR9_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked
#define IOMUXC_LPSR_GPR_GPR9_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked