20#ifndef STM32H7xx_HAL_DMA_EX_H
21#define STM32H7xx_HAL_DMA_EX_H
112#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0U
113#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 1U
114#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 2U
115#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 3U
116#define HAL_DMAMUX1_SYNC_LPTIM2_OUT 4U
117#define HAL_DMAMUX1_SYNC_LPTIM3_OUT 5U
118#define HAL_DMAMUX1_SYNC_EXTI0 6U
119#define HAL_DMAMUX1_SYNC_TIM12_TRGO 7U
121#define HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0U
122#define HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 1U
123#define HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 2U
124#define HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 3U
125#define HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 4U
126#define HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 5U
127#define HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP 6U
128#define HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP 7U
129#define HAL_DMAMUX2_SYNC_LPTIM2_OUT 8U
130#define HAL_DMAMUX2_SYNC_LPTIM3_OUT 9U
131#define HAL_DMAMUX2_SYNC_I2C4_WKUP 10U
132#define HAL_DMAMUX2_SYNC_SPI6_WKUP 11U
133#define HAL_DMAMUX2_SYNC_COMP1_OUT 12U
134#define HAL_DMAMUX2_SYNC_RTC_WKUP 13U
135#define HAL_DMAMUX2_SYNC_EXTI0 14U
136#define HAL_DMAMUX2_SYNC_EXTI2 15U
147#define HAL_DMAMUX_SYNC_NO_EVENT 0x00000000U
148#define HAL_DMAMUX_SYNC_RISING DMAMUX_CxCR_SPOL_0
149#define HAL_DMAMUX_SYNC_FALLING DMAMUX_CxCR_SPOL_1
150#define HAL_DMAMUX_SYNC_RISING_FALLING DMAMUX_CxCR_SPOL
162#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U
163#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U
164#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U
165#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U
166#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U
167#define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U
168#define HAL_DMAMUX1_REQ_GEN_EXTI0 6U
169#define HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U
171#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U
172#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U
173#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U
174#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U
175#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U
176#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U
177#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U
178#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U
179#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U
180#define HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U
181#define HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U
182#define HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U
183#define HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U
185#define HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 13U
188#define HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 14U
190#define HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U
191#define HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U
192#define HAL_DMAMUX2_REQ_GEN_COMP1_OUT 17U
193#define HAL_DMAMUX2_REQ_GEN_COMP2_OUT 18U
194#define HAL_DMAMUX2_REQ_GEN_RTC_WKUP 19U
195#define HAL_DMAMUX2_REQ_GEN_EXTI0 20U
196#define HAL_DMAMUX2_REQ_GEN_EXTI2 21U
197#define HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U
198#define HAL_DMAMUX2_REQ_GEN_SPI6_IT 23U
199#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U
200#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U
202#define HAL_DMAMUX2_REQ_GEN_ADC3_IT 26U
203#define HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 27U
205#define HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U
206#define HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U
218#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U
219#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0
220#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1
221#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL
268#define IS_DMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO)
269#define IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2)
271#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
273#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
274 ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \
275 ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \
276 ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
278#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
280#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \
283#define IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_TIM12_TRGO)
284#define IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT)
286#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
288#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
289 ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \
290 ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
291 ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
HAL_DMA_MemoryTypeDef
HAL DMA Memory definition.
Definition: stm32h7xx_hal_dma_ex.h:49
@ MEMORY1
Definition: stm32h7xx_hal_dma_ex.h:51
@ MEMORY0
Definition: stm32h7xx_hal_dma_ex.h:50
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
HAL DMAMUX request generator parameters structure definition.
Definition: stm32h7xx_hal_dma_ex.h:83
uint32_t Polarity
Definition: stm32h7xx_hal_dma_ex.h:87
uint32_t RequestNumber
Definition: stm32h7xx_hal_dma_ex.h:90
uint32_t SignalID
Definition: stm32h7xx_hal_dma_ex.h:84
HAL DMAMUX Synchronization configuration structure definition.
Definition: stm32h7xx_hal_dma_ex.h:59
uint32_t RequestNumber
Definition: stm32h7xx_hal_dma_ex.h:73
FunctionalState EventEnable
Definition: stm32h7xx_hal_dma_ex.h:70
FunctionalState SyncEnable
Definition: stm32h7xx_hal_dma_ex.h:66
uint32_t SyncSignalID
Definition: stm32h7xx_hal_dma_ex.h:60
uint32_t SyncPolarity
Definition: stm32h7xx_hal_dma_ex.h:63
DMA handle Structure definition.
Definition: stm32h7xx_hal_dma.h:138