38#ifndef _RTEMS_SCORE_CPU_H
39#define _RTEMS_SCORE_CPU_H
83 #if defined(RTEMS_SMP)
84 #define SPARC_USE_SYNCHRONOUS_FP_SWITCH
86 #define SPARC_USE_LAZY_FP_SWITCH
100#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
110#define CPU_ISR_PASSES_FRAME_POINTER FALSE
120#if ( SPARC_HAS_FPU == 1 ) && !defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH)
121 #define CPU_HARDWARE_FP TRUE
123 #define CPU_HARDWARE_FP FALSE
130#define CPU_SOFTWARE_FP FALSE
140#define CPU_ALL_TASKS_ARE_FP FALSE
151#define CPU_IDLE_TASK_IS_FP FALSE
153#define CPU_USE_DEFERRED_FP_SWITCH FALSE
155#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
166#define CPU_STACK_GROWS_UP FALSE
169#define CPU_CACHE_LINE_BYTES 64
171#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
180#define CPU_MODES_INTERRUPT_MASK 0x0000000F
248#define CPU_STACK_FRAME_L0_OFFSET 0x00
250#define CPU_STACK_FRAME_L1_OFFSET 0x04
252#define CPU_STACK_FRAME_L2_OFFSET 0x08
254#define CPU_STACK_FRAME_L3_OFFSET 0x0c
256#define CPU_STACK_FRAME_L4_OFFSET 0x10
258#define CPU_STACK_FRAME_L5_OFFSET 0x14
260#define CPU_STACK_FRAME_L6_OFFSET 0x18
262#define CPU_STACK_FRAME_L7_OFFSET 0x1c
264#define CPU_STACK_FRAME_I0_OFFSET 0x20
266#define CPU_STACK_FRAME_I1_OFFSET 0x24
268#define CPU_STACK_FRAME_I2_OFFSET 0x28
270#define CPU_STACK_FRAME_I3_OFFSET 0x2c
272#define CPU_STACK_FRAME_I4_OFFSET 0x30
274#define CPU_STACK_FRAME_I5_OFFSET 0x34
276#define CPU_STACK_FRAME_I6_FP_OFFSET 0x38
278#define CPU_STACK_FRAME_I7_OFFSET 0x3c
280#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x40
282#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x44
284#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x48
286#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x4c
288#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0x50
290#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0x54
292#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0x58
294#define CPU_STACK_FRAME_PAD0_OFFSET 0x5c
296#define CPU_MAXIMUM_PROCESSORS 32
396 uint32_t isr_dispatch_disable;
398#if defined(SPARC_USE_LAZY_FP_SWITCH)
402#if defined(RTEMS_SMP)
403 volatile uint32_t is_executing;
412#define _CPU_Context_Get_SP( _context ) \
416 static inline bool _CPU_Context_Get_is_executing(
423 static inline void _CPU_Context_Set_is_executing(
428 context->is_executing = is_executing;
439#define G5_OFFSET 0x00
441#define G7_OFFSET 0x04
444#define L0_OFFSET 0x08
446#define L1_OFFSET 0x0C
448#define L2_OFFSET 0x10
450#define L3_OFFSET 0x14
452#define L4_OFFSET 0x18
454#define L5_OFFSET 0x1C
456#define L6_OFFSET 0x20
458#define L7_OFFSET 0x24
461#define I0_OFFSET 0x28
463#define I1_OFFSET 0x2C
465#define I2_OFFSET 0x30
467#define I3_OFFSET 0x34
469#define I4_OFFSET 0x38
471#define I5_OFFSET 0x3C
473#define I6_FP_OFFSET 0x40
475#define I7_OFFSET 0x44
478#define O6_SP_OFFSET 0x48
480#define O7_OFFSET 0x4C
483#define PSR_OFFSET 0x50
485#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x54
487#if defined(RTEMS_SMP)
488 #define SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x58
541#define FO_F1_OFFSET 0x00
543#define F2_F3_OFFSET 0x08
545#define F4_F5_OFFSET 0x10
547#define F6_F7_OFFSET 0x18
549#define F8_F9_OFFSET 0x20
551#define F1O_F11_OFFSET 0x28
553#define F12_F13_OFFSET 0x30
555#define F14_F15_OFFSET 0x38
557#define F16_F17_OFFSET 0x40
559#define F18_F19_OFFSET 0x48
561#define F2O_F21_OFFSET 0x50
563#define F22_F23_OFFSET 0x58
565#define F24_F25_OFFSET 0x60
567#define F26_F27_OFFSET 0x68
569#define F28_F29_OFFSET 0x70
571#define F3O_F31_OFFSET 0x78
573#define FSR_OFFSET 0x80
576#define CONTEXT_CONTROL_FP_SIZE 0x84
671#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
680#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
705#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256
711#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511
717#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
727#define CPU_STACK_MINIMUM_SIZE (1024*4)
732#define CPU_SIZEOF_POINTER 4
740#define CPU_ALIGNMENT 8
753#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
759#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
761#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
777#define _CPU_ISR_Disable( _level ) \
778 (_level) = sparc_disable_interrupts()
785#define _CPU_ISR_Enable( _level ) \
786 sparc_enable_interrupts( _level )
794#define _CPU_ISR_Flash( _level ) \
795 sparc_flash_interrupts( _level )
797#define _CPU_ISR_Is_enabled( _isr_cookie ) \
798 sparc_interrupt_is_enabled( _isr_cookie )
800static inline bool _CPU_ISR_Is_enabled( uint32_t level )
810#define _CPU_ISR_Set_level( _newlevel ) \
811 sparc_enable_interrupts( _newlevel << 8)
847void _CPU_Context_Initialize(
849 uint32_t *stack_base,
870#define _CPU_Context_Initialization_at_thread_begin() \
872 __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \
883#define _CPU_Context_Restart_self( _the_context ) \
884 _CPU_Context_restore( (_the_context) );
889#define _CPU_Context_Initialize_fp( _destination ) \
895#define _CPU_Context_save_fp( _fp_context_ptr ) \
901#define _CPU_Context_restore_fp( _fp_context_ptr ) \
905#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
909#if ( SPARC_HAS_BITSCAN == 0 )
914 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
916 #error "scan instruction not currently supported by RTEMS!!"
930typedef void ( *CPU_ISR_raw_handler )( void );
944 CPU_ISR_raw_handler new_handler,
945 CPU_ISR_raw_handler *old_handler
948typedef void ( *CPU_ISR_handler )( uint32_t );
962 CPU_ISR_handler new_handler,
963 CPU_ISR_handler *old_handler
996#if !defined(RTEMS_SMP)
1012#define _CPU_Start_multitasking( _heir ) _SPARC_Start_multitasking( _heir )
1015#if defined(RTEMS_SMP)
1016 uint32_t _CPU_SMP_Initialize(
void );
1018 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
1020 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
1022 void _CPU_SMP_Prepare_start_multitasking(
void );
1024 #if defined(__leon__) && !defined(RTEMS_PARAVIRT)
1025 static inline uint32_t _CPU_SMP_Get_current_processor(
void )
1027 return _LEON3_Get_current_processor();
1030 uint32_t _CPU_SMP_Get_current_processor(
void );
1033 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1036#if defined(SPARC_USE_LAZY_FP_SWITCH)
1037#define _CPU_Context_Destroy( _the_thread, _the_context ) \
1039 Per_CPU_Control *cpu_self = _Per_CPU_Get(); \
1040 Thread_Control *_fp_owner = cpu_self->cpu_per_cpu.fp_owner; \
1041 if ( _fp_owner == _the_thread ) { \
1042 cpu_self->cpu_per_cpu.fp_owner = NULL; \
1053 uint32_t local[ 8 ];
1056 uint32_t input[ 8 ];
1083 uint32_t global[ 8 ];
1086 uint32_t output[ 8 ] ;
1094#if SPARC_HAS_FPU == 1
1125static inline uint32_t CPU_swap_u32(
1129 uint32_t byte1, byte2, byte3, byte4, swapped;
1131 byte4 = (value >> 24) & 0xff;
1132 byte3 = (value >> 16) & 0xff;
1133 byte2 = (value >> 8) & 0xff;
1134 byte1 = value & 0xff;
1136 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1147#define CPU_swap_u16( value ) \
1148 (((value&0xff) << 8) | ((value >> 8)&0xff))
1150typedef uint32_t CPU_Counter_ticks;
This header file provides basic definitions used by the API and the implementation.
void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.c:100
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
#define pc
pc, used on mips16 */
Definition: regs.h:67
#define fp
frame-pointer */
Definition: regs.h:65
rtems_termios_device_context * context
Definition: console-config.c:62
const CPU_Trap_table_entry _CPU_Trap_slot_template
Definition: sparc-isr-install.c:54
void _SPARC_Interrupt_dispatch(uint32_t irq)
Dispatches the installed interrupt handlers.
Definition: bsp_isr_handler.c:47
RTEMS_NO_RETURN void _SPARC_Start_multitasking(Context_Control *heir)
Starts multitasking in uniprocessor configurations.
This header file provides information required to build RTEMS for a particular member of the SPARC fa...
#define SPARC_PSR_PIL_MASK
Definition: sparc.h:148
#define SPARC_NUMBER_OF_REGISTER_WINDOWS
Definition: sparc.h:84
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
uint32_t y
This member contains the Y register value.
Definition: cpu.h:1080
uint32_t npc
This member contains the nPC value.
Definition: cpu.h:1071
uint32_t wim
This member contains the WIM register value.
Definition: cpu.h:1077
uint32_t trap
This member contains the trap number.
Definition: cpu.h:1074
uint32_t psr
This member contains the PSR register value.
Definition: cpu.h:1065
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
uint32_t g4
Definition: cpu.h:606
uint32_t i1
Definition: cpu.h:616
uint32_t i3
Definition: cpu.h:620
SPARC_Minimum_stack_frame Stack_frame
Definition: cpu.h:592
uint32_t g1
Definition: cpu.h:600
uint32_t tpc
Definition: cpu.h:632
uint32_t g2
Definition: cpu.h:602
uint32_t i6_fp
Definition: cpu.h:626
uint32_t i2
Definition: cpu.h:618
uint32_t i7
Definition: cpu.h:628
uint32_t pc
Definition: cpu.h:596
uint32_t reserved_for_alignment
Definition: cpu.h:610
uint32_t y
Definition: cpu.h:630
uint32_t g7
Definition: cpu.h:612
uint32_t psr
Definition: cpu.h:594
uint32_t g5
Definition: cpu.h:608
uint32_t i5
Definition: cpu.h:624
uint32_t i0
Definition: cpu.h:614
uint32_t i4
Definition: cpu.h:622
uint32_t npc
Definition: cpu.h:598
uint32_t g3
Definition: cpu.h:604
uint32_t mov_vector_l3
Definition: cpu.h:654
uint32_t mov_psr_l0
Definition: cpu.h:648
uint32_t jmp_to_low_of_handler_plus_l4
Definition: cpu.h:652
uint32_t sethi_of_handler_to_l4
Definition: cpu.h:650
SPARC basic context.
Definition: cpu.h:213
double f24_f25
Definition: cpu.h:523
double f28_f29
Definition: cpu.h:527
uint32_t fsr
Definition: cpu.h:531
double f2_f3
Definition: cpu.h:501
double f0_f1
Definition: cpu.h:499
double f16_f17
Definition: cpu.h:515
double f4_f5
Definition: cpu.h:503
double f20_f21
Definition: cpu.h:519
double f26_f27
Definition: cpu.h:525
double f8_f9
Definition: cpu.h:507
double f30_f31
Definition: cpu.h:529
double f18_f19
Definition: cpu.h:517
double f10_f11
Definition: cpu.h:509
double f22_f23
Definition: cpu.h:521
double f6_f7
Definition: cpu.h:505
double f12_f13
Definition: cpu.h:511
double f14_f15
Definition: cpu.h:513
Thread register context.
Definition: cpu.h:173
uint32_t i4
Definition: cpu.h:373
uint32_t i5
Definition: cpu.h:375
uint32_t i3
Definition: cpu.h:371
uint32_t o6_sp
Definition: cpu.h:382
uint32_t g7
Definition: cpu.h:341
uint32_t l5
Definition: cpu.h:358
uint32_t g5
Definition: cpu.h:339
uint32_t i0
Definition: cpu.h:365
uint32_t psr
Definition: cpu.h:390
uint32_t l3
Definition: cpu.h:354
uint32_t l4
Definition: cpu.h:356
uint32_t o7
Definition: cpu.h:387
uint32_t l2
Definition: cpu.h:352
uint32_t i7
Definition: cpu.h:379
uint32_t i2
Definition: cpu.h:369
uint32_t i1
Definition: cpu.h:367
uint32_t l6
Definition: cpu.h:360
uint32_t i6_fp
Definition: cpu.h:377
uint32_t l7
Definition: cpu.h:362
double l0_and_l1
Definition: cpu.h:350
uint32_t l7
Definition: cpu.h:205
uint32_t saved_arg5
Definition: cpu.h:240
uint32_t saved_arg4
Definition: cpu.h:238
uint32_t saved_arg1
Definition: cpu.h:232
uint32_t pad0
Definition: cpu.h:242
uint32_t i7
Definition: cpu.h:221
uint32_t i2
Definition: cpu.h:211
uint32_t l0
Definition: cpu.h:191
uint32_t l3
Definition: cpu.h:197
uint32_t l1
Definition: cpu.h:193
uint32_t i0
Definition: cpu.h:207
uint32_t i3
Definition: cpu.h:213
uint32_t saved_arg2
Definition: cpu.h:234
uint32_t i6_fp
Definition: cpu.h:219
uint32_t l2
Definition: cpu.h:195
void * structure_return_address
Definition: cpu.h:223
uint32_t saved_arg0
Definition: cpu.h:230
uint32_t i4
Definition: cpu.h:215
uint32_t l6
Definition: cpu.h:203
uint32_t saved_arg3
Definition: cpu.h:236
uint32_t i1
Definition: cpu.h:209
uint32_t l5
Definition: cpu.h:201
uint32_t i5
Definition: cpu.h:217
uint32_t l4
Definition: cpu.h:199
This structure contains the local and input registers of a register window.
Definition: cpu.h:1051