RTEMS 6.1-rc7
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Modules | Data Structures | Macros
PGMC_MIF Peripheral Access Layer

Modules

 PGMC_MIF Register Masks
 

Data Structures

struct  PGMC_MIF_Type
 

Macros

#define PGMC_CPC0_MIF0_BASE   (0x40C89100u)
 
#define PGMC_CPC0_MIF0   ((PGMC_MIF_Type *)PGMC_CPC0_MIF0_BASE)
 
#define PGMC_CPC0_MIF1_BASE   (0x40C89200u)
 
#define PGMC_CPC0_MIF1   ((PGMC_MIF_Type *)PGMC_CPC0_MIF1_BASE)
 
#define PGMC_CPC1_MIF0_BASE   (0x40C89500u)
 
#define PGMC_CPC1_MIF0   ((PGMC_MIF_Type *)PGMC_CPC1_MIF0_BASE)
 
#define PGMC_CPC1_MIF1_BASE   (0x40C89600u)
 
#define PGMC_CPC1_MIF1   ((PGMC_MIF_Type *)PGMC_CPC1_MIF1_BASE)
 
#define PGMC_MIF_BASE_ADDRS   { PGMC_CPC0_MIF0_BASE, PGMC_CPC0_MIF1_BASE, PGMC_CPC1_MIF0_BASE, PGMC_CPC1_MIF1_BASE }
 
#define PGMC_MIF_BASE_PTRS   { PGMC_CPC0_MIF0, PGMC_CPC0_MIF1, PGMC_CPC1_MIF0, PGMC_CPC1_MIF1 }
 
#define PGMC_CPC0_MIF0_BASE   (0x40C89100u)
 
#define PGMC_CPC0_MIF0   ((PGMC_MIF_Type *)PGMC_CPC0_MIF0_BASE)
 
#define PGMC_CPC0_MIF1_BASE   (0x40C89200u)
 
#define PGMC_CPC0_MIF1   ((PGMC_MIF_Type *)PGMC_CPC0_MIF1_BASE)
 
#define PGMC_CPC1_MIF0_BASE   (0x40C89500u)
 
#define PGMC_CPC1_MIF0   ((PGMC_MIF_Type *)PGMC_CPC1_MIF0_BASE)
 
#define PGMC_CPC1_MIF1_BASE   (0x40C89600u)
 
#define PGMC_CPC1_MIF1   ((PGMC_MIF_Type *)PGMC_CPC1_MIF1_BASE)
 
#define PGMC_MIF_BASE_ADDRS   { PGMC_CPC0_MIF0_BASE, PGMC_CPC0_MIF1_BASE, PGMC_CPC1_MIF0_BASE, PGMC_CPC1_MIF1_BASE }
 
#define PGMC_MIF_BASE_PTRS   { PGMC_CPC0_MIF0, PGMC_CPC0_MIF1, PGMC_CPC1_MIF0, PGMC_CPC1_MIF1 }
 

Detailed Description

Macro Definition Documentation

◆ PGMC_CPC0_MIF0 [1/2]

#define PGMC_CPC0_MIF0   ((PGMC_MIF_Type *)PGMC_CPC0_MIF0_BASE)

Peripheral PGMC_CPC0_MIF0 base pointer

◆ PGMC_CPC0_MIF0 [2/2]

#define PGMC_CPC0_MIF0   ((PGMC_MIF_Type *)PGMC_CPC0_MIF0_BASE)

Peripheral PGMC_CPC0_MIF0 base pointer

◆ PGMC_CPC0_MIF0_BASE [1/2]

#define PGMC_CPC0_MIF0_BASE   (0x40C89100u)

Peripheral PGMC_CPC0_MIF0 base address

◆ PGMC_CPC0_MIF0_BASE [2/2]

#define PGMC_CPC0_MIF0_BASE   (0x40C89100u)

Peripheral PGMC_CPC0_MIF0 base address

◆ PGMC_CPC0_MIF1 [1/2]

#define PGMC_CPC0_MIF1   ((PGMC_MIF_Type *)PGMC_CPC0_MIF1_BASE)

Peripheral PGMC_CPC0_MIF1 base pointer

◆ PGMC_CPC0_MIF1 [2/2]

#define PGMC_CPC0_MIF1   ((PGMC_MIF_Type *)PGMC_CPC0_MIF1_BASE)

Peripheral PGMC_CPC0_MIF1 base pointer

◆ PGMC_CPC0_MIF1_BASE [1/2]

#define PGMC_CPC0_MIF1_BASE   (0x40C89200u)

Peripheral PGMC_CPC0_MIF1 base address

◆ PGMC_CPC0_MIF1_BASE [2/2]

#define PGMC_CPC0_MIF1_BASE   (0x40C89200u)

Peripheral PGMC_CPC0_MIF1 base address

◆ PGMC_CPC1_MIF0 [1/2]

#define PGMC_CPC1_MIF0   ((PGMC_MIF_Type *)PGMC_CPC1_MIF0_BASE)

Peripheral PGMC_CPC1_MIF0 base pointer

◆ PGMC_CPC1_MIF0 [2/2]

#define PGMC_CPC1_MIF0   ((PGMC_MIF_Type *)PGMC_CPC1_MIF0_BASE)

Peripheral PGMC_CPC1_MIF0 base pointer

◆ PGMC_CPC1_MIF0_BASE [1/2]

#define PGMC_CPC1_MIF0_BASE   (0x40C89500u)

Peripheral PGMC_CPC1_MIF0 base address

◆ PGMC_CPC1_MIF0_BASE [2/2]

#define PGMC_CPC1_MIF0_BASE   (0x40C89500u)

Peripheral PGMC_CPC1_MIF0 base address

◆ PGMC_CPC1_MIF1 [1/2]

#define PGMC_CPC1_MIF1   ((PGMC_MIF_Type *)PGMC_CPC1_MIF1_BASE)

Peripheral PGMC_CPC1_MIF1 base pointer

◆ PGMC_CPC1_MIF1 [2/2]

#define PGMC_CPC1_MIF1   ((PGMC_MIF_Type *)PGMC_CPC1_MIF1_BASE)

Peripheral PGMC_CPC1_MIF1 base pointer

◆ PGMC_CPC1_MIF1_BASE [1/2]

#define PGMC_CPC1_MIF1_BASE   (0x40C89600u)

Peripheral PGMC_CPC1_MIF1 base address

◆ PGMC_CPC1_MIF1_BASE [2/2]

#define PGMC_CPC1_MIF1_BASE   (0x40C89600u)

Peripheral PGMC_CPC1_MIF1 base address

◆ PGMC_MIF_BASE_ADDRS [1/2]

Array initializer of PGMC_MIF peripheral base addresses

◆ PGMC_MIF_BASE_ADDRS [2/2]

Array initializer of PGMC_MIF peripheral base addresses

◆ PGMC_MIF_BASE_PTRS [1/2]

#define PGMC_MIF_BASE_PTRS   { PGMC_CPC0_MIF0, PGMC_CPC0_MIF1, PGMC_CPC1_MIF0, PGMC_CPC1_MIF1 }

Array initializer of PGMC_MIF peripheral base pointers

◆ PGMC_MIF_BASE_PTRS [2/2]

#define PGMC_MIF_BASE_PTRS   { PGMC_CPC0_MIF0, PGMC_CPC0_MIF1, PGMC_CPC1_MIF0, PGMC_CPC1_MIF1 }

Array initializer of PGMC_MIF peripheral base pointers