RTEMS 6.1-rc7
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fsl_cache.h
1/*
2 * Copyright 2016-2021 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7#ifndef _FSL_CACHE_H_
8#define _FSL_CACHE_H_
9
10#include "fsl_common.h"
11
17/*******************************************************************************
18 * Definitions
19 ******************************************************************************/
20
24#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
27#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
28#ifndef FSL_SDK_DISBLE_L2CACHE_PRESENT
29#define FSL_SDK_DISBLE_L2CACHE_PRESENT 0
30#endif
31#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
32/*******************************************************************************
33 * Definitions
34 ******************************************************************************/
35#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
36
38typedef enum _l2cache_way_num
39{
40 kL2CACHE_8ways = 0,
41#if defined(FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY) && FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY
42 kL2CACHE_16ways
43#endif /* FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY */
44} l2cache_way_num_t;
45
47typedef enum _l2cache_way_size
48{
49 kL2CACHE_16KBSize = 1,
50 kL2CACHE_32KBSize = 2,
51 kL2CACHE_64KBSize = 3,
52 kL2CACHE_128KBSize = 4,
53 kL2CACHE_256KBSize = 5,
54 kL2CACHE_512KBSize = 6
55} l2cache_way_size;
56
58typedef enum _l2cache_replacement
59{
60 kL2CACHE_Pseudorandom = 0U,
61 kL2CACHE_Roundrobin
62} l2cache_replacement_t;
63
65typedef enum _l2cache_writealloc
66{
67 kL2CACHE_UseAwcache = 0,
68 kL2CACHE_NoWriteallocate,
69 kL2CACHE_forceWriteallocate
70} l2cache_writealloc_t;
71
73typedef enum _l2cache_latency
74{
75 kL2CACHE_1CycleLate = 0,
76 kL2CACHE_2CycleLate,
77 kL2CACHE_3CycleLate,
78 kL2CACHE_4CycleLate,
79 kL2CACHE_5CycleLate,
80 kL2CACHE_6CycleLate,
81 kL2CACHE_7CycleLate,
82 kL2CACHE_8CycleLate
83} l2cache_latency_t;
84
86typedef struct _l2cache_latency_config
87{
88 l2cache_latency_t tagWriteLate;
89 l2cache_latency_t tagReadLate;
90 l2cache_latency_t tagSetupLate;
91 l2cache_latency_t dataWriteLate;
92 l2cache_latency_t dataReadLate;
93 l2cache_latency_t dataSetupLate;
94} L2cache_latency_config_t;
95
97typedef struct _l2cache_config
98{
99 /* ------------------------ l2 cachec basic settings ---------------------------- */
100 l2cache_way_num_t wayNum;
101 l2cache_way_size waySize;
102 l2cache_replacement_t repacePolicy;
103 /* ------------------------ tag/data ram latency settings ----------------------- */
104 L2cache_latency_config_t *lateConfig;
105 /* ------------------------ Prefetch enable settings ---------------------------- */
106 bool istrPrefetchEnable;
107 bool dataPrefetchEnable;
108 /* ------------------------ Non-secure access settings -------------------------- */
109 bool nsLockdownEnable;
110 /* ------------------------ other settings -------------------------------------- */
111 l2cache_writealloc_t writeAlloc;
112} l2cache_config_t;
113#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
114/*******************************************************************************
115 * API
116 ******************************************************************************/
117
118#if defined(__cplusplus)
119extern "C" {
120#endif
121
131static inline void L1CACHE_EnableICache(void)
132{
134}
135
140static inline void L1CACHE_DisableICache(void)
141{
142 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
143 {
145 }
146}
147
152static inline void L1CACHE_InvalidateICache(void)
153{
155}
156
167void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte);
168
173static inline void L1CACHE_EnableDCache(void)
174{
176}
177
182static inline void L1CACHE_DisableDCache(void)
183{
184 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
185 {
187 }
188}
189
194static inline void L1CACHE_InvalidateDCache(void)
195{
197}
198
203static inline void L1CACHE_CleanDCache(void)
204{
206}
207
212static inline void L1CACHE_CleanInvalidateDCache(void)
213{
215}
216
227static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
228{
229 SCB_InvalidateDCache_by_Addr((uint32_t *)address, (int32_t)size_byte);
230}
231
242static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte)
243{
244 SCB_CleanDCache_by_Addr((uint32_t *)address, (int32_t)size_byte);
245}
246
257static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
258{
259 SCB_CleanInvalidateDCache_by_Addr((uint32_t *)address, (int32_t)size_byte);
260}
263#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
274void L2CACHE_Init(l2cache_config_t *config);
275
293void L2CACHE_GetDefaultConfig(l2cache_config_t *config);
294
301void L2CACHE_Enable(void);
302
309void L2CACHE_Disable(void);
310
316void L2CACHE_Invalidate(void);
317
329void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
330
336void L2CACHE_Clean(void);
337
349void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte);
350
356void L2CACHE_CleanInvalidate(void);
357
369void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte);
370
388void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable);
389
391#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
392
411void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
412
425void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
426
439void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte);
440
453void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte);
454
457#if defined(__cplusplus)
458}
459#endif
460
463#endif /* _FSL_CACHE_H_*/
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr(volatile void *addr, int32_t dsize)
D-Cache Invalidate by address.
Definition: cachel1_armv7.h:358
__STATIC_FORCEINLINE void SCB_EnableDCache(void)
Enable D-Cache.
Definition: cachel1_armv7.h:141
__STATIC_FORCEINLINE void SCB_DisableICache(void)
Disable I-Cache.
Definition: cachel1_armv7.h:78
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache(void)
Clean & Invalidate D-Cache.
Definition: cachel1_armv7.h:319
__STATIC_FORCEINLINE void SCB_InvalidateICache(void)
Invalidate I-Cache.
Definition: cachel1_armv7.h:95
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr(volatile void *addr, int32_t dsize)
D-Cache Clean and Invalidate by address.
Definition: cachel1_armv7.h:418
__STATIC_FORCEINLINE void SCB_EnableICache(void)
Enable I-Cache.
Definition: cachel1_armv7.h:57
__STATIC_FORCEINLINE void SCB_InvalidateDCache(void)
Invalidate D-Cache.
Definition: cachel1_armv7.h:249
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr(volatile void *addr, int32_t dsize)
D-Cache Clean by address.
Definition: cachel1_armv7.h:388
__STATIC_FORCEINLINE void SCB_CleanDCache(void)
Clean D-Cache.
Definition: cachel1_armv7.h:284
__STATIC_FORCEINLINE void SCB_DisableDCache(void)
Disable D-Cache.
Definition: cachel1_armv7.h:181
#define SCB_CCR_DC_Msk
Definition: core_cm7.h:618
#define SCB_CCR_IC_Msk
Definition: core_cm7.h:615
#define SCB
Definition: core_cm4.h:1572
void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
Invalidates all instruction caches by range.
Definition: fsl_cache.c:527
void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
Cleans all data caches by range.
Definition: fsl_cache.c:572
void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
Invalidates all data caches by range.
Definition: fsl_cache.c:550
void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
Cleans and Invalidates all data caches by range.
Definition: fsl_cache.c:594
void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
Invalidate cortex-m7 L1 instruction cache by range.
Definition: fsl_cache.c:411
Definition: deflate.c:114