40#ifndef _RTEMS_SCORE_CPU_H
41#define _RTEMS_SCORE_CPU_H
63#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
71#define CPU_ISR_PASSES_FRAME_POINTER FALSE
82#if ( M68K_HAS_FPU == 1 ) || ( M68K_HAS_EMAC == 1 )
83 #define CPU_HARDWARE_FP TRUE
84 #define CPU_SOFTWARE_FP FALSE
86 #define CPU_HARDWARE_FP FALSE
87 #if defined( __GNUC__ )
88 #define CPU_SOFTWARE_FP TRUE
90 #define CPU_SOFTWARE_FP FALSE
101#define CPU_ALL_TASKS_ARE_FP FALSE
102#define CPU_IDLE_TASK_IS_FP FALSE
103#define CPU_USE_DEFERRED_FP_SWITCH TRUE
104#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
106#define CPU_STACK_GROWS_UP FALSE
109#define CPU_CACHE_LINE_BYTES 16
111#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
113#define CPU_MAXIMUM_PROCESSORS 32
115#if ( CPU_HARDWARE_FP == TRUE ) && !defined( __mcoldfire__ )
116 #if defined( __mc68060__ )
117 #define M68K_FP_STATE_SIZE 16
119 #define M68K_FP_STATE_SIZE 216
145 #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 )
148 void *thread_pointer;
151#define _CPU_Context_Get_SP( _context ) \
158#if ( CPU_SOFTWARE_FP == TRUE )
166 uint16_t _exception_bits;
167 uint16_t _trap_enable_bits;
168 uint16_t _sticky_bits;
169 uint16_t _rounding_mode;
171 uint16_t _last_operation;
182 #define _CPU_Context_Initialize_fp( _fp_area ) \
184 Context_Control_fp *_fp; \
185 _fp = *(Context_Control_fp **)_fp_area; \
186 _fp->_exception_bits = 0; \
187 _fp->_trap_enable_bits = 0; \
188 _fp->_sticky_bits = 0; \
189 _fp->_rounding_mode = 0; \
191 _fp->_last_operation = 0; \
192 _fp->_operand1.df = 0; \
193 _fp->_operand2.df = 0; \
197#if ( CPU_HARDWARE_FP == TRUE )
198 #if defined( __mcoldfire__ )
202 #if ( M68K_HAS_FPU == 1 )
208 extern uint32_t _CPU_cacr_shadow;
218 uint32_t emac_accext01;
219 uint32_t emac_accext23;
221 #if ( M68K_HAS_FPU == 1 )
222 uint16_t fp_state_format;
223 uint16_t fp_state_fpcr;
225 uint32_t fp_state_fpsr;
244 #define _CPU_Context_Initialize_fp( _fp_area ) \
245 memset( *(_fp_area), 0, sizeof( Context_Control_fp ) )
258 uint8_t fp_save_area [M68K_FP_STATE_SIZE + 112];
266 #define _CPU_Context_Initialize_fp( _fp_area ) \
268 uint32_t *_fp_context = (uint32_t *) \
269 ( (uintptr_t) *( _fp_area ) + CPU_CONTEXT_FP_SIZE - 4 ); \
270 *(--(_fp_context)) = 0; \
271 *(_fp_area) = (void *)(_fp_context); \
291 uint32_t d0, d1, d2, d3, d4, d5, d6, d7;
292 uint32_t a0, a1, a2, a3, a4, a5, a6, a7;
308#define CPU_MODES_INTERRUPT_MASK 0x00000007
314#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
320#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
326#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256
327#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
334#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
340#define CPU_STACK_MINIMUM_SIZE M68K_CPU_STACK_MINIMUM_SIZE
345#define CPU_PRIORITY_MAXIMUM M68K_CPU_PRIORITY_MAXIMUM
347#define CPU_SIZEOF_POINTER 4
353#define CPU_ALIGNMENT 4
354#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
361#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
363#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
379#define _CPU_ISR_Disable( _level ) \
380 m68k_disable_interrupts( _level )
382#define _CPU_ISR_Enable( _level ) \
383 m68k_enable_interrupts( _level )
385#define _CPU_ISR_Flash( _level ) \
386 m68k_flash_interrupts( _level )
388static inline bool _CPU_ISR_Is_enabled( uint32_t level )
390 return ( level & 0x0700 ) == 0;
393#define _CPU_ISR_Set_level( _newlevel ) \
394 m68k_set_interrupt_level( _newlevel )
410void _CPU_Context_Initialize(
412 void *stack_area_begin,
413 size_t stack_area_size,
415 void (*entry_point)(
void ),
424#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
440#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
442#if ( M68K_HAS_BFFFO != 1 )
446extern const unsigned char _CPU_m68k_BFFFO_table[256];
449#if ( M68K_HAS_BFFFO == 1 )
451#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
452 __asm__ volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
454#elif ( __mcfisaaplus__ )
456#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
468#if ( defined(__mcoldfire__) )
470#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
479 " move.b (%3,%1),%0\n" \
481 "1: move.w %2,%1\n" \
482 " move.b (%3,%1),%0\n" \
484 "0: and.l #0xff,%0\n" \
485 : "=&d" ((_output)), "=&d" ((dumby)) \
486 : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
489#elif ( M68K_HAS_EXTB_L == 1 )
490#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
494 __asm__ volatile ( " move.w %2,%1\n" \
497 " move.b (%3,%1.w),%0\n" \
500 "1: moveq.l #8,%0\n" \
501 " add.b (%3,%2.w),%0\n" \
503 : "=&d" ((_output)), "=&d" ((dumby)) \
504 : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
508#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
512 __asm__ volatile ( " move.w %2,%1\n" \
515 " move.b (%3,%1.w),%0\n" \
516 " and.l #0x000000ff,%0\n"\
518 "1: moveq.l #8,%0\n" \
519 " add.b (%3,%2.w),%0\n" \
521 : "=&d" ((_output)), "=&d" ((dumby)) \
522 : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
541#define _CPU_Priority_Mask( _bit_number ) \
542 ( 0x8000 >> (_bit_number) )
544#define _CPU_Priority_bits_index( _priority ) \
559typedef void ( *CPU_ISR_raw_handler )( void );
563 CPU_ISR_raw_handler new_handler,
564 CPU_ISR_raw_handler *old_handler
567typedef void ( *CPU_ISR_handler )( uint32_t );
571 CPU_ISR_handler new_handler,
572 CPU_ISR_handler *old_handler
619typedef uint32_t CPU_Counter_ticks;
625#if (M68K_HAS_FPSP_PACKAGE == 1)
651void M68KFPSPInstallExceptionHandlers (
void);
653extern int (*_FPSP_install_raw_handler)(
655 CPU_ISR_raw_handler new_handler,
656 CPU_ISR_raw_handler *old_handler
This header file provides basic definitions used by the API and the implementation.
void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.c:100
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
Motorola M68K CPU Dependent Source.
#define _CPU_Context_restore_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:901
#define _CPU_Context_save_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:895
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
uint32_t pc
This member contains the PC value.
Definition: cpu.h:290
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
SPARC basic context.
Definition: cpu.h:213
Thread register context.
Definition: cpu.h:173