RTEMS 6.1-rc7
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Data Fields
OCTOSPI_TypeDef Struct Reference

OCTO Serial Peripheral Interface. More...

#include <stm32h723xx.h>

Data Fields

__IO uint32_t CR
 
uint32_t RESERVED
 
__IO uint32_t DCR1
 
__IO uint32_t DCR2
 
__IO uint32_t DCR3
 
__IO uint32_t DCR4
 
uint32_t RESERVED1 [2]
 
__IO uint32_t SR
 
__IO uint32_t FCR
 
uint32_t RESERVED2 [6]
 
__IO uint32_t DLR
 
uint32_t RESERVED3
 
__IO uint32_t AR
 
uint32_t RESERVED4
 
__IO uint32_t DR
 
uint32_t RESERVED5 [11]
 
__IO uint32_t PSMKR
 
uint32_t RESERVED6
 
__IO uint32_t PSMAR
 
uint32_t RESERVED7
 
__IO uint32_t PIR
 
uint32_t RESERVED8 [27]
 
__IO uint32_t CCR
 
uint32_t RESERVED9
 
__IO uint32_t TCR
 
uint32_t RESERVED10
 
__IO uint32_t IR
 
uint32_t RESERVED11 [3]
 
__IO uint32_t ABR
 
uint32_t RESERVED12 [3]
 
__IO uint32_t LPTR
 
uint32_t RESERVED13 [3]
 
__IO uint32_t WPCCR
 
uint32_t RESERVED14
 
__IO uint32_t WPTCR
 
uint32_t RESERVED15
 
__IO uint32_t WPIR
 
uint32_t RESERVED16 [3]
 
__IO uint32_t WPABR
 
uint32_t RESERVED17 [7]
 
__IO uint32_t WCCR
 
uint32_t RESERVED18
 
__IO uint32_t WTCR
 
uint32_t RESERVED19
 
__IO uint32_t WIR
 
uint32_t RESERVED20 [3]
 
__IO uint32_t WABR
 
uint32_t RESERVED21 [23]
 
__IO uint32_t HLCR
 
uint32_t RESERVED22 [122]
 
__IO uint32_t HWCFGR
 
__IO uint32_t VER
 
__IO uint32_t ID
 
__IO uint32_t MID
 

Detailed Description

OCTO Serial Peripheral Interface.

Field Documentation

◆ ABR

__IO uint32_t OCTOSPI_TypeDef::ABR

OCTOSPI Alternate Bytes register, Address offset: 0x120

◆ AR

__IO uint32_t OCTOSPI_TypeDef::AR

OCTOSPI Address register, Address offset: 0x048

◆ CCR

__IO uint32_t OCTOSPI_TypeDef::CCR

OCTOSPI Communication Configuration register, Address offset: 0x100

◆ CR

__IO uint32_t OCTOSPI_TypeDef::CR

OCTOSPI Control register, Address offset: 0x000

◆ DCR1

__IO uint32_t OCTOSPI_TypeDef::DCR1

OCTOSPI Device Configuration register 1, Address offset: 0x008

◆ DCR2

__IO uint32_t OCTOSPI_TypeDef::DCR2

OCTOSPI Device Configuration register 2, Address offset: 0x00C

◆ DCR3

__IO uint32_t OCTOSPI_TypeDef::DCR3

OCTOSPI Device Configuration register 3, Address offset: 0x010

◆ DCR4

__IO uint32_t OCTOSPI_TypeDef::DCR4

OCTOSPI Device Configuration register 4, Address offset: 0x014

◆ DLR

__IO uint32_t OCTOSPI_TypeDef::DLR

OCTOSPI Data Length register, Address offset: 0x040

◆ DR

__IO uint32_t OCTOSPI_TypeDef::DR

OCTOSPI Data register, Address offset: 0x050

◆ FCR

__IO uint32_t OCTOSPI_TypeDef::FCR

OCTOSPI Flag Clear register, Address offset: 0x024

◆ HLCR

__IO uint32_t OCTOSPI_TypeDef::HLCR

OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200

◆ HWCFGR

__IO uint32_t OCTOSPI_TypeDef::HWCFGR

OCTOSPI HW Configuration register, Address offset: 0x3F0

◆ ID

__IO uint32_t OCTOSPI_TypeDef::ID

OCTOSPI Identification register, Address offset: 0x3F8

◆ IR

__IO uint32_t OCTOSPI_TypeDef::IR

OCTOSPI Instruction register, Address offset: 0x110

◆ LPTR

__IO uint32_t OCTOSPI_TypeDef::LPTR

OCTOSPI Low Power Timeout register, Address offset: 0x130

◆ MID

__IO uint32_t OCTOSPI_TypeDef::MID

OCTOPSI HW Magic ID register, Address offset: 0x3FC

◆ PIR

__IO uint32_t OCTOSPI_TypeDef::PIR

OCTOSPI Polling Interval register, Address offset: 0x090

◆ PSMAR

__IO uint32_t OCTOSPI_TypeDef::PSMAR

OCTOSPI Polling Status Match register, Address offset: 0x088

◆ PSMKR

__IO uint32_t OCTOSPI_TypeDef::PSMKR

OCTOSPI Polling Status Mask register, Address offset: 0x080

◆ RESERVED

uint32_t OCTOSPI_TypeDef::RESERVED

Reserved, Address offset: 0x004

◆ RESERVED1

uint32_t OCTOSPI_TypeDef::RESERVED1

Reserved, Address offset: 0x018-0x01C

◆ RESERVED10

uint32_t OCTOSPI_TypeDef::RESERVED10

Reserved, Address offset: 0x10C

◆ RESERVED11

uint32_t OCTOSPI_TypeDef::RESERVED11

Reserved, Address offset: 0x114-0x11C

◆ RESERVED12

uint32_t OCTOSPI_TypeDef::RESERVED12

Reserved, Address offset: 0x124-0x12C

◆ RESERVED13

uint32_t OCTOSPI_TypeDef::RESERVED13

Reserved, Address offset: 0x134-0x13C

◆ RESERVED14

uint32_t OCTOSPI_TypeDef::RESERVED14

Reserved, Address offset: 0x144

◆ RESERVED15

uint32_t OCTOSPI_TypeDef::RESERVED15

Reserved, Address offset: 0x14C

◆ RESERVED16

uint32_t OCTOSPI_TypeDef::RESERVED16

Reserved, Address offset: 0x154-0x15C

◆ RESERVED17

uint32_t OCTOSPI_TypeDef::RESERVED17

Reserved, Address offset: 0x164-0x17C

◆ RESERVED18

uint32_t OCTOSPI_TypeDef::RESERVED18

Reserved, Address offset: 0x184

◆ RESERVED19

uint32_t OCTOSPI_TypeDef::RESERVED19

Reserved, Address offset: 0x18C

◆ RESERVED2

uint32_t OCTOSPI_TypeDef::RESERVED2

Reserved, Address offset: 0x028-0x03C

◆ RESERVED20

uint32_t OCTOSPI_TypeDef::RESERVED20

Reserved, Address offset: 0x194-0x19C

◆ RESERVED21

uint32_t OCTOSPI_TypeDef::RESERVED21

Reserved, Address offset: 0x1A4-0x1FC

◆ RESERVED22

uint32_t OCTOSPI_TypeDef::RESERVED22

Reserved, Address offset: 0x204-0x3EC

◆ RESERVED3

uint32_t OCTOSPI_TypeDef::RESERVED3

Reserved, Address offset: 0x044

◆ RESERVED4

uint32_t OCTOSPI_TypeDef::RESERVED4

Reserved, Address offset: 0x04C

◆ RESERVED5

uint32_t OCTOSPI_TypeDef::RESERVED5

Reserved, Address offset: 0x054-0x07C

◆ RESERVED6

uint32_t OCTOSPI_TypeDef::RESERVED6

Reserved, Address offset: 0x084

◆ RESERVED7

uint32_t OCTOSPI_TypeDef::RESERVED7

Reserved, Address offset: 0x08C

◆ RESERVED8

uint32_t OCTOSPI_TypeDef::RESERVED8

Reserved, Address offset: 0x094-0x0FC

◆ RESERVED9

uint32_t OCTOSPI_TypeDef::RESERVED9

Reserved, Address offset: 0x104

◆ SR

__IO uint32_t OCTOSPI_TypeDef::SR

OCTOSPI Status register, Address offset: 0x020

◆ TCR

__IO uint32_t OCTOSPI_TypeDef::TCR

OCTOSPI Timing Configuration register, Address offset: 0x108

◆ VER

__IO uint32_t OCTOSPI_TypeDef::VER

OCTOSPI Version register, Address offset: 0x3F4

◆ WABR

__IO uint32_t OCTOSPI_TypeDef::WABR

OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0

◆ WCCR

__IO uint32_t OCTOSPI_TypeDef::WCCR

OCTOSPI Write Communication Configuration register, Address offset: 0x180

◆ WIR

__IO uint32_t OCTOSPI_TypeDef::WIR

OCTOSPI Write Instruction register, Address offset: 0x190

◆ WPABR

__IO uint32_t OCTOSPI_TypeDef::WPABR

OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160

◆ WPCCR

__IO uint32_t OCTOSPI_TypeDef::WPCCR

OCTOSPI Wrap Communication Configuration register, Address offset: 0x140

◆ WPIR

__IO uint32_t OCTOSPI_TypeDef::WPIR

OCTOSPI Wrap Instruction register, Address offset: 0x150

◆ WPTCR

__IO uint32_t OCTOSPI_TypeDef::WPTCR

OCTOSPI Wrap Timing Configuration register, Address offset: 0x148

◆ WTCR

__IO uint32_t OCTOSPI_TypeDef::WTCR

OCTOSPI Write Timing Configuration register, Address offset: 0x188


The documentation for this struct was generated from the following files: