25#if defined ( __ICCARM__ )
26 #pragma system_include
27#elif defined (__clang__)
28 #pragma clang system_header
31#ifndef __CORE_CM4_H_GENERIC
32#define __CORE_CM4_H_GENERIC
66#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
67#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
68#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
69 __CM4_CMSIS_VERSION_SUB )
71#define __CORTEX_M (4U)
76#if defined ( __CC_ARM )
77 #if defined __TARGET_FPU_VFP
78 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
88#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
90 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
93 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
100#elif defined (__ti__)
101 #if defined (__ARM_FP)
102 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
103 #define __FPU_USED 1U
105 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #define __FPU_USED 0U
109 #define __FPU_USED 0U
112#elif defined ( __GNUC__ )
113 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
114 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
115 #define __FPU_USED 1U
117 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
118 #define __FPU_USED 0U
121 #define __FPU_USED 0U
124#elif defined ( __ICCARM__ )
125 #if defined __ARMVFP__
126 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
127 #define __FPU_USED 1U
129 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
130 #define __FPU_USED 0U
133 #define __FPU_USED 0U
136#elif defined ( __TI_ARM__ )
137 #if defined __TI_VFP_SUPPORT__
138 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
139 #define __FPU_USED 1U
141 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
142 #define __FPU_USED 0U
145 #define __FPU_USED 0U
148#elif defined ( __TASKING__ )
149 #if defined __FPU_VFP__
150 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
151 #define __FPU_USED 1U
153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154 #define __FPU_USED 0U
157 #define __FPU_USED 0U
160#elif defined ( __CSMC__ )
161 #if ( __CSMC__ & 0x400U)
162 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
163 #define __FPU_USED 1U
165 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
166 #define __FPU_USED 0U
169 #define __FPU_USED 0U
183#ifndef __CMSIS_GENERIC
185#ifndef __CORE_CM4_H_DEPENDANT
186#define __CORE_CM4_H_DEPENDANT
193#if defined __CHECK_DEVICE_DEFINES
195 #define __CM4_REV 0x0000U
196 #warning "__CM4_REV not defined in device header file; using default!"
199 #ifndef __FPU_PRESENT
200 #define __FPU_PRESENT 0U
201 #warning "__FPU_PRESENT not defined in device header file; using default!"
204 #ifndef __MPU_PRESENT
205 #define __MPU_PRESENT 0U
206 #warning "__MPU_PRESENT not defined in device header file; using default!"
209 #ifndef __VTOR_PRESENT
210 #define __VTOR_PRESENT 1U
211 #warning "__VTOR_PRESENT not defined in device header file; using default!"
214 #ifndef __NVIC_PRIO_BITS
215 #define __NVIC_PRIO_BITS 3U
216 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
219 #ifndef __Vendor_SysTickConfig
220 #define __Vendor_SysTickConfig 0U
221 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
236 #define __I volatile const
242#define __IM volatile const
244#define __IOM volatile
293#define APSR_N_Pos 31U
294#define APSR_N_Msk (1UL << APSR_N_Pos)
296#define APSR_Z_Pos 30U
297#define APSR_Z_Msk (1UL << APSR_Z_Pos)
299#define APSR_C_Pos 29U
300#define APSR_C_Msk (1UL << APSR_C_Pos)
302#define APSR_V_Pos 28U
303#define APSR_V_Msk (1UL << APSR_V_Pos)
305#define APSR_Q_Pos 27U
306#define APSR_Q_Msk (1UL << APSR_Q_Pos)
308#define APSR_GE_Pos 16U
309#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)
326#define IPSR_ISR_Pos 0U
327#define IPSR_ISR_Msk (0x1FFUL )
354#define xPSR_N_Pos 31U
355#define xPSR_N_Msk (1UL << xPSR_N_Pos)
357#define xPSR_Z_Pos 30U
358#define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
360#define xPSR_C_Pos 29U
361#define xPSR_C_Msk (1UL << xPSR_C_Pos)
363#define xPSR_V_Pos 28U
364#define xPSR_V_Msk (1UL << xPSR_V_Pos)
366#define xPSR_Q_Pos 27U
367#define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
369#define xPSR_ICI_IT_2_Pos 25U
370#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)
372#define xPSR_T_Pos 24U
373#define xPSR_T_Msk (1UL << xPSR_T_Pos)
375#define xPSR_GE_Pos 16U
376#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
378#define xPSR_ICI_IT_1_Pos 10U
379#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)
381#define xPSR_ISR_Pos 0U
382#define xPSR_ISR_Msk (0x1FFUL )
401#define CONTROL_FPCA_Pos 2U
402#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
404#define CONTROL_SPSEL_Pos 1U
405#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
407#define CONTROL_nPRIV_Pos 0U
408#define CONTROL_nPRIV_Msk (1UL )
425 __IOM uint32_t ISER[8U];
426 uint32_t RESERVED0[24U];
427 __IOM uint32_t ICER[8U];
428 uint32_t RESERVED1[24U];
429 __IOM uint32_t ISPR[8U];
430 uint32_t RESERVED2[24U];
431 __IOM uint32_t ICPR[8U];
432 uint32_t RESERVED3[24U];
433 __IOM uint32_t IABR[8U];
434 uint32_t RESERVED4[56U];
435 __IOM uint8_t IP[240U];
436 uint32_t RESERVED5[644U];
441#define NVIC_STIR_INTID_Pos 0U
442#define NVIC_STIR_INTID_Msk (0x1FFUL )
465 __IOM uint8_t SHP[12U];
473 __IM uint32_t PFR[2U];
476 __IM uint32_t MMFR[4U];
477 __IM uint32_t ISAR[5U];
478 uint32_t RESERVED0[5U];
483#define SCB_CPUID_IMPLEMENTER_Pos 24U
484#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
486#define SCB_CPUID_VARIANT_Pos 20U
487#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
489#define SCB_CPUID_ARCHITECTURE_Pos 16U
490#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
492#define SCB_CPUID_PARTNO_Pos 4U
493#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
495#define SCB_CPUID_REVISION_Pos 0U
496#define SCB_CPUID_REVISION_Msk (0xFUL )
499#define SCB_ICSR_NMIPENDSET_Pos 31U
500#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
502#define SCB_ICSR_PENDSVSET_Pos 28U
503#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
505#define SCB_ICSR_PENDSVCLR_Pos 27U
506#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
508#define SCB_ICSR_PENDSTSET_Pos 26U
509#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
511#define SCB_ICSR_PENDSTCLR_Pos 25U
512#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
514#define SCB_ICSR_ISRPREEMPT_Pos 23U
515#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
517#define SCB_ICSR_ISRPENDING_Pos 22U
518#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
520#define SCB_ICSR_VECTPENDING_Pos 12U
521#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
523#define SCB_ICSR_RETTOBASE_Pos 11U
524#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
526#define SCB_ICSR_VECTACTIVE_Pos 0U
527#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
530#define SCB_VTOR_TBLOFF_Pos 7U
531#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
534#define SCB_AIRCR_VECTKEY_Pos 16U
535#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
537#define SCB_AIRCR_VECTKEYSTAT_Pos 16U
538#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
540#define SCB_AIRCR_ENDIANESS_Pos 15U
541#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
543#define SCB_AIRCR_PRIGROUP_Pos 8U
544#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
546#define SCB_AIRCR_SYSRESETREQ_Pos 2U
547#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
549#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
550#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
552#define SCB_AIRCR_VECTRESET_Pos 0U
553#define SCB_AIRCR_VECTRESET_Msk (1UL )
556#define SCB_SCR_SEVONPEND_Pos 4U
557#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
559#define SCB_SCR_SLEEPDEEP_Pos 2U
560#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
562#define SCB_SCR_SLEEPONEXIT_Pos 1U
563#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
566#define SCB_CCR_STKALIGN_Pos 9U
567#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
569#define SCB_CCR_BFHFNMIGN_Pos 8U
570#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
572#define SCB_CCR_DIV_0_TRP_Pos 4U
573#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
575#define SCB_CCR_UNALIGN_TRP_Pos 3U
576#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
578#define SCB_CCR_USERSETMPEND_Pos 1U
579#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
581#define SCB_CCR_NONBASETHRDENA_Pos 0U
582#define SCB_CCR_NONBASETHRDENA_Msk (1UL )
585#define SCB_SHCSR_USGFAULTENA_Pos 18U
586#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
588#define SCB_SHCSR_BUSFAULTENA_Pos 17U
589#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
591#define SCB_SHCSR_MEMFAULTENA_Pos 16U
592#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
594#define SCB_SHCSR_SVCALLPENDED_Pos 15U
595#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
597#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
598#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
600#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
601#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
603#define SCB_SHCSR_USGFAULTPENDED_Pos 12U
604#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
606#define SCB_SHCSR_SYSTICKACT_Pos 11U
607#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
609#define SCB_SHCSR_PENDSVACT_Pos 10U
610#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
612#define SCB_SHCSR_MONITORACT_Pos 8U
613#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
615#define SCB_SHCSR_SVCALLACT_Pos 7U
616#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
618#define SCB_SHCSR_USGFAULTACT_Pos 3U
619#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
621#define SCB_SHCSR_BUSFAULTACT_Pos 1U
622#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
624#define SCB_SHCSR_MEMFAULTACT_Pos 0U
625#define SCB_SHCSR_MEMFAULTACT_Msk (1UL )
628#define SCB_CFSR_USGFAULTSR_Pos 16U
629#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
631#define SCB_CFSR_BUSFAULTSR_Pos 8U
632#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
634#define SCB_CFSR_MEMFAULTSR_Pos 0U
635#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL )
638#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U)
639#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
641#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U)
642#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)
644#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U)
645#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
647#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U)
648#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
650#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U)
651#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
653#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U)
654#define SCB_CFSR_IACCVIOL_Msk (1UL )
657#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
658#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
660#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)
661#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)
663#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
664#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
666#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
667#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
669#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
670#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
672#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
673#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
675#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
676#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
679#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
680#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
682#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
683#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
685#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
686#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
688#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
689#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
691#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
692#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
694#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
695#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
698#define SCB_HFSR_DEBUGEVT_Pos 31U
699#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
701#define SCB_HFSR_FORCED_Pos 30U
702#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
704#define SCB_HFSR_VECTTBL_Pos 1U
705#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
708#define SCB_DFSR_EXTERNAL_Pos 4U
709#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
711#define SCB_DFSR_VCATCH_Pos 3U
712#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
714#define SCB_DFSR_DWTTRAP_Pos 2U
715#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
717#define SCB_DFSR_BKPT_Pos 1U
718#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
720#define SCB_DFSR_HALTED_Pos 0U
721#define SCB_DFSR_HALTED_Msk (1UL )
738 uint32_t RESERVED0[1U];
744#define SCnSCB_ICTR_INTLINESNUM_Pos 0U
745#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL )
748#define SCnSCB_ACTLR_DISOOFP_Pos 9U
749#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos)
751#define SCnSCB_ACTLR_DISFPCA_Pos 8U
752#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos)
754#define SCnSCB_ACTLR_DISFOLD_Pos 2U
755#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
757#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U
758#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)
760#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U
761#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL )
785#define SysTick_CTRL_COUNTFLAG_Pos 16U
786#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
788#define SysTick_CTRL_CLKSOURCE_Pos 2U
789#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
791#define SysTick_CTRL_TICKINT_Pos 1U
792#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
794#define SysTick_CTRL_ENABLE_Pos 0U
795#define SysTick_CTRL_ENABLE_Msk (1UL )
798#define SysTick_LOAD_RELOAD_Pos 0U
799#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )
802#define SysTick_VAL_CURRENT_Pos 0U
803#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL )
806#define SysTick_CALIB_NOREF_Pos 31U
807#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
809#define SysTick_CALIB_SKEW_Pos 30U
810#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
812#define SysTick_CALIB_TENMS_Pos 0U
813#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL )
836 uint32_t RESERVED0[864U];
838 uint32_t RESERVED1[15U];
840 uint32_t RESERVED2[15U];
842 uint32_t RESERVED3[32U];
843 uint32_t RESERVED4[43U];
846 uint32_t RESERVED5[6U];
862#define ITM_TPR_PRIVMASK_Pos 0U
863#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL )
866#define ITM_TCR_BUSY_Pos 23U
867#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
869#define ITM_TCR_TRACEBUSID_Pos 16U
870#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
872#define ITM_TCR_GTSFREQ_Pos 10U
873#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
875#define ITM_TCR_TSPRESCALE_Pos 8U
876#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)
878#define ITM_TCR_SWOENA_Pos 4U
879#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
881#define ITM_TCR_DWTENA_Pos 3U
882#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
884#define ITM_TCR_SYNCENA_Pos 2U
885#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
887#define ITM_TCR_TSENA_Pos 1U
888#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
890#define ITM_TCR_ITMENA_Pos 0U
891#define ITM_TCR_ITMENA_Msk (1UL )
894#define ITM_LSR_BYTEACC_Pos 2U
895#define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos)
897#define ITM_LSR_ACCESS_Pos 1U
898#define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos)
900#define ITM_LSR_PRESENT_Pos 0U
901#define ITM_LSR_PRESENT_Msk (1UL )
929 uint32_t RESERVED0[1U];
933 uint32_t RESERVED1[1U];
937 uint32_t RESERVED2[1U];
944#define DWT_CTRL_NUMCOMP_Pos 28U
945#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
947#define DWT_CTRL_NOTRCPKT_Pos 27U
948#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
950#define DWT_CTRL_NOEXTTRIG_Pos 26U
951#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
953#define DWT_CTRL_NOCYCCNT_Pos 25U
954#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
956#define DWT_CTRL_NOPRFCNT_Pos 24U
957#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
959#define DWT_CTRL_CYCEVTENA_Pos 22U
960#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
962#define DWT_CTRL_FOLDEVTENA_Pos 21U
963#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
965#define DWT_CTRL_LSUEVTENA_Pos 20U
966#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
968#define DWT_CTRL_SLEEPEVTENA_Pos 19U
969#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
971#define DWT_CTRL_EXCEVTENA_Pos 18U
972#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
974#define DWT_CTRL_CPIEVTENA_Pos 17U
975#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
977#define DWT_CTRL_EXCTRCENA_Pos 16U
978#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
980#define DWT_CTRL_PCSAMPLENA_Pos 12U
981#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
983#define DWT_CTRL_SYNCTAP_Pos 10U
984#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
986#define DWT_CTRL_CYCTAP_Pos 9U
987#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
989#define DWT_CTRL_POSTINIT_Pos 5U
990#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
992#define DWT_CTRL_POSTPRESET_Pos 1U
993#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
995#define DWT_CTRL_CYCCNTENA_Pos 0U
996#define DWT_CTRL_CYCCNTENA_Msk (0x1UL )
999#define DWT_CPICNT_CPICNT_Pos 0U
1000#define DWT_CPICNT_CPICNT_Msk (0xFFUL )
1003#define DWT_EXCCNT_EXCCNT_Pos 0U
1004#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL )
1007#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
1008#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL )
1011#define DWT_LSUCNT_LSUCNT_Pos 0U
1012#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL )
1015#define DWT_FOLDCNT_FOLDCNT_Pos 0U
1016#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL )
1019#define DWT_MASK_MASK_Pos 0U
1020#define DWT_MASK_MASK_Msk (0x1FUL )
1023#define DWT_FUNCTION_MATCHED_Pos 24U
1024#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
1026#define DWT_FUNCTION_DATAVADDR1_Pos 16U
1027#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
1029#define DWT_FUNCTION_DATAVADDR0_Pos 12U
1030#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
1032#define DWT_FUNCTION_DATAVSIZE_Pos 10U
1033#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
1035#define DWT_FUNCTION_LNK1ENA_Pos 9U
1036#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
1038#define DWT_FUNCTION_DATAVMATCH_Pos 8U
1039#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
1041#define DWT_FUNCTION_CYCMATCH_Pos 7U
1042#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
1044#define DWT_FUNCTION_EMITRANGE_Pos 5U
1045#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
1047#define DWT_FUNCTION_FUNCTION_Pos 0U
1048#define DWT_FUNCTION_FUNCTION_Msk (0xFUL )
1067 uint32_t RESERVED0[2U];
1069 uint32_t RESERVED1[55U];
1071 uint32_t RESERVED2[131U];
1075 uint32_t RESERVED3[759U];
1079 uint32_t RESERVED4[1U];
1083 uint32_t RESERVED5[39U];
1086 uint32_t RESERVED7[8U];
1092#define TPI_ACPR_PRESCALER_Pos 0U
1093#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL )
1096#define TPI_SPPR_TXMODE_Pos 0U
1097#define TPI_SPPR_TXMODE_Msk (0x3UL )
1100#define TPI_FFSR_FtNonStop_Pos 3U
1101#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1103#define TPI_FFSR_TCPresent_Pos 2U
1104#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1106#define TPI_FFSR_FtStopped_Pos 1U
1107#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1109#define TPI_FFSR_FlInProg_Pos 0U
1110#define TPI_FFSR_FlInProg_Msk (0x1UL )
1113#define TPI_FFCR_TrigIn_Pos 8U
1114#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1116#define TPI_FFCR_EnFCont_Pos 1U
1117#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1120#define TPI_TRIGGER_TRIGGER_Pos 0U
1121#define TPI_TRIGGER_TRIGGER_Msk (0x1UL )
1124#define TPI_FIFO0_ITM_ATVALID_Pos 29U
1125#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)
1127#define TPI_FIFO0_ITM_bytecount_Pos 27U
1128#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
1130#define TPI_FIFO0_ETM_ATVALID_Pos 26U
1131#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)
1133#define TPI_FIFO0_ETM_bytecount_Pos 24U
1134#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
1136#define TPI_FIFO0_ETM2_Pos 16U
1137#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
1139#define TPI_FIFO0_ETM1_Pos 8U
1140#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
1142#define TPI_FIFO0_ETM0_Pos 0U
1143#define TPI_FIFO0_ETM0_Msk (0xFFUL )
1146#define TPI_ITATBCTR2_ATREADY2_Pos 0U
1147#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL )
1149#define TPI_ITATBCTR2_ATREADY1_Pos 0U
1150#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL )
1153#define TPI_FIFO1_ITM_ATVALID_Pos 29U
1154#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)
1156#define TPI_FIFO1_ITM_bytecount_Pos 27U
1157#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
1159#define TPI_FIFO1_ETM_ATVALID_Pos 26U
1160#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)
1162#define TPI_FIFO1_ETM_bytecount_Pos 24U
1163#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
1165#define TPI_FIFO1_ITM2_Pos 16U
1166#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
1168#define TPI_FIFO1_ITM1_Pos 8U
1169#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
1171#define TPI_FIFO1_ITM0_Pos 0U
1172#define TPI_FIFO1_ITM0_Msk (0xFFUL )
1175#define TPI_ITATBCTR0_ATREADY2_Pos 0U
1176#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL )
1178#define TPI_ITATBCTR0_ATREADY1_Pos 0U
1179#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL )
1182#define TPI_ITCTRL_Mode_Pos 0U
1183#define TPI_ITCTRL_Mode_Msk (0x3UL )
1186#define TPI_DEVID_NRZVALID_Pos 11U
1187#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1189#define TPI_DEVID_MANCVALID_Pos 10U
1190#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1192#define TPI_DEVID_PTINVALID_Pos 9U
1193#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1195#define TPI_DEVID_MinBufSz_Pos 6U
1196#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
1198#define TPI_DEVID_AsynClkIn_Pos 5U
1199#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
1201#define TPI_DEVID_NrTraceInput_Pos 0U
1202#define TPI_DEVID_NrTraceInput_Msk (0x1FUL )
1205#define TPI_DEVTYPE_SubType_Pos 4U
1206#define TPI_DEVTYPE_SubType_Msk (0xFUL )
1208#define TPI_DEVTYPE_MajorType_Pos 0U
1209#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1214#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1228 __IOM uint32_t CTRL;
1230 __IOM uint32_t RBAR;
1231 __IOM uint32_t RASR;
1232 __IOM uint32_t RBAR_A1;
1233 __IOM uint32_t RASR_A1;
1234 __IOM uint32_t RBAR_A2;
1235 __IOM uint32_t RASR_A2;
1236 __IOM uint32_t RBAR_A3;
1237 __IOM uint32_t RASR_A3;
1240#define MPU_TYPE_RALIASES 4U
1243#define MPU_TYPE_IREGION_Pos 16U
1244#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1246#define MPU_TYPE_DREGION_Pos 8U
1247#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1249#define MPU_TYPE_SEPARATE_Pos 0U
1250#define MPU_TYPE_SEPARATE_Msk (1UL )
1253#define MPU_CTRL_PRIVDEFENA_Pos 2U
1254#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1256#define MPU_CTRL_HFNMIENA_Pos 1U
1257#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1259#define MPU_CTRL_ENABLE_Pos 0U
1260#define MPU_CTRL_ENABLE_Msk (1UL )
1263#define MPU_RNR_REGION_Pos 0U
1264#define MPU_RNR_REGION_Msk (0xFFUL )
1267#define MPU_RBAR_ADDR_Pos 5U
1268#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
1270#define MPU_RBAR_VALID_Pos 4U
1271#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
1273#define MPU_RBAR_REGION_Pos 0U
1274#define MPU_RBAR_REGION_Msk (0xFUL )
1277#define MPU_RASR_ATTRS_Pos 16U
1278#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
1280#define MPU_RASR_XN_Pos 28U
1281#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
1283#define MPU_RASR_AP_Pos 24U
1284#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
1286#define MPU_RASR_TEX_Pos 19U
1287#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
1289#define MPU_RASR_S_Pos 18U
1290#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
1292#define MPU_RASR_C_Pos 17U
1293#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
1295#define MPU_RASR_B_Pos 16U
1296#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
1298#define MPU_RASR_SRD_Pos 8U
1299#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
1301#define MPU_RASR_SIZE_Pos 1U
1302#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
1304#define MPU_RASR_ENABLE_Pos 0U
1305#define MPU_RASR_ENABLE_Msk (1UL )
1323 uint32_t RESERVED0[1U];
1333#define FPU_FPCCR_ASPEN_Pos 31U
1334#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
1336#define FPU_FPCCR_LSPEN_Pos 30U
1337#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
1339#define FPU_FPCCR_MONRDY_Pos 8U
1340#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
1342#define FPU_FPCCR_BFRDY_Pos 6U
1343#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
1345#define FPU_FPCCR_MMRDY_Pos 5U
1346#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
1348#define FPU_FPCCR_HFRDY_Pos 4U
1349#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
1351#define FPU_FPCCR_THREAD_Pos 3U
1352#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
1354#define FPU_FPCCR_USER_Pos 1U
1355#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
1357#define FPU_FPCCR_LSPACT_Pos 0U
1358#define FPU_FPCCR_LSPACT_Msk (1UL )
1361#define FPU_FPCAR_ADDRESS_Pos 3U
1362#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
1365#define FPU_FPDSCR_AHP_Pos 26U
1366#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
1368#define FPU_FPDSCR_DN_Pos 25U
1369#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
1371#define FPU_FPDSCR_FZ_Pos 24U
1372#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
1374#define FPU_FPDSCR_RMode_Pos 22U
1375#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
1378#define FPU_MVFR0_FP_rounding_modes_Pos 28U
1379#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
1381#define FPU_MVFR0_Short_vectors_Pos 24U
1382#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
1384#define FPU_MVFR0_Square_root_Pos 20U
1385#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
1387#define FPU_MVFR0_Divide_Pos 16U
1388#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
1390#define FPU_MVFR0_FP_excep_trapping_Pos 12U
1391#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
1393#define FPU_MVFR0_Double_precision_Pos 8U
1394#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
1396#define FPU_MVFR0_Single_precision_Pos 4U
1397#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
1399#define FPU_MVFR0_A_SIMD_registers_Pos 0U
1400#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL )
1403#define FPU_MVFR1_FP_fused_MAC_Pos 28U
1404#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
1406#define FPU_MVFR1_FP_HPFP_Pos 24U
1407#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
1409#define FPU_MVFR1_D_NaN_mode_Pos 4U
1410#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
1412#define FPU_MVFR1_FtZ_mode_Pos 0U
1413#define FPU_MVFR1_FtZ_mode_Msk (0xFUL )
1417#define FPU_MVFR2_VFP_Misc_Pos 4U
1418#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos)
1442#define CoreDebug_DHCSR_DBGKEY_Pos 16U
1443#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1445#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1446#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1448#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1449#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1451#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1452#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1454#define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1455#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1457#define CoreDebug_DHCSR_S_HALT_Pos 17U
1458#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1460#define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1461#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1463#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
1464#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1466#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1467#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1469#define CoreDebug_DHCSR_C_STEP_Pos 2U
1470#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1472#define CoreDebug_DHCSR_C_HALT_Pos 1U
1473#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1475#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1476#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL )
1479#define CoreDebug_DCRSR_REGWnR_Pos 16U
1480#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1482#define CoreDebug_DCRSR_REGSEL_Pos 0U
1483#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL )
1486#define CoreDebug_DEMCR_TRCENA_Pos 24U
1487#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1489#define CoreDebug_DEMCR_MON_REQ_Pos 19U
1490#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1492#define CoreDebug_DEMCR_MON_STEP_Pos 18U
1493#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1495#define CoreDebug_DEMCR_MON_PEND_Pos 17U
1496#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1498#define CoreDebug_DEMCR_MON_EN_Pos 16U
1499#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1501#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1502#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1504#define CoreDebug_DEMCR_VC_INTERR_Pos 9U
1505#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1507#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
1508#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1510#define CoreDebug_DEMCR_VC_STATERR_Pos 7U
1511#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1513#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
1514#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1516#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
1517#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1519#define CoreDebug_DEMCR_VC_MMERR_Pos 4U
1520#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1522#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1523#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL )
1541#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1549#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1562#define SCS_BASE (0xE000E000UL)
1563#define ITM_BASE (0xE0000000UL)
1564#define DWT_BASE (0xE0001000UL)
1565#define TPI_BASE (0xE0040000UL)
1566#define CoreDebug_BASE (0xE000EDF0UL)
1567#define SysTick_BASE (SCS_BASE + 0x0010UL)
1568#define NVIC_BASE (SCS_BASE + 0x0100UL)
1569#define SCB_BASE (SCS_BASE + 0x0D00UL)
1571#define SCnSCB ((SCnSCB_Type *) SCS_BASE )
1572#define SCB ((SCB_Type *) SCB_BASE )
1573#define SysTick ((SysTick_Type *) SysTick_BASE )
1574#define NVIC ((NVIC_Type *) NVIC_BASE )
1575#define ITM ((ITM_Type *) ITM_BASE )
1576#define DWT ((DWT_Type *) DWT_BASE )
1577#define TPI ((TPI_Type *) TPI_BASE )
1578#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
1580#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1581 #define MPU_BASE (SCS_BASE + 0x0D90UL)
1582 #define MPU ((MPU_Type *) MPU_BASE )
1585#define FPU_BASE (SCS_BASE + 0x0F30UL)
1586#define FPU ((FPU_Type *) FPU_BASE )
1601#define ITM_TCR_TraceBusID_Pos (ITM_TCR_TRACEBUSID_Pos)
1602#define ITM_TCR_TraceBusID_Msk (ITM_TCR_TRACEBUSID_Msk)
1604#define ITM_TCR_TSPrescale_Pos (ITM_TCR_TSPRESCALE_Pos)
1605#define ITM_TCR_TSPrescale_Msk (ITM_TCR_TSPRESCALE_Msk)
1608#define ITM_LSR_ByteAcc_Pos (ITM_LSR_BYTEACC_Pos)
1609#define ITM_LSR_ByteAcc_Msk (ITM_LSR_BYTEACC_Msk)
1611#define ITM_LSR_Access_Pos (ITM_LSR_ACCESS_Pos)
1612#define ITM_LSR_Access_Msk (ITM_LSR_ACCESS_Msk)
1614#define ITM_LSR_Present_Pos (ITM_LSR_PRESENT_Pos)
1615#define ITM_LSR_Present_Msk (ITM_LSR_PRESENT_Msk)
1643#ifdef CMSIS_NVIC_VIRTUAL
1644 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1645 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1647 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1649 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1650 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1651 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1652 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1653 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1654 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1655 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1656 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1657 #define NVIC_GetActive __NVIC_GetActive
1658 #define NVIC_SetPriority __NVIC_SetPriority
1659 #define NVIC_GetPriority __NVIC_GetPriority
1660 #define NVIC_SystemReset __NVIC_SystemReset
1663#ifdef CMSIS_VECTAB_VIRTUAL
1664 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1665 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1667 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1669 #define NVIC_SetVector __NVIC_SetVector
1670 #define NVIC_GetVector __NVIC_GetVector
1673#define NVIC_USER_IRQ_OFFSET 16
1677#define EXC_RETURN_HANDLER (0xFFFFFFF1UL)
1678#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL)
1679#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL)
1680#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL)
1681#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL)
1682#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL)
1697 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1699 reg_value =
SCB->AIRCR;
1701 reg_value = (reg_value |
1704 SCB->AIRCR = reg_value;
1727 if ((int32_t)(IRQn) >= 0)
1729 __COMPILER_BARRIER();
1730 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1731 __COMPILER_BARRIER();
1746 if ((int32_t)(IRQn) >= 0)
1748 return((uint32_t)(((
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1765 if ((int32_t)(IRQn) >= 0)
1767 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1784 if ((int32_t)(IRQn) >= 0)
1786 return((uint32_t)(((
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1803 if ((int32_t)(IRQn) >= 0)
1805 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1818 if ((int32_t)(IRQn) >= 0)
1820 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1835 if ((int32_t)(IRQn) >= 0)
1837 return((uint32_t)(((
NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1857 if ((int32_t)(IRQn) >= 0)
1859 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1863 SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1880 if ((int32_t)(IRQn) >= 0)
1882 return(((uint32_t)
NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
1886 return(((uint32_t)
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1902__STATIC_INLINE uint32_t
NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1904 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1905 uint32_t PreemptPriorityBits;
1906 uint32_t SubPriorityBits;
1908 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1909 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1912 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1913 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1929__STATIC_INLINE
void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t*
const pPreemptPriority, uint32_t*
const pSubPriority)
1931 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1932 uint32_t PreemptPriorityBits;
1933 uint32_t SubPriorityBits;
1935 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1936 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1938 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1939 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1954 uint32_t *vectors = (uint32_t *)
SCB->VTOR;
1955 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1970 uint32_t *vectors = (uint32_t *)
SCB->VTOR;
1971 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1999#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2050#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2063__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2070 SysTick->LOAD = (uint32_t)(ticks - 1UL);
2071 NVIC_SetPriority (
SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);
2094#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
2108 ((
ITM->TER & 1UL ) != 0UL) )
2110 while (
ITM->PORT[0U].u32 == 0UL)
2114 ITM->PORT[0U].u8 = (uint8_t)ch;
CMSIS compiler generic header file.
CMSIS Core(M) Version definitions.
#define __NOP()
No Operation.
Definition: cmsis_gcc.h:245
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:286
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:275
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: core_cm4.h:1979
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: core_cm4.h:1952
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_cm4.h:1929
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: core_cm4.h:1968
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm4.h:1855
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm4.h:1816
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm4.h:1782
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_cm4.h:2022
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: core_cm4.h:1725
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: core_cm4.h:1713
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_cm4.h:1833
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm4.h:1801
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: core_cm4.h:1744
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_cm4.h:1902
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: core_cm4.h:1763
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm4.h:1877
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: core_cm4.h:1694
#define FPU_MVFR0_Double_precision_Msk
Definition: core_cm4.h:1394
#define FPU_MVFR0_Single_precision_Msk
Definition: core_cm4.h:1397
#define ITM_TCR_ITMENA_Msk
Definition: core_cm4.h:891
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_cm4.h:544
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_cm4.h:535
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm4.h:534
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm4.h:547
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_cm4.h:543
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm4.h:795
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm4.h:799
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm4.h:792
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm4.h:789
__IOM uint32_t MASK2
Definition: core_cm4.h:935
__IM uint32_t SSPSR
Definition: core_cm4.h:1065
__IOM uint32_t TCR
Definition: core_cm4.h:841
__IM uint32_t FIFO1
Definition: core_cm4.h:1081
__IOM uint32_t ICSR
Definition: core_cm4.h:460
__IOM uint32_t CFSR
Definition: core_cm4.h:467
__IOM uint32_t CLAIMCLR
Definition: core_cm4.h:1085
__IOM uint32_t CYCCNT
Definition: core_cm4.h:919
volatile int32_t ITM_RxBuffer
__IOM uint32_t SPPR
Definition: core_cm4.h:1070
__IOM uint32_t ACTLR
Definition: core_cm4.h:740
__IOM uint32_t HFSR
Definition: core_cm4.h:468
__IOM uint32_t VTOR
Definition: core_cm4.h:461
__IOM uint32_t DFSR
Definition: core_cm4.h:469
uint32_t w
Definition: core_cm4.h:350
__IOM uint32_t FOLDCNT
Definition: core_cm4.h:924
uint32_t Z
Definition: core_cm4.h:347
__IM uint32_t CPUID
Definition: core_cm4.h:459
uint32_t Q
Definition: core_cm4.h:283
__IOM uint32_t MASK3
Definition: core_cm4.h:939
__IM uint32_t PID7
Definition: core_cm4.h:850
__IOM uint32_t CPICNT
Definition: core_cm4.h:920
__IOM uint32_t MMFAR
Definition: core_cm4.h:470
uint32_t GE
Definition: core_cm4.h:340
__IOM uint32_t CCR
Definition: core_cm4.h:464
uint32_t N
Definition: core_cm4.h:348
__IM uint32_t CID0
Definition: core_cm4.h:855
__IM uint32_t ICTR
Definition: core_cm4.h:739
uint32_t nPRIV
Definition: core_cm4.h:392
__OM uint32_t STIR
Definition: core_cm4.h:437
__IM uint32_t LSR
Definition: core_cm4.h:845
__IOM uint32_t COMP1
Definition: core_cm4.h:930
__IOM uint32_t SCR
Definition: core_cm4.h:463
uint32_t Z
Definition: core_cm4.h:286
uint32_t ISR
Definition: core_cm4.h:337
__IOM uint32_t FFCR
Definition: core_cm4.h:1073
__IOM uint32_t BFAR
Definition: core_cm4.h:471
uint32_t C
Definition: core_cm4.h:346
__IOM uint32_t SLEEPCNT
Definition: core_cm4.h:922
__IM uint32_t CID3
Definition: core_cm4.h:858
__IOM uint32_t LOAD
Definition: core_cm4.h:779
__IM uint32_t MVFR2
Definition: core_cm4.h:1329
uint32_t w
Definition: core_cm4.h:322
__IM uint32_t TRIGGER
Definition: core_cm4.h:1076
__IM uint32_t MVFR0
Definition: core_cm4.h:1327
__IOM uint32_t FUNCTION3
Definition: core_cm4.h:940
__IOM uint32_t FPCAR
Definition: core_cm4.h:1325
__IOM uint32_t FUNCTION0
Definition: core_cm4.h:928
__OM uint32_t u32
Definition: core_cm4.h:834
__IOM uint32_t FPDSCR
Definition: core_cm4.h:1326
__IOM uint32_t COMP2
Definition: core_cm4.h:934
__IOM uint32_t COMP0
Definition: core_cm4.h:926
__IM uint32_t PCSR
Definition: core_cm4.h:925
__IM uint32_t MVFR1
Definition: core_cm4.h:1328
uint32_t w
Definition: core_cm4.h:397
__IM uint32_t FFSR
Definition: core_cm4.h:1072
uint32_t _reserved1
Definition: core_cm4.h:341
__IOM uint32_t SHCSR
Definition: core_cm4.h:466
uint32_t N
Definition: core_cm4.h:287
uint32_t T
Definition: core_cm4.h:342
__OM uint32_t LAR
Definition: core_cm4.h:844
__IM uint32_t CID2
Definition: core_cm4.h:857
uint32_t V
Definition: core_cm4.h:284
__IOM uint32_t MASK0
Definition: core_cm4.h:927
__IM uint32_t PID2
Definition: core_cm4.h:853
__IM uint32_t DFR
Definition: core_cm4.h:474
__IOM uint32_t COMP3
Definition: core_cm4.h:938
uint32_t C
Definition: core_cm4.h:285
__IOM uint32_t CTRL
Definition: core_cm4.h:778
__IOM uint32_t CSPSR
Definition: core_cm4.h:1066
__IM uint32_t PID1
Definition: core_cm4.h:852
uint32_t SPSEL
Definition: core_cm4.h:393
__IOM uint32_t FUNCTION1
Definition: core_cm4.h:932
__OM uint16_t u16
Definition: core_cm4.h:833
__IOM uint32_t VAL
Definition: core_cm4.h:780
__IOM uint32_t ACPR
Definition: core_cm4.h:1068
__IOM uint32_t EXCCNT
Definition: core_cm4.h:921
__IM uint32_t FIFO0
Definition: core_cm4.h:1077
uint32_t ICI_IT_1
Definition: core_cm4.h:339
#define ITM_RXBUFFER_EMPTY
Definition: core_cm4.h:2094
__IOM uint32_t ITCTRL
Definition: core_cm4.h:1082
__IM uint32_t ITATBCTR0
Definition: core_cm4.h:1080
__IOM uint32_t DCRDR
Definition: core_cm4.h:1437
__IOM uint32_t MASK1
Definition: core_cm4.h:931
__IM uint32_t PID4
Definition: core_cm4.h:847
__IOM uint32_t FUNCTION2
Definition: core_cm4.h:936
__IM uint32_t ITATBCTR2
Definition: core_cm4.h:1078
uint32_t ISR
Definition: core_cm4.h:319
__IM uint32_t PID0
Definition: core_cm4.h:851
__IOM uint32_t AFSR
Definition: core_cm4.h:472
__IM uint32_t DEVID
Definition: core_cm4.h:1087
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: core_cm4.h:2126
__IM uint32_t CID1
Definition: core_cm4.h:856
uint32_t FPCA
Definition: core_cm4.h:394
uint32_t _reserved1
Definition: core_cm4.h:282
__IOM uint32_t CPACR
Definition: core_cm4.h:479
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
ITM Send Character.
Definition: core_cm4.h:2105
__IOM uint32_t LSUCNT
Definition: core_cm4.h:923
__IOM uint32_t TER
Definition: core_cm4.h:837
uint32_t _reserved0
Definition: core_cm4.h:320
__IM uint32_t PID6
Definition: core_cm4.h:849
__IOM uint32_t AIRCR
Definition: core_cm4.h:462
__IOM uint32_t DHCSR
Definition: core_cm4.h:1435
__IM uint32_t FSCR
Definition: core_cm4.h:1074
__IM uint32_t DEVTYPE
Definition: core_cm4.h:1088
uint32_t GE
Definition: core_cm4.h:281
__IOM uint32_t CTRL
Definition: core_cm4.h:918
uint32_t Q
Definition: core_cm4.h:344
uint32_t ICI_IT_2
Definition: core_cm4.h:343
uint32_t w
Definition: core_cm4.h:289
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: core_cm4.h:2146
__OM uint8_t u8
Definition: core_cm4.h:832
__IOM uint32_t TPR
Definition: core_cm4.h:839
__IOM uint32_t DEMCR
Definition: core_cm4.h:1438
__IM uint32_t ADR
Definition: core_cm4.h:475
uint32_t V
Definition: core_cm4.h:345
__IOM uint32_t FPCCR
Definition: core_cm4.h:1324
__IM uint32_t PID3
Definition: core_cm4.h:854
uint32_t _reserved0
Definition: core_cm4.h:338
__IOM uint32_t CLAIMSET
Definition: core_cm4.h:1084
uint32_t _reserved0
Definition: core_cm4.h:395
__OM uint32_t DCRSR
Definition: core_cm4.h:1436
__IM uint32_t PID5
Definition: core_cm4.h:848
uint32_t _reserved0
Definition: core_cm4.h:280
__IM uint32_t CALIB
Definition: core_cm4.h:781
#define SCB
Definition: core_cm4.h:1572
#define ITM
Definition: core_cm4.h:1575
#define FPU
Definition: core_cm4.h:1586
#define NVIC
Definition: core_cm4.h:1574
#define SysTick
Definition: core_cm4.h:1573
@ SysTick_IRQn
Definition: same70j19.h:68
IRQn_Type
STM32H7XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32h723xx.h:49
This header file provides CMSIS interfaces.
Structure type to access the Core Debug Register (CoreDebug).
Definition: core_cm4.h:1434
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_cm4.h:917
Structure type to access the Floating Point Unit (FPU).
Definition: core_cm4.h:1322
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_cm4.h:829
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm4.h:424
Structure type to access the System Control Block (SCB).
Definition: core_cm4.h:458
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_cm4.h:737
Structure type to access the System Timer (SysTick).
Definition: core_cm4.h:777
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_cm4.h:1064
Union type to access the Application Program Status Register (APSR).
Definition: core_cm4.h:277
Union type to access the Control Registers (CONTROL).
Definition: core_cm4.h:389
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm4.h:316
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm4.h:334