41#ifndef _RTEMS_SCORE_CPU_H
42#define _RTEMS_SCORE_CPU_H
51#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
53#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
55#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
57#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE
59#define CPU_ISR_PASSES_FRAME_POINTER FALSE
61#define CPU_HARDWARE_FP FALSE
63#define CPU_SOFTWARE_FP FALSE
65#define CPU_ALL_TASKS_ARE_FP FALSE
67#define CPU_IDLE_TASK_IS_FP FALSE
69#define CPU_USE_DEFERRED_FP_SWITCH FALSE
71#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
73#define CPU_STACK_GROWS_UP FALSE
76#define CPU_CACHE_LINE_BYTES 32
78#define CPU_STRUCTURE_ALIGNMENT \
79 RTEMS_SECTION( ".sdata" ) RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
81#define CPU_STACK_MINIMUM_SIZE (4 * 1024)
83#define CPU_SIZEOF_POINTER 4
89#define CPU_ALIGNMENT 4
91#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
97#define CPU_STACK_ALIGNMENT 4
99#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
108#define CPU_MODES_INTERRUPT_MASK 0x3f
110#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
112#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
114#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
116#define CPU_MAXIMUM_PROCESSORS 32
148 uint32_t isr_dispatch_disable;
150 uint32_t stack_mpubase;
151 uint32_t stack_mpuacc;
154#define _CPU_Context_Get_SP( _context ) \
214#define _CPU_ISR_Disable( _isr_cookie ) \
218 "rdctl %0, status\n" \
219 "movhi %1, %%hiadj(_Nios2_ISR_Status_mask)\n" \
220 "addi %1, %1, %%lo(_Nios2_ISR_Status_mask)\n" \
222 "ori %1, %1, %%lo(_Nios2_ISR_Status_bits)\n" \
224 : "=&r" (_isr_cookie), "=&r" (_tmp) \
234#define _CPU_ISR_Enable( _isr_cookie ) \
235 __builtin_wrctl( 0, (int) _isr_cookie )
248#define _CPU_ISR_Flash( _isr_cookie ) \
250 int _status = __builtin_rdctl( 0 ); \
251 __builtin_wrctl( 0, (int) _isr_cookie ); \
252 __builtin_wrctl( 0, _status ); \
255bool _CPU_ISR_Is_enabled( uint32_t level );
299void _CPU_Context_Initialize(
301 void *stack_area_begin,
302 size_t stack_area_size,
304 void (*entry_point)(
void ),
309#define _CPU_Context_Restart_self( _the_context ) \
310 _CPU_Context_restore( (_the_context) );
317typedef void ( *CPU_ISR_handler )( uint32_t );
321 CPU_ISR_handler new_handler,
322 CPU_ISR_handler *old_handler
333static inline uint32_t CPU_swap_u32( uint32_t value )
335 uint32_t byte1, byte2, byte3, byte4, swapped;
337 byte4 = (value >> 24) & 0xff;
338 byte3 = (value >> 16) & 0xff;
339 byte2 = (value >> 8) & 0xff;
340 byte1 = value & 0xff;
342 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
347#define CPU_swap_u16( value ) \
348 (((value&0xff) << 8) | ((value >> 8)&0xff))
350typedef uint32_t CPU_Counter_ticks;
This header file provides basic definitions used by the API and the implementation.
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
#define _CPU_ISR_Set_level(_new_level)
Definition: cpu.h:378
#define ra
return address */
Definition: regs.h:66
#define sp
stack-pointer */
Definition: regs.h:64
#define fp
frame-pointer */
Definition: regs.h:65
#define gp
global data pointer */
Definition: regs.h:63
NIOS II Set up Basic CPU Dependency Settings Based on Compiler Settings.
rtems_termios_device_context * context
Definition: console-config.c:62
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
Thread register context.
Definition: cpu.h:173