55#ifndef _RTEMS_SCORE_CPU_H
56#define _RTEMS_SCORE_CPU_H
63#include <rtems/score/no_cpu.h>
78#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
89#define CPU_ISR_PASSES_FRAME_POINTER FALSE
126#if ( NO_CPU_HAS_FPU == 1 )
127#define CPU_HARDWARE_FP TRUE
129#define CPU_HARDWARE_FP FALSE
131#define CPU_SOFTWARE_FP FALSE
157#define CPU_ALL_TASKS_ARE_FP TRUE
174#define CPU_IDLE_TASK_IS_FP FALSE
205#define CPU_USE_DEFERRED_FP_SWITCH TRUE
217#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
230#define CPU_STACK_GROWS_UP TRUE
237#define CPU_CACHE_LINE_BYTES 32
250#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
263#define CPU_MODES_INTERRUPT_MASK 0x00000001
269#define CPU_MAXIMUM_PROCESSORS 32
277#define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE
413 volatile bool is_executing;
426#define _CPU_Context_Get_SP( _context ) \
427 (_context)->stack_pointer
453 uint32_t special_interrupt_register;
508#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
519#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
531#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
543#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
551#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
564#define CPU_STACK_MINIMUM_SIZE (1024*4)
573#define CPU_SIZEOF_POINTER 4
586#define CPU_ALIGNMENT 8
610#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
624#define CPU_STACK_ALIGNMENT CPU_HEAP_ALIGNMENT
632#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
650#define _CPU_ISR_Disable( _isr_cookie ) \
668#define _CPU_ISR_Enable( _isr_cookie ) \
686#define _CPU_ISR_Flash( _isr_cookie ) \
699static inline bool _CPU_ISR_Is_enabled( uint32_t level )
721#define _CPU_ISR_Set_level( new_level ) \
758#define _CPU_Context_Destroy( _the_thread, _the_context ) \
799#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
800 _isr, _entry_point, _is_fp, _tls_area ) \
819#define _CPU_Context_Restart_self( _the_context ) \
820 _CPU_Context_restore( (_the_context) );
840#define _CPU_Context_Initialize_fp( _destination ) \
842 *(*(_destination)) = _CPU_Null_fp_context; \
864#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
930#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
931#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
950#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
952#define _CPU_Priority_Mask( _bit_number ) \
953 ( 1 << (_bit_number) )
971#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
973#define _CPU_Priority_bits_index( _priority ) \
991typedef void ( *CPU_ISR_raw_handler )( void );
1011 CPU_ISR_raw_handler new_handler,
1012 CPU_ISR_raw_handler *old_handler
1015typedef void ( *CPU_ISR_handler )( uint32_t );
1035 CPU_ISR_handler new_handler,
1036 CPU_ISR_handler *old_handler
1153 uint32_t processor_state_register;
1154 uint32_t integer_registers [1];
1155 double float_registers [1];
1165#ifdef RTEMS_EXCEPTION_EXTENSIONS
1199 void _CPU_Exception_disable_thread_dispatch(
void );
1265static inline uint32_t CPU_swap_u32(
1269 uint32_t byte1, byte2, byte3, byte4, swapped;
1271 byte4 = (value >> 24) & 0xff;
1272 byte3 = (value >> 16) & 0xff;
1273 byte2 = (value >> 8) & 0xff;
1274 byte1 = value & 0xff;
1276 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1286#define CPU_swap_u16( value ) \
1287 (((value&0xff) << 8) | ((value >> 8)&0xff))
1294typedef uint32_t CPU_Counter_ticks;
1332 uint32_t _CPU_SMP_Initialize(
void );
1347 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
1363 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
1375 void _CPU_SMP_Prepare_start_multitasking(
void );
1384 static inline uint32_t _CPU_SMP_Get_current_processor(
void )
1397 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1404 static inline bool _CPU_Context_Get_is_executing(
1417 static inline void _CPU_Context_Set_is_executing(
1422 context->is_executing = is_executing;
This header file provides basic definitions used by the API and the implementation.
void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.c:100
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
rtems_termios_device_context * context
Definition: console-config.c:62
#define _CPU_Context_restore_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:901
#define _CPU_Context_save_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:895
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
SPARC basic context.
Definition: cpu.h:213
double some_float_register
Definition: cpu.h:437
Thread register context.
Definition: cpu.h:173
uint32_t some_integer_register
Definition: cpu.h:355
uint32_t some_system_register
Definition: cpu.h:360
uint32_t stack_pointer
Definition: cpu.h:366