RTEMS 6.1-rc7
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irq.h
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/*
4 * RTEMS generic MPC83xx BSP
5 *
6 * This file declares constants of the interrupt controller.
7 */
8
9/*
10 * Copyright (C) 2008, 2010 embedded brains GmbH & Co. KG
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#ifndef GEN83xx_IRQ_IRQ_H
35#define GEN83xx_IRQ_IRQ_H
36
37#include <rtems.h>
38#include <rtems/irq.h>
39#include <rtems/irq-extension.h>
40
41#include <bspopts.h>
42
43/*
44 * the following definitions specify the indices used
45 * to interface the interrupt handler API
46 */
47
48/*
49 * Peripheral IRQ handlers related definitions
50 */
51#define BSP_IPIC_PER_IRQ_NUMBER 128
52#define BSP_IPIC_IRQ_LOWEST_OFFSET 0
53#define BSP_IPIC_IRQ_MAX_OFFSET (BSP_IPIC_IRQ_LOWEST_OFFSET\
54 +BSP_IPIC_PER_IRQ_NUMBER-1)
55
56#define BSP_IS_IPIC_IRQ(irqnum) \
57 (((irqnum) >= BSP_IPIC_IRQ_LOWEST_OFFSET) && \
58 ((irqnum) <= BSP_IPIC_IRQ_MAX_OFFSET))
59/*
60 * Processor IRQ handlers related definitions
61 */
62#define BSP_PROCESSOR_IRQ_NUMBER 1
63#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_IPIC_IRQ_MAX_OFFSET+1)
64#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\
65 +BSP_PROCESSOR_IRQ_NUMBER-1)
66
67#define BSP_IS_PROCESSOR_IRQ(irqnum) \
68 (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) && \
69 ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET))
70/*
71 * Summary
72 */
73#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET+1)
74#define BSP_LOWEST_OFFSET BSP_IPIC_IRQ_LOWEST_OFFSET
75#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET
76
77#define BSP_IS_VALID_IRQ(irqnum) \
78 (BSP_IS_PROCESSOR_IRQ(irqnum) \
79 || BSP_IS_IPIC_IRQ(irqnum))
80
81#ifndef ASM
82#ifdef __cplusplus
83extern "C" {
84#endif
85
86/*
87 * index table for the module specific handlers, a few entries are only placeholders
88 */
89 typedef enum {
90 BSP_IPIC_IRQ_FIRST = BSP_IPIC_IRQ_LOWEST_OFFSET,
91 BSP_IPIC_IRQ_ERROR = BSP_IPIC_IRQ_LOWEST_OFFSET + 0,
92#if MPC83XX_CHIP_TYPE / 10 == 830
93 BSP_IPIC_IRQ_DMA1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 3,
94 BSP_IPIC_IRQ_UART = BSP_IPIC_IRQ_LOWEST_OFFSET + 9,
95 BSP_IPIC_IRQ_FLEXCAN = BSP_IPIC_IRQ_LOWEST_OFFSET + 10,
96#else
97 BSP_IPIC_IRQ_UART1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 9,
98 BSP_IPIC_IRQ_UART2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 10,
99 BSP_IPIC_IRQ_SEC = BSP_IPIC_IRQ_LOWEST_OFFSET + 11,
100#endif
101 BSP_IPIC_IRQ_I2C1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 14,
102 BSP_IPIC_IRQ_I2C2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 15,
103 BSP_IPIC_IRQ_SPI = BSP_IPIC_IRQ_LOWEST_OFFSET + 16,
104 BSP_IPIC_IRQ_IRQ1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 17,
105 BSP_IPIC_IRQ_IRQ2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 18,
106 BSP_IPIC_IRQ_IRQ3 = BSP_IPIC_IRQ_LOWEST_OFFSET + 19,
107#if MPC83XX_CHIP_TYPE / 10 == 830
108 BSP_IPIC_IRQ_QUICC_HI = BSP_IPIC_IRQ_LOWEST_OFFSET + 32,
109 BSP_IPIC_IRQ_QUICC_LO = BSP_IPIC_IRQ_LOWEST_OFFSET + 33,
110#else
111 BSP_IPIC_IRQ_IRQ4 = BSP_IPIC_IRQ_LOWEST_OFFSET + 20,
112 BSP_IPIC_IRQ_IRQ5 = BSP_IPIC_IRQ_LOWEST_OFFSET + 21,
113 BSP_IPIC_IRQ_IRQ6 = BSP_IPIC_IRQ_LOWEST_OFFSET + 22,
114 BSP_IPIC_IRQ_IRQ7 = BSP_IPIC_IRQ_LOWEST_OFFSET + 23,
115 BSP_IPIC_IRQ_TSEC1_TX = BSP_IPIC_IRQ_LOWEST_OFFSET + 32,
116 BSP_IPIC_IRQ_TSEC1_RX = BSP_IPIC_IRQ_LOWEST_OFFSET + 33,
117 BSP_IPIC_IRQ_TSEC1_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 34,
118 BSP_IPIC_IRQ_TSEC2_TX = BSP_IPIC_IRQ_LOWEST_OFFSET + 35,
119 BSP_IPIC_IRQ_TSEC2_RX = BSP_IPIC_IRQ_LOWEST_OFFSET + 36,
120 BSP_IPIC_IRQ_TSEC2_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 37,
121#endif
122 BSP_IPIC_IRQ_USB_DR = BSP_IPIC_IRQ_LOWEST_OFFSET + 38,
123#if MPC83XX_CHIP_TYPE / 10 == 830
124 BSP_IPIC_IRQ_ESDHC = BSP_IPIC_IRQ_LOWEST_OFFSET + 42,
125#else
126 BSP_IPIC_IRQ_USB_MPH = BSP_IPIC_IRQ_LOWEST_OFFSET + 39,
127#endif
128 BSP_IPIC_IRQ_IRQ0 = BSP_IPIC_IRQ_LOWEST_OFFSET + 48,
129 BSP_IPIC_IRQ_RTC_SEC = BSP_IPIC_IRQ_LOWEST_OFFSET + 64,
130 BSP_IPIC_IRQ_PIT = BSP_IPIC_IRQ_LOWEST_OFFSET + 65,
131 BSP_IPIC_IRQ_PCI1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 66,
132#if MPC83XX_CHIP_TYPE / 10 == 830
133 BSP_IPIC_IRQ_MSIR1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 67,
134#else
135 BSP_IPIC_IRQ_PCI2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 67,
136#endif
137 BSP_IPIC_IRQ_RTC_ALR = BSP_IPIC_IRQ_LOWEST_OFFSET + 68,
138 BSP_IPIC_IRQ_MU = BSP_IPIC_IRQ_LOWEST_OFFSET + 69,
139 BSP_IPIC_IRQ_SBA = BSP_IPIC_IRQ_LOWEST_OFFSET + 70,
140 BSP_IPIC_IRQ_DMA = BSP_IPIC_IRQ_LOWEST_OFFSET + 71,
141 BSP_IPIC_IRQ_GTM4 = BSP_IPIC_IRQ_LOWEST_OFFSET + 72,
142 BSP_IPIC_IRQ_GTM8 = BSP_IPIC_IRQ_LOWEST_OFFSET + 73,
143#if MPC83XX_CHIP_TYPE / 10 == 830
144 BSP_IPIC_IRQ_QUICC_PORTS = BSP_IPIC_IRQ_LOWEST_OFFSET + 74,
145 BSP_IPIC_IRQ_GPIO = BSP_IPIC_IRQ_LOWEST_OFFSET + 75,
146#else
147 BSP_IPIC_IRQ_GPIO1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 74,
148 BSP_IPIC_IRQ_GPIO2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 75,
149#endif
150 BSP_IPIC_IRQ_DDR = BSP_IPIC_IRQ_LOWEST_OFFSET + 76,
151 BSP_IPIC_IRQ_LBC = BSP_IPIC_IRQ_LOWEST_OFFSET + 77,
152 BSP_IPIC_IRQ_GTM2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 78,
153 BSP_IPIC_IRQ_GTM6 = BSP_IPIC_IRQ_LOWEST_OFFSET + 79,
154 BSP_IPIC_IRQ_PMC = BSP_IPIC_IRQ_LOWEST_OFFSET + 80,
155#if MPC83XX_CHIP_TYPE / 10 == 830
156 BSP_IPIC_IRQ_MSIR2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 81,
157 BSP_IPIC_IRQ_MSIR3 = BSP_IPIC_IRQ_LOWEST_OFFSET + 82,
158#else
159 BSP_IPIC_IRQ_GTM3 = BSP_IPIC_IRQ_LOWEST_OFFSET + 84,
160 BSP_IPIC_IRQ_GTM7 = BSP_IPIC_IRQ_LOWEST_OFFSET + 85,
161#endif
162#if MPC83XX_CHIP_TYPE / 10 == 830
163 BSP_IPIC_IRQ_MSIR4 = BSP_IPIC_IRQ_LOWEST_OFFSET + 86,
164 BSP_IPIC_IRQ_MSIR5 = BSP_IPIC_IRQ_LOWEST_OFFSET + 87,
165 BSP_IPIC_IRQ_MSIR6 = BSP_IPIC_IRQ_LOWEST_OFFSET + 88,
166 BSP_IPIC_IRQ_MSIR7 = BSP_IPIC_IRQ_LOWEST_OFFSET + 89,
167#endif
168 BSP_IPIC_IRQ_GTM1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 90,
169 BSP_IPIC_IRQ_GTM5 = BSP_IPIC_IRQ_LOWEST_OFFSET + 91,
170#if MPC83XX_CHIP_TYPE / 10 == 830
171 BSP_IPIC_IRQ_DMA1_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 94,
172 BSP_IPIC_IRQ_DPTC = BSP_IPIC_IRQ_LOWEST_OFFSET + 95,
173#endif
174
175 BSP_IPIC_IRQ_LAST = BSP_IPIC_IRQ_MAX_OFFSET,
176 } rtems_irq_symbolic_name;
177
178#define BSP_INTERRUPT_VECTOR_COUNT (BSP_MAX_OFFSET + 1)
179
180rtems_status_code mpc83xx_ipic_set_mask( rtems_vector_number vector, rtems_vector_number mask_vector, bool mask);
181
182#define MPC83XX_IPIC_INTERRUPT_NORMAL 0
183
184#define MPC83XX_IPIC_INTERRUPT_SYSTEM 1
185
186#define MPC83XX_IPIC_INTERRUPT_CRITICAL 2
187
188rtems_status_code mpc83xx_ipic_set_highest_priority_interrupt( rtems_vector_number vector, int type);
189
190#ifdef __cplusplus
191}
192#endif
193#endif /* ASM */
194
195#endif /* GEN83XX_IRQ_IRQ_H */
ISR_Vector_number rtems_vector_number
This integer type represents interrupt vector numbers.
Definition: intr.h:102
rtems_status_code
This enumeration provides status codes for directives of the Classic API.
Definition: status.h:85
This header file is provided for backward compatiblility.
This header file defines the RTEMS Classic API.