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fsl_gpc.h
1/*
2 * Copyright 2019-2021 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_GPC_H_
10#define _FSL_GPC_H_
11
12#include "fsl_common.h"
13
19/*******************************************************************************
20 * Definitions
21 ******************************************************************************/
22
26#define FSL_GPC_RIVER_VERSION (MAKE_VERSION(2, 2, 0))
29#define GPC_RESERVED_USE_MACRO 0xFFFFFFFFU
30
31/* GPC CPU module step control register offset. */
32#define GPC_CM_SLEEP_SSAR_CTRL_OFFSET (0x200)
33#define GPC_CM_SLEEP_LPCG_CTRL_OFFSET (0x208)
34#define GPC_CM_SLEEP_PLL_CTRL_OFFSET (0x210)
35#define GPC_CM_SLEEP_ISO_CTRL_OFFSET (0x218)
36#define GPC_CM_SLEEP_RESET_CTRL_OFFSET (0x220)
37#define GPC_CM_SLEEP_POWER_CTRL_OFFSET (0x228)
38#define GPC_CM_WAKEUP_POWER_CTRL_OFFSET (0x290)
39#define GPC_CM_WAKEUP_RESET_CTRL_OFFSET (0x298)
40#define GPC_CM_WAKEUP_ISO_CTRL_OFFSET (0x2A0)
41#define GPC_CM_WAKEUP_PLL_CTRL_OFFSET (0x2A8)
42#define GPC_CM_WAKEUP_LPCG_CTRL_OFFSET (0x2B0)
43#define GPC_CM_WAKEUP_SSAR_CTRL_OFFSET (0x2B8)
44
45/* GPC set point module step control register offset. */
46#define GPC_SP_SSAR_SAVE_CTRL_OFFSET (0x100)
47#define GPC_SP_LPCG_OFF_CTRL_OFFSET (0x110)
48#define GPC_SP_GROUP_DOWN_CTRL_OFFSET (0x120)
49#define GPC_SP_ROOT_DOWN_CTRL_OFFSET (0x130)
50#define GPC_SP_PLL_OFF_CTRL_OFFSET (0x140)
51#define GPC_SP_ISO_ON_CTRL_OFFSET (0x150)
52#define GPC_SP_RESET_EARLY_CTRL_OFFSET (0x160)
53#define GPC_SP_POWER_OFF_CTRL_OFFSET (0x170)
54#define GPC_SP_BIAS_OFF_CTRL_OFFSET (0x180)
55#define GPC_SP_BG_PLDO_OFF_CTRL_OFFSET (0x190)
56#define GPC_SP_LDO_PRE_CTRL_OFFSET (0x1A0)
57#define GPC_SP_DCDC_DOWN_CTRL_OFFSET (0x1B0)
58#define GPC_SP_DCDC_UP_CTRL_OFFSET (0x2B0)
59#define GPC_SP_LDO_POST_CTRL_OFFSET (0x210)
60#define GPC_SP_BG_PLDO_ON_CTRL_OFFSET (0x220)
61#define GPC_SP_BIAS_ON_CTRL_OFFSET (0x230)
62#define GPC_SP_POWER_ON_CTRL_OFFSET (0x240)
63#define GPC_SP_RESET_LATE_CTRL_OFFSET (0x250)
64#define GPC_SP_ISO_OFF_CTRL_OFFSET (0x260)
65#define GPC_SP_PLL_ON_CTRL_OFFSET (0x270)
66#define GPC_SP_ROOT_UP_CTRL_OFFSET (0x280)
67#define GPC_SP_GROUP_UP_CTRL_OFFSET (0x290)
68#define GPC_SP_LPCG_ON_CTRL_OFFSET (0x2A0)
69#define GPC_SP_SSAR_RESTORE_CTRL_OFFSET (0x2B0)
70
71/* GPC standby module step control register offset. */
72#define GPC_STBY_LPCG_IN_CTRL_OFFSET (0xF0)
73#define GPC_STBY_PLL_IN_CTRL_OFFSET (0x100)
74#define GPC_STBY_BIAS_IN_CTRL_OFFSET (0x110)
75#define GPC_STBY_PLDO_IN_CTRL_OFFSET (0x120)
76#define GPC_STBY_BANDGAP_IN_CTRL_OFFSET (0x128)
77#define GPC_STBY_LDO_IN_CTRL_OFFSET (0x130)
78#define GPC_STBY_DCDC_IN_CTRL_OFFSET (0x140)
79#define GPC_STBY_PMIC_IN_CTRL_OFFSET (0x150)
80#define GPC_STBY_PMIC_OUT_CTRL_OFFSET (0x200)
81#define GPC_STBY_DCDC_OUT_CTRL_OFFSET (0x210)
82#define GPC_STBY_LDO_OUT_CTRL_OFFSET (0x220)
83#define GPC_STBY_BANDGAP_OUT_CTRL_OFFSET (0x238)
84#define GPC_STBY_PLDO_OUT_CTRL_OFFSET (0x238)
85#define GPC_STBY_BIAS_OUT_CTRL_OFFSET (0x240)
86#define GPC_STBY_PLL_OUT_CTRL_OFFSET (0x250)
87#define GPC_STBY_LPCG_OUT_CTRL_OFFSET (0x260)
88
89/* GPC CPU module step register offset. */
90#define GPC_CM_STEP_REG_OFFSET \
91 { \
92 GPC_CM_SLEEP_SSAR_CTRL_OFFSET, GPC_CM_SLEEP_LPCG_CTRL_OFFSET, GPC_CM_SLEEP_PLL_CTRL_OFFSET, \
93 GPC_CM_SLEEP_ISO_CTRL_OFFSET, GPC_CM_SLEEP_RESET_CTRL_OFFSET, GPC_CM_SLEEP_POWER_CTRL_OFFSET, \
94 GPC_RESERVED_USE_MACRO, GPC_RESERVED_USE_MACRO, GPC_RESERVED_USE_MACRO, GPC_RESERVED_USE_MACRO, \
95 GPC_CM_WAKEUP_POWER_CTRL_OFFSET, GPC_CM_WAKEUP_RESET_CTRL_OFFSET, GPC_CM_WAKEUP_ISO_CTRL_OFFSET, \
96 GPC_CM_WAKEUP_PLL_CTRL_OFFSET, GPC_CM_WAKEUP_LPCG_CTRL_OFFSET, GPC_CM_WAKEUP_SSAR_CTRL_OFFSET, \
97 }
98
99/* GPC set point module step control register offset. */
100#define GPC_SP_STEP_REG_OFFSET \
101 { \
102 GPC_SP_SSAR_SAVE_CTRL_OFFSET, GPC_SP_LPCG_OFF_CTRL_OFFSET, GPC_SP_GROUP_DOWN_CTRL_OFFSET, \
103 GPC_SP_ROOT_DOWN_CTRL_OFFSET, GPC_SP_PLL_OFF_CTRL_OFFSET, GPC_SP_ISO_ON_CTRL_OFFSET, \
104 GPC_SP_RESET_EARLY_CTRL_OFFSET, GPC_SP_POWER_OFF_CTRL_OFFSET, GPC_SP_BIAS_OFF_CTRL_OFFSET, \
105 GPC_SP_BG_PLDO_OFF_CTRL_OFFSET, GPC_SP_LDO_PRE_CTRL_OFFSET, GPC_SP_DCDC_DOWN_CTRL_OFFSET, \
106 GPC_SP_DCDC_UP_CTRL_OFFSET, GPC_SP_LDO_POST_CTRL_OFFSET, GPC_SP_BG_PLDO_ON_CTRL_OFFSET, \
107 GPC_SP_BIAS_ON_CTRL_OFFSET, GPC_SP_POWER_ON_CTRL_OFFSET, GPC_SP_RESET_LATE_CTRL_OFFSET, \
108 GPC_SP_ISO_OFF_CTRL_OFFSET, GPC_SP_PLL_ON_CTRL_OFFSET, GPC_SP_ROOT_UP_CTRL_OFFSET, \
109 GPC_SP_GROUP_UP_CTRL_OFFSET, GPC_SP_LPCG_ON_CTRL_OFFSET, GPC_SP_SSAR_RESTORE_CTRL_OFFSET, \
110 }
111
112/* GPC standby module step register offset. */
113#define GPC_STBY_STEP_REG_OFFSET \
114 { \
115 GPC_STBY_LPCG_IN_CTRL_OFFSET, GPC_STBY_PLL_IN_CTRL_OFFSET, GPC_STBY_BIAS_IN_CTRL_OFFSET, \
116 GPC_STBY_PLDO_IN_CTRL_OFFSET, GPC_STBY_BANDGAP_IN_CTRL_OFFSET, GPC_STBY_LDO_IN_CTRL_OFFSET, \
117 GPC_STBY_DCDC_IN_CTRL_OFFSET, GPC_STBY_PMIC_IN_CTRL_OFFSET, GPC_STBY_PMIC_OUT_CTRL_OFFSET, \
118 GPC_STBY_DCDC_OUT_CTRL_OFFSET, GPC_STBY_LDO_OUT_CTRL_OFFSET, GPC_STBY_BANDGAP_OUT_CTRL_OFFSET, \
119 GPC_STBY_PLDO_OUT_CTRL_OFFSET, GPC_STBY_BIAS_OUT_CTRL_OFFSET, GPC_STBY_PLL_OUT_CTRL_OFFSET, \
120 GPC_STBY_LPCG_OUT_CTRL_OFFSET, \
121 }
122
123/* Make/Get status. */
124/* Make the mask/shift value of GPC status register in a variable. */
125#define GPC_STAT(mask, shift) (uint32_t)(((uint32_t)(shift) << 16UL) + ((uint32_t)(mask) >> (uint32_t)(shift)))
126
127#define GPC_CM_ALL_INTERRUPT_STATUS \
128 (GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_MASK | \
129 GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_MASK | \
130 GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_MASK)
131
133enum
134{
136 GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK,
138 GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK,
139};
140
141/* @brief _gpc_setpoint_map GPC setpoint map. */
142enum
143{
144 kGPC_SetPoint0 = 1UL << 0UL,
145 kGPC_SetPoint1 = 1UL << 1UL,
146 kGPC_SetPoint2 = 1UL << 2UL,
147 kGPC_SetPoint3 = 1UL << 3UL,
148 kGPC_SetPoint4 = 1UL << 4UL,
149 kGPC_SetPoint5 = 1UL << 5UL,
150 kGPC_SetPoint6 = 1UL << 6UL,
151 kGPC_SetPoint7 = 1UL << 7UL,
152 kGPC_SetPoint8 = 1UL << 8UL,
153 kGPC_SetPoint9 = 1UL << 9UL,
154 kGPC_SetPoint10 = 1UL << 10UL,
155 kGPC_SetPoint11 = 1UL << 11UL,
156 kGPC_SetPoint12 = 1UL << 12UL,
157 kGPC_SetPoint13 = 1UL << 13UL,
158 kGPC_SetPoint14 = 1UL << 14UL,
159 kGPC_SetPoint15 = 1UL << 15UL,
160};
161
165enum
166{
167 kGPC_CM_SoftSPNotAllowedStatusFlag = GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_MASK,
168 kGPC_CM_WaitSPNotAllowedStatusFlag = GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_MASK,
169 kGPC_CM_SleepSPNotAllowedStatusFlag = GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_MASK,
170};
171
174{
175 kGPC_CM_SleepBusy = GPC_STAT(
176 GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_MASK,
177 GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_SHIFT),
178 kGPC_CM_WakeupBusy = GPC_STAT(
179 GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_MASK,
180 GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_SHIFT),
182
185{
203
206{
208 0UL,
210 1UL,
216
219{
245
247typedef enum _gpc_cpu_mode
248{
249 kGPC_RunMode = 0x0UL,
254
257{
258 uint32_t stepCount;
262
265{
267 0UL,
270
273{
291/*******************************************************************************
292 * API
293 ******************************************************************************/
294#if defined(__cplusplus)
295extern "C" {
296#endif
297
303/*
304 * @brief Hold core in sleep state.
305 *
306 * This function is used to hold the core in sleep state once it enters WFI, and until finishing wakeup sequence. If a
307 * wakeup IRQ happens during the delay between core sleeps and core clock stops, the core will be woken up but GPC is on
308 * sleep sequence and shut off the clock when core is processing the IRQ, this may leads to an unpredictable status.
309 *
310 * @param base GPC CPU module base address.
311 */
312static inline void GPC_CM_EnableCpuSleepHold(GPC_CPU_MODE_CTRL_Type *base, bool enable)
313{
314 if (enable)
315 {
316 base->CM_MISC |= GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK;
317 }
318 else
319 {
320 base->CM_MISC &= ~GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK;
321 }
322}
323
334static inline void GPC_CM_SetNextCpuMode(GPC_CPU_MODE_CTRL_Type *base, gpc_cpu_mode_t mode)
335{
336 base->CM_MODE_CTRL = (base->CM_MODE_CTRL & ~GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK) |
338}
339
346static inline gpc_cpu_mode_t GPC_CM_GetCurrentCpuMode(GPC_CPU_MODE_CTRL_Type *base)
347{
348 return (gpc_cpu_mode_t)(uint32_t)((base->CM_MODE_STAT & GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK) >>
349 GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT);
350}
351
358static inline gpc_cpu_mode_t GPC_CM_GetPreviousCpuMode(GPC_CPU_MODE_CTRL_Type *base)
359{
360 return (gpc_cpu_mode_t)(uint32_t)((base->CM_MODE_STAT & GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK) >>
361 GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT);
362}
363
373void GPC_CM_EnableIrqWakeup(GPC_CPU_MODE_CTRL_Type *base, uint32_t irqId, bool enable);
374
384static inline void GPC_CM_EnableNonIrqWakeup(GPC_CPU_MODE_CTRL_Type *base, uint32_t mask, bool enable)
385{
386 assert(mask < 2UL);
387
388 if (true == enable)
389 {
390 base->CM_NON_IRQ_WAKEUP_MASK &= ~mask;
391 }
392 else
393 {
394 base->CM_NON_IRQ_WAKEUP_MASK |= mask;
395 }
396}
397
405bool GPC_CM_GetIrqWakeupStatus(GPC_CPU_MODE_CTRL_Type *base, uint32_t irqId);
406
414static inline bool GPC_CM_GetNonIrqWakeupStatus(GPC_CPU_MODE_CTRL_Type *base, uint32_t mask)
415{
416 return (mask == (base->CM_NON_IRQ_WAKEUP_STAT & mask));
417}
418
433
446 uint8_t setPointSleep,
447 uint8_t setPointWakeup,
448 gpc_cm_wakeup_sp_sel_t wakeupSel);
449
459
472static inline void GPC_CM_SetSetPointMapping(GPC_CPU_MODE_CTRL_Type *base, uint32_t setPoint, uint32_t map)
473{
474 assert(setPoint < 16UL);
475
476 base->CM_SP_MAPPING[setPoint] = (map & 0xFFFFUL);
477}
478
493
501
509
517static inline bool GPC_CM_GetStandbyModeStatus(GPC_CPU_MODE_CTRL_Type *base, uint32_t mask)
518{
519 return (mask == (base->CM_STBY_CTRL & mask));
520}
521
528static inline uint32_t GPC_CM_GetInterruptStatusFlags(GPC_CPU_MODE_CTRL_Type *base)
529{
530 return ((base->CM_INT_CTRL) & GPC_CM_ALL_INTERRUPT_STATUS);
531}
532
540
560static inline void GPC_SP_SetSetpointPriority(GPC_SET_POINT_CTRL_Type *base, uint32_t setPoint, uint32_t priority)
561{
562 assert(priority < 16UL);
563 assert(setPoint < 16UL);
564
565 if (setPoint < 8UL)
566 {
567 base->SP_PRIORITY_0_7 |= (priority << (setPoint * 4UL));
568 }
569 else
570 {
571 base->SP_PRIORITY_8_15 |= (priority << ((setPoint - 8UL) * 4UL));
572 }
573}
574
585
592static inline uint8_t GPC_SP_GetCurrentSetPoint(GPC_SET_POINT_CTRL_Type *base)
593{
594 return (uint8_t)((base->SP_SYS_STAT & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_MASK) >>
595 GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_SHIFT);
596}
597
604static inline uint8_t GPC_SP_GetPreviousSetPoint(GPC_SET_POINT_CTRL_Type *base)
605{
606 return (uint8_t)((base->SP_SYS_STAT & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_MASK) >>
607 GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_SHIFT);
608}
609
616static inline uint8_t GPC_SP_GetTargetSetPoint(GPC_SET_POINT_CTRL_Type *base)
617{
618 return (uint8_t)((base->SP_SYS_STAT & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_MASK) >>
619 GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_SHIFT);
620}
640
645#if defined(__cplusplus)
646}
647#endif
651#endif /* _FSL_GPC_H_ */
#define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET(x)
Definition: MIMXRT1166_cm4.h:41394
enum _gpc_sp_tran_step gpc_sp_tran_step_t
GPC set point transition steps.
bool GPC_CM_GetIrqWakeupStatus(GPC_CPU_MODE_CTRL_Type *base, uint32_t irqId)
Get the status of the IRQ wakeup request.
Definition: fsl_gpc.c:67
_gpc_cm_tran_step
CPU mode transition step in sleep/wakeup sequence.
Definition: fsl_gpc.h:185
enum _gpc_cm_wakeup_sp_sel gpc_cm_wakeup_sp_sel_t
CPU wakeup sequence setpoint options.
void GPC_CM_SetCpuModeSetPointMapping(GPC_CPU_MODE_CTRL_Type *base, gpc_cpu_mode_t mode, uint32_t map)
Set the set point mapping value for each cpu mode.
Definition: fsl_gpc.c:182
void GPC_CM_ClearInterruptStatusFlags(GPC_CPU_MODE_CTRL_Type *base, uint32_t mask)
Clears CPU module interrut status flags.
Definition: fsl_gpc.c:267
void GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL_Type *base, gpc_sp_tran_step_t step, const gpc_tran_step_config_t *config)
Config the set point transition step.
Definition: fsl_gpc.c:283
_gpc_sp_tran_step
GPC set point transition steps.
Definition: fsl_gpc.h:219
struct _gpc_tran_step_config gpc_tran_step_config_t
Configuration for GPC transition step.
_gpc_stby_tran_step
GPC standby mode transition steps.
Definition: fsl_gpc.h:273
enum _gpc_cm_standby_mode_status gpc_cm_standby_mode_status_t
CPU standby mode status.
_gpc_cm_wakeup_sp_sel
CPU wakeup sequence setpoint options.
Definition: fsl_gpc.h:265
void GPC_CM_EnableIrqWakeup(GPC_CPU_MODE_CTRL_Type *base, uint32_t irqId, bool enable)
Enable IRQ wakeup request.
Definition: fsl_gpc.c:43
_gpc_cm_standby_mode_status
CPU standby mode status.
Definition: fsl_gpc.h:174
_gpc_cpu_mode
CPU mode.
Definition: fsl_gpc.h:248
enum _gpc_tran_step_counter_mode gpc_tran_step_counter_mode_t
Step counter work mode.
void GPC_CM_ClearStandbyModeRequest(GPC_CPU_MODE_CTRL_Type *base, const gpc_cpu_mode_t mode)
Clear the standby mode request.
Definition: fsl_gpc.c:240
_gpc_tran_step_counter_mode
Step counter work mode.
Definition: fsl_gpc.h:206
void GPC_CM_RequestRunModeSetPointTransition(GPC_CPU_MODE_CTRL_Type *base, uint8_t setPointRun)
Request a set point transition during run mode.
Definition: fsl_gpc.c:156
void GPC_CM_RequestStandbyMode(GPC_CPU_MODE_CTRL_Type *base, const gpc_cpu_mode_t mode)
Request the chip into standby mode.
Definition: fsl_gpc.c:213
void GPC_CM_ConfigCpuModeTransitionStep(GPC_CPU_MODE_CTRL_Type *base, gpc_cm_tran_step_t step, const gpc_tran_step_config_t *config)
Config the cpu mode transition step.
Definition: fsl_gpc.c:90
void GPC_CM_RequestSleepModeSetPointTransition(GPC_CPU_MODE_CTRL_Type *base, uint8_t setPointSleep, uint8_t setPointWakeup, gpc_cm_wakeup_sp_sel_t wakeupSel)
Request a set point transition before the CPU transfers into a sleep mode.
Definition: fsl_gpc.c:128
enum _gpc_cm_tran_step gpc_cm_tran_step_t
CPU mode transition step in sleep/wakeup sequence.
enum _gpc_cpu_mode gpc_cpu_mode_t
CPU mode.
enum _gpc_stby_tran_step gpc_stby_tran_step_t
GPC standby mode transition steps.
void GPC_STBY_ConfigStandbyTransitionStep(GPC_STBY_CTRL_Type *base, gpc_stby_tran_step_t step, const gpc_tran_step_config_t *config)
Config the standby transition step.
Definition: fsl_gpc.c:314
@ kGPC_CM_SleepReset
Definition: fsl_gpc.h:190
@ kGPC_CM_SleepSP
Definition: fsl_gpc.h:192
@ kGPC_CM_WakeupSTBY
Definition: fsl_gpc.h:194
@ kGPC_CM_SleepLpcg
Definition: fsl_gpc.h:187
@ kGPC_CM_WakeupSsar
Definition: fsl_gpc.h:201
@ kGPC_CM_SleepPower
Definition: fsl_gpc.h:191
@ kGPC_CM_WakeupPll
Definition: fsl_gpc.h:199
@ kGPC_CM_SleepIso
Definition: fsl_gpc.h:189
@ kGPC_CM_WakeupIso
Definition: fsl_gpc.h:198
@ kGPC_CM_WakeupPower
Definition: fsl_gpc.h:196
@ kGPC_CM_SleepPll
Definition: fsl_gpc.h:188
@ kGPC_CM_WakeupReset
Definition: fsl_gpc.h:197
@ kGPC_CM_WakeupLpcg
Definition: fsl_gpc.h:200
@ kGPC_CM_SleepSTBY
Definition: fsl_gpc.h:193
@ kGPC_CM_WakeupSP
Definition: fsl_gpc.h:195
@ kGPC_CM_SleepSsar
Definition: fsl_gpc.h:186
@ kGPC_SP_BandgapPllLdoOff
Definition: fsl_gpc.h:229
@ kGPC_SP_LdoPost
Definition: fsl_gpc.h:233
@ kGPC_SP_GroupDown
Definition: fsl_gpc.h:222
@ kGPC_SP_BiasOff
Definition: fsl_gpc.h:228
@ kGPC_SP_LdoPre
Definition: fsl_gpc.h:230
@ kGPC_SP_LpcgOff
Definition: fsl_gpc.h:221
@ kGPC_SP_DcdcDown
Definition: fsl_gpc.h:231
@ kGPC_SP_PllOff
Definition: fsl_gpc.h:224
@ kGPC_SP_LpcgOn
Definition: fsl_gpc.h:242
@ kGPC_SP_ResetEarly
Definition: fsl_gpc.h:226
@ kGPC_SP_PowerOff
Definition: fsl_gpc.h:227
@ kGPC_SP_DcdcUp
Definition: fsl_gpc.h:232
@ kGPC_SP_BandgapPllLdoOn
Definition: fsl_gpc.h:234
@ kGPC_SP_RootDown
Definition: fsl_gpc.h:223
@ kGPC_SP_PllOn
Definition: fsl_gpc.h:239
@ kGPC_SP_GroupUp
Definition: fsl_gpc.h:241
@ kGPC_SP_SsarSave
Definition: fsl_gpc.h:220
@ kGPC_SP_IsoOff
Definition: fsl_gpc.h:238
@ kGPC_SP_RootUp
Definition: fsl_gpc.h:240
@ kGPC_SP_PowerOn
Definition: fsl_gpc.h:236
@ kGPC_SP_SsarRestore
Definition: fsl_gpc.h:243
@ kGPC_SP_IsoOn
Definition: fsl_gpc.h:225
@ kGPC_SP_BiasOn
Definition: fsl_gpc.h:235
@ kGPC_SP_ResetLate
Definition: fsl_gpc.h:237
@ kGPC_STBY_PldoOut
Definition: fsl_gpc.h:286
@ kGPC_STBY_BiasOut
Definition: fsl_gpc.h:287
@ kGPC_STBY_DcdcOut
Definition: fsl_gpc.h:283
@ kGPC_STBY_PldoIn
Definition: fsl_gpc.h:277
@ kGPC_STBY_PmicIn
Definition: fsl_gpc.h:281
@ kGPC_STBY_BiasIn
Definition: fsl_gpc.h:276
@ kGPC_STBY_LdoIn
Definition: fsl_gpc.h:279
@ kGPC_STBY_LdoOut
Definition: fsl_gpc.h:284
@ kGPC_STBY_BandgapOut
Definition: fsl_gpc.h:285
@ kGPC_STBY_PmicOut
Definition: fsl_gpc.h:282
@ kGPC_STBY_PllIn
Definition: fsl_gpc.h:275
@ kGPC_STBY_PllOut
Definition: fsl_gpc.h:288
@ kGPC_STBY_BandgapIn
Definition: fsl_gpc.h:278
@ kGPC_STBY_LpcgIn
Definition: fsl_gpc.h:274
@ kGPC_STBY_DcdcIn
Definition: fsl_gpc.h:280
@ kGPC_STBY_LpcgOut
Definition: fsl_gpc.h:289
@ kGPC_CM_WakeupSetpoint
Definition: fsl_gpc.h:266
@ kGPC_CM_RequestPreviousSetpoint
Definition: fsl_gpc.h:268
@ kGPC_CM_SleepBusy
Definition: fsl_gpc.h:175
@ kGPC_CM_WakeupBusy
Definition: fsl_gpc.h:178
@ kGPC_StopMode
Definition: fsl_gpc.h:251
@ kGPC_RunMode
Definition: fsl_gpc.h:249
@ kGPC_SuspendMode
Definition: fsl_gpc.h:252
@ kGPC_WaitMode
Definition: fsl_gpc.h:250
@ kGPC_StepCounterIgnoreResponseMode
Definition: fsl_gpc.h:211
@ kGPC_StepCounterTimeOutMode
Definition: fsl_gpc.h:213
@ kGPC_StepCounterDisableMode
Definition: fsl_gpc.h:207
@ kGPC_StepCounterDelayMode
Definition: fsl_gpc.h:209
@ kGPC_CM_DebugWakeupRequest
Definition: fsl_gpc.h:137
@ kGPC_CM_EventWakeupRequest
Definition: fsl_gpc.h:135
@ kGPC_SetPoint0
Definition: fsl_gpc.h:144
@ kGPC_SetPoint3
Definition: fsl_gpc.h:147
@ kGPC_SetPoint14
Definition: fsl_gpc.h:158
@ kGPC_SetPoint11
Definition: fsl_gpc.h:155
@ kGPC_SetPoint9
Definition: fsl_gpc.h:153
@ kGPC_SetPoint4
Definition: fsl_gpc.h:148
@ kGPC_SetPoint15
Definition: fsl_gpc.h:159
@ kGPC_SetPoint7
Definition: fsl_gpc.h:151
@ kGPC_SetPoint2
Definition: fsl_gpc.h:146
@ kGPC_SetPoint12
Definition: fsl_gpc.h:156
@ kGPC_SetPoint5
Definition: fsl_gpc.h:149
@ kGPC_SetPoint1
Definition: fsl_gpc.h:145
@ kGPC_SetPoint10
Definition: fsl_gpc.h:154
@ kGPC_SetPoint13
Definition: fsl_gpc.h:157
@ kGPC_SetPoint6
Definition: fsl_gpc.h:150
@ kGPC_SetPoint8
Definition: fsl_gpc.h:152
Definition: MIMXRT1166_cm4.h:41200
Definition: MIMXRT1166_cm4.h:42183
Definition: MIMXRT1166_cm4.h:43163
Configuration for GPC transition step.
Definition: fsl_gpc.h:257
gpc_tran_step_counter_mode_t cntMode
Definition: fsl_gpc.h:259
bool enableStep
Definition: fsl_gpc.h:260
uint32_t stepCount
Definition: fsl_gpc.h:258
Definition: mm.c:60
Definition: deflate.c:114