RTEMS 6.1-rc7
Loading...
Searching...
No Matches

CTRL - Control Register

#define SRAM_CTRL_RAM_RD_EN_MASK   (0x1U)
 
#define SRAM_CTRL_RAM_RD_EN_SHIFT   (0U)
 
#define SRAM_CTRL_RAM_RD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_RD_EN_SHIFT)) & SRAM_CTRL_RAM_RD_EN_MASK)
 
#define SRAM_CTRL_RAM_WR_EN_MASK   (0x2U)
 
#define SRAM_CTRL_RAM_WR_EN_SHIFT   (1U)
 
#define SRAM_CTRL_RAM_WR_EN(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_WR_EN_SHIFT)) & SRAM_CTRL_RAM_WR_EN_MASK)
 
#define SRAM_CTRL_PWR_EN_MASK   (0x3CU)
 
#define SRAM_CTRL_PWR_EN_SHIFT   (2U)
 
#define SRAM_CTRL_PWR_EN(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_PWR_EN_SHIFT)) & SRAM_CTRL_PWR_EN_MASK)
 
#define SRAM_CTRL_TAMPER_BLOCK_EN_MASK   (0x40U)
 
#define SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT   (6U)
 
#define SRAM_CTRL_TAMPER_BLOCK_EN(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT)) & SRAM_CTRL_TAMPER_BLOCK_EN_MASK)
 
#define SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK   (0x80U)
 
#define SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT   (7U)
 
#define SRAM_CTRL_TAMPER_PWR_OFF_EN(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT)) & SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK)
 
#define SRAM_CTRL_LOCK_BIT_MASK   (0xFF0000U)
 
#define SRAM_CTRL_LOCK_BIT_SHIFT   (16U)
 
#define SRAM_CTRL_LOCK_BIT(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_LOCK_BIT_SHIFT)) & SRAM_CTRL_LOCK_BIT_MASK)
 

CTRL - Control Register

#define SRAM_CTRL_RAM_RD_EN_MASK   (0x1U)
 
#define SRAM_CTRL_RAM_RD_EN_SHIFT   (0U)
 
#define SRAM_CTRL_RAM_RD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_RD_EN_SHIFT)) & SRAM_CTRL_RAM_RD_EN_MASK)
 
#define SRAM_CTRL_RAM_WR_EN_MASK   (0x2U)
 
#define SRAM_CTRL_RAM_WR_EN_SHIFT   (1U)
 
#define SRAM_CTRL_RAM_WR_EN(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_WR_EN_SHIFT)) & SRAM_CTRL_RAM_WR_EN_MASK)
 
#define SRAM_CTRL_PWR_EN_MASK   (0x3CU)
 
#define SRAM_CTRL_PWR_EN_SHIFT   (2U)
 
#define SRAM_CTRL_PWR_EN(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_PWR_EN_SHIFT)) & SRAM_CTRL_PWR_EN_MASK)
 
#define SRAM_CTRL_TAMPER_BLOCK_EN_MASK   (0x40U)
 
#define SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT   (6U)
 
#define SRAM_CTRL_TAMPER_BLOCK_EN(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT)) & SRAM_CTRL_TAMPER_BLOCK_EN_MASK)
 
#define SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK   (0x80U)
 
#define SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT   (7U)
 
#define SRAM_CTRL_TAMPER_PWR_OFF_EN(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT)) & SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK)
 
#define SRAM_CTRL_LOCK_BIT_MASK   (0xFF0000U)
 
#define SRAM_CTRL_LOCK_BIT_SHIFT   (16U)
 
#define SRAM_CTRL_LOCK_BIT(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_LOCK_BIT_SHIFT)) & SRAM_CTRL_LOCK_BIT_MASK)
 

Detailed Description

Macro Definition Documentation

◆ SRAM_CTRL_LOCK_BIT [1/2]

#define SRAM_CTRL_LOCK_BIT (   x)    (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_LOCK_BIT_SHIFT)) & SRAM_CTRL_LOCK_BIT_MASK)

LOCK_BIT - Lock bits

◆ SRAM_CTRL_LOCK_BIT [2/2]

#define SRAM_CTRL_LOCK_BIT (   x)    (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_LOCK_BIT_SHIFT)) & SRAM_CTRL_LOCK_BIT_MASK)

LOCK_BIT - Lock bits

◆ SRAM_CTRL_PWR_EN [1/2]

#define SRAM_CTRL_PWR_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_PWR_EN_SHIFT)) & SRAM_CTRL_PWR_EN_MASK)

PWR_EN - Power Enable (with lock)

◆ SRAM_CTRL_PWR_EN [2/2]

#define SRAM_CTRL_PWR_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_PWR_EN_SHIFT)) & SRAM_CTRL_PWR_EN_MASK)

PWR_EN - Power Enable (with lock)

◆ SRAM_CTRL_RAM_RD_EN [1/2]

#define SRAM_CTRL_RAM_RD_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_RD_EN_SHIFT)) & SRAM_CTRL_RAM_RD_EN_MASK)

RAM_RD_EN - RAM Read Enable (with lock) 0b0..Disable read access 0b1..Enable read access

◆ SRAM_CTRL_RAM_RD_EN [2/2]

#define SRAM_CTRL_RAM_RD_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_RD_EN_SHIFT)) & SRAM_CTRL_RAM_RD_EN_MASK)

RAM_RD_EN - RAM Read Enable (with lock) 0b0..Disable read access 0b1..Enable read access

◆ SRAM_CTRL_RAM_WR_EN [1/2]

#define SRAM_CTRL_RAM_WR_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_WR_EN_SHIFT)) & SRAM_CTRL_RAM_WR_EN_MASK)

RAM_WR_EN - RAM Write Enable (with lock) 0b0..Disable write access 0b1..Enable write access

◆ SRAM_CTRL_RAM_WR_EN [2/2]

#define SRAM_CTRL_RAM_WR_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_WR_EN_SHIFT)) & SRAM_CTRL_RAM_WR_EN_MASK)

RAM_WR_EN - RAM Write Enable (with lock) 0b0..Disable write access 0b1..Enable write access

◆ SRAM_CTRL_TAMPER_BLOCK_EN [1/2]

#define SRAM_CTRL_TAMPER_BLOCK_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT)) & SRAM_CTRL_TAMPER_BLOCK_EN_MASK)

TAMPER_BLOCK_EN - Tamper Block Enable (with lock) 0b0..Allow R/W access to secure RAM when tamper is detected 0b1..Block R/W access to secure RAM when tamper is detected

◆ SRAM_CTRL_TAMPER_BLOCK_EN [2/2]

#define SRAM_CTRL_TAMPER_BLOCK_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT)) & SRAM_CTRL_TAMPER_BLOCK_EN_MASK)

TAMPER_BLOCK_EN - Tamper Block Enable (with lock) 0b0..Allow R/W access to secure RAM when tamper is detected 0b1..Block R/W access to secure RAM when tamper is detected

◆ SRAM_CTRL_TAMPER_PWR_OFF_EN [1/2]

#define SRAM_CTRL_TAMPER_PWR_OFF_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT)) & SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK)

TAMPER_PWR_OFF_EN - Turn off power on tamper event (with lock) 0b0..Disable the turn off function when tamper is detected 0b1..Turn off power for all secure RAM banks when tamper is detected

◆ SRAM_CTRL_TAMPER_PWR_OFF_EN [2/2]

#define SRAM_CTRL_TAMPER_PWR_OFF_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT)) & SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK)

TAMPER_PWR_OFF_EN - Turn off power on tamper event (with lock) 0b0..Disable the turn off function when tamper is detected 0b1..Turn off power for all secure RAM banks when tamper is detected