RTEMS 6.1-rc7
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Data Fields

This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only. More...

#include <stm32h723xx.h>

Data Fields

__IO uint32_t IMR1
 
__IO uint32_t EMR1
 
__IO uint32_t PR1
 
uint32_t RESERVED1
 
__IO uint32_t IMR2
 
__IO uint32_t EMR2
 
__IO uint32_t PR2
 
uint32_t RESERVED2
 
__IO uint32_t IMR3
 
__IO uint32_t EMR3
 
__IO uint32_t PR3
 

Detailed Description

This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only.

Field Documentation

◆ EMR1

__IO uint32_t EXTI_Core_TypeDef::EMR1

EXTI Event mask register, Address offset: 0x04

◆ EMR2

__IO uint32_t EXTI_Core_TypeDef::EMR2

EXTI Event mask register, Address offset: 0x14

◆ EMR3

__IO uint32_t EXTI_Core_TypeDef::EMR3

EXTI Event mask register, Address offset: 0x24

◆ IMR1

__IO uint32_t EXTI_Core_TypeDef::IMR1

EXTI Interrupt mask register, Address offset: 0x00

◆ IMR2

__IO uint32_t EXTI_Core_TypeDef::IMR2

EXTI Interrupt mask register, Address offset: 0x10

◆ IMR3

__IO uint32_t EXTI_Core_TypeDef::IMR3

EXTI Interrupt mask register, Address offset: 0x20

◆ PR1

__IO uint32_t EXTI_Core_TypeDef::PR1

EXTI Pending register, Address offset: 0x08

◆ PR2

__IO uint32_t EXTI_Core_TypeDef::PR2

EXTI Pending register, Address offset: 0x18

◆ PR3

__IO uint32_t EXTI_Core_TypeDef::PR3

EXTI Pending register, Address offset: 0x28

◆ RESERVED1

uint32_t EXTI_Core_TypeDef::RESERVED1

Reserved, 0x0C

◆ RESERVED2

uint32_t EXTI_Core_TypeDef::RESERVED2

Reserved, 0x1C


The documentation for this struct was generated from the following files: