RTEMS 6.1-rc7
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cpu.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2024 Matheus Pecoraro
13 * Copyright (c) 2018 Amaan Cheval <amaan.cheval@gmail.com>
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 */
36
37#ifndef _RTEMS_SCORE_CPU_H
38#define _RTEMS_SCORE_CPU_H
39
40#ifdef __cplusplus
41extern "C" {
42#endif
43
45#include <rtems/score/cpu_asm.h>
46#include <rtems/score/x86_64.h>
47
48#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
49#define CPU_ISR_PASSES_FRAME_POINTER FALSE
50#define CPU_HARDWARE_FP TRUE
51#define CPU_SOFTWARE_FP FALSE
52#define CPU_ALL_TASKS_ARE_FP TRUE
53#define CPU_IDLE_TASK_IS_FP FALSE
54#define CPU_USE_DEFERRED_FP_SWITCH FALSE
55#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
56#define CPU_STACK_GROWS_UP FALSE
57
58#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED(64)
59#define CPU_CACHE_LINE_BYTES 64
60#define CPU_MODES_INTERRUPT_MASK 0x00000001
61#define CPU_MAXIMUM_PROCESSORS 32
62
63#define CPU_EFLAGS_INTERRUPTS_ON 0x00003202
64#define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002
65
66#define CPU_CONTEXT_CONTROL_EFLAGS 0
67
68#define CPU_CONTEXT_CONTROL_RBX CPU_CONTEXT_CONTROL_EFLAGS + 8
69#define CPU_CONTEXT_CONTROL_RSP CPU_CONTEXT_CONTROL_RBX + 8
70#define CPU_CONTEXT_CONTROL_RBP CPU_CONTEXT_CONTROL_RSP + 8
71#define CPU_CONTEXT_CONTROL_R12 CPU_CONTEXT_CONTROL_RBP + 8
72#define CPU_CONTEXT_CONTROL_R13 CPU_CONTEXT_CONTROL_R12 + 8
73#define CPU_CONTEXT_CONTROL_R14 CPU_CONTEXT_CONTROL_R13 + 8
74#define CPU_CONTEXT_CONTROL_R15 CPU_CONTEXT_CONTROL_R14 + 8
75
76#define CPU_CONTEXT_CONTROL_FS CPU_CONTEXT_CONTROL_R15 + 8
77
78#define CPU_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE CPU_CONTEXT_CONTROL_FS + 8
79
80#define CPU_CONTEXT_CONTROL_IS_EXECUTING CPU_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE + 4
81
82#ifndef ASM
83
84typedef struct {
85 uint64_t rflags;
86
91 uint64_t rbx;
92 void *rsp;
93 void *rbp;
94 uint64_t r12;
95 uint64_t r13;
96 uint64_t r14;
97 uint64_t r15;
98
99 /* Thread pointer */
100 uint64_t fs;
101
102 uint32_t isr_dispatch_disable;
103
104#ifdef RTEMS_SMP
105 volatile uint16_t is_executing;
106#endif
108
109typedef struct {
114 uint32_t mxcsr;
115 uint16_t fpucw;
117
118#define _CPU_Context_Get_SP( _context ) \
119 (_context)->rsp
120
121#endif /* !ASM */
122
123#define CPU_INTERRUPT_FRAME_SSE_STATE 0
124
125#define CPU_INTERRUPT_FRAME_RAX CPU_INTERRUPT_FRAME_SSE_STATE + 512
126#define CPU_INTERRUPT_FRAME_RCX CPU_INTERRUPT_FRAME_RAX + 8
127#define CPU_INTERRUPT_FRAME_RDX CPU_INTERRUPT_FRAME_RCX + 8
128#define CPU_INTERRUPT_FRAME_RSI CPU_INTERRUPT_FRAME_RDX + 8
129#define CPU_INTERRUPT_FRAME_R8 CPU_INTERRUPT_FRAME_RSI + 8
130#define CPU_INTERRUPT_FRAME_R9 CPU_INTERRUPT_FRAME_R8 + 8
131#define CPU_INTERRUPT_FRAME_R10 CPU_INTERRUPT_FRAME_R9 + 8
132#define CPU_INTERRUPT_FRAME_R11 CPU_INTERRUPT_FRAME_R10 + 8
133#define CPU_INTERRUPT_FRAME_RSP CPU_INTERRUPT_FRAME_R11 + 8
134
135#ifndef ASM
136
137/*
138 * Caller-saved registers for interrupt frames
139 */
140typedef struct {
141 /* Registers saved by CPU */
142 uint64_t error_code; /* only in some exceptions */
143 uint64_t rip;
144 uint64_t cs;
145 uint64_t rflags;
146 uint64_t rsp;
147 uint64_t ss;
148
149 /* Saved in rtems_irq_prologue_* */
150 uint64_t rdi;
151 uint64_t rbp;
152 uint64_t rbx;
153
154 /* SSE state saved by the FXSAVE instruction */
155 uint8_t sse_state[512];
156
157 uint64_t rax;
158 uint64_t rcx;
159 uint64_t rdx;
160 uint64_t rsi;
161 uint64_t r8;
162 uint64_t r9;
163 uint64_t r10;
164 uint64_t r11;
165
166 /*
167 * This holds the rsp just before _ISR_Handler is called; it's needed because
168 * in the handler, we align the stack to make further calls, and we're not
169 * sure how alignment may move the stack-pointer around, leaving no way to get
170 * back to the stack, and therefore the interrupt frame.
171 */
172 uint64_t saved_rsp;
173
179 uint8_t padding[8];
181
182extern Context_Control_fp _CPU_Null_fp_context;
183
184#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
185
186#endif /* !ASM */
187
188#define CPU_INTERRUPT_FRAME_X86_64_SIZE 48
189#define CPU_INTERRUPT_FRAME_PROLOGUE_SIZE 24
190#define CPU_INTERRUPT_FRAME_CALLER_SAVED_SIZE (512 + 72)
191#define CPU_INTERRUPT_FRAME_PADDING_SIZE 8
192
193#define CPU_INTERRUPT_FRAME_SIZE \
194 (CPU_INTERRUPT_FRAME_X86_64_SIZE + \
195 CPU_INTERRUPT_FRAME_PROLOGUE_SIZE + \
196 CPU_INTERRUPT_FRAME_CALLER_SAVED_SIZE + \
197 CPU_INTERRUPT_FRAME_PADDING_SIZE)
198
199/*
200 * When SMP is enabled, percpuasm.c has a similar assert, but since we use the
201 * interrupt frame regardless of SMP, we'll confirm it here.
202 */
203#ifndef ASM
205 sizeof(CPU_Interrupt_frame) == CPU_INTERRUPT_FRAME_SIZE,
206 CPU_INTERRUPT_FRAME_SIZE
207 );
208#endif
209
210#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
211#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
212#define CPU_STACK_MINIMUM_SIZE (1024*8)
213#define CPU_SIZEOF_POINTER 8
214#define CPU_ALIGNMENT 16
215#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
216#define CPU_STACK_ALIGNMENT 16
217#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
218
219/*
220 * ISR handler macros
221 */
222
223/* ISR_Level is an uint32_t meaning we can't use RFLAGS to represent it */
224#define CPU_ISR_LEVEL_ENABLED 0
225
226#ifndef ASM
227
228#define _CPU_ISR_Enable(_level) \
229{ \
230 if (_level == 0) { \
231 amd64_enable_interrupts(); \
232 } \
233}
234
235#define _CPU_ISR_Disable(_level) \
236{ \
237 _level = _CPU_ISR_Get_level(); \
238 amd64_disable_interrupts(); \
239}
240
241#define _CPU_ISR_Flash(_level) \
242{ \
243 if (_level == 0) { \
244 amd64_enable_interrupts(); \
245 } \
246 amd64_disable_interrupts(); \
247}
248
249static inline bool _CPU_ISR_Is_enabled(uint32_t level)
250{
251 return level == 0;
252}
253
254static inline void _CPU_ISR_Set_level(uint32_t new_level)
255{
256 if ( new_level ) {
257 amd64_disable_interrupts();
258 }
259 else {
260 amd64_enable_interrupts();
261 }
262}
263
264static inline uint32_t _CPU_ISR_Get_level(void)
265{
266 uint64_t rflags;
267
268 __asm__ volatile ( "pushf; \
269 popq %0"
270 : "=rm" (rflags)
271 );
272
273 uint32_t level = (rflags & EFLAGS_INTR_ENABLE) ? 0 : 1;
274 return level;
275}
276
277/* end of ISR handler macros */
278
279/* Context handler macros */
280#define _CPU_Context_Destroy( _the_thread, _the_context ) \
281 { \
282 }
283
284void _CPU_Context_Initialize(
285 Context_Control *the_context,
286 void *stack_area_begin,
287 size_t stack_area_size,
288 uint32_t new_level,
289 void (*entry_point)( void ),
290 bool is_fp,
291 void *tls_area
292);
293
294#define _CPU_Context_Restart_self( _the_context ) \
295 _CPU_Context_restore( (_the_context) );
296
297#define _CPU_Context_Initialize_fp( _destination ) \
298 { \
299 *(*(_destination)) = _CPU_Null_fp_context; \
300 }
301
302/* end of Context handler macros */
303
304#define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE
305
306/* Bitfield handler macros */
307
308#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
309
310#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
311#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
312 { \
313 (_output) = 0; /* do something to prevent warnings */ \
314 }
315#endif
316
317/* end of Bitfield handler macros */
318
319#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
320#define _CPU_Priority_Mask( _bit_number ) \
321 ( 1 << (_bit_number) )
322#endif
323
324#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
325#define _CPU_Priority_bits_index( _priority ) \
326 (_priority)
327#endif
328
329/* end of Priority handler macros */
330
331/* functions */
332
333void _CPU_Initialize(void);
334
335RTEMS_NO_RETURN void *_CPU_Thread_Idle_body( uintptr_t ignored );
336
338 Context_Control *run,
339 Context_Control *heir
340);
341
342RTEMS_NO_RETURN void _CPU_Context_switch_no_return(
343 Context_Control *executing,
344 Context_Control *heir
345);
346
347RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context );
348
349typedef struct {
350 uint32_t processor_state_register;
351 uint32_t integer_registers [1];
352 double float_registers [1];
354
356 Context_Control_fp **fp_context_ptr
357);
358
360 Context_Control_fp **fp_context_ptr
361);
362
364
365static inline uint32_t CPU_swap_u32(
366 uint32_t value
367)
368{
369 uint32_t byte1, byte2, byte3, byte4, swapped;
370
371 byte4 = (value >> 24) & 0xff;
372 byte3 = (value >> 16) & 0xff;
373 byte2 = (value >> 8) & 0xff;
374 byte1 = value & 0xff;
375
376 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
377 return swapped;
378}
379
380#define _CPU_Context_save_fp(fp_context_pp) \
381 do { \
382 __asm__ __volatile__( \
383 "fstcw %0" \
384 :"=m"((*(fp_context_pp))->fpucw) \
385 ); \
386 __asm__ __volatile__( \
387 "stmxcsr %0" \
388 :"=m"((*(fp_context_pp))->mxcsr) \
389 ); \
390 } while (0)
391
392#define _CPU_Context_restore_fp(fp_context_pp) \
393 do { \
394 __asm__ __volatile__( \
395 "fldcw %0" \
396 :"=m"((*(fp_context_pp))->fpucw) \
397 ); \
398 __asm__ __volatile__( \
399 "ldmxcsr %0" \
400 :"=m"((*(fp_context_pp))->mxcsr) \
401 ); \
402 } while (0)
403
404#define CPU_swap_u16( value ) \
405 (((value&0xff) << 8) | ((value >> 8)&0xff))
406
407typedef uint32_t CPU_Counter_ticks;
408
409uint32_t _CPU_Counter_frequency( void );
410
411CPU_Counter_ticks _CPU_Counter_read( void );
412
413#ifdef RTEMS_SMP
414
415 uint32_t _CPU_SMP_Initialize( void );
416
417 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
418
419 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
420
421 void _CPU_SMP_Prepare_start_multitasking( void );
422
423 uint32_t _CPU_SMP_Get_current_processor( void );
424
425 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
426
427 static inline bool _CPU_Context_Get_is_executing(
429 )
430 {
431 return context->is_executing;
432 }
433
434 static inline void _CPU_Context_Set_is_executing(
436 bool is_executing
437 )
438 {
439 context->is_executing = is_executing;
440 }
441
442#endif /* RTEMS_SMP */
443
444typedef uintptr_t CPU_Uint32ptr;
445
446#ifdef __cplusplus
447}
448#endif
449
450#endif /* ASM */
451
452#endif /* _RTEMS_SCORE_CPU_H */
This header file provides basic definitions used by the API and the implementation.
#define RTEMS_STATIC_ASSERT(_cond, _msg)
It is defined if a static analysis run is performed.
Definition: basedefs.h:841
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
#define _CPU_ISR_Set_level(_new_level)
Definition: cpu.h:378
rtems_termios_device_context * context
Definition: console-config.c:62
#define _CPU_Context_restore_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:901
#define _CPU_Context_save_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:895
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
SPARC basic context.
Definition: cpu.h:213
uint32_t mxcsr
Definition: cpu.h:114
Thread register context.
Definition: cpu.h:173
uint64_t rbx
Definition: cpu.h:91