RTEMS 6.1-rc7
Loading...
Searching...
No Matches
tm27.h
Go to the documentation of this file.
1/* SPDX-License-Identifier: BSD-2-Clause */
2
12/*
13 * Copyright (C) 2022 embedded brains GmbH & Co. KG
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _RTEMS_TMTEST27
38#error "This is an RTEMS internal file you must not include directly."
39#endif
40
41#ifndef __tm27_h
42#define __tm27_h
43
44#include <bsp/irq-generic.h>
45#include <rtems/score/assert.h>
47#include <rtems/score/percpu.h>
48
49#define MUST_WAIT_FOR_INTERRUPT 1
50
51static bool riscv_tm27_can_use_mtime;
52
53static rtems_interrupt_entry riscv_tm27_interrupt_entry;
54
55static inline void Install_tm27_vector( rtems_interrupt_handler handler )
56{
58 bool enabled;
59
60 irq = RISCV_INTERRUPT_VECTOR_TIMER;
61 enabled = false;
62 rtems_interrupt_vector_is_enabled( irq, &enabled );
63
64 if ( enabled ) {
65 irq = RISCV_INTERRUPT_VECTOR_SOFTWARE;
66 } else {
67 riscv_tm27_can_use_mtime = true;
68 }
69
70 rtems_interrupt_entry_initialize(
71 &riscv_tm27_interrupt_entry,
72 handler,
73 NULL,
74 "tm27"
75 );
76
78 irq,
80 &riscv_tm27_interrupt_entry
81 );
82}
83
84static inline void Cause_tm27_intr( void )
85{
86 if ( riscv_tm27_can_use_mtime ) {
88 Per_CPU_Control *cpu_self;
89
91 cpu_self = _Per_CPU_Get();
92 cpu_self->cpu_per_cpu.clint_mtimecmp->val_64 = 0;
94 } else {
95 (void) rtems_interrupt_raise( RISCV_INTERRUPT_VECTOR_SOFTWARE );
96 }
97}
98
99static inline void Clear_tm27_intr( void )
100{
101 if ( riscv_tm27_can_use_mtime ) {
103 Per_CPU_Control *cpu_self;
104
106 cpu_self = _Per_CPU_Get();
107 cpu_self->cpu_per_cpu.clint_mtimecmp->val_64 = UINT64_MAX;
109 } else {
110 (void) rtems_interrupt_clear( RISCV_INTERRUPT_VECTOR_SOFTWARE );
111 }
112}
113
114static inline void Lower_tm27_intr( void )
115{
117
118 /*
119 * This is an ugly hack just to for tm27. The support for nested interrupts
120 * is currently quite bad on RISC-V.
121 */
122 irq = RISCV_INTERRUPT_VECTOR_SOFTWARE;
123
124 if ( bsp_interrupt_dispatch_table[ irq ] == NULL ) {
125 _Assert( riscv_tm27_can_use_mtime );
126 bsp_interrupt_dispatch_table[ irq ] = &riscv_tm27_interrupt_entry;
127 (void) rtems_interrupt_vector_enable( irq );
128 }
129
130 _ISR_Set_level( 0 );
131 (void) rtems_interrupt_raise( irq );
132}
133
134#endif
This header file provides the interfaces of the Assert Handler.
rtems_status_code rtems_interrupt_entry_install(rtems_vector_number vector, rtems_option options, rtems_interrupt_entry *entry)
Installs the interrupt entry at the interrupt vector.
Definition: irq-generic.c:264
ISR_Vector_number rtems_vector_number
This integer type represents interrupt vector numbers.
Definition: intr.h:102
#define RTEMS_INTERRUPT_SHARED
This interrupt handler install option allows that the interrupt handler may share the interrupt vecto...
Definition: intr.h:960
rtems_status_code rtems_interrupt_vector_is_enabled(rtems_vector_number vector, bool *enabled)
Checks if the interrupt vector is enabled.
Definition: irq-enable-disable.c:69
#define rtems_interrupt_local_disable(_isr_cookie)
Disables the maskable interrupts on the current processor.
Definition: intr.h:427
ISR_Level rtems_interrupt_level
This integer type represents interrupt levels.
Definition: intr.h:111
rtems_status_code rtems_interrupt_raise(rtems_vector_number vector)
Raises the interrupt vector.
Definition: irq-raise-clear.c:59
void(* rtems_interrupt_handler)(void *)
Interrupt handler routines shall have this type.
Definition: intr.h:1030
rtems_status_code rtems_interrupt_vector_enable(rtems_vector_number vector)
Enables the interrupt vector.
Definition: irq-enable-disable.c:85
#define rtems_interrupt_local_enable(_isr_cookie)
Restores the previous interrupt level on the current processor.
Definition: intr.h:468
rtems_status_code rtems_interrupt_clear(rtems_vector_number vector)
Clears the interrupt vector.
Definition: irq-raise-clear.c:92
#define _Assert(_e)
Assertion similar to assert() controlled via RTEMS_DEBUG instead of NDEBUG and static analysis runs.
Definition: assert.h:96
#define _ISR_Set_level(_new_level)
Set current interrupt level.
Definition: isrlevel.h:159
This header file provides interfaces of the Interrupt Manager implementation.
rtems_interrupt_entry * bsp_interrupt_dispatch_table[]
Each member of this table references the first installed entry at the corresponding interrupt vector ...
Definition: irq-generic.c:47
RISCV utility.
This header file provides the interfaces of the Per-CPU Information.
Per CPU Core Structure.
Definition: percpu.h:384
This structure represents an interrupt entry.
Definition: intr.h:1070