20#ifndef STM32H7xx_HAL_PWR_EX_H
21#define STM32H7xx_HAL_PWR_EX_H
80#if defined (PWR_CSR1_MMCVDO)
86 PWR_MMC_VOLTAGE_BELOW_1V2,
87 PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2
88} PWREx_MMC_VoltageLevel;
106#define PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6
107#if defined (PWR_WKUPEPR_WKUPEN5)
108#define PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5
110#define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4
111#if defined (PWR_WKUPEPR_WKUPEN3)
112#define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3
114#define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2
115#define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1
118#define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6
119#if defined (PWR_WKUPEPR_WKUPEN5)
120#define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5
122#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4
123#if defined (PWR_WKUPEPR_WKUPEN3)
124#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3
126#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2
127#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1
130#define PWR_WAKEUP_PIN6_LOW (PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6)
131#if defined (PWR_WKUPEPR_WKUPP5)
132#define PWR_WAKEUP_PIN5_LOW (PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5)
134#define PWR_WAKEUP_PIN4_LOW (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4)
135#if defined (PWR_WKUPEPR_WKUPP3)
136#define PWR_WAKEUP_PIN3_LOW (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3)
138#define PWR_WAKEUP_PIN2_LOW (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2)
139#define PWR_WAKEUP_PIN1_LOW (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1)
148#define PWR_PIN_POLARITY_HIGH (0x00000000U)
149#define PWR_PIN_POLARITY_LOW (0x00000001U)
158#define PWR_PIN_NO_PULL (0x00000000U)
159#define PWR_PIN_PULL_UP (0x00000001U)
160#define PWR_PIN_PULL_DOWN (0x00000002U)
169#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1
170#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2
171#if defined (PWR_WKUPFR_WKUPF3)
172#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3
174#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4
175#if defined (PWR_WKUPFR_WKUPF5)
176#define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5
178#define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6
179#if defined (PWR_WKUPFR_WKUPF3)
180#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\
181 PWR_WKUPFR_WKUPF3 | PWR_WKUPFR_WKUPF4 |\
182 PWR_WKUPFR_WKUPF5 | PWR_WKUPFR_WKUPF6)
184#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\
185 PWR_WKUPFR_WKUPF4 | PWR_WKUPFR_WKUPF6)
191#if defined (DUAL_CORE)
196#define PWR_CORE_CPU1 (0x00000000U)
197#define PWR_CORE_CPU2 (0x00000001U)
207#define PWR_D1_DOMAIN (0x00000000U)
208#if defined (PWR_CPUCR_PDDS_D2)
209#define PWR_D2_DOMAIN (0x00000001U)
211#define PWR_D3_DOMAIN (0x00000002U)
220#if defined (DUAL_CORE)
221#define PWR_D1_DOMAIN_FLAGS (0x00000000U)
222#define PWR_D2_DOMAIN_FLAGS (0x00000001U)
223#define PWR_ALL_DOMAIN_FLAGS (0x00000002U)
225#define PWR_CPU_FLAGS (0x00000000U)
235#define PWR_D3_DOMAIN_STOP (0x00000000U)
236#define PWR_D3_DOMAIN_RUN (0x00000800U)
246#define PWR_LDO_SUPPLY PWR_CR3_LDOEN
248#define PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN
249#define PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)
250#define PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)
251#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)
252#define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)
253#define PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS)
254#define PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS)
256#define PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS
259#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \
260 PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
262#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
273#define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0
275#define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1
277#define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2
279#define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3
289#define PWR_AVD_MODE_NORMAL (0x00000000U)
290#define PWR_AVD_MODE_IT_RISING (0x00010001U)
291#define PWR_AVD_MODE_IT_FALLING (0x00010002U)
292#define PWR_AVD_MODE_IT_RISING_FALLING (0x00010003U)
293#define PWR_AVD_MODE_EVENT_RISING (0x00020001U)
294#define PWR_AVD_MODE_EVENT_FALLING (0x00020002U)
295#define PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U)
304#define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0)
305#define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1)
306#define PWR_REGULATOR_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)
315#define PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000U)
316#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS
325#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U)
326#define PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CR2_VBATL
327#define PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CR2_VBATH
336#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U)
337#define PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CR2_TEMPL
338#define PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CR2_TEMPH
346#define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16
352#if defined (PWR_CR1_SRDRAMSO)
357#define PWR_SRD_AHB_MEMORY_BLOCK PWR_CR1_SRDRAMSO
358#define PWR_USB_FDCAN_MEMORY_BLOCK PWR_CR1_HSITFSO
359#define PWR_GFXMMU_JPEG_MEMORY_BLOCK PWR_CR1_GFXSO
360#define PWR_TCM_ECM_MEMORY_BLOCK PWR_CR1_ITCMSO
361#define PWR_RAM1_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM1SO
362#define PWR_RAM2_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM2SO
363#define PWR_RAM1_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM1SO
364#define PWR_RAM2_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM2SO
365#define PWR_RAM3_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM3SO
366#define PWR_MEMORY_BLOCK_KEEP_ON 0U
367#define PWR_MEMORY_BLOCK_SHUT_OFF 1U
387#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
389#if defined (DUAL_CORE)
394#define __HAL_PWR_AVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
401#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
403#if defined (DUAL_CORE)
408#define __HAL_PWR_AVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
415#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
417#if defined (DUAL_CORE)
422#define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
429#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
431#if defined (DUAL_CORE)
436#define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
443#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
449#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
455#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
461#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
467#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
469 __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \
470 __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \
477#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
479 __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \
480 __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \
487#define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
489#if defined (DUAL_CORE)
494#define __HAL_PWR_AVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
501#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD)
503#if defined (DUAL_CORE)
508#define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD)
515#define __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD)
530uint32_t HAL_PWREx_GetSupplyConfig (
void);
532uint32_t HAL_PWREx_GetVoltageRange (
void);
533HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling);
534uint32_t HAL_PWREx_GetStopModeVoltageRange (
void);
543#if defined (PWR_CPUCR_RETDS_CD)
544void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry);
546void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain);
547void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain);
548void HAL_PWREx_ConfigD3Domain (uint32_t D3State);
550void HAL_PWREx_ClearPendingEvent (
void);
551#if defined (DUAL_CORE)
553void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags);
556void HAL_PWREx_ReleaseCore (uint32_t CPU);
559void HAL_PWREx_EnableFlashPowerDown (
void);
560void HAL_PWREx_DisableFlashPowerDown (
void);
561#if defined (PWR_CR1_SRDRAMSO)
563void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock);
564void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock);
568void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin);
569uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag);
572void HAL_PWREx_WAKEUP_PIN_IRQHandler (
void);
573void HAL_PWREx_WKUP1_Callback (
void);
574void HAL_PWREx_WKUP2_Callback (
void);
575#if defined (PWR_WKUPEPR_WKUPEN3)
576void HAL_PWREx_WKUP3_Callback (
void);
578void HAL_PWREx_WKUP4_Callback (
void);
579#if defined (PWR_WKUPEPR_WKUPEN5)
580void HAL_PWREx_WKUP5_Callback (
void);
582void HAL_PWREx_WKUP6_Callback (
void);
596void HAL_PWREx_EnableUSBVoltageDetector (
void);
597void HAL_PWREx_DisableUSBVoltageDetector (
void);
599void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue);
600void HAL_PWREx_DisableBatteryCharging (
void);
601#if defined (PWR_CR1_BOOSTE)
603void HAL_PWREx_EnableAnalogBooster (
void);
604void HAL_PWREx_DisableAnalogBooster (
void);
614void HAL_PWREx_EnableMonitoring (
void);
615void HAL_PWREx_DisableMonitoring (
void);
616uint32_t HAL_PWREx_GetTemperatureLevel (
void);
617uint32_t HAL_PWREx_GetVBATLevel (
void);
618#if defined (PWR_CSR1_MMCVDO)
619PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (
void);
623void HAL_PWREx_EnableAVD (
void);
624void HAL_PWREx_DisableAVD (
void);
626void HAL_PWREx_PVD_AVD_IRQHandler (
void);
627void HAL_PWREx_AVDCallback (
void);
650#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\
651 ((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY) ||\
652 ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO) ||\
653 ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO) ||\
654 ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||\
655 ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||\
656 ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT) ||\
657 ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT) ||\
658 ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
661#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\
662 ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
666#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3) ||\
667 ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4) ||\
668 ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5))
671#if defined (PWR_CPUCR_PDDS_D2)
672#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\
673 ((DOMAIN) == PWR_D2_DOMAIN) ||\
674 ((DOMAIN) == PWR_D3_DOMAIN))
676#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\
677 ((DOMAIN) == PWR_D3_DOMAIN))
681#define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) ||\
682 ((STATE) == PWR_D3_DOMAIN_RUN))
685#if defined (PWR_WKUPEPR_WKUPEN3)
686#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\
687 ((PIN) == PWR_WAKEUP_PIN2) ||\
688 ((PIN) == PWR_WAKEUP_PIN3) ||\
689 ((PIN) == PWR_WAKEUP_PIN4) ||\
690 ((PIN) == PWR_WAKEUP_PIN5) ||\
691 ((PIN) == PWR_WAKEUP_PIN6) ||\
692 ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\
693 ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\
694 ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\
695 ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\
696 ((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\
697 ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\
698 ((PIN) == PWR_WAKEUP_PIN1_LOW) ||\
699 ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\
700 ((PIN) == PWR_WAKEUP_PIN3_LOW) ||\
701 ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\
702 ((PIN) == PWR_WAKEUP_PIN5_LOW) ||\
703 ((PIN) == PWR_WAKEUP_PIN6_LOW))
705#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\
706 ((PIN) == PWR_WAKEUP_PIN2) ||\
707 ((PIN) == PWR_WAKEUP_PIN4) ||\
708 ((PIN) == PWR_WAKEUP_PIN6) ||\
709 ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\
710 ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\
711 ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\
712 ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\
713 ((PIN) == PWR_WAKEUP_PIN1_LOW) ||\
714 ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\
715 ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\
716 ((PIN) == PWR_WAKEUP_PIN6_LOW))
720#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\
721 ((POLARITY) == PWR_PIN_POLARITY_LOW))
724#define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) ||\
725 ((PULL) == PWR_PIN_PULL_UP) ||\
726 ((PULL) == PWR_PIN_PULL_DOWN))
729#if defined (PWR_WKUPEPR_WKUPEN3)
730#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\
731 ((FLAG) == PWR_WAKEUP_FLAG2) ||\
732 ((FLAG) == PWR_WAKEUP_FLAG3) ||\
733 ((FLAG) == PWR_WAKEUP_FLAG4) ||\
734 ((FLAG) == PWR_WAKEUP_FLAG5) ||\
735 ((FLAG) == PWR_WAKEUP_FLAG6) ||\
736 ((FLAG) == PWR_WAKEUP_FLAG_ALL))
738#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\
739 ((FLAG) == PWR_WAKEUP_FLAG2) ||\
740 ((FLAG) == PWR_WAKEUP_FLAG4) ||\
741 ((FLAG) == PWR_WAKEUP_FLAG6) ||\
742 ((FLAG) == PWR_WAKEUP_FLAG_ALL))
746#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) ||\
747 ((LEVEL) == PWR_AVDLEVEL_1) ||\
748 ((LEVEL) == PWR_AVDLEVEL_2) ||\
749 ((LEVEL) == PWR_AVDLEVEL_3))
752#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING) ||\
753 ((MODE) == PWR_AVD_MODE_IT_FALLING) ||\
754 ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) ||\
755 ((MODE) == PWR_AVD_MODE_EVENT_RISING) ||\
756 ((MODE) == PWR_AVD_MODE_EVENT_FALLING) ||\
757 ((MODE) == PWR_AVD_MODE_NORMAL) ||\
758 ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING))
761#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
762 ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
764#define IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID)
766#if defined (DUAL_CORE)
768#define IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2))
771#define IS_PWR_D2_CPU(CPU) ((CPU) == CM4_CPUID)
774#define IS_PWR_DOMAIN_FLAG(FLAG) (((FLAG) == PWR_D1_DOMAIN_FLAGS) || \
775 ((FLAG) == PWR_D2_DOMAIN_FLAGS) || \
776 ((FLAG) == PWR_ALL_DOMAIN_FLAGS))
779#if defined (PWR_CR1_SRDRAMSO)
781#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_SRD_AHB_MEMORY_BLOCK) || \
782 ((BLOCK) == PWR_USB_FDCAN_MEMORY_BLOCK) || \
783 ((BLOCK) == PWR_GFXMMU_JPEG_MEMORY_BLOCK) || \
784 ((BLOCK) == PWR_TCM_ECM_MEMORY_BLOCK) || \
785 ((BLOCK) == PWR_RAM1_AHB_MEMORY_BLOCK) || \
786 ((BLOCK) == PWR_RAM2_AHB_MEMORY_BLOCK) || \
787 ((BLOCK) == PWR_RAM1_AXI_MEMORY_BLOCK) || \
788 ((BLOCK) == PWR_RAM2_AXI_MEMORY_BLOCK) || \
789 ((BLOCK) == PWR_RAM3_AXI_MEMORY_BLOCK))
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
PWREx AVD configuration structure definition.
Definition: stm32h7xx_hal_pwr_ex.h:47
uint32_t Mode
Definition: stm32h7xx_hal_pwr_ex.h:53
uint32_t AVDLevel
Definition: stm32h7xx_hal_pwr_ex.h:48
PWREx Wakeup pin configuration structure definition.
Definition: stm32h7xx_hal_pwr_ex.h:63
uint32_t WakeUpPin
Definition: stm32h7xx_hal_pwr_ex.h:64
uint32_t PinPolarity
Definition: stm32h7xx_hal_pwr_ex.h:69
uint32_t PinPull
Definition: stm32h7xx_hal_pwr_ex.h:74