RTEMS 6.1-rc7
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cpu.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
12/*
13 * COPYRIGHT (c) 1989-2011.
14 * On-Line Applications Research Corporation (OAR).
15 *
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions
18 * are met:
19 * 1. Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#ifndef _RTEMS_SCORE_CPU_H
39#define _RTEMS_SCORE_CPU_H
40
41#ifdef __cplusplus
42extern "C" {
43#endif
44
46#include <rtems/score/sparc.h>
47
48/* conditional compilation parameters */
49
50/*
51 * The SPARC ABI is a bit special with respect to the floating point context.
52 * The complete floating point context is volatile. Thus, from an ABI point
53 * of view nothing needs to be saved and restored during a context switch.
54 * Instead the floating point context must be saved and restored during
55 * interrupt processing. Historically, the deferred floating point switch was
56 * used for SPARC and the complete floating point context is saved and
57 * restored during a context switch to the new floating point unit owner.
58 * This is a bit dangerous since post-switch actions (e.g. signal handlers)
59 * and context switch extensions may silently corrupt the floating point
60 * context.
61 *
62 * The floating point unit is disabled for interrupt handlers. Thus, in case
63 * an interrupt handler uses the floating point unit then this will result in a
64 * trap (INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT).
65 *
66 * In uniprocessor configurations, a lazy floating point context switch is
67 * used. In case an active floating point thread is interrupted (PSR[EF] == 1)
68 * and a thread dispatch is carried out, then this thread is registered as the
69 * floating point owner. When a floating point owner is present during a
70 * context switch, the floating point unit is disabled for the heir thread
71 * (PSR[EF] == 0). The floating point disabled trap checks that the use of the
72 * floating point unit is allowed and saves/restores the floating point context
73 * on demand.
74 *
75 * In SMP configurations, the deferred floating point switch is not supported
76 * in principle. So, use here a synchronous floating point switching.
77 * Synchronous means that the volatile floating point context is saved and
78 * restored around a thread dispatch issued during interrupt processing. Thus
79 * post-switch actions and context switch extensions may safely use the
80 * floating point unit.
81 */
82#if SPARC_HAS_FPU == 1
83 #if defined(RTEMS_SMP)
84 #define SPARC_USE_SYNCHRONOUS_FP_SWITCH
85 #else
86 #define SPARC_USE_LAZY_FP_SWITCH
87 #endif
88#endif
89
100#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
101
110#define CPU_ISR_PASSES_FRAME_POINTER FALSE
111
120#if ( SPARC_HAS_FPU == 1 ) && !defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH)
121 #define CPU_HARDWARE_FP TRUE
122#else
123 #define CPU_HARDWARE_FP FALSE
124#endif
125
130#define CPU_SOFTWARE_FP FALSE
131
140#define CPU_ALL_TASKS_ARE_FP FALSE
141
151#define CPU_IDLE_TASK_IS_FP FALSE
152
153#define CPU_USE_DEFERRED_FP_SWITCH FALSE
154
155#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
156
166#define CPU_STACK_GROWS_UP FALSE
167
168/* LEON3 systems may use a cache line size of 64 */
169#define CPU_CACHE_LINE_BYTES 64
170
171#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
172
180#define CPU_MODES_INTERRUPT_MASK 0x0000000F
181
182#ifndef ASM
189typedef struct {
191 uint32_t l0;
193 uint32_t l1;
195 uint32_t l2;
197 uint32_t l3;
199 uint32_t l4;
201 uint32_t l5;
203 uint32_t l6;
205 uint32_t l7;
207 uint32_t i0;
209 uint32_t i1;
211 uint32_t i2;
213 uint32_t i3;
215 uint32_t i4;
217 uint32_t i5;
219 uint32_t i6_fp;
221 uint32_t i7;
224
225 /*
226 * The following are for the callee to save the register arguments in
227 * should this be necessary.
228 */
230 uint32_t saved_arg0;
232 uint32_t saved_arg1;
234 uint32_t saved_arg2;
236 uint32_t saved_arg3;
238 uint32_t saved_arg4;
240 uint32_t saved_arg5;
242 uint32_t pad0;
244
245#endif /* ASM */
246
248#define CPU_STACK_FRAME_L0_OFFSET 0x00
250#define CPU_STACK_FRAME_L1_OFFSET 0x04
252#define CPU_STACK_FRAME_L2_OFFSET 0x08
254#define CPU_STACK_FRAME_L3_OFFSET 0x0c
256#define CPU_STACK_FRAME_L4_OFFSET 0x10
258#define CPU_STACK_FRAME_L5_OFFSET 0x14
260#define CPU_STACK_FRAME_L6_OFFSET 0x18
262#define CPU_STACK_FRAME_L7_OFFSET 0x1c
264#define CPU_STACK_FRAME_I0_OFFSET 0x20
266#define CPU_STACK_FRAME_I1_OFFSET 0x24
268#define CPU_STACK_FRAME_I2_OFFSET 0x28
270#define CPU_STACK_FRAME_I3_OFFSET 0x2c
272#define CPU_STACK_FRAME_I4_OFFSET 0x30
274#define CPU_STACK_FRAME_I5_OFFSET 0x34
276#define CPU_STACK_FRAME_I6_FP_OFFSET 0x38
278#define CPU_STACK_FRAME_I7_OFFSET 0x3c
280#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x40
282#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x44
284#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x48
286#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x4c
288#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0x50
290#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0x54
292#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0x58
294#define CPU_STACK_FRAME_PAD0_OFFSET 0x5c
295
296#define CPU_MAXIMUM_PROCESSORS 32
297
319#ifndef ASM
321
337typedef struct {
339 uint32_t g5;
341 uint32_t g7;
342
350 double l0_and_l1;
352 uint32_t l2;
354 uint32_t l3;
356 uint32_t l4;
358 uint32_t l5;
360 uint32_t l6;
362 uint32_t l7;
363
365 uint32_t i0;
367 uint32_t i1;
369 uint32_t i2;
371 uint32_t i3;
373 uint32_t i4;
375 uint32_t i5;
377 uint32_t i6_fp;
379 uint32_t i7;
380
382 uint32_t o6_sp;
387 uint32_t o7;
388
390 uint32_t psr;
396 uint32_t isr_dispatch_disable;
397
398#if defined(SPARC_USE_LAZY_FP_SWITCH)
399 Context_Control_fp *fp_context;
400#endif
401
402#if defined(RTEMS_SMP)
403 volatile uint32_t is_executing;
404#endif
406
412#define _CPU_Context_Get_SP( _context ) \
413 (_context)->o6_sp
414
415#ifdef RTEMS_SMP
416 static inline bool _CPU_Context_Get_is_executing(
418 )
419 {
420 return context->is_executing;
421 }
422
423 static inline void _CPU_Context_Set_is_executing(
425 bool is_executing
426 )
427 {
428 context->is_executing = is_executing;
429 }
430#endif
431
432#endif /* ASM */
433
434/*
435 * Offsets of fields with Context_Control for assembly routines.
436 */
437
439#define G5_OFFSET 0x00
441#define G7_OFFSET 0x04
442
444#define L0_OFFSET 0x08
446#define L1_OFFSET 0x0C
448#define L2_OFFSET 0x10
450#define L3_OFFSET 0x14
452#define L4_OFFSET 0x18
454#define L5_OFFSET 0x1C
456#define L6_OFFSET 0x20
458#define L7_OFFSET 0x24
459
461#define I0_OFFSET 0x28
463#define I1_OFFSET 0x2C
465#define I2_OFFSET 0x30
467#define I3_OFFSET 0x34
469#define I4_OFFSET 0x38
471#define I5_OFFSET 0x3C
473#define I6_FP_OFFSET 0x40
475#define I7_OFFSET 0x44
476
478#define O6_SP_OFFSET 0x48
480#define O7_OFFSET 0x4C
481
483#define PSR_OFFSET 0x50
485#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x54
486
487#if defined(RTEMS_SMP)
488 #define SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x58
489#endif
490
491#ifndef ASM
497struct Context_Control_fp {
499 double f0_f1;
501 double f2_f3;
503 double f4_f5;
505 double f6_f7;
507 double f8_f9;
509 double f10_f11;
511 double f12_f13;
513 double f14_f15;
515 double f16_f17;
517 double f18_f19;
519 double f20_f21;
521 double f22_f23;
523 double f24_f25;
525 double f26_f27;
527 double f28_f29;
529 double f30_f31;
531 uint32_t fsr;
532};
533
534#endif /* ASM */
535
536/*
537 * Offsets of fields with Context_Control_fp for assembly routines.
538 */
539
541#define FO_F1_OFFSET 0x00
543#define F2_F3_OFFSET 0x08
545#define F4_F5_OFFSET 0x10
547#define F6_F7_OFFSET 0x18
549#define F8_F9_OFFSET 0x20
551#define F1O_F11_OFFSET 0x28
553#define F12_F13_OFFSET 0x30
555#define F14_F15_OFFSET 0x38
557#define F16_F17_OFFSET 0x40
559#define F18_F19_OFFSET 0x48
561#define F2O_F21_OFFSET 0x50
563#define F22_F23_OFFSET 0x58
565#define F24_F25_OFFSET 0x60
567#define F26_F27_OFFSET 0x68
569#define F28_F29_OFFSET 0x70
571#define F3O_F31_OFFSET 0x78
573#define FSR_OFFSET 0x80
574
576#define CONTEXT_CONTROL_FP_SIZE 0x84
577
578#ifndef ASM
579
590typedef struct {
594 uint32_t psr;
596 uint32_t pc;
598 uint32_t npc;
600 uint32_t g1;
602 uint32_t g2;
604 uint32_t g3;
606 uint32_t g4;
608 uint32_t g5;
612 uint32_t g7;
614 uint32_t i0;
616 uint32_t i1;
618 uint32_t i2;
620 uint32_t i3;
622 uint32_t i4;
624 uint32_t i5;
626 uint32_t i6_fp;
628 uint32_t i7;
630 uint32_t y;
632 uint32_t tpc;
634
635#endif /* ASM */
636
637#ifndef ASM
646typedef struct {
648 uint32_t mov_psr_l0;
656
667
671#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
672
673#endif
674
680#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
681
705#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256
706
711#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511
712
717#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
718
727#define CPU_STACK_MINIMUM_SIZE (1024*4)
728
732#define CPU_SIZEOF_POINTER 4
733
740#define CPU_ALIGNMENT 8
741
753#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
754
759#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
760
761#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
762
763#ifndef ASM
764
771void _SPARC_Interrupt_dispatch( uint32_t irq );
772
777#define _CPU_ISR_Disable( _level ) \
778 (_level) = sparc_disable_interrupts()
779
785#define _CPU_ISR_Enable( _level ) \
786 sparc_enable_interrupts( _level )
787
794#define _CPU_ISR_Flash( _level ) \
795 sparc_flash_interrupts( _level )
796
797#define _CPU_ISR_Is_enabled( _isr_cookie ) \
798 sparc_interrupt_is_enabled( _isr_cookie )
799
800static inline bool _CPU_ISR_Is_enabled( uint32_t level )
801{
802 return ( level & SPARC_PSR_PIL_MASK ) == 0;
803}
804
810#define _CPU_ISR_Set_level( _newlevel ) \
811 sparc_enable_interrupts( _newlevel << 8)
812
820uint32_t _CPU_ISR_Get_level( void );
821
822/* end of ISR handler macros */
823
824/* Context handler macros */
825
847void _CPU_Context_Initialize(
848 Context_Control *the_context,
849 uint32_t *stack_base,
850 uint32_t size,
851 uint32_t new_level,
852 void *entry_point,
853 bool is_fp,
854 void *tls_area
855);
856
870#define _CPU_Context_Initialization_at_thread_begin() \
871 do { \
872 __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \
873 } while (0)
874
883#define _CPU_Context_Restart_self( _the_context ) \
884 _CPU_Context_restore( (_the_context) );
885
889#define _CPU_Context_Initialize_fp( _destination ) \
890 do { } while ( 0 )
891
895#define _CPU_Context_save_fp( _fp_context_ptr ) \
896 do { } while ( 0 )
897
901#define _CPU_Context_restore_fp( _fp_context_ptr ) \
902 do { } while ( 0 )
903/* end of Context handler macros */
904
905#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
906
907/* Bitfield handler macros */
908
909#if ( SPARC_HAS_BITSCAN == 0 )
914 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
915#else
916 #error "scan instruction not currently supported by RTEMS!!"
917#endif
918
919/* end of Bitfield handler macros */
920
921/* functions */
922
928void _CPU_Initialize(void);
929
930typedef void ( *CPU_ISR_raw_handler )( void );
931
943 uint32_t vector,
944 CPU_ISR_raw_handler new_handler,
945 CPU_ISR_raw_handler *old_handler
946);
947
948typedef void ( *CPU_ISR_handler )( uint32_t );
949
961 uint32_t vector,
962 CPU_ISR_handler new_handler,
963 CPU_ISR_handler *old_handler
964);
965
966RTEMS_NO_RETURN void *_CPU_Thread_Idle_body( uintptr_t ignored );
967
977 Context_Control *run,
978 Context_Control *heir
979);
980
981RTEMS_NO_RETURN void _CPU_Context_switch_no_return(
982 Context_Control *executing,
983 Context_Control *heir
984);
985
994RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context );
995
996#if !defined(RTEMS_SMP)
1011
1012#define _CPU_Start_multitasking( _heir ) _SPARC_Start_multitasking( _heir )
1013#endif
1014
1015#if defined(RTEMS_SMP)
1016 uint32_t _CPU_SMP_Initialize( void );
1017
1018 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
1019
1020 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
1021
1022 void _CPU_SMP_Prepare_start_multitasking( void );
1023
1024 #if defined(__leon__) && !defined(RTEMS_PARAVIRT)
1025 static inline uint32_t _CPU_SMP_Get_current_processor( void )
1026 {
1027 return _LEON3_Get_current_processor();
1028 }
1029 #else
1030 uint32_t _CPU_SMP_Get_current_processor( void );
1031 #endif
1032
1033 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1034#endif
1035
1036#if defined(SPARC_USE_LAZY_FP_SWITCH)
1037#define _CPU_Context_Destroy( _the_thread, _the_context ) \
1038 do { \
1039 Per_CPU_Control *cpu_self = _Per_CPU_Get(); \
1040 Thread_Control *_fp_owner = cpu_self->cpu_per_cpu.fp_owner; \
1041 if ( _fp_owner == _the_thread ) { \
1042 cpu_self->cpu_per_cpu.fp_owner = NULL; \
1043 } \
1044 } while ( 0 )
1045#endif
1046
1051typedef struct {
1053 uint32_t local[ 8 ];
1054
1056 uint32_t input[ 8 ];
1058
1063typedef struct {
1065 uint32_t psr;
1066
1068 uint32_t pc;
1069
1071 uint32_t npc;
1072
1074 uint32_t trap;
1075
1077 uint32_t wim;
1078
1080 uint32_t y;
1081
1083 uint32_t global[ 8 ];
1084
1086 uint32_t output[ 8 ] ;
1087
1093
1094#if SPARC_HAS_FPU == 1
1096 uint32_t fsr;
1097
1099 uint64_t fp[ 16 ];
1100#endif
1102
1104
1125static inline uint32_t CPU_swap_u32(
1126 uint32_t value
1127)
1128{
1129 uint32_t byte1, byte2, byte3, byte4, swapped;
1130
1131 byte4 = (value >> 24) & 0xff;
1132 byte3 = (value >> 16) & 0xff;
1133 byte2 = (value >> 8) & 0xff;
1134 byte1 = value & 0xff;
1135
1136 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1137 return( swapped );
1138}
1139
1147#define CPU_swap_u16( value ) \
1148 (((value&0xff) << 8) | ((value >> 8)&0xff))
1149
1150typedef uint32_t CPU_Counter_ticks;
1151
1152uint32_t _CPU_Counter_frequency( void );
1153
1154CPU_Counter_ticks _CPU_Counter_read( void );
1155
1157typedef uintptr_t CPU_Uint32ptr;
1158
1159#endif /* ASM */
1160
1161#ifdef __cplusplus
1162}
1163#endif
1164
1165#endif
This header file provides basic definitions used by the API and the implementation.
void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.c:100
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
#define pc
pc, used on mips16 *‍/
Definition: regs.h:67
#define fp
frame-pointer *‍/
Definition: regs.h:65
rtems_termios_device_context * context
Definition: console-config.c:62
const CPU_Trap_table_entry _CPU_Trap_slot_template
Definition: sparc-isr-install.c:54
void _SPARC_Interrupt_dispatch(uint32_t irq)
Dispatches the installed interrupt handlers.
Definition: bsp_isr_handler.c:47
RTEMS_NO_RETURN void _SPARC_Start_multitasking(Context_Control *heir)
Starts multitasking in uniprocessor configurations.
This header file provides information required to build RTEMS for a particular member of the SPARC fa...
#define SPARC_PSR_PIL_MASK
Definition: sparc.h:148
#define SPARC_NUMBER_OF_REGISTER_WINDOWS
Definition: sparc.h:84
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
uint32_t y
This member contains the Y register value.
Definition: cpu.h:1080
uint32_t npc
This member contains the nPC value.
Definition: cpu.h:1071
uint32_t wim
This member contains the WIM register value.
Definition: cpu.h:1077
uint32_t trap
This member contains the trap number.
Definition: cpu.h:1074
uint32_t psr
This member contains the PSR register value.
Definition: cpu.h:1065
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
uint32_t g4
Definition: cpu.h:606
uint32_t i1
Definition: cpu.h:616
uint32_t i3
Definition: cpu.h:620
SPARC_Minimum_stack_frame Stack_frame
Definition: cpu.h:592
uint32_t g1
Definition: cpu.h:600
uint32_t tpc
Definition: cpu.h:632
uint32_t g2
Definition: cpu.h:602
uint32_t i6_fp
Definition: cpu.h:626
uint32_t i2
Definition: cpu.h:618
uint32_t i7
Definition: cpu.h:628
uint32_t pc
Definition: cpu.h:596
uint32_t reserved_for_alignment
Definition: cpu.h:610
uint32_t y
Definition: cpu.h:630
uint32_t g7
Definition: cpu.h:612
uint32_t psr
Definition: cpu.h:594
uint32_t g5
Definition: cpu.h:608
uint32_t i5
Definition: cpu.h:624
uint32_t i0
Definition: cpu.h:614
uint32_t i4
Definition: cpu.h:622
uint32_t npc
Definition: cpu.h:598
uint32_t g3
Definition: cpu.h:604
Definition: cpu.h:646
uint32_t mov_vector_l3
Definition: cpu.h:654
uint32_t mov_psr_l0
Definition: cpu.h:648
uint32_t jmp_to_low_of_handler_plus_l4
Definition: cpu.h:652
uint32_t sethi_of_handler_to_l4
Definition: cpu.h:650
SPARC basic context.
Definition: cpu.h:213
double f24_f25
Definition: cpu.h:523
double f28_f29
Definition: cpu.h:527
uint32_t fsr
Definition: cpu.h:531
double f2_f3
Definition: cpu.h:501
double f0_f1
Definition: cpu.h:499
double f16_f17
Definition: cpu.h:515
double f4_f5
Definition: cpu.h:503
double f20_f21
Definition: cpu.h:519
double f26_f27
Definition: cpu.h:525
double f8_f9
Definition: cpu.h:507
double f30_f31
Definition: cpu.h:529
double f18_f19
Definition: cpu.h:517
double f10_f11
Definition: cpu.h:509
double f22_f23
Definition: cpu.h:521
double f6_f7
Definition: cpu.h:505
double f12_f13
Definition: cpu.h:511
double f14_f15
Definition: cpu.h:513
Thread register context.
Definition: cpu.h:173
uint32_t i4
Definition: cpu.h:373
uint32_t i5
Definition: cpu.h:375
uint32_t i3
Definition: cpu.h:371
uint32_t o6_sp
Definition: cpu.h:382
uint32_t g7
Definition: cpu.h:341
uint32_t l5
Definition: cpu.h:358
uint32_t g5
Definition: cpu.h:339
uint32_t i0
Definition: cpu.h:365
uint32_t psr
Definition: cpu.h:390
uint32_t l3
Definition: cpu.h:354
uint32_t l4
Definition: cpu.h:356
uint32_t o7
Definition: cpu.h:387
uint32_t l2
Definition: cpu.h:352
uint32_t i7
Definition: cpu.h:379
uint32_t i2
Definition: cpu.h:369
uint32_t i1
Definition: cpu.h:367
uint32_t l6
Definition: cpu.h:360
uint32_t i6_fp
Definition: cpu.h:377
uint32_t l7
Definition: cpu.h:362
double l0_and_l1
Definition: cpu.h:350
Definition: cpu.h:189
uint32_t l7
Definition: cpu.h:205
uint32_t saved_arg5
Definition: cpu.h:240
uint32_t saved_arg4
Definition: cpu.h:238
uint32_t saved_arg1
Definition: cpu.h:232
uint32_t pad0
Definition: cpu.h:242
uint32_t i7
Definition: cpu.h:221
uint32_t i2
Definition: cpu.h:211
uint32_t l0
Definition: cpu.h:191
uint32_t l3
Definition: cpu.h:197
uint32_t l1
Definition: cpu.h:193
uint32_t i0
Definition: cpu.h:207
uint32_t i3
Definition: cpu.h:213
uint32_t saved_arg2
Definition: cpu.h:234
uint32_t i6_fp
Definition: cpu.h:219
uint32_t l2
Definition: cpu.h:195
void * structure_return_address
Definition: cpu.h:223
uint32_t saved_arg0
Definition: cpu.h:230
uint32_t i4
Definition: cpu.h:215
uint32_t l6
Definition: cpu.h:203
uint32_t saved_arg3
Definition: cpu.h:236
uint32_t i1
Definition: cpu.h:209
uint32_t l5
Definition: cpu.h:201
uint32_t i5
Definition: cpu.h:217
uint32_t l4
Definition: cpu.h:199
This structure contains the local and input registers of a register window.
Definition: cpu.h:1051