38#ifndef _RTEMS_SCORE_CPUIMPL_H
39#define _RTEMS_SCORE_CPUIMPL_H
41#include <rtems/score/cpu.h>
54#define SPARC_MINIMUM_STACK_FRAME_SIZE 0x60
61#define ISF_PSR_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x00
63#define ISF_PC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x04
65#define ISF_NPC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x08
67#define ISF_G1_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x0c
69#define ISF_G2_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x10
71#define ISF_G3_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x14
73#define ISF_G4_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x18
75#define ISF_G5_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x1c
77#define ISF_G7_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x24
79#define ISF_I0_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x28
81#define ISF_I1_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x2c
83#define ISF_I2_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x30
85#define ISF_I3_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x34
87#define ISF_I4_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x38
89#define ISF_I5_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x3c
91#define ISF_I6_FP_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x40
93#define ISF_I7_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x44
95#define ISF_Y_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x48
97#define ISF_TPC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x4c
100#define CPU_INTERRUPT_FRAME_SIZE SPARC_MINIMUM_STACK_FRAME_SIZE + 0x50
102#define SPARC_FP_CONTEXT_OFFSET_F0_F1 0
103#define SPARC_FP_CONTEXT_OFFSET_F2_F3 8
104#define SPARC_FP_CONTEXT_OFFSET_F4_F5 16
105#define SPARC_FP_CONTEXT_OFFSET_F6_F7 24
106#define SPARC_FP_CONTEXT_OFFSET_F8_F9 32
107#define SPARC_FP_CONTEXT_OFFSET_F10_F11 40
108#define SPARC_FP_CONTEXT_OFFSET_F12_F13 48
109#define SPARC_FP_CONTEXT_OFFSET_F14_F15 56
110#define SPARC_FP_CONTEXT_OFFSET_F16_F17 64
111#define SPARC_FP_CONTEXT_OFFSET_F18_F19 72
112#define SPARC_FP_CONTEXT_OFFSET_F20_F21 80
113#define SPARC_FP_CONTEXT_OFFSET_F22_F23 88
114#define SPARC_FP_CONTEXT_OFFSET_F24_F25 96
115#define SPARC_FP_CONTEXT_OFFSET_F26_F27 104
116#define SPARC_FP_CONTEXT_OFFSET_F28_F29 112
117#define SPARC_FP_CONTEXT_OFFSET_F30_F31 120
118#define SPARC_FP_CONTEXT_OFFSET_FSR 128
120#if ( SPARC_HAS_FPU == 1 )
121 #define CPU_PER_CPU_CONTROL_SIZE 8
123 #define CPU_PER_CPU_CONTROL_SIZE 0
126#define CPU_THREAD_LOCAL_STORAGE_VARIANT 20
128#if ( SPARC_HAS_FPU == 1 )
133 #define SPARC_PER_CPU_FSR_OFFSET 0
135 #if defined(SPARC_USE_LAZY_FP_SWITCH)
140 #define SPARC_PER_CPU_FP_OWNER_OFFSET 4
144#define SPARC_REGISTER_WINDOW_OFFSET_LOCAL( i ) ( ( i ) * 4 )
145#define SPARC_REGISTER_WINDOW_OFFSET_INPUT( i ) ( ( i ) * 4 + 32 )
146#define SPARC_REGISTER_WINDOW_SIZE 64
148#define SPARC_EXCEPTION_OFFSET_PSR 0
149#define SPARC_EXCEPTION_OFFSET_PC 4
150#define SPARC_EXCEPTION_OFFSET_NPC 8
151#define SPARC_EXCEPTION_OFFSET_TRAP 12
152#define SPARC_EXCEPTION_OFFSET_WIM 16
153#define SPARC_EXCEPTION_OFFSET_Y 20
154#define SPARC_EXCEPTION_OFFSET_GLOBAL( i ) ( ( i ) * 4 + 24 )
155#define SPARC_EXCEPTION_OFFSET_OUTPUT( i ) ( ( i ) * 4 + 56 )
156#define SPARC_EXCEPTION_OFFSET_WINDOWS( i ) ( ( i ) * 64 + 88 )
158#if SPARC_HAS_FPU == 1
159#define SPARC_EXCEPTION_OFFSET_FSR 536
160#define SPARC_EXCEPTION_OFFSET_FP( i ) ( ( i ) * 8 + 544 )
161#define SPARC_EXCEPTION_FRAME_SIZE 672
163#define SPARC_EXCEPTION_FRAME_SIZE 536
166#if defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH)
167#define SPARC_FP_FRAME_OFFSET_FO_F1 (SPARC_MINIMUM_STACK_FRAME_SIZE + 0)
168#define SPARC_FP_FRAME_OFFSET_F2_F3 (SPARC_FP_FRAME_OFFSET_FO_F1 + 8)
169#define SPARC_FP_FRAME_OFFSET_F4_F5 (SPARC_FP_FRAME_OFFSET_F2_F3 + 8)
170#define SPARC_FP_FRAME_OFFSET_F6_F7 (SPARC_FP_FRAME_OFFSET_F4_F5 + 8)
171#define SPARC_FP_FRAME_OFFSET_F8_F9 (SPARC_FP_FRAME_OFFSET_F6_F7 + 8)
172#define SPARC_FP_FRAME_OFFSET_F1O_F11 (SPARC_FP_FRAME_OFFSET_F8_F9 + 8)
173#define SPARC_FP_FRAME_OFFSET_F12_F13 (SPARC_FP_FRAME_OFFSET_F1O_F11 + 8)
174#define SPARC_FP_FRAME_OFFSET_F14_F15 (SPARC_FP_FRAME_OFFSET_F12_F13 + 8)
175#define SPARC_FP_FRAME_OFFSET_F16_F17 (SPARC_FP_FRAME_OFFSET_F14_F15 + 8)
176#define SPARC_FP_FRAME_OFFSET_F18_F19 (SPARC_FP_FRAME_OFFSET_F16_F17 + 8)
177#define SPARC_FP_FRAME_OFFSET_F2O_F21 (SPARC_FP_FRAME_OFFSET_F18_F19 + 8)
178#define SPARC_FP_FRAME_OFFSET_F22_F23 (SPARC_FP_FRAME_OFFSET_F2O_F21 + 8)
179#define SPARC_FP_FRAME_OFFSET_F24_F25 (SPARC_FP_FRAME_OFFSET_F22_F23 + 8)
180#define SPARC_FP_FRAME_OFFSET_F26_F27 (SPARC_FP_FRAME_OFFSET_F24_F25 + 8)
181#define SPARC_FP_FRAME_OFFSET_F28_F29 (SPARC_FP_FRAME_OFFSET_F26_F27 + 8)
182#define SPARC_FP_FRAME_OFFSET_F3O_F31 (SPARC_FP_FRAME_OFFSET_F28_F29 + 8)
183#define SPARC_FP_FRAME_OFFSET_FSR (SPARC_FP_FRAME_OFFSET_F3O_F31 + 8)
184#define SPARC_FP_FRAME_SIZE (SPARC_FP_FRAME_OFFSET_FSR + 8)
194#if ( SPARC_HAS_FPU == 1 )
204#if defined(SPARC_USE_LAZY_FP_SWITCH)
211 uint32_t reserved_for_alignment_of_interrupt_frame;
222#define _CPU_Get_current_per_CPU_control() _SPARC_Per_CPU_current
224#define _CPU_Get_thread_executing() ( _SPARC_Per_CPU_current->executing )
226void _CPU_Context_volatile_clobber( uintptr_t pattern );
228void _CPU_Context_validate( uintptr_t pattern );
230static inline void _CPU_Instruction_illegal(
void )
232 __asm__
volatile (
"unimp 0" );
235static inline void _CPU_Instruction_no_operation(
void )
237 __asm__
volatile (
"nop" );
240static inline void _CPU_Use_thread_local_storage(
244 register uint32_t g7 __asm__(
"g7" );
249 __asm__
volatile (
"" : :
"r" ( g7 ) );
252static inline void *_CPU_Get_TLS_thread_pointer(
259#if defined(RTEMS_PROFILING)
263CPU_Counter_ticks _SPARC_Counter_read_ISR_disabled(
void );
rtems_termios_device_context * context
Definition: console-config.c:62
The CPU specific per-CPU control.
Definition: cpuimpl.h:91
Thread register context.
Definition: cpu.h:173
Per CPU Core Structure.
Definition: percpu.h:384