RTEMS 6.1-rc7
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fsl_cache.h
1/*
2 * Copyright 2016-2021 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_CACHE_H_
9#define _FSL_CACHE_H_
10
11#include "fsl_common.h"
12
18/*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
25#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 6))
29#define L1CODEBUSCACHE_LINESIZE_BYTE \
30 FSL_FEATURE_L1ICACHE_LINESIZE_BYTE
31#define L1SYSTEMBUSCACHE_LINESIZE_BYTE \
32 L1CODEBUSCACHE_LINESIZE_BYTE
34/*******************************************************************************
35 * API
36 ******************************************************************************/
37
38#if defined(__cplusplus)
39extern "C" {
40#endif
41
42#if (FSL_FEATURE_SOC_LMEM_COUNT == 1)
52void L1CACHE_EnableCodeCache(void);
53
58void L1CACHE_DisableCodeCache(void);
59
64void L1CACHE_InvalidateCodeCache(void);
65
76void L1CACHE_InvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte);
77
82void L1CACHE_CleanCodeCache(void);
83
94void L1CACHE_CleanCodeCacheByRange(uint32_t address, uint32_t size_byte);
95
100void L1CACHE_CleanInvalidateCodeCache(void);
101
112void L1CACHE_CleanInvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte);
113
121static inline void L1CACHE_EnableCodeCacheWriteBuffer(bool enable)
122{
123 if (enable)
124 {
125 LMEM->PCCCR |= LMEM_PCCCR_ENWRBUF_MASK;
126 }
127 else
128 {
129 LMEM->PCCCR &= ~LMEM_PCCCR_ENWRBUF_MASK;
130 }
131}
132
133#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
138void L1CACHE_EnableSystemCache(void);
139
144void L1CACHE_DisableSystemCache(void);
145
150void L1CACHE_InvalidateSystemCache(void);
151
162void L1CACHE_InvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte);
163
168void L1CACHE_CleanSystemCache(void);
169
180void L1CACHE_CleanSystemCacheByRange(uint32_t address, uint32_t size_byte);
181
186void L1CACHE_CleanInvalidateSystemCache(void);
187
198void L1CACHE_CleanInvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte);
199
207static inline void L1CACHE_EnableSystemCacheWriteBuffer(bool enable)
208{
209 if (enable)
210 {
211 LMEM->PSCCR |= LMEM_PSCCR_ENWRBUF_MASK;
212 }
213 else
214 {
215 LMEM->PSCCR &= ~LMEM_PSCCR_ENWRBUF_MASK;
216 }
217}
219#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
220
233void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte);
234
242static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
243{
244 L1CACHE_InvalidateICacheByRange(address, size_byte);
245}
246
254void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte);
255
263void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte);
265#endif /* FSL_FEATURE_SOC_LMEM_COUNT == 1 */
266
282static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
283{
284 L1CACHE_InvalidateICacheByRange(address, size_byte);
285}
286
297static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
298{
299 L1CACHE_InvalidateDCacheByRange(address, size_byte);
300}
301
312static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
313{
314 L1CACHE_CleanDCacheByRange(address, size_byte);
315}
316
327static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
328{
329 L1CACHE_CleanInvalidateDCacheByRange(address, size_byte);
330}
331
334#if defined(__cplusplus)
335}
336#endif
337
340#endif /* _FSL_CACHE_H_*/
#define LMEM
Definition: MIMXRT1166_cm4.h:58953
void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
Invalidate cortex-m7 L1 instruction cache by range.
Definition: fsl_cache.c:411