RTEMS 6.1-rc7
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Data Fields

Debug MCU. More...

#include <stm32h723xx.h>

Data Fields

__IO uint32_t IDCODE
 
__IO uint32_t CR
 
uint32_t RESERVED4 [11]
 
__IO uint32_t APB3FZ1
 
uint32_t RESERVED5
 
__IO uint32_t APB1LFZ1
 
uint32_t RESERVED6
 
__IO uint32_t APB1HFZ1
 
uint32_t RESERVED7
 
__IO uint32_t APB2FZ1
 
uint32_t RESERVED8
 
__IO uint32_t APB4FZ1
 
__IO uint32_t RESERVED9 [990]
 
__IO uint32_t PIDR4
 
__IO uint32_t RESERVED10 [3]
 
__IO uint32_t PIDR0
 
__IO uint32_t PIDR1
 
__IO uint32_t PIDR2
 
__IO uint32_t PIDR3
 
__IO uint32_t CIDR0
 
__IO uint32_t CIDR1
 
__IO uint32_t CIDR2
 
__IO uint32_t CIDR3
 
__IO uint32_t RESERVED4 [11]
 
__IO uint32_t APB3FZ2
 
__IO uint32_t APB1LFZ2
 
__IO uint32_t APB1HFZ2
 
__IO uint32_t APB2FZ2
 
__IO uint32_t APB4FZ2
 

Detailed Description

Debug MCU.

Field Documentation

◆ APB1HFZ1

__IO uint32_t DBGMCU_TypeDef::APB1HFZ1

Debug MCU APB1LFZ1 freeze register, Address offset: 0x44

◆ APB1HFZ2

__IO uint32_t DBGMCU_TypeDef::APB1HFZ2

Debug MCU APB1LFZ2 freeze register, Address offset: 0x48

◆ APB1LFZ1

__IO uint32_t DBGMCU_TypeDef::APB1LFZ1

Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C

◆ APB1LFZ2

__IO uint32_t DBGMCU_TypeDef::APB1LFZ2

Debug MCU APB1LFZ2 freeze register, Address offset: 0x40

◆ APB2FZ1

__IO uint32_t DBGMCU_TypeDef::APB2FZ1

Debug MCU APB2FZ1 freeze register, Address offset: 0x4C

◆ APB2FZ2

__IO uint32_t DBGMCU_TypeDef::APB2FZ2

Debug MCU APB2FZ2 freeze register, Address offset: 0x50

◆ APB3FZ1

__IO uint32_t DBGMCU_TypeDef::APB3FZ1

Debug MCU APB3FZ1 freeze register, Address offset: 0x34

◆ APB3FZ2

__IO uint32_t DBGMCU_TypeDef::APB3FZ2

Debug MCU APB3FZ2 freeze register, Address offset: 0x38

◆ APB4FZ1

__IO uint32_t DBGMCU_TypeDef::APB4FZ1

Debug MCU APB4FZ1 freeze register, Address offset: 0x54

◆ APB4FZ2

__IO uint32_t DBGMCU_TypeDef::APB4FZ2

Debug MCU APB4FZ2 freeze register, Address offset: 0x58

◆ CIDR0

__IO uint32_t DBGMCU_TypeDef::CIDR0

Debug MCU component identity register 0, Address offset: 0xFF0

◆ CIDR1

__IO uint32_t DBGMCU_TypeDef::CIDR1

Debug MCU component identity register 1, Address offset: 0xFF4

◆ CIDR2

__IO uint32_t DBGMCU_TypeDef::CIDR2

Debug MCU component identity register 2, Address offset: 0xFF8

◆ CIDR3

__IO uint32_t DBGMCU_TypeDef::CIDR3

Debug MCU component identity register 3, Address offset: 0xFFC

◆ CR

__IO uint32_t DBGMCU_TypeDef::CR

Debug MCU configuration register, Address offset: 0x04

◆ IDCODE

__IO uint32_t DBGMCU_TypeDef::IDCODE

MCU device ID code, Address offset: 0x00

◆ PIDR0

__IO uint32_t DBGMCU_TypeDef::PIDR0

Debug MCU peripheral identity register 0, Address offset: 0xFE0

◆ PIDR1

__IO uint32_t DBGMCU_TypeDef::PIDR1

Debug MCU peripheral identity register 1, Address offset: 0xFE4

◆ PIDR2

__IO uint32_t DBGMCU_TypeDef::PIDR2

Debug MCU peripheral identity register 2, Address offset: 0xFE8

◆ PIDR3

__IO uint32_t DBGMCU_TypeDef::PIDR3

Debug MCU peripheral identity register 3, Address offset: 0xFEC

◆ PIDR4

__IO uint32_t DBGMCU_TypeDef::PIDR4

Debug MCU peripheral identity register 4, Address offset: 0xFD0

◆ RESERVED10

__IO uint32_t DBGMCU_TypeDef::RESERVED10

Reserved, Address offset: 0xFD4-0xFDC

◆ RESERVED4 [1/2]

uint32_t DBGMCU_TypeDef::RESERVED4

Reserved, Address offset: 0x08

◆ RESERVED4 [2/2]

__IO uint32_t DBGMCU_TypeDef::RESERVED4[11]

Reserved, Address offset: 0x08

◆ RESERVED5

uint32_t DBGMCU_TypeDef::RESERVED5

Reserved, Address offset: 0x38

◆ RESERVED6

uint32_t DBGMCU_TypeDef::RESERVED6

Reserved, Address offset: 0x40

◆ RESERVED7

uint32_t DBGMCU_TypeDef::RESERVED7

Reserved, Address offset: 0x48

◆ RESERVED8

uint32_t DBGMCU_TypeDef::RESERVED8

Reserved, Address offset: 0x50

◆ RESERVED9

__IO uint32_t DBGMCU_TypeDef::RESERVED9

Reserved, Address offset: 0x58-0xFCC


The documentation for this struct was generated from the following files: