RTEMS 6.1-rc7
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Data Fields

Secure digital input/output Interface. More...

#include <stm32h723xx.h>

Data Fields

__IO uint32_t POWER
 
__IO uint32_t CLKCR
 
__IO uint32_t ARG
 
__IO uint32_t CMD
 
__I uint32_t RESPCMD
 
__I uint32_t RESP1
 
__I uint32_t RESP2
 
__I uint32_t RESP3
 
__I uint32_t RESP4
 
__IO uint32_t DTIMER
 
__IO uint32_t DLEN
 
__IO uint32_t DCTRL
 
__I uint32_t DCOUNT
 
__I uint32_t STA
 
__IO uint32_t ICR
 
__IO uint32_t MASK
 
__IO uint32_t ACKTIME
 
uint32_t RESERVED0 [3]
 
__IO uint32_t IDMACTRL
 
__IO uint32_t IDMABSIZE
 
__IO uint32_t IDMABASE0
 
__IO uint32_t IDMABASE1
 
uint32_t RESERVED1 [8]
 
__IO uint32_t FIFO
 
uint32_t RESERVED2 [222]
 
__IO uint32_t IPVR
 

Detailed Description

Secure digital input/output Interface.

Field Documentation

◆ ACKTIME

__IO uint32_t SDMMC_TypeDef::ACKTIME

SDMMC Acknowledgement timer register, Address offset: 0x40

◆ ARG

__IO uint32_t SDMMC_TypeDef::ARG

SDMMC argument register, Address offset: 0x08

◆ CLKCR

__IO uint32_t SDMMC_TypeDef::CLKCR

SDMMC clock control register, Address offset: 0x04

◆ CMD

__IO uint32_t SDMMC_TypeDef::CMD

SDMMC command register, Address offset: 0x0C

◆ DCOUNT

__I uint32_t SDMMC_TypeDef::DCOUNT

SDMMC data counter register, Address offset: 0x30

◆ DCTRL

__IO uint32_t SDMMC_TypeDef::DCTRL

SDMMC data control register, Address offset: 0x2C

◆ DLEN

__IO uint32_t SDMMC_TypeDef::DLEN

SDMMC data length register, Address offset: 0x28

◆ DTIMER

__IO uint32_t SDMMC_TypeDef::DTIMER

SDMMC data timer register, Address offset: 0x24

◆ FIFO

__IO uint32_t SDMMC_TypeDef::FIFO

SDMMC data FIFO register, Address offset: 0x80

◆ ICR

__IO uint32_t SDMMC_TypeDef::ICR

SDMMC interrupt clear register, Address offset: 0x38

◆ IDMABASE0

__IO uint32_t SDMMC_TypeDef::IDMABASE0

SDMMC DMA buffer 0 base address register, Address offset: 0x58

◆ IDMABASE1

__IO uint32_t SDMMC_TypeDef::IDMABASE1

SDMMC DMA buffer 1 base address register, Address offset: 0x5C

◆ IDMABSIZE

__IO uint32_t SDMMC_TypeDef::IDMABSIZE

SDMMC DMA buffer size register, Address offset: 0x54

◆ IDMACTRL

__IO uint32_t SDMMC_TypeDef::IDMACTRL

SDMMC DMA control register, Address offset: 0x50

◆ IPVR

__IO uint32_t SDMMC_TypeDef::IPVR

SDMMC data FIFO register, Address offset: 0x3FC

◆ MASK

__IO uint32_t SDMMC_TypeDef::MASK

SDMMC mask register, Address offset: 0x3C

◆ POWER

__IO uint32_t SDMMC_TypeDef::POWER

SDMMC power control register, Address offset: 0x00

◆ RESERVED0

uint32_t SDMMC_TypeDef::RESERVED0

Reserved, 0x44 - 0x4C - 0x4C

◆ RESERVED1

uint32_t SDMMC_TypeDef::RESERVED1

Reserved, 0x60-0x7C

◆ RESERVED2

uint32_t SDMMC_TypeDef::RESERVED2

Reserved, 0x84-0x3F8

◆ RESP1

__I uint32_t SDMMC_TypeDef::RESP1

SDMMC response 1 register, Address offset: 0x14

◆ RESP2

__I uint32_t SDMMC_TypeDef::RESP2

SDMMC response 2 register, Address offset: 0x18

◆ RESP3

__I uint32_t SDMMC_TypeDef::RESP3

SDMMC response 3 register, Address offset: 0x1C

◆ RESP4

__I uint32_t SDMMC_TypeDef::RESP4

SDMMC response 4 register, Address offset: 0x20

◆ RESPCMD

__I uint32_t SDMMC_TypeDef::RESPCMD

SDMMC command response register, Address offset: 0x10

◆ STA

__I uint32_t SDMMC_TypeDef::STA

SDMMC status register, Address offset: 0x34


The documentation for this struct was generated from the following files: