RTEMS 6.1-rc7
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raspberrypi.h
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1
9/*
10 * Copyright (c) 2022 Mohd Noor Aman
11 * Copyright (c) 2024 Ning Yang
12 *
13 * The license and distribution terms for this file may be
14 * found in the file LICENSE in this distribution or at
15 *
16 * http://www.rtems.org/license/LICENSE
17 *
18 */
19
20
21#ifndef LIBBSP_AARCH64_RASPBERRYPI_RASPBERRYPI_4_H
22#define LIBBSP_AARCH64_RASPBERRYPI_RASPBERRYPI_4_H
23
24
25#include <bspopts.h>
26#include <stdint.h>
27#include <bsp/utility.h>
28
29
46#define BCM2711_REG(x) (*(volatile uint64_t *)(x))
47#define BCM2711_BIT(n) (1 << (n))
48#define BCM2835_REG(addr) (*(volatile uint32_t*)(addr))
49
58#define RPI_PERIPHERAL_BASE 0xFE000000
59#define BASE_OFFSET 0xFE000000
60#define RPI_PERIPHERAL_SIZE 0x01800000
61
67#define BUS_TO_PHY(x) ((x) - BASE_OFFSET)
68
77#define BCM2711_CLOCK_FREQ 250000000
78
79#define BCM2711_TIMER_BASE (RPI_PERIPHERAL_BASE + 0xB400)
80
81#define BCM2711_TIMER_LOD (BCM2711_TIMER_BASE + 0x00)
82#define BCM2711_TIMER_VAL (BCM2711_TIMER_BASE + 0x04)
83#define BCM2711_TIMER_CTL (BCM2711_TIMER_BASE + 0x08)
84#define BCM2711_TIMER_CLI (BCM2711_TIMER_BASE + 0x0C)
85#define BCM2711_TIMER_RIS (BCM2711_TIMER_BASE + 0x10)
86#define BCM2711_TIMER_MIS (BCM2711_TIMER_BASE + 0x14)
87#define BCM2711_TIMER_RLD (BCM2711_TIMER_BASE + 0x18)
88#define BCM2711_TIMER_DIV (BCM2711_TIMER_BASE + 0x1C)
89#define BCM2711_TIMER_CNT (BCM2711_TIMER_BASE + 0x20)
90
91#define BCM2711_TIMER_PRESCALE 0xF9
92
101#define BCM2711_PM_PASSWD_MAGIC 0x5a000000
102
103#define BCM2711_PM_BASE (RPI_PERIPHERAL_BASE + 0x100000)
104
105#define BCM2711_PM_GNRIC (BCM2711_PM_BASE + 0x00)
106#define BCM2711_PM_GNRIC_POWUP 0x00000001
107#define BCM2711_PM_GNRIC_POWOK 0x00000002
108#define BCM2711_PM_GNRIC_ISPOW 0x00000004
109#define BCM2711_PM_GNRIC_MEMREP 0x00000008
110#define BCM2711_PM_GNRIC_MRDONE 0x00000010
111#define BCM2711_PM_GNRIC_ISFUNC 0x00000020
112#define BCM2711_PM_GNRIC_RSTN 0x00000fc0
113#define BCM2711_PM_GNRIC_ENAB 0x00001000
114#define BCM2711_PM_GNRIC_CFG 0x007f0000
115
116#define BCM2711_PM_AUDIO (BCM2711_PM_BASE + 0x04)
117#define BCM2711_PM_AUDIO_APSM 0x000fffff
118#define BCM2711_PM_AUDIO_CTRLEN 0x00100000
119#define BCM2711_PM_AUDIO_RSTN 0x00200000
120
121#define BCM2711_PM_STATUS (BCM2711_PM_BASE + 0x18)
122
123#define BCM2711_PM_RSTC (BCM2711_PM_BASE + 0x1c)
124#define BCM2711_PM_RSTC_DRCFG 0x00000003
125#define BCM2711_PM_RSTC_WRCFG 0x00000030
126#define BCM2711_PM_RSTC_WRCFG_FULL 0x00000020
127#define BCM2711_PM_RSTC_WRCFG_CLR 0xffffffcf
128#define BCM2711_PM_RSTC_SRCFG 0x00000300
129#define BCM2711_PM_RSTC_QRCFG 0x00003000
130#define BCM2711_PM_RSTC_FRCFG 0x00030000
131#define BCM2711_PM_RSTC_HRCFG 0x00300000
132#define BCM2711_PM_RSTC_RESET 0x00000102
133
134#define BCM2711_PM_RSTS (BCM2711_PM_BASE + 0x20)
135#define BCM2711_PM_RSTS_HADDRQ 0x00000001
136#define BCM2711_PM_RSTS_HADDRF 0x00000002
137#define BCM2711_PM_RSTS_HADDRH 0x00000004
138#define BCM2711_PM_RSTS_HADWRQ 0x00000010
139#define BCM2711_PM_RSTS_HADWRF 0x0000002
140#define BCM2711_PM_RSTS_HADWRH 0x00000040
141#define BCM2711_PM_RSTS_HADSRQ 0x00000100
142#define BCM2711_PM_RSTS_HADSRF 0x00000200
143#define BCM2711_PM_RSTS_HADSRH 0x00000400
144#define BCM2711_PM_RSTS_HADPOR 0x00001000
145
146#define BCM2711_PM_WDOG (BCM2711_PM_BASE + 0x24)
147#define BCM2711_PM_WDOG_MASK 0x000fffff
148
160#define BCM2711_AUX_BASE (RPI_PERIPHERAL_BASE + 0x215000)
161
162#define AUX_ENABLES (BCM2711_AUX_BASE + 0x04)
163#define AUX_MU_IO_REG (BCM2711_AUX_BASE + 0x40)
164#define AUX_MU_IER_REG (BCM2711_AUX_BASE + 0x44)
165#define AUX_MU_IIR_REG (BCM2711_AUX_BASE + 0x48)
166#define AUX_MU_LCR_REG (BCM2711_AUX_BASE + 0x4C)
167#define AUX_MU_MCR_REG (BCM2711_AUX_BASE + 0x50)
168#define AUX_MU_LSR_REG (BCM2711_AUX_BASE + 0x54)
169#define AUX_MU_MSR_REG (BCM2711_AUX_BASE + 0x58)
170#define AUX_MU_SCRATCH (BCM2711_AUX_BASE + 0x5C)
171#define AUX_MU_CNTL_REG (BCM2711_AUX_BASE + 0x60)
172#define AUX_MU_STAT_REG (BCM2711_AUX_BASE + 0x64)
173#define AUX_MU_BAUD_REG (BCM2711_AUX_BASE + 0x68)
174
182#define BCM2711_PL011_BASE (RPI_PERIPHERAL_BASE + 0x201000)
183#define BCM2711_PL011_SIZE 0xc00
184#define BCM2711_PL011_DEVICE_SIZE 0x200
185
186#define BCM2711_UART0_BASE (BCM2711_PL011_BASE + 0x000)
187#define BCM2711_UART0_SIZE BCM2711_PL011_DEVICE_SIZE
188#define BCM2711_UART2_BASE (BCM2711_PL011_BASE + 0x400)
189#define BCM2711_UART2_SIZE BCM2711_PL011_DEVICE_SIZE
190#define BCM2711_UART3_BASE (BCM2711_PL011_BASE + 0x600)
191#define BCM2711_UART3_SIZE BCM2711_PL011_DEVICE_SIZE
192#define BCM2711_UART4_BASE (BCM2711_PL011_BASE + 0x800)
193#define BCM2711_UART4_SIZE BCM2711_PL011_DEVICE_SIZE
194#define BCM2711_UART5_BASE (BCM2711_PL011_BASE + 0xa00)
195#define BCM2711_UART5_SIZE BCM2711_PL011_DEVICE_SIZE
209#define BCM2711_GPU_TIMER_BASE (RPI_PERIPHERAL_BASE + 0x3000)
210
211#define BCM2711_GPU_TIMER_CS (BCM2711_GPU_TIMER_BASE + 0x00)
212#define BCM2711_GPU_TIMER_CS_M0 0x00000001
213#define BCM2711_GPU_TIMER_CS_M1 0x00000002
214#define BCM2711_GPU_TIMER_CS_M2 0x00000004
215#define BCM2711_GPU_TIMER_CS_M3 0x00000008
216#define BCM2711_GPU_TIMER_CLO (BCM2711_GPU_TIMER_BASE + 0x04)
217#define BCM2711_GPU_TIMER_CHI (BCM2711_GPU_TIMER_BASE + 0x08)
218#define BCM2711_GPU_TIMER_C0 (BCM2711_GPU_TIMER_BASE + 0x0C)
219#define BCM2711_GPU_TIMER_C1 (BCM2711_GPU_TIMER_BASE + 0x10)
220#define BCM2711_GPU_TIMER_C2 (BCM2711_GPU_TIMER_BASE + 0x14)
221#define BCM2711_GPU_TIMER_C3 (BCM2711_GPU_TIMER_BASE + 0x18)
222
226#define BCM2835_GPU_TIMER_CS_M3 BCM2711_GPU_TIMER_CS_M3
227#define BCM2835_GPU_TIMER_C3 BCM2711_GPU_TIMER_C3
228#define BCM2835_GPU_TIMER_CLO BCM2711_GPU_TIMER_CLO
229#define BCM2835_GPU_TIMER_CS BCM2711_GPU_TIMER_CS
238#define BCM2711_GPIO_BASE (RPI_PERIPHERAL_BASE + 0x200000)
239#define BCM2711_GPIO_SIZE 0xf4
240
241#define BCM2711_GPIO_PIN_COUNT 58
242
256#define BCM2711_EMMC_BASE (RPI_PERIPHERAL_BASE + 0x300000)
257
266#define BCM2711_SPI0_BASE (RPI_PERIPHERAL_BASE + 0x204000)
267#define BCM2711_SPI3_BASE (RPI_PERIPHERAL_BASE + 0x204600)
268#define BCM2711_SPI4_BASE (RPI_PERIPHERAL_BASE + 0x204800)
269#define BCM2711_SPI5_BASE (RPI_PERIPHERAL_BASE + 0x204A00)
270#define BCM2711_SPI6_BASE (RPI_PERIPHERAL_BASE + 0x204C00)
271
280#define BCM2711_MBOX_BASE (RPI_PERIPHERAL_BASE+0xB880)
281
282#define BCM2711_MBOX_READ (BCM2711_MBOX_BASE+0x00)
283#define BCM2711_MBOX_PEEK (BCM2711_MBOX_BASE+0x10)
284#define BCM2711_MBOX_SENDER (BCM2711_MBOX_BASE+0x14)
285#define BCM2711_MBOX_STATUS (BCM2711_MBOX_BASE+0x18)
286#define BCM2711_MBOX_WRITE (BCM2711_MBOX_BASE+0x20)
287#define BCM2711_MBOX_CONFIG (BCM2711_MBOX_BASE+0x1C)
288
289#define BCM2711_MBOX_RESPONSE 0x80000000
290#define BCM2711_MBOX_FULL 0x80000000
291#define BCM2711_MBOX_EMPTY 0x40000000
292
301/* Power Manager channel */
302#define BCM2711_MBOX_CHANNEL_PM 0
303/* Framebuffer channel */
304#define BCM2711_MBOX_CHANNEL_FB 1
305 /* Virtual UART channel */
306#define BCM2711_MBOX_CHANNEL_VUART 2
307 /* VCHIQ channel */
308#define BCM2711_MBOX_CHANNEL_VCHIQ 3
309 /* LEDs channel */
310#define BCM2711_MBOX_CHANNEL_LED 4
311 /* Button channel */
312#define BCM2711_MBOX_CHANNEL_BUTTON 5
313 /* Touch screen channel */
314#define BCM2711_MBOX_CHANNEL_TOUCHS 6
315
316#define BCM2711_MBOX_CHANNEL_COUNT 7
317/* Property tags (ARM <-> VC) channel */
318#define BCM2711_MBOX_CHANNEL_PROP_AVC 8
319 /* Property tags (VC <-> ARM) channel */
320#define BCM2711_MBOX_CHANNEL_PROP_VCA 9
321
332/* Timers interrupt control registers */
333#define BCM2711_CORE0_TIMER_IRQ_CTRL_BASE 0xFF800040
334#define BCM2711_CORE1_TIMER_IRQ_CTRL_BASE 0xFF800044
335#define BCM2711_CORE2_TIMER_IRQ_CTRL_BASE 0xFF800048
336#define BCM2711_CORE3_TIMER_IRQ_CTRL_BASE 0xFF80004C
337
338#define BCM2711_CORE_TIMER_IRQ_CTRL(cpuidx) \
339 (BCM2711_CORE0_TIMER_IRQ_CTRL_BASE + 0x4 * (cpuidx))
340
341
348#define BCM2711_LOCAL_REGS_BASE 0x4C0000000
349#define BCM2711_LOCAL_REGS_SIZE 0x100
350
351#define BCM2711_LOCAL_ARM_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x00)
352#define BCM2711_LOCAL_CORE_IRQ_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x0c)
353#define BCM2711_LOCAL_PMU_CONTROL_SET (BCM2711_LOCAL_REGS_BASE + 0x10)
354#define BCM2711_LOCAL_PMU_CONTROL_CLR (BCM2711_LOCAL_REGS_BASE + 0x14)
355#define BCM2711_LOCAL_PERI_IRQ_ROUTE0 (BCM2711_LOCAL_REGS_BASE + 0x24)
356#define BCM2711_LOCAL_AXI_QUIET_TIME (BCM2711_LOCAL_REGS_BASE + 0x30)
357#define BCM2711_LOCAL_LOCAL_TIMER_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x34)
358#define BCM2711_LOCAL_LOCAL_TIMER_IRQ (BCM2711_LOCAL_REGS_BASE + 0x38)
359
360#define BCM2711_LOCAL_TIMER_CNTRL0 (BCM2711_LOCAL_REGS_BASE + 0x40)
361#define BCM2711_LOCAL_TIMER_CNTRL1 (BCM2711_LOCAL_REGS_BASE + 0x44)
362#define BCM2711_LOCAL_TIMER_CNTRL2 (BCM2711_LOCAL_REGS_BASE + 0x48)
363#define BCM2711_LOCAL_TIMER_CNTRL3 (BCM2711_LOCAL_REGS_BASE + 0x4c)
364
365#define BCM2711_LOCAL_MAILBOX_CNTRL0 (BCM2711_LOCAL_REGS_BASE + 0x50)
366#define BCM2711_LOCAL_MAILBOX_CNTRL1 (BCM2711_LOCAL_REGS_BASE + 0x54)
367#define BCM2711_LOCAL_MAILBOX_CNTRL2 (BCM2711_LOCAL_REGS_BASE + 0x58)
368#define BCM2711_LOCAL_MAILBOX_CNTRL3 (BCM2711_LOCAL_REGS_BASE + 0x5c)
369
370#define BCM2711_LOCAL_IRQ_SOURCE0 (BCM2711_LOCAL_REGS_BASE + 0x60)
371#define BCM2711_LOCAL_IRQ_SOURCE1 (BCM2711_LOCAL_REGS_BASE + 0x64)
372#define BCM2711_LOCAL_IRQ_SOURCE2 (BCM2711_LOCAL_REGS_BASE + 0x68)
373#define BCM2711_LOCAL_IRQ_SOURCE3 (BCM2711_LOCAL_REGS_BASE + 0x6c)
374
375#define BCM2711_LOCAL_FIQ_SOURCE0 (BCM2711_LOCAL_REGS_BASE + 0x70)
376#define BCM2711_LOCAL_FIQ_SOURCE1 (BCM2711_LOCAL_REGS_BASE + 0x74)
377#define BCM2711_LOCAL_FIQ_SOURCE2 (BCM2711_LOCAL_REGS_BASE + 0x78)
378#define BCM2711_LOCAL_FIQ_SOURCE3 (BCM2711_LOCAL_REGS_BASE + 0x7c)
379
388#define BCM2711_MAILBOX_00_WRITE_SET_BASE 0x4C000080
389#define BCM2711_MAILBOX_01_WRITE_SET_BASE 0x4C000084
390#define BCM2711_MAILBOX_02_WRITE_SET_BASE 0x4C000088
391#define BCM2711_MAILBOX_03_WRITE_SET_BASE 0x4C00008C
392#define BCM2711_MAILBOX_04_WRITE_SET_BASE 0x4C000090
393#define BCM2711_MAILBOX_05_WRITE_SET_BASE 0x4C000094
394#define BCM2711_MAILBOX_06_WRITE_SET_BASE 0x4C000098
395#define BCM2711_MAILBOX_07_WRITE_SET_BASE 0x4C00009C
396#define BCM2711_MAILBOX_08_WRITE_SET_BASE 0x4C0000A0
397#define BCM2711_MAILBOX_09_WRITE_SET_BASE 0x4C0000A4
398#define BCM2711_MAILBOX_10_WRITE_SET_BASE 0x4C0000A8
399#define BCM2711_MAILBOX_11_WRITE_SET_BASE 0x4C0000AC
400#define BCM2711_MAILBOX_12_WRITE_SET_BASE 0x4C0000B0
401#define BCM2711_MAILBOX_13_WRITE_SET_BASE 0x4C0000B4
402#define BCM2711_MAILBOX_14_WRITE_SET_BASE 0x4C0000B8
403#define BCM2711_MAILBOX_15_WRITE_SET_BASE 0x4C0000BC
404
405#define BCM2711_MAILBOX_00_READ_CLEAR_BASE 0x4C0000C0
406#define BCM2711_MAILBOX_01_READ_CLEAR_BASE 0x4C0000C4
407#define BCM2711_MAILBOX_02_READ_CLEAR_BASE 0x4C0000C8
408#define BCM2711_MAILBOX_03_READ_CLEAR_BASE 0x4C0000CC
409#define BCM2711_MAILBOX_04_READ_CLEAR_BASE 0x4C0000D0
410#define BCM2711_MAILBOX_05_READ_CLEAR_BASE 0x4C0000D4
411#define BCM2711_MAILBOX_06_READ_CLEAR_BASE 0x4C0000D8
412#define BCM2711_MAILBOX_07_READ_CLEAR_BASE 0x4C0000DC
413#define BCM2711_MAILBOX_08_READ_CLEAR_BASE 0x4C0000E0
414#define BCM2711_MAILBOX_09_READ_CLEAR_BASE 0x4C0000E4
415#define BCM2711_MAILBOX_10_READ_CLEAR_BASE 0x4C0000E8
416#define BCM2711_MAILBOX_11_READ_CLEAR_BASE 0x4C0000EC
417#define BCM2711_MAILBOX_12_READ_CLEAR_BASE 0x4C0000F0
418#define BCM2711_MAILBOX_13_READ_CLEAR_BASE 0x4C0000F4
419#define BCM2711_MAILBOX_14_READ_CLEAR_BASE 0x4C0000F8
420#define BCM2711_MAILBOX_15_READ_CLEAR_BASE 0x4C0000FC
421
422
429#define BCM2711_ARMC_REGS_BASE (RPI_PERIPHERAL_BASE + 0xB200)
430#define BCM2711_ARMC_REGS_SIZE 0x200
431
432#define BCM2711_ARMC_IRQ0_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x00)
433#define BCM2711_ARMC_IRQ0_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x04)
434#define BCM2711_ARMC_IRQ0_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x08)
435#define BCM2711_ARMC_IRQ0_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x10)
436#define BCM2711_ARMC_IRQ0_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x14)
437#define BCM2711_ARMC_IRQ0_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x18)
438#define BCM2711_ARMC_IRQ0_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x20)
439#define BCM2711_ARMC_IRQ0_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x24)
440#define BCM2711_ARMC_IRQ0_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x28)
441
442#define BCM2711_ARMC_IRQ_STATUS0 (BCM2711_ARMC_REGS_BASE + 0x30)
443#define BCM2711_ARMC_IRQ_STATUS1 (BCM2711_ARMC_REGS_BASE + 0x34)
444#define BCM2711_ARMC_IRQ_STATUS2 (BCM2711_ARMC_REGS_BASE + 0x38)
445
446#define BCM2711_ARMC_IRQ1_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x40)
447#define BCM2711_ARMC_IRQ1_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x44)
448#define BCM2711_ARMC_IRQ1_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x48)
449#define BCM2711_ARMC_IRQ1_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x50)
450#define BCM2711_ARMC_IRQ1_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x54)
451#define BCM2711_ARMC_IRQ1_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x58)
452#define BCM2711_ARMC_IRQ1_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x60)
453#define BCM2711_ARMC_IRQ1_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x64)
454#define BCM2711_ARMC_IRQ1_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x68)
455
456#define BCM2711_ARMC_IRQ2_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x80)
457#define BCM2711_ARMC_IRQ2_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x84)
458#define BCM2711_ARMC_IRQ2_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x88)
459#define BCM2711_ARMC_IRQ2_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x90)
460#define BCM2711_ARMC_IRQ2_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x94)
461#define BCM2711_ARMC_IRQ2_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x98)
462#define BCM2711_ARMC_IRQ2_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0xA0)
463#define BCM2711_ARMC_IRQ2_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0xA4)
464#define BCM2711_ARMC_IRQ2_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0xA8)
465
466#define BCM2711_ARMC_IRQ3_PENDING0 (BCM2711_ARMC_REGS_BASE + 0xC0)
467#define BCM2711_ARMC_IRQ3_PENDING1 (BCM2711_ARMC_REGS_BASE + 0xC4)
468#define BCM2711_ARMC_IRQ3_PENDING2 (BCM2711_ARMC_REGS_BASE + 0xC8)
469#define BCM2711_ARMC_IRQ3_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0xD0)
470#define BCM2711_ARMC_IRQ3_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0xD4)
471#define BCM2711_ARMC_IRQ3_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0xD8)
472#define BCM2711_ARMC_IRQ3_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0xE0)
473#define BCM2711_ARMC_IRQ3_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0xE4)
474#define BCM2711_ARMC_IRQ3_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0xE8)
475
476
477
478#define BCM2711_ARMC_FIQ0_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x100)
479#define BCM2711_ARMC_FIQ0_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x104)
480#define BCM2711_ARMC_FIQ0_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x108)
481#define BCM2711_ARMC_FIQ0_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x110)
482#define BCM2711_ARMC_FIQ0_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x114)
483#define BCM2711_ARMC_FIQ0_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x118)
484#define BCM2711_ARMC_FIQ0_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x120)
485#define BCM2711_ARMC_FIQ0_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x124)
486#define BCM2711_ARMC_FIQ0_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x128)
487
488#define BCM2711_ARMC_FIQ1_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x140)
489#define BCM2711_ARMC_FIQ1_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x144)
490#define BCM2711_ARMC_FIQ1_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x148)
491#define BCM2711_ARMC_FIQ1_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x150)
492#define BCM2711_ARMC_FIQ1_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x154)
493#define BCM2711_ARMC_FIQ1_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x158)
494#define BCM2711_ARMC_FIQ1_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x160)
495#define BCM2711_ARMC_FIQ1_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x164)
496#define BCM2711_ARMC_FIQ1_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x168)
497
498#define BCM2711_ARMC_FIQ2_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x180)
499#define BCM2711_ARMC_FIQ2_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x184)
500#define BCM2711_ARMC_FIQ2_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x188)
501#define BCM2711_ARMC_FIQ2_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x190)
502#define BCM2711_ARMC_FIQ2_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x194)
503#define BCM2711_ARMC_FIQ2_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x198)
504#define BCM2711_ARMC_FIQ2_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1A0)
505#define BCM2711_ARMC_FIQ2_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1A4)
506#define BCM2711_ARMC_FIQ2_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1A8)
507
508#define BCM2711_ARMC_FIQ3_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x1C0)
509#define BCM2711_ARMC_FIQ3_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x1C4)
510#define BCM2711_ARMC_FIQ3_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x1C8)
511#define BCM2711_ARMC_FIQ3_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1D0)
512#define BCM2711_ARMC_FIQ3_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1D4)
513#define BCM2711_ARMC_FIQ3_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1D8)
514#define BCM2711_ARMC_FIQ3_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1E0)
515#define BCM2711_ARMC_FIQ3_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1E4)
516#define BCM2711_ARMC_FIQ3_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1E8)
517
518#define BCM2711_ARMC_SWIRQ_SET (BCM2711_ARMC_REGS_BASE + 0x1F0)
519#define BCM2711_ARMC_SWIRQ_CLEAR (BCM2711_ARMC_REGS_BASE + 0x1F4)
520
521
522
523
524
527#endif /* LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H */
This header file provides utility macros for BSPs.