56#ifndef _RTEMS_SCORE_CPU_H
57#define _RTEMS_SCORE_CPU_H
60#if defined(RTEMS_PARAVIRT)
61#include <rtems/score/paravirt.h>
84#define CPU_STACK_GROWS_UP FALSE
86#define CPU_CACHE_LINE_BYTES PPC_STRUCTURE_ALIGNMENT
88#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
106#if ( PPC_HAS_FPU == 1 )
107#define CPU_HARDWARE_FP TRUE
108#define CPU_SOFTWARE_FP FALSE
110#define CPU_HARDWARE_FP FALSE
111#define CPU_SOFTWARE_FP FALSE
127#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP
141#define CPU_IDLE_TASK_IS_FP FALSE
143#define CPU_MAXIMUM_PROCESSORS 32
185 #define PPC_GPR_TYPE uintptr_t
186 #if defined(__powerpc64__)
187 #define PPC_GPR_SIZE 8
188 #define PPC_GPR_LOAD ld
189 #define PPC_GPR_STORE std
191 #define PPC_GPR_SIZE 4
192 #define PPC_GPR_LOAD lwz
193 #define PPC_GPR_STORE stw
196 #define PPC_GPR_TYPE uint64_t
197 #define PPC_GPR_SIZE 8
198 #define PPC_GPR_LOAD evldd
199 #define PPC_GPR_STORE evstdd
202#if defined(__powerpc64__)
203 #define PPC_REG_SIZE 8
204 #define PPC_REG_LOAD ld
205 #define PPC_REG_STORE std
206 #define PPC_REG_STORE_UPDATE stdu
207 #define PPC_REG_CMP cmpd
209 #define PPC_REG_SIZE 4
210 #define PPC_REG_LOAD lwz
211 #define PPC_REG_STORE stw
212 #define PPC_REG_STORE_UPDATE stwu
213 #define PPC_REG_CMP cmpw
246 uint32_t isr_dispatch_disable;
247 uint32_t reserved_for_alignment;
248 #if defined(PPC_MULTILIB_ALTIVEC)
249 #if !defined(__powerpc64__)
250 uint32_t reserved_for_alignment_2[4];
253 uint32_t reserved_for_alignment_3[2];
268 #elif defined(__ALTIVEC__)
278 uint8_t altivec[16*12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE];
280 #if defined(PPC_MULTILIB_FPU)
306 #if defined(RTEMS_SMP)
307 volatile uint32_t is_executing;
313 PPC_DEFAULT_CACHE_LINE_SIZE
315 + (
sizeof(
ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE == 0
317 : PPC_DEFAULT_CACHE_LINE_SIZE
318 -
sizeof(
ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE)
324 uintptr_t clsz = PPC_DEFAULT_CACHE_LINE_SIZE;
325 uintptr_t mask = clsz - 1;
326 uintptr_t addr = (uintptr_t)
context;
331#define _CPU_Context_Get_SP( _context ) \
332 ppc_get_context(_context)->gpr1
335 static inline bool _CPU_Context_Get_is_executing(
339 return ppc_get_context(
context)->is_executing;
342 static inline void _CPU_Context_Set_is_executing(
347 ppc_get_context(
context)->is_executing = is_executing;
352#define PPC_CONTEXT_OFFSET_MSR (PPC_DEFAULT_CACHE_LINE_SIZE)
353#define PPC_CONTEXT_OFFSET_CR (PPC_DEFAULT_CACHE_LINE_SIZE + 4)
354#define PPC_CONTEXT_OFFSET_GPR1 (PPC_DEFAULT_CACHE_LINE_SIZE + 8)
355#define PPC_CONTEXT_OFFSET_LR (PPC_DEFAULT_CACHE_LINE_SIZE + PPC_REG_SIZE + 8)
357#define PPC_CONTEXT_GPR_OFFSET( gpr ) \
358 (((gpr) - 14) * PPC_GPR_SIZE + \
359 PPC_DEFAULT_CACHE_LINE_SIZE + 8 + 2 * PPC_REG_SIZE)
361#define PPC_CONTEXT_OFFSET_GPR14 PPC_CONTEXT_GPR_OFFSET( 14 )
362#define PPC_CONTEXT_OFFSET_GPR15 PPC_CONTEXT_GPR_OFFSET( 15 )
363#define PPC_CONTEXT_OFFSET_GPR16 PPC_CONTEXT_GPR_OFFSET( 16 )
364#define PPC_CONTEXT_OFFSET_GPR17 PPC_CONTEXT_GPR_OFFSET( 17 )
365#define PPC_CONTEXT_OFFSET_GPR18 PPC_CONTEXT_GPR_OFFSET( 18 )
366#define PPC_CONTEXT_OFFSET_GPR19 PPC_CONTEXT_GPR_OFFSET( 19 )
367#define PPC_CONTEXT_OFFSET_GPR20 PPC_CONTEXT_GPR_OFFSET( 20 )
368#define PPC_CONTEXT_OFFSET_GPR21 PPC_CONTEXT_GPR_OFFSET( 21 )
369#define PPC_CONTEXT_OFFSET_GPR22 PPC_CONTEXT_GPR_OFFSET( 22 )
370#define PPC_CONTEXT_OFFSET_GPR23 PPC_CONTEXT_GPR_OFFSET( 23 )
371#define PPC_CONTEXT_OFFSET_GPR24 PPC_CONTEXT_GPR_OFFSET( 24 )
372#define PPC_CONTEXT_OFFSET_GPR25 PPC_CONTEXT_GPR_OFFSET( 25 )
373#define PPC_CONTEXT_OFFSET_GPR26 PPC_CONTEXT_GPR_OFFSET( 26 )
374#define PPC_CONTEXT_OFFSET_GPR27 PPC_CONTEXT_GPR_OFFSET( 27 )
375#define PPC_CONTEXT_OFFSET_GPR28 PPC_CONTEXT_GPR_OFFSET( 28 )
376#define PPC_CONTEXT_OFFSET_GPR29 PPC_CONTEXT_GPR_OFFSET( 29 )
377#define PPC_CONTEXT_OFFSET_GPR30 PPC_CONTEXT_GPR_OFFSET( 30 )
378#define PPC_CONTEXT_OFFSET_GPR31 PPC_CONTEXT_GPR_OFFSET( 31 )
379#define PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE PPC_CONTEXT_GPR_OFFSET( 32 )
381#ifdef PPC_MULTILIB_ALTIVEC
383 #define PPC_CONTEXT_OFFSET_VRSAVE \
384 ( PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8 )
386 #define PPC_CONTEXT_OFFSET_VRSAVE \
387 ( PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 24 )
389 #define PPC_CONTEXT_OFFSET_VSCR ( PPC_CONTEXT_OFFSET_VRSAVE + 12 )
390 #define PPC_CONTEXT_OFFSET_V( v ) \
391 ( ( ( v ) - 20 ) * 16 + PPC_CONTEXT_OFFSET_VRSAVE + 16)
392 #define PPC_CONTEXT_OFFSET_V20 PPC_CONTEXT_OFFSET_V( 20 )
393 #define PPC_CONTEXT_OFFSET_V21 PPC_CONTEXT_OFFSET_V( 21 )
394 #define PPC_CONTEXT_OFFSET_V22 PPC_CONTEXT_OFFSET_V( 22 )
395 #define PPC_CONTEXT_OFFSET_V23 PPC_CONTEXT_OFFSET_V( 23 )
396 #define PPC_CONTEXT_OFFSET_V24 PPC_CONTEXT_OFFSET_V( 24 )
397 #define PPC_CONTEXT_OFFSET_V25 PPC_CONTEXT_OFFSET_V( 25 )
398 #define PPC_CONTEXT_OFFSET_V26 PPC_CONTEXT_OFFSET_V( 26 )
399 #define PPC_CONTEXT_OFFSET_V27 PPC_CONTEXT_OFFSET_V( 27 )
400 #define PPC_CONTEXT_OFFSET_V28 PPC_CONTEXT_OFFSET_V( 28 )
401 #define PPC_CONTEXT_OFFSET_V29 PPC_CONTEXT_OFFSET_V( 29 )
402 #define PPC_CONTEXT_OFFSET_V30 PPC_CONTEXT_OFFSET_V( 30 )
403 #define PPC_CONTEXT_OFFSET_V31 PPC_CONTEXT_OFFSET_V( 31 )
404 #define PPC_CONTEXT_OFFSET_F( f ) \
405 ( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_V( 32 ) )
407 #define PPC_CONTEXT_OFFSET_F( f ) \
408 ( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8 )
411#ifdef PPC_MULTILIB_FPU
412 #define PPC_CONTEXT_OFFSET_F14 PPC_CONTEXT_OFFSET_F( 14 )
413 #define PPC_CONTEXT_OFFSET_F15 PPC_CONTEXT_OFFSET_F( 15 )
414 #define PPC_CONTEXT_OFFSET_F16 PPC_CONTEXT_OFFSET_F( 16 )
415 #define PPC_CONTEXT_OFFSET_F17 PPC_CONTEXT_OFFSET_F( 17 )
416 #define PPC_CONTEXT_OFFSET_F18 PPC_CONTEXT_OFFSET_F( 18 )
417 #define PPC_CONTEXT_OFFSET_F19 PPC_CONTEXT_OFFSET_F( 19 )
418 #define PPC_CONTEXT_OFFSET_F20 PPC_CONTEXT_OFFSET_F( 20 )
419 #define PPC_CONTEXT_OFFSET_F21 PPC_CONTEXT_OFFSET_F( 21 )
420 #define PPC_CONTEXT_OFFSET_F22 PPC_CONTEXT_OFFSET_F( 22 )
421 #define PPC_CONTEXT_OFFSET_F23 PPC_CONTEXT_OFFSET_F( 23 )
422 #define PPC_CONTEXT_OFFSET_F24 PPC_CONTEXT_OFFSET_F( 24 )
423 #define PPC_CONTEXT_OFFSET_F25 PPC_CONTEXT_OFFSET_F( 25 )
424 #define PPC_CONTEXT_OFFSET_F26 PPC_CONTEXT_OFFSET_F( 26 )
425 #define PPC_CONTEXT_OFFSET_F27 PPC_CONTEXT_OFFSET_F( 27 )
426 #define PPC_CONTEXT_OFFSET_F28 PPC_CONTEXT_OFFSET_F( 28 )
427 #define PPC_CONTEXT_OFFSET_F29 PPC_CONTEXT_OFFSET_F( 29 )
428 #define PPC_CONTEXT_OFFSET_F30 PPC_CONTEXT_OFFSET_F( 30 )
429 #define PPC_CONTEXT_OFFSET_F31 PPC_CONTEXT_OFFSET_F( 31 )
432#if defined(PPC_MULTILIB_FPU)
433 #define PPC_CONTEXT_VOLATILE_SIZE PPC_CONTEXT_OFFSET_F( 32 )
434#elif defined(PPC_MULTILIB_ALTIVEC)
435 #define PPC_CONTEXT_VOLATILE_SIZE PPC_CONTEXT_OFFSET_V( 33 )
436#elif defined(__ALTIVEC__)
437 #define PPC_CONTEXT_VOLATILE_SIZE \
438 (PPC_CONTEXT_GPR_OFFSET( 32 ) + 8 \
439 + 16 * 12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE)
441 #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_GPR_OFFSET( 32 ) + 8)
444#define PPC_CONTEXT_OFFSET_TP PPC_CONTEXT_VOLATILE_SIZE
447 #define PPC_CONTEXT_OFFSET_IS_EXECUTING \
448 (PPC_CONTEXT_OFFSET_TP + PPC_REG_SIZE)
452#if (PPC_HAS_FPU == 1)
460#if (PPC_HAS_DOUBLE == 1)
483#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
491#define CPU_ISR_PASSES_FRAME_POINTER FALSE
529#define CPU_USE_DEFERRED_FP_SWITCH FALSE
531#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
555#define CPU_MODES_INTERRUPT_MASK 0x00000001
564#if (PPC_HAS_FPU == 1)
565#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
574#define CPU_STACK_CHECK_PATTERN_INITIALIZER \
575 { 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
576 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
577 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
578 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
579 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
580 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
581 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
582 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06 }
590#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
599#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
612static inline bool _CPU_ISR_Is_enabled( uint32_t level )
614 return ( level & MSR_EE ) != 0;
617#if !defined(PPC_DISABLE_INLINE_ISR_DISABLE_ENABLE)
623 if (msr & MSR_EE)
return 0;
631 if (!(level & CPU_MODES_INTERRUPT_MASK)) {
632 msr |= ppc_interrupt_get_disable_mask();
635 msr &= ~ppc_interrupt_get_disable_mask();
641uint32_t ppc_get_interrupt_level(
void );
642void ppc_set_interrupt_level( uint32_t level );
643#define _CPU_ISR_Get_level( _new_level ) ppc_get_interrupt_level()
644#define _CPU_ISR_Set_level( _new_level ) ppc_set_interrupt_level(_new_level)
654#define CPU_STACK_MINIMUM_SIZE (1024*8)
656#if defined(__powerpc64__)
657#define CPU_SIZEOF_POINTER 8
659#define CPU_SIZEOF_POINTER 4
667#define CPU_ALIGNMENT (PPC_ALIGNMENT)
681#define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT)
683#define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT)
685#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
708static inline uint32_t CPU_swap_u32(
714 __asm__
volatile(
"rlwimi %0,%1,8,24,31;"
715 "rlwimi %0,%1,24,16,23;"
716 "rlwimi %0,%1,8,8,15;"
717 "rlwimi %0,%1,24,0,7;" :
718 "=&r" ((swapped)) :
"r" ((value)));
723#define CPU_swap_u16( value ) \
724 (((value&0xff) << 8) | ((value >> 8)&0xff))
726typedef uint32_t CPU_Counter_ticks;
732 CPU_Counter_ticks value;
734#if defined(__PPC_CPU_E6500__)
736 __asm__
volatile(
"mfspr %0, 526" :
"=r" (value) );
738 __asm__
volatile(
"mftb %0" :
"=r" (value) );
740 __asm__
volatile(
"mfspr %0, 268" :
"=r" (value) );
768void _CPU_Context_Initialize(
788#define _CPU_Context_Restart_self( _the_context ) \
789 _CPU_Context_restore( (_the_context) );
803#define _CPU_Context_Initialize_fp( _destination ) \
804 memset( *(_destination), 0, sizeof( **(_destination) ) )
811#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
815#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
872#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
874 __asm__ volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
876 (_output) = (_output) - 16; \
887#define _CPU_Priority_Mask( _bit_number ) \
888 ( 0x8000u >> (_bit_number) )
897#define _CPU_Priority_bits_index( _priority ) \
944#if (PPC_HAS_FPU == 1)
967 uint32_t _CPU_SMP_Initialize(
void );
969 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
971 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
973 void _CPU_SMP_Prepare_start_multitasking(
void );
975 static inline uint32_t _CPU_SMP_Get_current_processor(
void )
988 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
994 uint32_t _EXC_number;
995 uint32_t RESERVED_FOR_ALIGNMENT_0;
1000 uintptr_t RESERVED_FOR_ALIGNMENT_1;
1002 uint32_t EXC_SPEFSCR;
1037 uintptr_t RESERVED_FOR_ALIGNMENT_2;
1038 #ifdef PPC_MULTILIB_ALTIVEC
1040 uint32_t RESERVED_FOR_ALIGNMENT_3[3];
1043 uint32_t RESERVED_FOR_ALIGNMENT_4[3];
1079 #ifdef PPC_MULTILIB_FPU
1113 uint64_t RESERVED_FOR_ALIGNMENT_5;
1125_CPU_Initialize_altivec(
void);
1134_CPU_Context_switch_altivec(
1146_CPU_Context_restore_altivec(
1157_CPU_Context_initialize_altivec(
1161void _CPU_Fatal_error(
This header file provides basic definitions used by the API and the implementation.
IBM/Motorola PowerPC Definitions.
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
#define _CPU_ISR_Set_level(_new_level)
Definition: cpu.h:378
rtems_termios_device_context * context
Definition: console-config.c:62
#define _CPU_Context_restore_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:901
#define _CPU_Context_save_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:895
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
SPARC basic context.
Definition: cpu.h:213
Thread register context.
Definition: cpu.h:173