37#ifndef LIBBSP_MIPS_AU1X00_IRQ_H
38#define LIBBSP_MIPS_AU1X00_IRQ_H
58#define AU1X00_IRQ_SW0 (MIPS_INTERRUPT_BASE + 0)
59#define AU1X00_IRQ_SW1 (MIPS_INTERRUPT_BASE + 1)
60#define AU1X00_IRQ_IC0_REQ0 (MIPS_INTERRUPT_BASE + 2)
61#define AU1X00_IRQ_IC0_REQ1 (MIPS_INTERRUPT_BASE + 3)
62#define AU1X00_IRQ_IC1_REQ0 (MIPS_INTERRUPT_BASE + 4)
63#define AU1X00_IRQ_IC1_REQ1 (MIPS_INTERRUPT_BASE + 5)
64#define AU1X00_IRQ_PERF (MIPS_INTERRUPT_BASE + 6)
65#define AU1X00_IRQ_CNT (MIPS_INTERRUPT_BASE + 7)
67#define AU1X00_IRQ_IC0_BASE (MIPS_INTERRUPT_BASE + 8)
68#define AU1X00_IRQ_UART0 (MIPS_INTERRUPT_BASE + 8)
69#define AU1X00_IRQ_INTA (MIPS_INTERRUPT_BASE + 9)
70#define AU1X00_IRQ_INTB (MIPS_INTERRUPT_BASE + 10)
71#define AU1X00_IRQ_UART3 (MIPS_INTERRUPT_BASE + 11)
72#define AU1X00_IRQ_INTC (MIPS_INTERRUPT_BASE + 12)
73#define AU1X00_IRQ_INTD (MIPS_INTERRUPT_BASE + 13)
74#define AU1X00_IRQ_DMA0 (MIPS_INTERRUPT_BASE + 14)
75#define AU1X00_IRQ_DMA1 (MIPS_INTERRUPT_BASE + 15)
76#define AU1X00_IRQ_DMA2 (MIPS_INTERRUPT_BASE + 16)
77#define AU1X00_IRQ_DMA3 (MIPS_INTERRUPT_BASE + 17)
78#define AU1X00_IRQ_DMA4 (MIPS_INTERRUPT_BASE + 18)
79#define AU1X00_IRQ_DMA5 (MIPS_INTERRUPT_BASE + 19)
80#define AU1X00_IRQ_DMA6 (MIPS_INTERRUPT_BASE + 20)
81#define AU1X00_IRQ_DMA7 (MIPS_INTERRUPT_BASE + 21)
82#define AU1X00_IRQ_TOY_TICK (MIPS_INTERRUPT_BASE + 22)
83#define AU1X00_IRQ_TOY_MATCH0 (MIPS_INTERRUPT_BASE + 23)
84#define AU1X00_IRQ_TOY_MATCH1 (MIPS_INTERRUPT_BASE + 24)
85#define AU1X00_IRQ_TOY_MATCH2 (MIPS_INTERRUPT_BASE + 25)
86#define AU1X00_IRQ_RTC_TICK (MIPS_INTERRUPT_BASE + 26)
87#define AU1X00_IRQ_RTC_MATCH0 (MIPS_INTERRUPT_BASE + 27)
88#define AU1X00_IRQ_RTC_MATCH1 (MIPS_INTERRUPT_BASE + 28)
89#define AU1X00_IRQ_RTC_MATCH2 (MIPS_INTERRUPT_BASE + 29)
90#define AU1X00_IRQ_PCI_ERR (MIPS_INTERRUPT_BASE + 30)
91#define AU1X00_IRQ_RSV0 (MIPS_INTERRUPT_BASE + 31)
92#define AU1X00_IRQ_USB_DEV (MIPS_INTERRUPT_BASE + 32)
93#define AU1X00_IRQ_USB_SUSPEND (MIPS_INTERRUPT_BASE + 33)
94#define AU1X00_IRQ_USB_HOST (MIPS_INTERRUPT_BASE + 34)
95#define AU1X00_IRQ_AC97_ACSYNC (MIPS_INTERRUPT_BASE + 35)
96#define AU1X00_IRQ_MAC0 (MIPS_INTERRUPT_BASE + 36)
97#define AU1X00_IRQ_MAC1 (MIPS_INTERRUPT_BASE + 37)
98#define AU1X00_IRQ_RSV1 (MIPS_INTERRUPT_BASE + 38)
99#define AU1X00_IRQ_AC97_CMD (MIPS_INTERRUPT_BASE + 39)
101#define AU1X00_IRQ_IC1_BASE (MIPS_INTERRUPT_BASE + 40)
102#define AU1X00_IRQ_GPIO0 (MIPS_INTERRUPT_BASE + 40)
103#define AU1X00_IRQ_GPIO1 (MIPS_INTERRUPT_BASE + 41)
104#define AU1X00_IRQ_GPIO2 (MIPS_INTERRUPT_BASE + 42)
105#define AU1X00_IRQ_GPIO3 (MIPS_INTERRUPT_BASE + 43)
106#define AU1X00_IRQ_GPIO4 (MIPS_INTERRUPT_BASE + 44)
107#define AU1X00_IRQ_GPIO5 (MIPS_INTERRUPT_BASE + 45)
108#define AU1X00_IRQ_GPIO6 (MIPS_INTERRUPT_BASE + 46)
109#define AU1X00_IRQ_GPIO7 (MIPS_INTERRUPT_BASE + 47)
110#define AU1X00_IRQ_GPIO8 (MIPS_INTERRUPT_BASE + 48)
111#define AU1X00_IRQ_GPIO9 (MIPS_INTERRUPT_BASE + 49)
112#define AU1X00_IRQ_GPIO10 (MIPS_INTERRUPT_BASE + 50)
113#define AU1X00_IRQ_GPIO11 (MIPS_INTERRUPT_BASE + 51)
114#define AU1X00_IRQ_GPIO12 (MIPS_INTERRUPT_BASE + 52)
115#define AU1X00_IRQ_GPIO13 (MIPS_INTERRUPT_BASE + 53)
116#define AU1X00_IRQ_GPIO14 (MIPS_INTERRUPT_BASE + 54)
117#define AU1X00_IRQ_GPIO15 (MIPS_INTERRUPT_BASE + 55)
118#define AU1X00_IRQ_GPIO200 (MIPS_INTERRUPT_BASE + 56)
119#define AU1X00_IRQ_GPIO201 (MIPS_INTERRUPT_BASE + 57)
120#define AU1X00_IRQ_GPIO202 (MIPS_INTERRUPT_BASE + 58)
121#define AU1X00_IRQ_GPIO203 (MIPS_INTERRUPT_BASE + 59)
122#define AU1X00_IRQ_GPIO20 (MIPS_INTERRUPT_BASE + 60)
123#define AU1X00_IRQ_GPIO204 (MIPS_INTERRUPT_BASE + 61)
124#define AU1X00_IRQ_GPIO205 (MIPS_INTERRUPT_BASE + 62)
125#define AU1X00_IRQ_GPIO23 (MIPS_INTERRUPT_BASE + 63)
126#define AU1X00_IRQ_GPIO24 (MIPS_INTERRUPT_BASE + 64)
127#define AU1X00_IRQ_GPIO25 (MIPS_INTERRUPT_BASE + 65)
128#define AU1X00_IRQ_GPIO26 (MIPS_INTERRUPT_BASE + 66)
129#define AU1X00_IRQ_GPIO27 (MIPS_INTERRUPT_BASE + 67)
130#define AU1X00_IRQ_GPIO28 (MIPS_INTERRUPT_BASE + 68)
131#define AU1X00_IRQ_GPIO206 (MIPS_INTERRUPT_BASE + 69)
132#define AU1X00_IRQ_GPIO207 (MIPS_INTERRUPT_BASE + 70)
133#define AU1X00_IRQ_GPIO208_215 (MIPS_INTERRUPT_BASE + 71)
135#define AU1X00_MAXIMUM_VECTORS (MIPS_INTERRUPT_BASE + 72)
137#define BSP_INTERRUPT_VECTOR_COUNT (AU1X00_MAXIMUM_VECTORS + 1)
This header file is provided for backward compatiblility.
Information to build RTEMS for a "no cpu" while in protected mode.
This header file defines the RTEMS Classic API.