RTEMS 6.1-rc7
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irq.h
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/*
4 * Copyright (c) 2024 Kevin Kirspel
5 *
6 * Copyright (c) 2015 University of York.
7 * Hesham Almatary <hesham@alumni.york.ac.uk>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31#ifndef LIBBSP_NIOSV_IRQ_H
32#define LIBBSP_NIOSV_IRQ_H
33
34#ifndef ASM
35
36#include <bsp.h>
37#include <rtems/irq.h>
38#include <rtems/irq-extension.h>
41
42#define NIOSV_INTERRUPT_VECTOR_SOFTWARE 0
43
44#define NIOSV_INTERRUPT_VECTOR_TIMER 1
45
46#define NIOSV_INTERRUPT_VECTOR_EXTERNAL(x) ((x) + 2)
47
48#define NIOSV_INTERRUPT_VECTOR_IS_EXTERNAL(x) ((x) >= 2)
49
50#define NIOSV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(x) ((x) - 2)
51
52#define BSP_INTERRUPT_VECTOR_COUNT \
53 NIOSV_INTERRUPT_VECTOR_EXTERNAL(NIOSV_MAXIMUM_EXTERNAL_INTERRUPTS)
54
55#define BSP_INTERRUPT_CUSTOM_VALID_VECTOR
56
57/*
58 * The following enumeration describes the value in the mcause CSR.
59 */
60enum alt_exception_cause_e {
61 NIOSV_UNDEFINED_CAUSE = -1,
62 NIOSV_INSTRUCTION_ADDRESS_MISALIGNED = 0,
63 NIOSV_INSTRUCTION_ACCESS_FAULT = 1,
64 NIOSV_ILLEGAL_INSTRUCTION = 2,
65 NIOSV_BREAKPOINT = 3,
66 NIOSV_LOAD_ADDRESS_MISALIGNED = 4,
67 NIOSV_LOAD_ACCESS_FAULT = 5,
68 NIOSV_STORE_AMO_ADDRESS_MISALIGNED = 6,
69 NIOSV_STORE_AMO_ACCESS_FAULT = 7,
70 NIOSV_ENVIRONMENT_CALL_FROM_U_MODE = 8,
71 NIOSV_ENVIRONMENT_CALL_FROM_S_MODE = 9,
72 NIOSV_RESERVED_BIT_10 = 10,
73 NIOSV_ENVIRONMENT_CALL_FROM_M_MODE = 11,
74 NIOSV_INSTRUCTION_PAGE_FAULT = 12,
75 NIOSV_LOAD_PAGE_FAULT = 13,
76 NIOSV_RESERVED_BIT_14 = 14,
77 NIOSV_STORE_AMO_PAGE_FAULT = 15
78};
79typedef enum alt_exception_cause_e alt_exception_cause;
80
81#ifdef __cplusplus
82extern "C"
83{
84#endif /* __cplusplus */
85
86static inline uint32_t alt_irq_pending(void)
87{
88 uint32_t active, enabled;
89
90 active = read_csr(mip);
91 enabled = read_csr(mie);
92
93 /*
94 * we want to only process the upper 16-bits, the interrupt lines connected
95 * via Platform Designer.
96 */
97 return (active & enabled) >> 16;
98}
99
100static inline uint32_t alt_irq_index(uint32_t active)
101{
102 uint32_t mask, i;
103
104 i = 0;
105 mask = 1;
106 /*
107 * Test each bit in turn looking for an active interrupt. Once one is
108 * found, the interrupt handler asigned by a call to alt_irq_register() is
109 * called to clear the interrupt condition.
110 */
111 do {
112 if (active & mask) {
113 return i;
114 }
115 mask <<= 1;
116 i++;
117 } while (1);
118 /* should not happen */
119 return 0;
120}
121
122static inline bool alt_irq_is_pending(uint32_t index)
123{
124 uint32_t mask, active;
125
126 active = alt_irq_pending();
127
128 if(active != 0) {
129 mask = 1 << index;
130 if (active & mask) {
131 return true;
132 }
133 }
134 return false;
135}
136
137static inline bool alt_irq_is_enabled(uint32_t index)
138{
139 uint32_t mask, enabled;
140
141 enabled = read_csr(mie) >> 16;
142
143 if(enabled != 0) {
144 mask = 1 << index;
145 if (enabled & mask) {
146 return true;
147 }
148 }
149 return false;
150}
151
152static inline void alt_irq_enable(uint32_t index)
153{
154 uint32_t mask;
155
156 mask = 1 << (index + 16);
157 set_csr(mie, mask);
158}
159
160static inline void alt_irq_disable(uint32_t index)
161{
162 uint32_t mask;
163
164 mask = 1 << (index + 16);
165 clear_csr(mie, mask);
166}
167
168#ifdef __cplusplus
169}
170#endif /* __cplusplus */
171
172#endif /* ASM */
173
174#endif /* LIBBSP_NIOSV_IRQ_H */
This header file is provided for backward compatiblility.
This header file provides the interfaces of the Processor Mask.
RISCV utility.