41#ifndef _RTEMS_SCORE_CPU_H
42#define _RTEMS_SCORE_CPU_H
59#define RTEMS_USE_32_BIT_OBJECT
72#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
74#define CPU_HARDWARE_FP FALSE
76#define CPU_SOFTWARE_FP FALSE
78#define CPU_ALL_TASKS_ARE_FP FALSE
80#define CPU_IDLE_TASK_IS_FP FALSE
82#define CPU_USE_DEFERRED_FP_SWITCH FALSE
84#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
97#define CPU_STACK_GROWS_UP FALSE
100#define CPU_CACHE_LINE_BYTES 32
102#define CPU_STRUCTURE_ALIGNMENT
113#define CPU_MODES_INTERRUPT_MASK 0x00000001
115#define CPU_MAXIMUM_PROCESSORS 32
166#define nogap __attribute__ ((packed))
187#define _CPU_Context_Get_SP( _context ) \
203#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
213#define CPU_INTERRUPT_NUMBER_OF_VECTORS 64
214#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER \
215 (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
221#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
231#define CPU_STACK_MINIMUM_SIZE (2048)
240#define CPU_SIZEOF_POINTER 4
250#define CPU_ALIGNMENT 8
267#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
269#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
271#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
285#define _CPU_ISR_Disable( _isr_cookie ) \
299#define _CPU_ISR_Enable( _isr_cookie ) \
301 (_isr_cookie) = (_isr_cookie); \
314#define _CPU_ISR_Flash( _isr_cookie ) \
316 _CPU_ISR_Enable( _isr_cookie ); \
317 _CPU_ISR_Disable( _isr_cookie ); \
320static inline bool _CPU_ISR_Is_enabled( uint32_t level )
339#define _CPU_ISR_Set_level( _new_level ) \
341 if (_new_level) asm volatile ( "nop\n" ); \
342 else asm volatile ( "nop\n" ); \
376#define CPU_CCR_INTERRUPTS_ON 0x80
377#define CPU_CCR_INTERRUPTS_OFF 0x00
379#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
380 _isr, _entry_point, _is_fp, _tls_area ) \
387 _stack = ((uintptr_t)(_stack_base)) + (_size) - 8; \
388 *((void (**)(void))(_stack)) = (_entry_point); \
390 (_the_context)->fp = (void *)_stack; \
391 (_the_context)->sp = (void *)_stack; \
408#define _CPU_Context_Restart_self( _the_context ) \
409 _CPU_Context_restore( (_the_context) );
413#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
415#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
430typedef void ( *CPU_ISR_handler )( uint32_t );
434 CPU_ISR_handler new_handler,
435 CPU_ISR_handler *old_handler
478 uint32_t integer_registers [16];
511static inline uint32_t CPU_swap_u32(
515 uint32_t byte1, byte2, byte3, byte4, swapped;
517 byte4 = (value >> 24) & 0xff;
518 byte3 = (value >> 16) & 0xff;
519 byte2 = (value >> 8) & 0xff;
520 byte1 = value & 0xff;
522 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
526#define CPU_swap_u16( value ) \
527 (((value&0xff) << 8) | ((value >> 8)&0xff))
529typedef uint32_t CPU_Counter_ticks;
This header file provides basic definitions used by the API and the implementation.
This header file provides the kernel character input/output support API.
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
#define sp
stack-pointer */
Definition: regs.h:64
#define fp
frame-pointer */
Definition: regs.h:65
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
uint32_t special_interrupt_register
Definition: cpu.h:191
Thread register context.
Definition: cpu.h:173