RTEMS 6.1-rc7
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fsl_flexspi_nor_config.h
1/*
2 * Copyright 2017-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Based on file for EVKBIMSRT1050 with values for other EVKs integrated.
8 */
9
10#ifndef __FSL_FLEXSPI_NOR_CONFIG__
11#define __FSL_FLEXSPI_NOR_CONFIG__
12
13#include <stdint.h>
14#include <stdbool.h>
15#include "fsl_common.h"
16
20#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
23/* FLEXSPI memory config block related defintions */
24#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
25#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
26#define FLEXSPI_CFG_BLK_SIZE (512)
27
28/* FLEXSPI Feature related definitions */
29#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
30
31/* Lookup table related defintions */
32#define CMD_INDEX_READ 0
33#define CMD_INDEX_READSTATUS 1
34#define CMD_INDEX_WRITEENABLE 2
35#define CMD_INDEX_WRITE 4
36
37#define CMD_LUT_SEQ_IDX_READ 0
38#define CMD_LUT_SEQ_IDX_READSTATUS 1
39#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
40#define CMD_LUT_SEQ_IDX_WRITE 9
41
42#define CMD_SDR 0x01
43#define CMD_DDR 0x21
44#define RADDR_SDR 0x02
45#define RADDR_DDR 0x22
46#define CADDR_SDR 0x03
47#define CADDR_DDR 0x23
48#define MODE1_SDR 0x04
49#define MODE1_DDR 0x24
50#define MODE2_SDR 0x05
51#define MODE2_DDR 0x25
52#define MODE4_SDR 0x06
53#define MODE4_DDR 0x26
54#define MODE8_SDR 0x07
55#define MODE8_DDR 0x27
56#define WRITE_SDR 0x08
57#define WRITE_DDR 0x28
58#define READ_SDR 0x09
59#define READ_DDR 0x29
60#define LEARN_SDR 0x0A
61#define LEARN_DDR 0x2A
62#define DATSZ_SDR 0x0B
63#define DATSZ_DDR 0x2B
64#define DUMMY_SDR 0x0C
65#define DUMMY_DDR 0x2C
66#define DUMMY_RWDS_SDR 0x0D
67#define DUMMY_RWDS_DDR 0x2D
68#define JMP_ON_CS 0x1F
69#define STOP 0
70
71#define FLEXSPI_1PAD 0
72#define FLEXSPI_2PAD 1
73#define FLEXSPI_4PAD 2
74#define FLEXSPI_8PAD 3
75
76#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
77 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
78 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
79
81typedef enum _FlexSpiSerialClockFreq
82{
83 kFlexSpiSerialClk_30MHz = 1,
84 kFlexSpiSerialClk_50MHz = 2,
85 kFlexSpiSerialClk_60MHz = 3,
86#if defined(MIMXRT1011_SERIES)
87 kFlexSpiSerialClk_75MHz = 4,
88 kFlexSpiSerialClk_80MHz = 5,
89 kFlexSpiSerialClk_100MHz = 6,
90 kFlexSpiSerialClk_120MHz = 7,
91 kFlexSpiSerialClk_133MHz = 8,
92#elif defined(MIMXRT1015_SERIES) || defined(MIMXRT1021_SERIES) || defined(MIMXRT1024_SERIES)
93 kFlexSpiSerialClk_75MHz = 4,
94 kFlexSpiSerialClk_80MHz = 5,
95 kFlexSpiSerialClk_100MHz = 6,
96 kFlexSpiSerialClk_133MHz = 7,
97#elif defined(MIMXRT1052_SERIES)
98 kFlexSpiSerialClk_75MHz = 4,
99 kFlexSpiSerialClk_80MHz = 5,
100 kFlexSpiSerialClk_100MHz = 6,
101 kFlexSpiSerialClk_133MHz = 7,
102 kFlexSpiSerialClk_166MHz = 8,
103#elif defined(MIMXRT1042_SERIES) || defined(MIMXRT1062_SERIES) || defined(MIMXRT1064_SERIES)
104 kFlexSpiSerialClk_75MHz = 4,
105 kFlexSpiSerialClk_80MHz = 5,
106 kFlexSpiSerialClk_100MHz = 6,
107 kFlexSpiSerialClk_120MHz = 7,
108 kFlexSpiSerialClk_133MHz = 8,
109 kFlexSpiSerialClk_166MHz = 9,
110#elif defined(MIMXRT1166_cm4_SERIES) || defined(MIMXRT1166_cm7_SERIES) || \
111 defined(MIMXRT1176_cm4_SERIES) || defined(MIMXRT1176_cm7_SERIES)
112 kFlexSpiSerialClk_80MHz = 4,
113 kFlexSpiSerialClk_100MHz = 5,
114 kFlexSpiSerialClk_120MHz = 6,
115 kFlexSpiSerialClk_133MHz = 7,
116 kFlexSpiSerialClk_166MHz = 8,
117 kFlexSpiSerialClk_200MHz = 9,
118#endif
119} flexspi_serial_clk_freq_t;
120
122enum
123{
124 kFlexSpiClk_SDR,
125 kFlexSpiClk_DDR,
126};
127
129typedef enum _FlashReadSampleClkSource
130{
131 kFlexSPIReadSampleClk_LoopbackInternally = 0,
132 kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
133 kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
134 kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
135} flexspi_read_sample_clk_t;
136
138enum
139{
140 kFlexSpiMiscOffset_DiffClkEnable = 0,
141 kFlexSpiMiscOffset_Ck2Enable = 1,
142 kFlexSpiMiscOffset_ParallelEnable = 2,
143 kFlexSpiMiscOffset_WordAddressableEnable = 3,
144 kFlexSpiMiscOffset_SafeConfigFreqEnable = 4,
145 kFlexSpiMiscOffset_PadSettingOverrideEnable = 5,
146 kFlexSpiMiscOffset_DdrModeEnable = 6,
147};
148
150enum
151{
152 kFlexSpiDeviceType_SerialNOR = 1,
153 kFlexSpiDeviceType_SerialNAND = 2,
154 kFlexSpiDeviceType_SerialRAM = 3,
155 kFlexSpiDeviceType_MCP_NOR_NAND = 0x12,
156 kFlexSpiDeviceType_MCP_NOR_RAM = 0x13,
157};
158
160enum
161{
162 kSerialFlash_1Pad = 1,
163 kSerialFlash_2Pads = 2,
164 kSerialFlash_4Pads = 4,
165 kSerialFlash_8Pads = 8,
166};
167
169typedef struct _lut_sequence
170{
171 uint8_t seqNum;
172 uint8_t seqId;
173 uint16_t reserved;
175
177enum
178{
179 kDeviceConfigCmdType_Generic,
180 kDeviceConfigCmdType_QuadEnable,
181 kDeviceConfigCmdType_Spi2Xpi,
182 kDeviceConfigCmdType_Xpi2Spi,
183 kDeviceConfigCmdType_Spi2NoCmd,
184 kDeviceConfigCmdType_Reset,
185};
186
188typedef struct _FlexSPIConfig
189{
190 uint32_t tag;
191 uint32_t version;
192 uint32_t reserved0;
194 uint8_t csHoldTime;
195 uint8_t csSetupTime;
205 uint32_t deviceModeArg;
207 uint8_t configModeType[3];
210 uint32_t reserved1;
211 uint32_t configCmdArgs[3];
212 uint32_t reserved2;
215 uint8_t deviceType;
221 uint32_t reserved3[2];
222 uint32_t sflashA1Size;
223 uint32_t sflashA2Size;
224 uint32_t sflashB1Size;
225 uint32_t sflashB2Size;
230 uint32_t timeoutInMs;
232 uint16_t dataValidTime[2];
233 uint16_t busyOffset;
236 uint32_t lookupTable[64];
238 uint32_t reserved4[4];
240
241/* */
242#define NOR_CMD_INDEX_READ CMD_INDEX_READ
243#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS
244#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE
245#define NOR_CMD_INDEX_ERASESECTOR 3
246#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE
247#define NOR_CMD_INDEX_CHIPERASE 5
248#define NOR_CMD_INDEX_DUMMY 6
249#define NOR_CMD_INDEX_ERASEBLOCK 7
250
251#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ
252#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
253 CMD_LUT_SEQ_IDX_READSTATUS
254#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
255 2
256#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
257 CMD_LUT_SEQ_IDX_WRITEENABLE
258#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
259 4
260#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
261#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8
262#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
263 CMD_LUT_SEQ_IDX_WRITE
264#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11
265#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13
266#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
267 14
268#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
269 15
270
271/*
272 * Serial NOR configuration block
273 */
275{
277 uint32_t pageSize;
278 uint32_t sectorSize;
282 uint8_t reserved0;
287 uint32_t blockSize;
288 uint32_t FlashStateCtx;
289 uint32_t reserve2[10];
291
292#ifdef __cplusplus
293extern "C" {
294#endif
295
296#ifdef __cplusplus
297}
298#endif
299#endif /* __FSL_FLEXSPI_NOR_CONFIG__ */
flexspi_mem_config_t memConfig
Common memory configuration info via FlexSPI.
Definition: fsl_flexspi_nor_config.h:276
uint8_t ipcmdSerialClkFreq
Clock frequency for IP command.
Definition: fsl_flexspi_nor_config.h:279
uint32_t blockSize
Block size.
Definition: fsl_flexspi_nor_config.h:287
uint8_t halfClkForNonReadCmd
Half the Serial Clock for non-read command: true/false.
Definition: fsl_flexspi_nor_config.h:285
uint8_t serialNorType
Serial NOR Flash type: 0/1/2/3.
Definition: fsl_flexspi_nor_config.h:283
uint32_t reserve2[10]
Reserved for future use.
Definition: fsl_flexspi_nor_config.h:289
uint8_t reserved0
Reserved for future use.
Definition: fsl_flexspi_nor_config.h:282
uint8_t isUniformBlockSize
Sector/Block size is the same.
Definition: fsl_flexspi_nor_config.h:280
uint32_t pageSize
Page size of Serial NOR.
Definition: fsl_flexspi_nor_config.h:277
uint8_t needExitNoCmdMode
Need to exit NoCmd mode before other IP command.
Definition: fsl_flexspi_nor_config.h:284
uint32_t sectorSize
Sector size of Serial NOR.
Definition: fsl_flexspi_nor_config.h:278
uint8_t isDataOrderSwapped
The data order is swapped in OPI DDR mode (only i.MXRT11*)
Definition: fsl_flexspi_nor_config.h:281
uint8_t needRestoreNoCmdMode
Need to Restore NoCmd mode after IP commmand execution.
Definition: fsl_flexspi_nor_config.h:286
FlexSPI Memory Configuration Block.
Definition: fsl_flexspi_nor_config.h:189
uint32_t version
[0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
Definition: fsl_flexspi_nor_config.h:191
uint8_t columnAddressWidth
Definition: fsl_flexspi_nor_config.h:196
uint32_t configCmdArgs[3]
[0x030-0x03b] Arguments/Parameters for device Configuration commands
Definition: fsl_flexspi_nor_config.h:211
uint32_t commandInterval
[0x074-0x077] CS deselect interval between two commands
Definition: fsl_flexspi_nor_config.h:231
flexspi_lut_seq_t lutCustomSeq[12]
[0x180-0x1af] Customizable LUT Sequences
Definition: fsl_flexspi_nor_config.h:237
uint8_t csSetupTime
[0x00e-0x00e] CS setup time, default value: 3
Definition: fsl_flexspi_nor_config.h:195
uint8_t sflashPadType
[0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
Definition: fsl_flexspi_nor_config.h:216
uint32_t sflashA2Size
[0x054-0x057] Size of Flash connected to A2
Definition: fsl_flexspi_nor_config.h:223
uint8_t lutCustomSeqEnable
Chapter for more details.
Definition: fsl_flexspi_nor_config.h:219
uint32_t sflashA1Size
[0x050-0x053] Size of Flash connected to A1
Definition: fsl_flexspi_nor_config.h:222
uint32_t csPadSettingOverride
[0x060-0x063] CS pad setting override value
Definition: fsl_flexspi_nor_config.h:226
uint32_t timeoutInMs
[0x070-0x073] Timeout threshold for read status command
Definition: fsl_flexspi_nor_config.h:230
uint8_t csHoldTime
[0x00d-0x00d] CS hold time, default value: 3
Definition: fsl_flexspi_nor_config.h:194
uint32_t reserved4[4]
[0x1b0-0x1bf] Reserved for future use
Definition: fsl_flexspi_nor_config.h:238
uint32_t reserved1
[0x02c-0x02f] Reserved for future use
Definition: fsl_flexspi_nor_config.h:210
uint32_t reserved2
[0x03c-0x03f] Reserved for future use
Definition: fsl_flexspi_nor_config.h:212
uint32_t tag
[0x000-0x003] Tag, fixed value 0x42464346UL
Definition: fsl_flexspi_nor_config.h:190
uint32_t deviceModeArg
sequence number, [31:16] Reserved
Definition: fsl_flexspi_nor_config.h:205
uint16_t dataValidTime[2]
[0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
Definition: fsl_flexspi_nor_config.h:232
uint16_t busyOffset
[0x07c-0x07d] Busy offset, valid value: 0-31
Definition: fsl_flexspi_nor_config.h:233
uint8_t deviceModeCfgEnable
Serial NAND, need to refer to datasheet.
Definition: fsl_flexspi_nor_config.h:198
uint32_t sflashB1Size
[0x058-0x05b] Size of Flash connected to B1
Definition: fsl_flexspi_nor_config.h:224
uint32_t controllerMiscOption
Definition: fsl_flexspi_nor_config.h:213
uint8_t configCmdEnable
[0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
Definition: fsl_flexspi_nor_config.h:206
uint32_t lookupTable[64]
busy flag is 0 when flash device is busy
Definition: fsl_flexspi_nor_config.h:236
uint32_t sflashB2Size
[0x05c-0x05f] Size of Flash connected to B2
Definition: fsl_flexspi_nor_config.h:225
uint16_t busyBitPolarity
Definition: fsl_flexspi_nor_config.h:234
uint32_t reserved3[2]
be done using 1 LUT sequence, currently, only applicable to HyperFLASH
Definition: fsl_flexspi_nor_config.h:221
uint8_t deviceModeType
Definition: fsl_flexspi_nor_config.h:199
uint8_t readSampleClkSrc
[0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
Definition: fsl_flexspi_nor_config.h:193
uint8_t deviceType
details
Definition: fsl_flexspi_nor_config.h:215
uint32_t dqsPadSettingOverride
[0x06c-0x06f] DQS pad setting override value
Definition: fsl_flexspi_nor_config.h:229
uint32_t reserved0
[0x008-0x00b] Reserved for future use
Definition: fsl_flexspi_nor_config.h:192
uint32_t sclkPadSettingOverride
[0x064-0x067] SCK pad setting override value
Definition: fsl_flexspi_nor_config.h:227
flexspi_lut_seq_t deviceModeSeq
DPI/QPI/OPI switch or reset command.
Definition: fsl_flexspi_nor_config.h:203
uint16_t waitTimeCfgCommands
Generic configuration, etc.
Definition: fsl_flexspi_nor_config.h:201
uint32_t dataPadSettingOverride
[0x068-0x06b] data pad setting override value
Definition: fsl_flexspi_nor_config.h:228
uint8_t configModeType[3]
[0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
Definition: fsl_flexspi_nor_config.h:207
flexspi_lut_seq_t configCmdSeqs[3]
[0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
Definition: fsl_flexspi_nor_config.h:209
uint8_t serialClkFreq
Definition: fsl_flexspi_nor_config.h:217
FLEXSPI Memory Configuration Block.
Definition: fsl_romapi.h:238
Serial NOR configuration block.
Definition: fsl_flexspi_nor_config.h:275
uint32_t FlashStateCtx
Flash State Context after being configured (only i.MXRT11*)
Definition: fsl_flexspi_nor_config.h:288
FlexSPI LUT Sequence structure.
Definition: fsl_flexspi_nor_config.h:170
uint8_t seqId
Sequence Index, valid number: 0-15.
Definition: fsl_flexspi_nor_config.h:172
uint8_t seqNum
Sequence Number, valid number: 1-16.
Definition: fsl_flexspi_nor_config.h:171