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RTEMS 6.1-rc7
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Pulse Width Modulation subsystem includes EPWM, ECAP , EQEP. There are different instances available for each one. For PWM there are three different individual EPWM module 0 , 1 and 2. So wherever pwmss word is used that affects whole PWM sub system such as EPWM, ECAP and EQEP. This code has only implementation Non high resolution PWM module. APIs for high resolution PWM has been yet to develop.
For Each EPWM instance, has two PWM channels, e.g. EPWM0 has two channel EPWM0A and EPWM0B. If you configure two PWM outputs(e.g. EPWM0A , EPWM0B) in the same device, then they must be configured with the same frequency. Changing frequency on one channel (e.g EPWMxA) will automatically change frequency on another channel(e.g. EPWMxB). However, it is possible to set different pulse-width/duty cycle to different channel at a time. So always set the frequency first and then pulse-width/duty cycle.
For more you can refer : http://www.ofitselfso.com/BBBCSIO/Source/PWMPortEnum.cs.html
Pulse Width Modulation uses the system frequency of Beagle Bone Black.
System frequency = SYSCLKOUT, that is, CPU clock. TBCLK = SYSCLKOUT(By Default) SYCLKOUT = 100 MHz
Please visit following link to check why SYSCLKDIV = 100MHz: https://groups.google.com/forum/#!topic/beagleboard/Ed2J9Txe_E4 (Refer Technical Reference Manual (TRM) Table 15-41 as well)
To generate different frequencies with the help of PWM module , SYSCLKOUT need to be scaled down, which will act as TBCLK and TBCLK will be base clock for the pwm subsystem.
CLKDIV and HSPCLKDIV bits are part of the TBCTL register (Refer TRM). CLKDIV - These bits determine part of the time-base clock prescale value. Please use the following values of CLKDIV to scale down sysclk respectively.
These bits determine part of the time-base clock prescale value. Please use following value of HSPCLKDIV to scale down sysclk respectively
For example, if you set CLKDIV = 3h and HSPCLKDIV= 2h Then SYSCLKOUT will be divided by (1/8)(1/4). It means SYSCLKOUT/32
How to generate frequency ?
freq = 1/Period
TBPRD register is responsible to generate the frequency. These bits determine the period of the time-base counter.
By default TBCLK = SYSCLKOUT = 100 MHz
Here by default period is 1/100MHz = 10 nsec
Following example shows value to be loaded into TBPRD
For duty cycle CMPA and CMPB are the responsible registers.
To generate single with 50% Duty cycle & 100MHz freq.
The value in the active CMPA register is continuously compared to the time-base counter (TBCNT). When the values are equal, the counter-compare module generates a "time-base counter equal to counter compare A" event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output depending on the configuration of the AQCTLA and AQCTLB registers.
List of pins for that can be used for different PWM instance :
| BBB_P8_13_2B | BBB_P8_34_1B | BBB_P9_21_0B |
| BBB_P8_19_2A | BBB_P8_36_1A | BBB_P9_22_0A | | BBB_P8_45_2A | BBB_P9_14_1A | BBB_P9_29_0B |
BBB_P8_13_2B represents P8 Header , pin number 13 , 2nd PWM instance and B channel.
Following sample program can be used to generate 7 Hz frequency.