RTEMS 6.1-rc7
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tm27.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
9/*
10 * COPYRIGHT (c) 2006.
11 * Aeroflex Gaisler AB.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _RTEMS_TMTEST27
36#error "This is an RTEMS internal file you must not include directly."
37#endif
38
39#ifndef __tm27_h
40#define __tm27_h
41
42#include <bsp.h>
43#include <bsp/irq-generic.h>
44
45#if defined(RTEMS_SMP)
46#include <rtems/score/smpimpl.h>
47#endif
48
49/*
50 * Define the interrupt mechanism for Time Test 27
51 *
52 * NOTE: Since the interrupt code for the SPARC supports both synchronous
53 * and asynchronous trap handlers, support for testing with both
54 * is included.
55 */
56
57#define SIS_USE_SYNCHRONOUS_TRAP 0
58
59/*
60 * The synchronous trap is an arbitrarily chosen software trap.
61 */
62
63#if (SIS_USE_SYNCHRONOUS_TRAP == 1)
64
65#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 )
66
67#define MUST_WAIT_FOR_INTERRUPT 1
68
69#define TM27_USE_VECTOR_HANDLER
70
71#define Install_tm27_vector( handler ) \
72 set_vector( (handler), TEST_VECTOR, 1 );
73
74#define Cause_tm27_intr() \
75 __asm__ volatile( "ta 0x10; nop " );
76
77#define Clear_tm27_intr() /* empty */
78
79#define Lower_tm27_intr() /* empty */
80
81/*
82 * The asynchronous trap is an arbitrarily chosen ERC32 interrupt source.
83 */
84
85#else /* use a regular asynchronous trap */
86
87extern uint32_t Interrupt_nest;
88
89#define TEST_INTERRUPT_SOURCE 5
90#define TEST_INTERRUPT_SOURCE2 6
91#define MUST_WAIT_FOR_INTERRUPT 1
92#define TM27_INTERRUPT_VECTOR_DEFAULT TEST_INTERRUPT_SOURCE
93
94static inline void Install_tm27_vector( rtems_interrupt_handler handler )
95{
96 static rtems_interrupt_entry entry_low;
97 static rtems_interrupt_entry entry_high;
98
99#if defined(RTEMS_SMP)
101 TEST_INTERRUPT_SOURCE,
102 _SMP_Get_online_processors()
103 );
105 TEST_INTERRUPT_SOURCE2,
106 _SMP_Get_online_processors()
107 );
108#endif
109
110 rtems_interrupt_entry_initialize(
111 &entry_low,
112 handler,
113 NULL,
114 "tm27 low"
115 );
117 TEST_INTERRUPT_SOURCE,
119 &entry_low
120 );
121 rtems_interrupt_entry_initialize(
122 &entry_high,
123 handler,
124 NULL,
125 "tm27 high"
126 );
128 TEST_INTERRUPT_SOURCE2,
130 &entry_high
131 );
132}
133
134static inline void Cause_tm27_intr( void )
135{
136 rtems_vector_number vector;
137
138 vector = TEST_INTERRUPT_SOURCE + ( Interrupt_nest >> 1 );
139#if defined(RTEMS_SMP)
141#else
142 (void) rtems_interrupt_raise( vector );
143#endif
144 nop();
145 nop();
146 nop();
147}
148
149static inline void Clear_tm27_intr( void )
150{
151 (void) rtems_interrupt_clear( TEST_INTERRUPT_SOURCE );
152}
153
154#define Lower_tm27_intr() /* empty */
155
156#endif
157
158#endif
This header file evaluates configuration options related to the BSP configuration.
rtems_status_code rtems_interrupt_entry_install(rtems_vector_number vector, rtems_option options, rtems_interrupt_entry *entry)
Installs the interrupt entry at the interrupt vector.
Definition: irq-generic.c:264
ISR_Vector_number rtems_vector_number
This integer type represents interrupt vector numbers.
Definition: intr.h:102
#define RTEMS_INTERRUPT_SHARED
This interrupt handler install option allows that the interrupt handler may share the interrupt vecto...
Definition: intr.h:960
rtems_status_code rtems_interrupt_raise_on(rtems_vector_number vector, uint32_t cpu_index)
Raises the interrupt vector on the processor.
Definition: irq-raise-clear.c:68
rtems_status_code rtems_interrupt_raise(rtems_vector_number vector)
Raises the interrupt vector.
Definition: irq-raise-clear.c:59
void(* rtems_interrupt_handler)(void *)
Interrupt handler routines shall have this type.
Definition: intr.h:1030
rtems_status_code rtems_interrupt_clear(rtems_vector_number vector)
Clears the interrupt vector.
Definition: irq-raise-clear.c:92
#define rtems_scheduler_get_processor()
Returns the index of the current processor.
Definition: scheduler.h:372
rtems_status_code bsp_interrupt_set_affinity(rtems_vector_number vector, const Processor_mask *affinity)
Sets the processor affinity set of the interrupt vector.
Definition: irq.c:406
This header file provides interfaces of the Interrupt Manager implementation.
This header file provides interfaces of the SMP Support which are only used by the implementation.
#define nop()
Definition: sparc.h:281
This structure represents an interrupt entry.
Definition: intr.h:1070