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RTEMS 6.1-rc7
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Reset and Clock Control. More...
#include <stm32h723xx.h>
Data Fields | |
__IO uint32_t | CR |
__IO uint32_t | HSICFGR |
__IO uint32_t | CRRCR |
__IO uint32_t | CSICFGR |
__IO uint32_t | CFGR |
uint32_t | RESERVED1 |
__IO uint32_t | D1CFGR |
__IO uint32_t | D2CFGR |
__IO uint32_t | D3CFGR |
uint32_t | RESERVED2 |
__IO uint32_t | PLLCKSELR |
__IO uint32_t | PLLCFGR |
__IO uint32_t | PLL1DIVR |
__IO uint32_t | PLL1FRACR |
__IO uint32_t | PLL2DIVR |
__IO uint32_t | PLL2FRACR |
__IO uint32_t | PLL3DIVR |
__IO uint32_t | PLL3FRACR |
uint32_t | RESERVED3 |
__IO uint32_t | D1CCIPR |
__IO uint32_t | D2CCIP1R |
__IO uint32_t | D2CCIP2R |
__IO uint32_t | D3CCIPR |
uint32_t | RESERVED4 |
__IO uint32_t | CIER |
__IO uint32_t | CIFR |
__IO uint32_t | CICR |
uint32_t | RESERVED5 |
__IO uint32_t | BDCR |
__IO uint32_t | CSR |
uint32_t | RESERVED6 |
__IO uint32_t | AHB3RSTR |
__IO uint32_t | AHB1RSTR |
__IO uint32_t | AHB2RSTR |
__IO uint32_t | AHB4RSTR |
__IO uint32_t | APB3RSTR |
__IO uint32_t | APB1LRSTR |
__IO uint32_t | APB1HRSTR |
__IO uint32_t | APB2RSTR |
__IO uint32_t | APB4RSTR |
__IO uint32_t | GCR |
uint32_t | RESERVED8 |
__IO uint32_t | D3AMR |
uint32_t | RESERVED11 [9] |
__IO uint32_t | RSR |
__IO uint32_t | AHB3ENR |
__IO uint32_t | AHB1ENR |
__IO uint32_t | AHB2ENR |
__IO uint32_t | AHB4ENR |
__IO uint32_t | APB3ENR |
__IO uint32_t | APB1LENR |
__IO uint32_t | APB1HENR |
__IO uint32_t | APB2ENR |
__IO uint32_t | APB4ENR |
uint32_t | RESERVED12 |
__IO uint32_t | AHB3LPENR |
__IO uint32_t | AHB1LPENR |
__IO uint32_t | AHB2LPENR |
__IO uint32_t | AHB4LPENR |
__IO uint32_t | APB3LPENR |
__IO uint32_t | APB1LLPENR |
__IO uint32_t | APB1HLPENR |
__IO uint32_t | APB2LPENR |
__IO uint32_t | APB4LPENR |
uint32_t | RESERVED13 [4] |
__IO uint32_t | CDCFGR1 |
__IO uint32_t | CDCFGR2 |
__IO uint32_t | SRDCFGR |
__IO uint32_t | CDCCIPR |
__IO uint32_t | CDCCIP1R |
__IO uint32_t | CDCCIP2R |
__IO uint32_t | SRDCCIPR |
uint32_t | RESERVED7 |
__IO uint32_t | SRDAMR |
uint32_t | RESERVED9 |
__IO uint32_t | CKGAENR |
uint32_t | RESERVED10 [31] |
Reset and Clock Control.
__IO uint32_t RCC_TypeDef::AHB1ENR |
RCC AHB1 peripheral clock register, Address offset: 0xD8
__IO uint32_t RCC_TypeDef::AHB1LPENR |
RCC AHB1 peripheral sleep clock register, Address offset: 0x100
__IO uint32_t RCC_TypeDef::AHB1RSTR |
RCC AHB1 peripheral reset register, Address offset: 0x80
__IO uint32_t RCC_TypeDef::AHB2ENR |
RCC AHB2 peripheral clock register, Address offset: 0xDC
__IO uint32_t RCC_TypeDef::AHB2LPENR |
RCC AHB2 peripheral sleep clock register, Address offset: 0x104
__IO uint32_t RCC_TypeDef::AHB2RSTR |
RCC AHB2 peripheral reset register, Address offset: 0x84
__IO uint32_t RCC_TypeDef::AHB3ENR |
RCC AHB3 peripheral clock register, Address offset: 0xD4
__IO uint32_t RCC_TypeDef::AHB3LPENR |
RCC AHB3 peripheral sleep clock register, Address offset: 0xFC
__IO uint32_t RCC_TypeDef::AHB3RSTR |
RCC AHB3 peripheral reset register, Address offset: 0x7C
__IO uint32_t RCC_TypeDef::AHB4ENR |
RCC AHB4 peripheral clock register, Address offset: 0xE0
__IO uint32_t RCC_TypeDef::AHB4LPENR |
RCC AHB4 peripheral sleep clock register, Address offset: 0x108
__IO uint32_t RCC_TypeDef::AHB4RSTR |
RCC AHB4 peripheral reset register, Address offset: 0x88
__IO uint32_t RCC_TypeDef::APB1HENR |
RCC APB1 peripheral clock High Word register, Address offset: 0xEC
__IO uint32_t RCC_TypeDef::APB1HLPENR |
RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114
__IO uint32_t RCC_TypeDef::APB1HRSTR |
RCC APB1 peripheral reset High Word register, Address offset: 0x94
__IO uint32_t RCC_TypeDef::APB1LENR |
RCC APB1 peripheral clock Low Word register, Address offset: 0xE8
__IO uint32_t RCC_TypeDef::APB1LLPENR |
RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110
__IO uint32_t RCC_TypeDef::APB1LRSTR |
RCC APB1 peripheral reset Low Word register, Address offset: 0x90
__IO uint32_t RCC_TypeDef::APB2ENR |
RCC APB2 peripheral clock register, Address offset: 0xF0
__IO uint32_t RCC_TypeDef::APB2LPENR |
RCC APB2 peripheral sleep clock register, Address offset: 0x118
__IO uint32_t RCC_TypeDef::APB2RSTR |
RCC APB2 peripheral reset register, Address offset: 0x98
__IO uint32_t RCC_TypeDef::APB3ENR |
RCC APB3 peripheral clock register, Address offset: 0xE4
__IO uint32_t RCC_TypeDef::APB3LPENR |
RCC APB3 peripheral sleep clock register, Address offset: 0x10C
__IO uint32_t RCC_TypeDef::APB3RSTR |
RCC APB3 peripheral reset register, Address offset: 0x8C
__IO uint32_t RCC_TypeDef::APB4ENR |
RCC APB4 peripheral clock register, Address offset: 0xF4
__IO uint32_t RCC_TypeDef::APB4LPENR |
RCC APB4 peripheral sleep clock register, Address offset: 0x11C
__IO uint32_t RCC_TypeDef::APB4RSTR |
RCC APB4 peripheral reset register, Address offset: 0x9C
__IO uint32_t RCC_TypeDef::BDCR |
RCC Vswitch Backup Domain Control Register, Address offset: 0x70
__IO uint32_t RCC_TypeDef::CDCCIP1R |
RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50
__IO uint32_t RCC_TypeDef::CDCCIP2R |
RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54
__IO uint32_t RCC_TypeDef::CDCCIPR |
RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C
__IO uint32_t RCC_TypeDef::CDCFGR1 |
RCC Domain 1 configuration register, Address offset: 0x18
__IO uint32_t RCC_TypeDef::CDCFGR2 |
RCC Domain 2 configuration register, Address offset: 0x1C
__IO uint32_t RCC_TypeDef::CFGR |
RCC clock configuration register, Address offset: 0x10
__IO uint32_t RCC_TypeDef::CICR |
RCC Clock Source Interrupt Clear Register Address offset: 0x68
__IO uint32_t RCC_TypeDef::CIER |
RCC Clock Source Interrupt Enable Register Address offset: 0x60
__IO uint32_t RCC_TypeDef::CIFR |
RCC Clock Source Interrupt Flag Register Address offset: 0x64
__IO uint32_t RCC_TypeDef::CKGAENR |
AXI Clocks Gating Enable Register, Address offset: 0xB0
__IO uint32_t RCC_TypeDef::CR |
RCC clock control register, Address offset: 0x00
__IO uint32_t RCC_TypeDef::CRRCR |
Clock Recovery RC Register, Address offset: 0x08
__IO uint32_t RCC_TypeDef::CSICFGR |
CSI Clock Calibration Register, Address offset: 0x0C
__IO uint32_t RCC_TypeDef::CSR |
RCC clock control & status register, Address offset: 0x74
__IO uint32_t RCC_TypeDef::D1CCIPR |
RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C
__IO uint32_t RCC_TypeDef::D1CFGR |
RCC Domain 1 configuration register, Address offset: 0x18
__IO uint32_t RCC_TypeDef::D2CCIP1R |
RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50
__IO uint32_t RCC_TypeDef::D2CCIP2R |
RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54
__IO uint32_t RCC_TypeDef::D2CFGR |
RCC Domain 2 configuration register, Address offset: 0x1C
__IO uint32_t RCC_TypeDef::D3AMR |
RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8
__IO uint32_t RCC_TypeDef::D3CCIPR |
RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58
__IO uint32_t RCC_TypeDef::D3CFGR |
RCC Domain 3 configuration register, Address offset: 0x20
__IO uint32_t RCC_TypeDef::GCR |
RCC RCC Global Control Register, Address offset: 0xA0
__IO uint32_t RCC_TypeDef::HSICFGR |
HSI Clock Calibration Register, Address offset: 0x04
__IO uint32_t RCC_TypeDef::PLL1DIVR |
RCC PLL1 Dividers Configuration Register, Address offset: 0x30
__IO uint32_t RCC_TypeDef::PLL1FRACR |
RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34
__IO uint32_t RCC_TypeDef::PLL2DIVR |
RCC PLL2 Dividers Configuration Register, Address offset: 0x38
__IO uint32_t RCC_TypeDef::PLL2FRACR |
RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C
__IO uint32_t RCC_TypeDef::PLL3DIVR |
RCC PLL3 Dividers Configuration Register, Address offset: 0x40
__IO uint32_t RCC_TypeDef::PLL3FRACR |
RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44
__IO uint32_t RCC_TypeDef::PLLCFGR |
RCC PLLs Configuration Register, Address offset: 0x2C
__IO uint32_t RCC_TypeDef::PLLCKSELR |
RCC PLLs Clock Source Selection Register, Address offset: 0x28
uint32_t RCC_TypeDef::RESERVED1 |
Reserved, Address offset: 0x14
uint32_t RCC_TypeDef::RESERVED10 |
Reserved, 0xAC-0xAF Address offset: 0xAC
uint32_t RCC_TypeDef::RESERVED11 |
Reserved, 0xAC-0xCC Address offset: 0xAC
uint32_t RCC_TypeDef::RESERVED12 |
Reserved, Address offset: 0xF8
uint32_t RCC_TypeDef::RESERVED13 |
Reserved, 0x120-0x12C Address offset: 0x120
uint32_t RCC_TypeDef::RESERVED2 |
Reserved, Address offset: 0x24
uint32_t RCC_TypeDef::RESERVED3 |
Reserved, Address offset: 0x48
uint32_t RCC_TypeDef::RESERVED4 |
Reserved, Address offset: 0x5C
uint32_t RCC_TypeDef::RESERVED5 |
Reserved, Address offset: 0x6C
uint32_t RCC_TypeDef::RESERVED6 |
Reserved, Address offset: 0x78
uint32_t RCC_TypeDef::RESERVED7 |
Reserved, Address offset: 0xA0
uint32_t RCC_TypeDef::RESERVED8 |
Reserved, Address offset: 0xA4
uint32_t RCC_TypeDef::RESERVED9 |
Reserved, 0xAC-0xAF Address offset: 0xAC
__IO uint32_t RCC_TypeDef::RSR |
RCC Reset status register, Address offset: 0xD0
__IO uint32_t RCC_TypeDef::SRDAMR |
RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8
__IO uint32_t RCC_TypeDef::SRDCCIPR |
RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58
__IO uint32_t RCC_TypeDef::SRDCFGR |
RCC Domain 3 configuration register, Address offset: 0x20