RTEMS 6.1-rc7
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altera_avalon_epcq_regs.h
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/*
4 *
5 * Copyright (C) 2024 Kevin Kirspel
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#ifndef _ALTERA_AVALON_EPCQ_REGS_H
30#define _ALTERA_AVALON_EPCQ_REGS_H
31
32#include <stdbool.h>
33#include <bsp_system.h>
34
35/*
36 * EPCQ_RD_STATUS register description macros
37 */
38
40#define ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_MASK (0x00000001)
41#define ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_AVAILABLE (0x00000000)
42#define ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_BUSY (0x00000001)
44/* 0.7 sec time out */
45#define ALTERA_EPCQ_CONTROLLER2_1US_TIMEOUT_VALUE 700000
46
47/*
48 * EPCQ_RD_SID register description macros
49 *
50 * Specific device values obtained from Table 14 of:
51 * "Serial Configuration (EPCS) Devices Datasheet"
52 */
53#define ALTERA_EPCQ_CONTROLLER2_SID_MASK (0x000000FF)
54#define ALTERA_EPCQ_CONTROLLER2_SID_EPCS16 (0x00000014)
55#define ALTERA_EPCQ_CONTROLLER2_SID_EPCS64 (0x00000016)
56#define ALTERA_EPCQ_CONTROLLER2_SID_EPCS128 (0x00000018)
57
58/*
59 * EPCQ_RD_RDID register description macros
60 *
61 * Specific device values obtained from Table 28 of:
62 * "Quad-Serial Configuration
63 * (EPCQ (www.altera.com/literature/hb/cfg/cfg_cf52012.pdf))
64 * Devices Datasheet"
65 */
66#define ALTERA_EPCQ_CONTROLLER2_RDID_MASK (0x000000FF)
67#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ16 (0x00000015)
68#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ32 (0x00000016)
69#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ64 (0x00000017)
70#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ128 (0x00000018)
71#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ256 (0x00000019)
72#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ512 (0x00000020)
73#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ1024 (0x00000021)
74
75/*
76 * EPCQ_MEM_OP register description macros
77 */
78#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_CMD_MASK (0x00000003)
79#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_BULK_ERASE_CMD (0x00000001)
80#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_ERASE_CMD (0x00000002)
81#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_PROTECT_CMD (0x00000003)
82#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_WRITE_ENABLE_CMD (0x00000004)
83
85#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_VALUE_MASK (0x00FFFF00)
86
87/*
88 * EPCQ_ISR register description macros
89 */
90#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_MASK (0x00000001)
91#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_ACTIVE (0x00000001)
92
93#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_MASK (0x00000002)
94#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_ACTIVE (0x00000002)
95
96/*
97 * EPCQ_IMR register description macros
98 */
99#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_ERASE_MASK (0x00000001)
100#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_ERASE_ENABLED (0x00000001)
101
102#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_WRITE_MASK (0x00000002)
103#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_WRITE_ENABLED (0x00000002)
104
105/*
106 * EPCQ_CHIP_SELECT register description macros
107 */
108#define ALTERA_EPCQ_CHIP1_SELECT (0x00000001)
109#define ALTERA_EPCQ_CHIP2_SELECT (0x00000002)
110#define ALTERA_EPCQ_CHIP3_SELECT (0x00000003)
111
112#ifdef __cplusplus
113extern "C" {
114#endif
115
116typedef struct
117{
118 volatile uint32_t rd_status;
119 volatile uint32_t rd_sid;
120 volatile uint32_t rd_rdid;
121 volatile uint32_t mem_op;
122 volatile uint32_t isr;
123 volatile uint32_t imr;
124 volatile uint32_t chip_select;
125 volatile uint32_t flag_status;
126 volatile uint32_t dev_id_0;
127 volatile uint32_t dev_id_1;
128 volatile uint32_t dev_id_2;
129 volatile uint32_t dev_id_3;
130 volatile uint32_t dev_id_4;
132
133#define EPCQ_REGS \
134 (( volatile altera_avalon_epcq_regs* )EPCQ_CONTROLLER_AVL_CSR_BASE )
135#define EPCQ_MEM \
136 (( volatile uint8_t* )EPCQ_CONTROLLER_AVL_MEM_BASE )
137#define EPCQ_MEM_32 \
138 (( volatile uint32_t* )EPCQ_CONTROLLER_AVL_MEM_BASE )
139
140void epcq_initialize( void );
141int epcq_read_buffer( int offset, uint8_t *dest_addr, int length );
142int epcq_write_buffer (
143 int offset,
144 const uint8_t* src_addr,
145 int length,
146 bool erase
147);
148
149#ifdef __cplusplus
150}
151#endif
152
153#endif
Definition: altera_avalon_epcq_regs.h:117