11#include "fsl_common.h"
25#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 6))
29#define L1CODEBUSCACHE_LINESIZE_BYTE \
30 FSL_FEATURE_L1ICACHE_LINESIZE_BYTE
31#define L1SYSTEMBUSCACHE_LINESIZE_BYTE \
32 L1CODEBUSCACHE_LINESIZE_BYTE
38#if defined(__cplusplus)
42#if (FSL_FEATURE_SOC_LMEM_COUNT == 1)
52void L1CACHE_EnableCodeCache(
void);
58void L1CACHE_DisableCodeCache(
void);
64void L1CACHE_InvalidateCodeCache(
void);
76void L1CACHE_InvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte);
82void L1CACHE_CleanCodeCache(
void);
94void L1CACHE_CleanCodeCacheByRange(uint32_t address, uint32_t size_byte);
100void L1CACHE_CleanInvalidateCodeCache(
void);
112void L1CACHE_CleanInvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte);
121static inline void L1CACHE_EnableCodeCacheWriteBuffer(
bool enable)
125 LMEM->PCCCR |= LMEM_PCCCR_ENWRBUF_MASK;
129 LMEM->PCCCR &= ~LMEM_PCCCR_ENWRBUF_MASK;
133#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
138void L1CACHE_EnableSystemCache(
void);
144void L1CACHE_DisableSystemCache(
void);
150void L1CACHE_InvalidateSystemCache(
void);
162void L1CACHE_InvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte);
168void L1CACHE_CleanSystemCache(
void);
180void L1CACHE_CleanSystemCacheByRange(uint32_t address, uint32_t size_byte);
186void L1CACHE_CleanInvalidateSystemCache(
void);
198void L1CACHE_CleanInvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte);
207static inline void L1CACHE_EnableSystemCacheWriteBuffer(
bool enable)
211 LMEM->PSCCR |= LMEM_PSCCR_ENWRBUF_MASK;
215 LMEM->PSCCR &= ~LMEM_PSCCR_ENWRBUF_MASK;
242static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
254void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte);
263void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte);
282static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
297static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
299 L1CACHE_InvalidateDCacheByRange(address, size_byte);
312static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
314 L1CACHE_CleanDCacheByRange(address, size_byte);
327static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
329 L1CACHE_CleanInvalidateDCacheByRange(address, size_byte);
334#if defined(__cplusplus)
#define LMEM
Definition: MIMXRT1166_cm4.h:58953
void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
Invalidate cortex-m7 L1 instruction cache by range.
Definition: fsl_cache.c:411