37#ifndef LIBBSP_MIPS_JMR3904_IRQ_H
38#define LIBBSP_MIPS_JMR3904_IRQ_H
60 #define TX3904_IRQ_INT1 MIPS_INTERRUPT_BASE+0
61 #define TX3904_IRQ_INT2 MIPS_INTERRUPT_BASE+1
62 #define TX3904_IRQ_INT3 MIPS_INTERRUPT_BASE+2
63 #define TX3904_IRQ_INT4 MIPS_INTERRUPT_BASE+3
64 #define TX3904_IRQ_INT5 MIPS_INTERRUPT_BASE+4
65 #define TX3904_IRQ_INT6 MIPS_INTERRUPT_BASE+5
66 #define TX3904_IRQ_INT7 MIPS_INTERRUPT_BASE+6
67 #define TX3904_IRQ_DMAC3 MIPS_INTERRUPT_BASE+7
68 #define TX3904_IRQ_DMAC2 MIPS_INTERRUPT_BASE+8
69 #define TX3904_IRQ_DMAC1 MIPS_INTERRUPT_BASE+9
70 #define TX3904_IRQ_DMAC0 MIPS_INTERRUPT_BASE+10
71 #define TX3904_IRQ_SIO0 MIPS_INTERRUPT_BASE+11
72 #define TX3904_IRQ_SIO1 MIPS_INTERRUPT_BASE+12
73 #define TX3904_IRQ_TMR0 MIPS_INTERRUPT_BASE+13
74 #define TX3904_IRQ_TMR1 MIPS_INTERRUPT_BASE+14
75 #define TX3904_IRQ_TMR2 MIPS_INTERRUPT_BASE+15
76 #define TX3904_IRQ_INT0 MIPS_INTERRUPT_BASE+16
77 #define TX3904_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+17
78 #define TX3904_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+18
79 #define TX3904_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+19
81#define BSP_INTERRUPT_VECTOR_COUNT (TX3904_MAXIMUM_VECTORS + 1)
This header file is provided for backward compatiblility.
Information to build RTEMS for a "no cpu" while in protected mode.
This header file defines the RTEMS Classic API.