RTEMS 6.1-rc7
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arm-gic-arch.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
12/*
13 * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
14 * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
15 *
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions
18 * are met:
19 * 1. Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#ifndef _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H
39#define _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H
40
41#include <rtems/score/cpu.h>
42#include <rtems/score/cpu_irq.h>
43
44#include <bsp/irq-generic.h>
45
46#ifdef __cplusplus
47extern "C" {
48#endif
49
56static inline uint32_t arm_interrupt_enable_interrupts(void)
57{
58 uint32_t status = _CPU_ISR_Get_level();
59 /* Enable interrupts for nesting */
61 return status;
62}
63
64static inline void arm_interrupt_restore_interrupts(uint32_t status)
65{
66 /* Restore interrupts to previous level */
67 _CPU_ISR_Set_level(status);
68}
69
70static inline void arm_interrupt_facility_set_exception_handler(void)
71{
72 AArch64_set_exception_handler(
73 AARCH64_EXCEPTION_SPx_IRQ,
74 _AArch64_Exception_interrupt_no_nest
75 );
76 AArch64_set_exception_handler(
77 AARCH64_EXCEPTION_SP0_IRQ,
78 _AArch64_Exception_interrupt_nest
79 );
80}
81
84#ifdef __cplusplus
85}
86#endif
87
88#endif /* _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H */
AArch64 IRQ definitions.
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
#define _CPU_ISR_Set_level(_new_level)
Definition: cpu.h:378
This header file provides interfaces of the Interrupt Manager implementation.