◆ CBNDTR
__IO uint32_t MDMA_Channel_TypeDef::CBNDTR |
MDMA Channel x block number of data register, Address offset: 0x54
◆ CBRUR
__IO uint32_t MDMA_Channel_TypeDef::CBRUR |
MDMA channel x Block Repeat address Update register, Address offset: 0x60
◆ CCR
__IO uint32_t MDMA_Channel_TypeDef::CCR |
MDMA channel x control register, Address offset: 0x4C
◆ CDAR
__IO uint32_t MDMA_Channel_TypeDef::CDAR |
MDMA channel x destination address register, Address offset: 0x5C
◆ CESR
__IO uint32_t MDMA_Channel_TypeDef::CESR |
MDMA Channel x error status register, Address offset: 0x48
◆ CIFCR
__IO uint32_t MDMA_Channel_TypeDef::CIFCR |
MDMA channel x interrupt flag clear register, Address offset: 0x44
◆ CISR
__IO uint32_t MDMA_Channel_TypeDef::CISR |
MDMA channel x interrupt/status register, Address offset: 0x40
◆ CLAR
__IO uint32_t MDMA_Channel_TypeDef::CLAR |
MDMA channel x Link Address register, Address offset: 0x64
◆ CMAR
__IO uint32_t MDMA_Channel_TypeDef::CMAR |
MDMA channel x Mask address register, Address offset: 0x70
◆ CMDR
__IO uint32_t MDMA_Channel_TypeDef::CMDR |
MDMA channel x Mask Data register, Address offset: 0x74
◆ CSAR
__IO uint32_t MDMA_Channel_TypeDef::CSAR |
MDMA channel x source address register, Address offset: 0x58
◆ CTBR
__IO uint32_t MDMA_Channel_TypeDef::CTBR |
MDMA channel x Trigger and Bus selection Register, Address offset: 0x68
◆ CTCR
__IO uint32_t MDMA_Channel_TypeDef::CTCR |
MDMA channel x Transfer Configuration register, Address offset: 0x50
◆ RESERVED0
uint32_t MDMA_Channel_TypeDef::RESERVED0 |
The documentation for this struct was generated from the following files: