58#ifndef __ALT_CACHE_H__
59#define __ALT_CACHE_H__
67#if ALT_CPU_DCACHE_SIZE > 0
68#define DCACHE_CLEAN_BY_INDEX_VAL(i) \
69__asm__ volatile(".insn i 0x0F, 0x2, zero, %[i_reg], 0x081" :: [i_reg] "r"(i));
71#define DCACHE_FLUSH_BY_INDEX_VAL(i) \
72__asm__ volatile(".insn i 0x0F, 0x2, zero, %[i_reg], 0x082" :: [i_reg] "r"(i));
74#define DCACHE_INVALIDATE_BY_INDEX_VAL(i) \
75__asm__ volatile(".insn i 0x0F, 0x2, zero, %[i_reg], 0x080" :: [i_reg] "r"(i));
77#define ALT_FLUSH_DATA(i) \
78__asm__ volatile(".option arch, +zicbom\n" "cbo.flush 0(%[addr])" :: [addr] "r"(i))
80#define ALT_INVALIDATE_DATA(i) \
81__asm__ volatile(".option arch, +zicbom\n" "cbo.inval 0(%[addr])" :: [addr] "r"(i))
99static inline void alt_icache_flush (
const void* start, uint32_t len)
101#if ALT_CPU_ICACHE_SIZE > 0
102 __asm__
volatile(
".option arch, +zifencei\n" "fence.i" :::
"memory");
112static inline void alt_dcache_flush (
const void* start, uint32_t len)
114#if ALT_CPU_DCACHE_SIZE > 0
116 const char* end = ((
char*)start) + len;
118 for (i = start; i < end; i+= ALT_CPU_DCACHE_LINE_SIZE) {
127 if (((uint32_t)start) & (ALT_CPU_DCACHE_LINE_SIZE - 1)) {
139static inline void alt_dcache_flush_no_writeback (
144#if ALT_CPU_DCACHE_SIZE > 0
146 const char* end = ((
char*)start) + len;
148 for (i = start; i < end; i+= ALT_CPU_DCACHE_LINE_SIZE) {
149 ALT_INVALIDATE_DATA(i);
157 if (((uint32_t)start) & (ALT_CPU_DCACHE_LINE_SIZE - 1)) {
158 ALT_INVALIDATE_DATA(i);
167static inline void alt_icache_flush_all (
void)
169#if ALT_CPU_ICACHE_SIZE > 0
170 __asm__
volatile(
".option arch, +zifencei\n" "fence.i" :::
"memory");
178static inline void alt_dcache_flush_all (
void)
180#if ALT_CPU_DCACHE_SIZE > 0
184 i < (
char*) ALT_CPU_DCACHE_SIZE;
185 i+= ALT_CPU_DCACHE_LINE_SIZE
187 DCACHE_CLEAN_BY_INDEX_VAL(i);