RTEMS 6.1-rc7
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bsp.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/* bsp.h
12 *
13 * This include file contains all MVME147 board IO definitions.
14 *
15 * COPYRIGHT (c) 1989-1999.
16 * On-Line Applications Research Corporation (OAR).
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions
20 * are met:
21 * 1. Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
28 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
31 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 *
39 * MVME147 port for TNI - Telecom Bretagne
40 * by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr)
41 * May 1996
42 */
43
44#ifndef LIBBSP_M68K_MVME147S_BSP_H
45#define LIBBSP_M68K_MVME147S_BSP_H
46
57#include <bspopts.h>
59
60#include <rtems.h>
61
62#ifdef __cplusplus
63extern "C" {
64#endif
65
66/* Constants */
67
68#define RAM_START 0x00007000
69#define RAM_END 0x003e0000
70#define DRAM_END 0x00400000
71 /* We leave 128k for the shared memory */
72
73 /* MVME 147 Peripheral controller chip
74 see MVME147/D1, 3.4 */
75
76struct pcc_map {
77 /* 32 bit registers */
78 uint32_t dma_table_address; /* 0xfffe1000 */
79 uint32_t dma_data_address; /* 0xfffe1004 */
80 uint32_t dma_bytecount; /* 0xfffe1008 */
81 uint32_t dma_data_holding; /* 0xfffe100c */
82
83 /* 16 bit registers */
84 uint16_t timer1_preload; /* 0xfffe1010 */
85 uint16_t timer1_count; /* 0xfffe1012 */
86 uint16_t timer2_preload; /* 0xfffe1014 */
87 uint16_t timer2_count; /* 0xfffe1016 */
88
89 /* 8 bit registers */
90 uint8_t timer1_int_control; /* 0xfffe1018 */
91 uint8_t timer1_control; /* 0xfffe1019 */
92 uint8_t timer2_int_control; /* 0xfffe101a */
93 uint8_t timer2_control; /* 0xfffe101b */
94
95 uint8_t acfail_int_control; /* 0xfffe101c */
96 uint8_t watchdog_control; /* 0xfffe101d */
97
98 uint8_t printer_int_control; /* 0xfffe101e */
99 uint8_t printer_control; /* 0xfffe102f */
100
101 uint8_t dma_int_control; /* 0xfffe1020 */
102 uint8_t dma_control; /* 0xfffe1021 */
103 uint8_t bus_error_int_control; /* 0xfffe1022 */
104 uint8_t dma_status; /* 0xfffe1023 */
105 uint8_t abort_int_control; /* 0xfffe1024 */
106 uint8_t table_address_function_code; /* 0xfffe1025 */
107 uint8_t serial_port_int_control; /* 0xfffe1026 */
108 uint8_t general_purpose_control; /* 0xfffe1027 */
109 uint8_t lan_int_control; /* 0xfffe1028 */
110 uint8_t general_purpose_status; /* 0xfffe1029 */
111 uint8_t scsi_port_int_control; /* 0xfffe102a */
112 uint8_t slave_base_address; /* 0xfffe102b */
113 uint8_t software_int_1_control; /* 0xfffe102c */
114 uint8_t int_base_vector; /* 0xfffe102d */
115 uint8_t software_int_2_control; /* 0xfffe102e */
116 uint8_t revision_level; /* 0xfffe102f */
117};
118
119#define pcc ((volatile struct pcc_map * const) 0xfffe1000)
120
121/* VME chip configuration registers */
122
124 uint8_t unused_1;
125 uint8_t system_controller; /* 0xfffe2001 */
126 uint8_t unused_2;
127 uint8_t vme_bus_requester; /* 0xfffe2003 */
128 uint8_t unused_3;
129 uint8_t master_configuration; /* 0xfffe2005 */
130 uint8_t unused_4;
131 uint8_t slave_configuration; /* 0xfffe2007 */
132 uint8_t unused_5;
133 uint8_t timer_configuration; /* 0xfffe2009 */
134 uint8_t unused_6;
135 uint8_t slave_address_modifier; /* 0xfffe200b */
136 uint8_t unused_7;
137 uint8_t master_address_modifier; /* 0xfffe200d */
138 uint8_t unused_8;
139 uint8_t interrupt_handler_mask; /* 0xfffe200f */
140 uint8_t unused_9;
141 uint8_t utility_interrupt_mask; /* 0xfffe2011 */
142 uint8_t unused_10;
143 uint8_t utility_interrupt_vector; /* 0xfffe2013 */
144 uint8_t unused_11;
145 uint8_t interrupt_request; /* 0xfffe2015 */
146 uint8_t unused_12;
147 uint8_t vme_bus_status_id; /* 0xfffe2017 */
148 uint8_t unused_13;
149 uint8_t bus_error_status; /* 0xfffe2019 */
150 uint8_t unused_14;
151 uint8_t gcsr_base_address; /* 0xfffe201b */
152};
153
154#define vme_lcsr ((volatile struct vme_lcsr_map * const) 0xfffe2000)
155
157 uint8_t unused_1;
158 uint8_t global_0; /* 0xfffe2021 */
159 uint8_t unused_2;
160 uint8_t global_1; /* 0xfffe2023 */
161 uint8_t unused_3;
162 uint8_t board_identification; /* 0xfffe2025 */
163 uint8_t unused_4;
164 uint8_t general_purpose_0; /* 0xfffe2027 */
165 uint8_t unused_5;
166 uint8_t general_purpose_1; /* 0xfffe2029 */
167 uint8_t unused_6;
168 uint8_t general_purpose_2; /* 0xfffe202b */
169 uint8_t unused_7;
170 uint8_t general_purpose_3; /* 0xfffe202d */
171 uint8_t unused_8;
172 uint8_t general_purpose_4; /* 0xfffe202f */
173};
174
175#define vme_gcsr ((volatile struct vme_gcsr_map * const) 0xfffe2020)
176
177#define z8530 0xfffe3001
178
179/* interrupt vectors - see MVME147/D1 4.14 */
180#define PCC_BASE_VECTOR 0x40 /* First user int */
181#define SCC_VECTOR PCC_BASE_VECTOR+3
182#define TIMER_1_VECTOR PCC_BASE_VECTOR+8
183#define TIMER_2_VECTOR PCC_BASE_VECTOR+9
184#define SOFT_1_VECTOR PCC_BASE_VECTOR+10
185#define SOFT_2_VECTOR PCC_BASE_VECTOR+11
186
187#define VME_BASE_VECTOR 0x50
188#define VME_SIGLP_VECTOR VME_BASE_VECTOR+1
189
190#define USE_CHANNEL_A 1 /* 1 = use channel A for console */
191#define USE_CHANNEL_B 0 /* 1 = use channel B for console */
192
193#if (USE_CHANNEL_A == 1)
194#define CONSOLE_CONTROL 0xfffe3002
195#define CONSOLE_DATA 0xfffe3003
196#elif (USE_CHANNEL_B == 1)
197#define CONSOLE_CONTROL 0xfffe3000
198#define CONSOLE_DATA 0xfffe3001
199#endif
200
201#define FOREVER 1 /* infinite loop */
202
203#ifdef M147_INIT
204#undef EXTERN
205#define EXTERN
206#else
207#undef EXTERN
208#define EXTERN extern
209#endif
210
211extern rtems_isr_entry M68Kvec[]; /* vector table address */
212
213/*
214 * NOTE: Use the standard Clock driver entry
215 */
216
217/* functions */
218
219rtems_isr_entry set_vector(
220 rtems_isr_entry handler,
221 rtems_vector_number vector,
222 int type
223);
224
225#ifdef __cplusplus
226}
227#endif
228
231#endif
This header file provides the default definition of BSP_INITIAL_EXTENSION.
ISR_Handler_entry rtems_isr_entry
Interrupt service routines installed by rtems_interrupt_catch() shall have this type.
Definition: intr.h:134
ISR_Vector_number rtems_vector_number
This integer type represents interrupt vector numbers.
Definition: intr.h:102
This header file defines the RTEMS Classic API.
Definition: bsp.h:74
Definition: bsp.h:156
Definition: bsp.h:123