RTEMS 6.1-rc7
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alt_cache.h
1/*
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2024 Kevin Kirspel
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28/******************************************************************************
29* *
30* License Agreement *
31* *
32* Copyright (c) 2003, 2007 Altera Corporation, San Jose, California, USA. *
33* All rights reserved. *
34* *
35* Permission is hereby granted, free of charge, to any person obtaining a *
36* copy of this software and associated documentation files (the "Software"), *
37* to deal in the Software without restriction, including without limitation *
38* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
39* and/or sell copies of the Software, and to permit persons to whom the *
40* Software is furnished to do so, subject to the following conditions: *
41* *
42* The above copyright notice and this permission notice shall be included in *
43* all copies or substantial portions of the Software. *
44* *
45* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
46* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
47* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
48* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
49* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
50* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
51* DEALINGS IN THE SOFTWARE. *
52* *
53* This agreement shall be governed in all respects by the laws of the State *
54* of California and by the laws of the United States of America. *
55* *
56******************************************************************************/
57
58#ifndef __ALT_CACHE_H__
59#define __ALT_CACHE_H__
60
61/*
62 * Cache maintenance macros
63 * CLEAN - Writeback to memory;
64 * FLUSH - Writeback to memory and invalidate.
65 */
66
67#if ALT_CPU_DCACHE_SIZE > 0
68#define DCACHE_CLEAN_BY_INDEX_VAL(i) \
69__asm__ volatile(".insn i 0x0F, 0x2, zero, %[i_reg], 0x081" :: [i_reg] "r"(i));
70
71#define DCACHE_FLUSH_BY_INDEX_VAL(i) \
72__asm__ volatile(".insn i 0x0F, 0x2, zero, %[i_reg], 0x082" :: [i_reg] "r"(i));
73
74#define DCACHE_INVALIDATE_BY_INDEX_VAL(i) \
75__asm__ volatile(".insn i 0x0F, 0x2, zero, %[i_reg], 0x080" :: [i_reg] "r"(i));
76
77#define ALT_FLUSH_DATA(i) \
78__asm__ volatile(".option arch, +zicbom\n" "cbo.flush 0(%[addr])" :: [addr] "r"(i))
79
80#define ALT_INVALIDATE_DATA(i) \
81__asm__ volatile(".option arch, +zicbom\n" "cbo.inval 0(%[addr])" :: [addr] "r"(i))
82#endif
83
84/*
85 * alt_cache.h defines the processor specific functions for manipulating the
86 * cache.
87 */
88
89#ifdef __cplusplus
90extern "C"
91{
92#endif /* __cplusplus */
93
94/*
95 * alt_icache_flush() is called to flush the instruction cache for a memory
96 * region of length "len" bytes, starting at address "start".
97 */
98
99static inline void alt_icache_flush (const void* start, uint32_t len)
100{
101#if ALT_CPU_ICACHE_SIZE > 0
102 __asm__ volatile(".option arch, +zifencei\n" "fence.i" ::: "memory");
103#endif
104}
105
106/*
107 * alt_dcache_flush() is called to flush the data cache for a memory
108 * region of length "len" bytes, starting at address "start".
109 * Any dirty lines in the data cache are written back to memory.
110 */
111
112static inline void alt_dcache_flush (const void* start, uint32_t len)
113{
114#if ALT_CPU_DCACHE_SIZE > 0
115 const char* i;
116 const char* end = ((char*)start) + len;
117
118 for (i = start; i < end; i+= ALT_CPU_DCACHE_LINE_SIZE) {
119 ALT_FLUSH_DATA(i);
120 }
121
122 /*
123 * For an unaligned flush request, we've got one more line left.
124 * Note that this is dependent on ALT_CPU_DCACHE_LINE_SIZE to be a
125 * multiple of 2 (which it always is).
126 */
127 if (((uint32_t)start) & (ALT_CPU_DCACHE_LINE_SIZE - 1)) {
128 ALT_FLUSH_DATA(i);
129 }
130#endif
131}
132
133/*
134 * alt_dcache_flush() is called to flush the data cache for a memory
135 * region of length "len" bytes, starting at address "start".
136 * Any dirty lines in the data cache are NOT written back to memory.
137 */
138
139static inline void alt_dcache_flush_no_writeback (
140 const void* start,
141 uint32_t len
142)
143{
144#if ALT_CPU_DCACHE_SIZE > 0
145 const char* i;
146 const char* end = ((char*)start) + len;
147
148 for (i = start; i < end; i+= ALT_CPU_DCACHE_LINE_SIZE) {
149 ALT_INVALIDATE_DATA(i);
150 }
151
152 /*
153 * For an unaligned invalidate request, we've got one more line left.
154 * Note that this is dependent on ALT_CPU_DCACHE_LINE_SIZE to be a
155 * multiple of 2 (which it always is).
156 */
157 if (((uint32_t)start) & (ALT_CPU_DCACHE_LINE_SIZE - 1)) {
158 ALT_INVALIDATE_DATA(i);
159 }
160#endif
161}
162
163/*
164 * Flush the entire instruction cache.
165 */
166
167static inline void alt_icache_flush_all (void)
168{
169#if ALT_CPU_ICACHE_SIZE > 0
170 __asm__ volatile(".option arch, +zifencei\n" "fence.i" ::: "memory");
171#endif
172}
173
174/*
175 * Flush the entire data cache.
176 */
177
178static inline void alt_dcache_flush_all (void)
179{
180#if ALT_CPU_DCACHE_SIZE > 0
181 char* i;
182 for (
183 i = (char*)0;
184 i < (char*) ALT_CPU_DCACHE_SIZE;
185 i+= ALT_CPU_DCACHE_LINE_SIZE
186 ) {
187 DCACHE_CLEAN_BY_INDEX_VAL(i);
188 }
189#endif
190}
191
192#ifdef __cplusplus
193}
194#endif
195
196#endif /* __ALT_CACHE_H__ */