RTEMS 6.1-rc7
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cpu.h
Go to the documentation of this file.
1
10/*
11 * COPYRIGHT (c) 1989-2008.
12 * On-Line Applications Research Corporation (OAR).
13 *
14 * The license and distribution terms for this file may be
15 * found in the file LICENSE in this distribution or at
16 * http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
27#include <rtems/score/lm32.h>
28
29/* conditional compilation parameters */
30
42#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
43
53#define CPU_ISR_PASSES_FRAME_POINTER TRUE
54
55#define CPU_HARDWARE_FP FALSE
56
57#define CPU_SOFTWARE_FP FALSE
58
83#define CPU_ALL_TASKS_ARE_FP FALSE
84
100#define CPU_IDLE_TASK_IS_FP FALSE
101
131#define CPU_USE_DEFERRED_FP_SWITCH TRUE
132
133#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
134
146#define CPU_STACK_GROWS_UP FALSE
147
148/* L2 cache lines are 32 bytes in Milkymist SoC */
149#define CPU_CACHE_LINE_BYTES 32
150
151#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
152
163#define CPU_MODES_INTERRUPT_MASK 0x00000001
164
165#define CPU_MAXIMUM_PROCESSORS 32
166
167/*
168 * Processor defined structures required for cpukit/score.
169 *
170 * Port Specific Information:
171 *
172 * XXX document implementation including references if appropriate
173 */
174
175/* may need to put some structures here. */
176
227typedef struct {
228 uint32_t r11;
229 uint32_t r12;
230 uint32_t r13;
231 uint32_t r14;
232 uint32_t r15;
233 uint32_t r16;
234 uint32_t r17;
235 uint32_t r18;
236 uint32_t r19;
237 uint32_t r20;
238 uint32_t r21;
239 uint32_t r22;
240 uint32_t r23;
241 uint32_t r24;
242 uint32_t r25;
243 uint32_t gp;
244 uint32_t fp;
245 uint32_t sp;
246 uint32_t ra;
247 uint32_t ie;
248 uint32_t epc;
250
259#define _CPU_Context_Get_SP( _context ) \
260 (_context)->sp
261
267typedef struct {
268 uint32_t r1;
269 uint32_t r2;
270 uint32_t r3;
271 uint32_t r4;
272 uint32_t r5;
273 uint32_t r6;
274 uint32_t r7;
275 uint32_t r8;
276 uint32_t r9;
277 uint32_t r10;
278 uint32_t ra;
279 uint32_t ba;
280 uint32_t ea;
282
293#if 0
294extern Context_Control_fp _CPU_Null_fp_context;
295#endif
296
307/*
308 * Nothing prevents the porter from declaring more CPU specific variables.
309 *
310 * Port Specific Information:
311 *
312 * XXX document implementation including references if appropriate
313 */
314
315/* XXX: if needed, put more variables here */
316
327#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
328
338#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
339
344#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
345
351#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
352
353
363#define CPU_STACK_MINIMUM_SIZE (1024*4)
364
365#define CPU_SIZEOF_POINTER 4
366
377#define CPU_ALIGNMENT 4
378
402#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
403
404#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
405
406#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
407
408/*
409 * ISR handler macros
410 */
411
427#define _CPU_ISR_Disable( _isr_cookie ) \
428 lm32_disable_interrupts( _isr_cookie );
429
441#define _CPU_ISR_Enable( _isr_cookie ) \
442 lm32_enable_interrupts( _isr_cookie );
443
456#define _CPU_ISR_Flash( _isr_cookie ) \
457 lm32_flash_interrupts( _isr_cookie );
458
459static inline bool _CPU_ISR_Is_enabled( uint32_t level )
460{
461 return ( level & 0x0001 ) != 0;
462}
463
479#define _CPU_ISR_Set_level( new_level ) \
480 { \
481 _CPU_ISR_Enable( ( new_level==0 ) ? 1 : 0 ); \
482 }
483
494uint32_t _CPU_ISR_Get_level( void );
495
496/* end of ISR handler macros */
497
500/* Context handler macros */
501
533extern char _gp[];
534
535#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
536 _isr, _entry_point, _is_fp, _tls_area ) \
537 do { \
538 uint32_t _stack = (uint32_t)(_stack_base) + (_size) - 4; \
539 \
540 (void) _is_fp; /* avoid warning for being unused */ \
541 (void) _isr; /* avoid warning for being unused */ \
542 (_the_context)->gp = (uint32_t)_gp; \
543 (_the_context)->fp = (uint32_t)_stack; \
544 (_the_context)->sp = (uint32_t)_stack; \
545 (_the_context)->ra = (uint32_t)(_entry_point); \
546 } while ( 0 )
547
563#define _CPU_Context_Restart_self( _the_context ) \
564 _CPU_Context_restore( (_the_context) );
565
584#define _CPU_Context_Initialize_fp( _destination )
585#if 0
586 { \
587 *(*(_destination)) = _CPU_Null_fp_context; \
588 }
589#endif
590
591/* end of Context handler macros */
592
593#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
594
595#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
596
597/* functions */
598
606void _CPU_Initialize(void);
607
613typedef void ( *CPU_ISR_raw_handler )( void );
614
615static inline void _CPU_ISR_install_raw_handler(
616 uint32_t vector,
617 CPU_ISR_raw_handler new_handler,
618 CPU_ISR_raw_handler *old_handler
619)
620{
621 /* TODO */
622}
623
624typedef void ( *CPU_ISR_handler )( uint32_t );
625
627 uint32_t vector,
628 CPU_ISR_handler new_handler,
629 CPU_ISR_handler *old_handler
630);
631
634RTEMS_NO_RETURN void *_CPU_Thread_Idle_body( uintptr_t ignored );
635
648 Context_Control *run,
649 Context_Control *heir
650);
651
669RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context );
670
673/* FIXME */
675
677
714static inline uint32_t CPU_swap_u32(
715 uint32_t value
716)
717{
718 uint32_t byte1, byte2, byte3, byte4, swapped;
719
720 byte4 = (value >> 24) & 0xff;
721 byte3 = (value >> 16) & 0xff;
722 byte2 = (value >> 8) & 0xff;
723 byte1 = value & 0xff;
724
725 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
726 return swapped;
727}
728
735static inline uint16_t CPU_swap_u16(uint16_t v)
736{
737 return v << 8 | v >> 8;
738}
739
742typedef uint32_t CPU_Counter_ticks;
743
744uint32_t _CPU_Counter_frequency( void );
745
746CPU_Counter_ticks _CPU_Counter_read( void );
747
749typedef uintptr_t CPU_Uint32ptr;
750
751#ifdef __cplusplus
752}
753#endif
754
755#endif
This header file provides basic definitions used by the API and the implementation.
void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.c:100
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
#define CPU_swap_u16(value)
Definition: cpu.h:597
#define ra
return address *‍/
Definition: regs.h:66
#define sp
stack-pointer *‍/
Definition: regs.h:64
#define fp
frame-pointer *‍/
Definition: regs.h:65
#define gp
global data pointer *‍/
Definition: regs.h:63
LM32 Set up Basic CPU Dependency Settings Based on Compiler Settings.
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
SPARC basic context.
Definition: cpu.h:213
Thread register context.
Definition: cpu.h:173
unsigned ie
Definition: tte.h:3