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RTEMS 6.1-rc7
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DSI Controller. More...
#include <stm32h747xg.h>
Data Fields | |
__IO uint32_t | VR |
__IO uint32_t | CR |
__IO uint32_t | CCR |
__IO uint32_t | LVCIDR |
__IO uint32_t | LCOLCR |
__IO uint32_t | LPCR |
__IO uint32_t | LPMCR |
uint32_t | RESERVED0 [4] |
__IO uint32_t | PCR |
__IO uint32_t | GVCIDR |
__IO uint32_t | MCR |
__IO uint32_t | VMCR |
__IO uint32_t | VPCR |
__IO uint32_t | VCCR |
__IO uint32_t | VNPCR |
__IO uint32_t | VHSACR |
__IO uint32_t | VHBPCR |
__IO uint32_t | VLCR |
__IO uint32_t | VVSACR |
__IO uint32_t | VVBPCR |
__IO uint32_t | VVFPCR |
__IO uint32_t | VVACR |
__IO uint32_t | LCCR |
__IO uint32_t | CMCR |
__IO uint32_t | GHCR |
__IO uint32_t | GPDR |
__IO uint32_t | GPSR |
__IO uint32_t | TCCR [6] |
__IO uint32_t | TDCR |
__IO uint32_t | CLCR |
__IO uint32_t | CLTCR |
__IO uint32_t | DLTCR |
__IO uint32_t | PCTLR |
__IO uint32_t | PCONFR |
__IO uint32_t | PUCR |
__IO uint32_t | PTTCR |
__IO uint32_t | PSR |
uint32_t | RESERVED1 [2] |
__IO uint32_t | ISR [2] |
__IO uint32_t | IER [2] |
uint32_t | RESERVED2 [3] |
__IO uint32_t | FIR [2] |
uint32_t | RESERVED3 [8] |
__IO uint32_t | VSCR |
uint32_t | RESERVED4 [2] |
__IO uint32_t | LCVCIDR |
__IO uint32_t | LCCCR |
uint32_t | RESERVED5 |
__IO uint32_t | LPMCCR |
uint32_t | RESERVED6 [7] |
__IO uint32_t | VMCCR |
__IO uint32_t | VPCCR |
__IO uint32_t | VCCCR |
__IO uint32_t | VNPCCR |
__IO uint32_t | VHSACCR |
__IO uint32_t | VHBPCCR |
__IO uint32_t | VLCCR |
__IO uint32_t | VVSACCR |
__IO uint32_t | VVBPCCR |
__IO uint32_t | VVFPCCR |
__IO uint32_t | VVACCR |
uint32_t | RESERVED7 [11] |
__IO uint32_t | TDCCR |
uint32_t | RESERVED8 [155] |
__IO uint32_t | WCFGR |
__IO uint32_t | WCR |
__IO uint32_t | WIER |
__IO uint32_t | WISR |
__IO uint32_t | WIFCR |
uint32_t | RESERVED9 |
__IO uint32_t | WPCR [5] |
uint32_t | RESERVED10 |
__IO uint32_t | WRPCR |
DSI Controller.
__IO uint32_t DSI_TypeDef::CCR |
DSI HOST Clock Control Register, Address offset: 0x08
__IO uint32_t DSI_TypeDef::CLCR |
DSI Host Clock Lane Configuration Register, Address offset: 0x94
__IO uint32_t DSI_TypeDef::CLTCR |
DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98
__IO uint32_t DSI_TypeDef::CMCR |
DSI Host Command Mode Configuration Register, Address offset: 0x68
__IO uint32_t DSI_TypeDef::CR |
DSI Host Control Register, Address offset: 0x04
__IO uint32_t DSI_TypeDef::DLTCR |
DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C
__IO uint32_t DSI_TypeDef::FIR |
DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF
__IO uint32_t DSI_TypeDef::GHCR |
DSI Host Generic Header Configuration Register, Address offset: 0x6C
__IO uint32_t DSI_TypeDef::GPDR |
DSI Host Generic Payload Data Register, Address offset: 0x70
__IO uint32_t DSI_TypeDef::GPSR |
DSI Host Generic Packet Status Register, Address offset: 0x74
__IO uint32_t DSI_TypeDef::GVCIDR |
DSI Host Generic VCID Register, Address offset: 0x30
__IO uint32_t DSI_TypeDef::IER |
DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB
__IO uint32_t DSI_TypeDef::ISR |
DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3
__IO uint32_t DSI_TypeDef::LCCCR |
DSI Host LTDC Current Color Coding Register, Address offset: 0x110
__IO uint32_t DSI_TypeDef::LCCR |
DSI Host LTDC Command Configuration Register, Address offset: 0x64
__IO uint32_t DSI_TypeDef::LCOLCR |
DSI Host LTDC Color Coding Register, Address offset: 0x10
__IO uint32_t DSI_TypeDef::LCVCIDR |
DSI Host LTDC Current VCID Register, Address offset: 0x10C
__IO uint32_t DSI_TypeDef::LPCR |
DSI Host LTDC Polarity Configuration Register, Address offset: 0x14
__IO uint32_t DSI_TypeDef::LPMCCR |
DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118
__IO uint32_t DSI_TypeDef::LPMCR |
DSI Host Low-Power Mode Configuration Register, Address offset: 0x18
__IO uint32_t DSI_TypeDef::LVCIDR |
DSI Host LTDC VCID Register, Address offset: 0x0C
__IO uint32_t DSI_TypeDef::MCR |
DSI Host Mode Configuration Register, Address offset: 0x34
__IO uint32_t DSI_TypeDef::PCONFR |
DSI Host PHY Configuration Register, Address offset: 0xA4
__IO uint32_t DSI_TypeDef::PCR |
DSI Host Protocol Configuration Register, Address offset: 0x2C
__IO uint32_t DSI_TypeDef::PCTLR |
DSI Host PHY Control Register, Address offset: 0xA0
__IO uint32_t DSI_TypeDef::PSR |
DSI Host PHY Status Register, Address offset: 0xB0
__IO uint32_t DSI_TypeDef::PTTCR |
DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC
__IO uint32_t DSI_TypeDef::PUCR |
DSI Host PHY ULPS Control Register, Address offset: 0xA8
uint32_t DSI_TypeDef::RESERVED0 |
Reserved, 0x1C - 0x2B
uint32_t DSI_TypeDef::RESERVED1 |
Reserved, 0xB4 - 0xBB
uint32_t DSI_TypeDef::RESERVED10 |
Reserved, 0x42C
uint32_t DSI_TypeDef::RESERVED2 |
Reserved, 0xD0 - 0xD7
uint32_t DSI_TypeDef::RESERVED3 |
Reserved, 0xE0 - 0xFF
uint32_t DSI_TypeDef::RESERVED4 |
Reserved, 0x104 - 0x10B
uint32_t DSI_TypeDef::RESERVED5 |
Reserved, 0x114
uint32_t DSI_TypeDef::RESERVED6 |
Reserved, 0x11C - 0x137
uint32_t DSI_TypeDef::RESERVED7 |
Reserved, 0x164 - 0x18F
uint32_t DSI_TypeDef::RESERVED8 |
Reserved, 0x194 - 0x3FF
uint32_t DSI_TypeDef::RESERVED9 |
Reserved, 0x414
__IO uint32_t DSI_TypeDef::TCCR |
DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F
__IO uint32_t DSI_TypeDef::TDCCR |
DSI Host 3D Current Configuration Register, Address offset: 0x190
__IO uint32_t DSI_TypeDef::TDCR |
DSI Host 3D Configuration Register, Address offset: 0x90
__IO uint32_t DSI_TypeDef::VCCCR |
DSI Host Video Chunks Current Configuration Register, Address offset: 0x140
__IO uint32_t DSI_TypeDef::VCCR |
DSI Host Video Chunks Configuration Register, Address offset: 0x40
__IO uint32_t DSI_TypeDef::VHBPCCR |
DSI Host Video HBP Current Configuration Register, Address offset: 0x14C
__IO uint32_t DSI_TypeDef::VHBPCR |
DSI Host Video HBP Configuration Register, Address offset: 0x4C
__IO uint32_t DSI_TypeDef::VHSACCR |
DSI Host Video HSA Current Configuration Register, Address offset: 0x148
__IO uint32_t DSI_TypeDef::VHSACR |
DSI Host Video HSA Configuration Register, Address offset: 0x48
__IO uint32_t DSI_TypeDef::VLCCR |
DSI Host Video Line Current Configuration Register, Address offset: 0x150
__IO uint32_t DSI_TypeDef::VLCR |
DSI Host Video Line Configuration Register, Address offset: 0x50
__IO uint32_t DSI_TypeDef::VMCCR |
DSI Host Video Mode Current Configuration Register, Address offset: 0x138
__IO uint32_t DSI_TypeDef::VMCR |
DSI Host Video Mode Configuration Register, Address offset: 0x38
__IO uint32_t DSI_TypeDef::VNPCCR |
DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144
__IO uint32_t DSI_TypeDef::VNPCR |
DSI Host Video Null Packet Configuration Register, Address offset: 0x44
__IO uint32_t DSI_TypeDef::VPCCR |
DSI Host Video Packet Current Configuration Register, Address offset: 0x13C
__IO uint32_t DSI_TypeDef::VPCR |
DSI Host Video Packet Configuration Register, Address offset: 0x3C
__IO uint32_t DSI_TypeDef::VR |
DSI Host Version Register, Address offset: 0x00
__IO uint32_t DSI_TypeDef::VSCR |
DSI Host Video Shadow Control Register, Address offset: 0x100
__IO uint32_t DSI_TypeDef::VVACCR |
DSI Host Video VA Current Configuration Register, Address offset: 0x160
__IO uint32_t DSI_TypeDef::VVACR |
DSI Host Video VA Configuration Register, Address offset: 0x60
__IO uint32_t DSI_TypeDef::VVBPCCR |
DSI Host Video VBP Current Configuration Register, Address offset: 0x158
__IO uint32_t DSI_TypeDef::VVBPCR |
DSI Host Video VBP Configuration Register, Address offset: 0x58
__IO uint32_t DSI_TypeDef::VVFPCCR |
DSI Host Video VFP Current Configuration Register, Address offset: 0x15C
__IO uint32_t DSI_TypeDef::VVFPCR |
DSI Host Video VFP Configuration Register, Address offset: 0x5C
__IO uint32_t DSI_TypeDef::VVSACCR |
DSI Host Video VSA Current Configuration Register, Address offset: 0x154
__IO uint32_t DSI_TypeDef::VVSACR |
DSI Host Video VSA Configuration Register, Address offset: 0x54
__IO uint32_t DSI_TypeDef::WCFGR |
DSI Wrapper Configuration Register, Address offset: 0x400
__IO uint32_t DSI_TypeDef::WCR |
DSI Wrapper Control Register, Address offset: 0x404
__IO uint32_t DSI_TypeDef::WIER |
DSI Wrapper Interrupt Enable Register, Address offset: 0x408
__IO uint32_t DSI_TypeDef::WIFCR |
DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410
__IO uint32_t DSI_TypeDef::WISR |
DSI Wrapper Interrupt and Status Register, Address offset: 0x40C
__IO uint32_t DSI_TypeDef::WPCR |
DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B
__IO uint32_t DSI_TypeDef::WRPCR |
DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430