37#ifndef _RTEMS_SCORE_CPU_H
38#define _RTEMS_SCORE_CPU_H
43#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
45#define CPU_ISR_PASSES_FRAME_POINTER FALSE
47#define CPU_HARDWARE_FP FALSE
49#define CPU_SOFTWARE_FP FALSE
51#define CPU_ALL_TASKS_ARE_FP FALSE
53#define CPU_IDLE_TASK_IS_FP FALSE
55#define CPU_USE_DEFERRED_FP_SWITCH FALSE
57#define CPU_STACK_GROWS_UP FALSE
62#define CPU_CACHE_LINE_BYTES 64
64#define CPU_STRUCTURE_ALIGNMENT
66#define CPU_MODES_INTERRUPT_MASK 0x00000001
68#define MICROBLAZE_EXCEPTION_FRAME_R1 0
69#define MICROBLAZE_EXCEPTION_FRAME_R2 4
70#define MICROBLAZE_EXCEPTION_FRAME_R3 8
71#define MICROBLAZE_EXCEPTION_FRAME_R4 12
72#define MICROBLAZE_EXCEPTION_FRAME_R5 16
73#define MICROBLAZE_EXCEPTION_FRAME_R6 20
74#define MICROBLAZE_EXCEPTION_FRAME_R7 24
75#define MICROBLAZE_EXCEPTION_FRAME_R8 28
76#define MICROBLAZE_EXCEPTION_FRAME_R9 32
77#define MICROBLAZE_EXCEPTION_FRAME_R10 36
78#define MICROBLAZE_EXCEPTION_FRAME_R11 40
79#define MICROBLAZE_EXCEPTION_FRAME_R12 44
80#define MICROBLAZE_EXCEPTION_FRAME_R13 48
81#define MICROBLAZE_EXCEPTION_FRAME_R14 52
82#define MICROBLAZE_EXCEPTION_FRAME_R15 56
83#define MICROBLAZE_EXCEPTION_FRAME_R16 60
84#define MICROBLAZE_EXCEPTION_FRAME_R17 64
85#define MICROBLAZE_EXCEPTION_FRAME_R18 68
86#define MICROBLAZE_EXCEPTION_FRAME_R19 72
87#define MICROBLAZE_EXCEPTION_FRAME_R20 76
88#define MICROBLAZE_EXCEPTION_FRAME_R21 80
89#define MICROBLAZE_EXCEPTION_FRAME_R22 84
90#define MICROBLAZE_EXCEPTION_FRAME_R23 88
91#define MICROBLAZE_EXCEPTION_FRAME_R24 92
92#define MICROBLAZE_EXCEPTION_FRAME_R25 96
93#define MICROBLAZE_EXCEPTION_FRAME_R26 100
94#define MICROBLAZE_EXCEPTION_FRAME_R27 104
95#define MICROBLAZE_EXCEPTION_FRAME_R28 108
96#define MICROBLAZE_EXCEPTION_FRAME_R29 112
97#define MICROBLAZE_EXCEPTION_FRAME_R30 116
98#define MICROBLAZE_EXCEPTION_FRAME_R31 120
99#define MICROBLAZE_EXCEPTION_FRAME_MSR 124
100#define MICROBLAZE_EXCEPTION_FRAME_EAR 128
101#define MICROBLAZE_EXCEPTION_FRAME_ESR 132
102#define MICROBLAZE_EXCEPTION_FRAME_BTR 136
104#define CPU_EXCEPTION_FRAME_SIZE 140
140 void *thread_pointer;
152#define _CPU_Context_Get_SP( _context ) \
155#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
157#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
159#define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE
161#define CPU_MAXIMUM_PROCESSORS 32
167#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
169#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
171#define CPU_STACK_MINIMUM_SIZE (1024*4)
173#define CPU_ALIGNMENT 4
175#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
177#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
179#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
185#define MICROBLAZE_MSR_VM ( 1 << 13 )
186#define MICROBLAZE_MSR_UM ( 1 << 11 )
187#define MICROBLAZE_MSR_PVR ( 1 << 10 )
188#define MICROBLAZE_MSR_EIP ( 1 << 9 )
189#define MICROBLAZE_MSR_EE ( 1 << 8 )
190#define MICROBLAZE_MSR_DCE ( 1 << 7 )
191#define MICROBLAZE_MSR_DZO ( 1 << 6 )
192#define MICROBLAZE_MSR_ICE ( 1 << 5 )
193#define MICROBLAZE_MSR_FSL ( 1 << 4 )
194#define MICROBLAZE_MSR_BIP ( 1 << 3 )
195#define MICROBLAZE_MSR_C ( 1 << 2 )
196#define MICROBLAZE_MSR_IE ( 1 << 1 )
198#define MICROBLAZE_ESR_DS ( 1 << 12 )
199#define MICROBLAZE_ESR_EC_MASK 0x1f
200#define MICROBLAZE_ESR_ESS_MASK 0x7f
201#define MICROBLAZE_ESR_ESS_SHIFT 5
203#define _CPU_MSR_GET( _msr_value ) \
206 __asm__ volatile ("mfs %0, rmsr" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
209#define _CPU_MSR_SET( _msr_value ) \
210{ __asm__ volatile ("mts rmsr, %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
212#define MICROBLAZE_PVR0_VERSION_GET( _pvr0_value ) \
213 ( ( _pvr0_value >> 8 ) & 0xff )
215#define _CPU_PVR0_GET( _pvr0_value ) \
217 ( _pvr0_value ) = 0; \
218 __asm__ volatile ( "mfs %0, rpvr0" : "=&r" ( ( _pvr0_value ) ) ); \
221#define MICROBLAZE_PVR3_BP_GET( _pvr3_value ) \
222 ( ( _pvr3_value >> 25 ) & 0xf )
224#define MICROBLAZE_PVR3_RWP_GET( _pvr3_value ) \
225 ( ( _pvr3_value >> 19 ) & 0x7 )
227#define MICROBLAZE_PVR3_WWP_GET( _pvr3_value ) \
228 ( ( _pvr3_value >> 13 ) & 0x7 )
230#define _CPU_PVR3_GET( _pvr3_value ) \
232 ( _pvr3_value ) = 0; \
233 __asm__ volatile ( "mfs %0, rpvr3" : "=&r" ( ( _pvr3_value ) ) ); \
236#define _CPU_ISR_Disable( _isr_cookie ) \
238 unsigned int _new_msr; \
239 _CPU_MSR_GET(_isr_cookie); \
240 _new_msr = (_isr_cookie) & ~(MICROBLAZE_MSR_IE); \
241 _CPU_MSR_SET(_new_msr); \
244#define _CPU_ISR_Enable( _isr_cookie ) \
246 uint32_t _microblaze_interrupt_enable; \
247 uint32_t _microblaze_switch_reg; \
249 _microblaze_interrupt_enable = (_isr_cookie) & (MICROBLAZE_MSR_IE); \
250 _CPU_MSR_GET(_microblaze_switch_reg); \
251 _microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE); \
252 _microblaze_switch_reg |= _microblaze_interrupt_enable; \
253 _CPU_MSR_SET(_microblaze_switch_reg); \
256#define _CPU_ISR_Flash( _isr_cookie ) \
258 unsigned int _new_msr; \
259 _CPU_MSR_SET(_isr_cookie); \
260 _new_msr = (_isr_cookie) & ~(MICROBLAZE_MSR_IE); \
261 _CPU_MSR_SET(_new_msr); \
268static inline bool _CPU_ISR_Is_enabled( uint32_t level )
270 return ( level & MICROBLAZE_MSR_IE ) != 0;
273void _CPU_Context_Initialize(
275 void *stack_area_begin,
276 size_t stack_area_size,
278 void (*entry_point)(
void ),
283#define _CPU_Context_Restart_self( _the_context ) \
284 _CPU_Context_restore( (_the_context) );
286#define _CPU_Context_Initialize_fp( _destination ) \
288 *(*(_destination)) = _CPU_Null_fp_context; \
295#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
297#define CPU_SIZEOF_POINTER 4
299#define CPU_PER_CPU_CONTROL_SIZE 0
346typedef void ( *CPU_ISR_handler )( uint32_t );
350 CPU_ISR_handler new_handler,
351 CPU_ISR_handler *old_handler
356void _MicroBlaze_Exception_install_handler(
357 MicroBlaze_Exception_handler new_handler,
358 MicroBlaze_Exception_handler *old_handler
361void _MicroBlaze_Exception_handle(
365void _MicroBlaze_Debug_install_handler(
366 MicroBlaze_Exception_handler new_handler,
367 MicroBlaze_Exception_handler *old_handler
370void _MicroBlaze_Debug_handle(
398void _CPU_Exception_disable_thread_dispatch(
void );
402void _CPU_Exception_frame_set_resume(
407void _CPU_Exception_frame_make_resume_next_instruction(
417static inline uint32_t CPU_swap_u32(
421 uint32_t byte1, byte2, byte3, byte4, swapped;
423 byte4 = (value >> 24) & 0xff;
424 byte3 = (value >> 16) & 0xff;
425 byte2 = (value >> 8) & 0xff;
426 byte1 = value & 0xff;
428 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
432#define CPU_swap_u16( value ) \
433 (((value&0xff) << 8) | ((value >> 8)&0xff))
437typedef uint32_t CPU_Counter_ticks;
445void bsp_interrupt_dispatch( uint32_t source );
This header file provides basic definitions used by the API and the implementation.
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
#define _CPU_ISR_Set_level(_new_level)
Definition: cpu.h:378
MicroBlaze architecture support.
rtems_termios_device_context * context
Definition: console-config.c:62
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Thread register context.
Definition: cpu.h:173