RTEMS 6.1-rc7
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cpu.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
12/*
13 *
14 *
15 * COPYRIGHT (c) 1989-2006. On-Line Applications Research Corporation (OAR).
16 *
17 * This file is based on the SPARC cpu.h file. Modifications are made
18 * to support the SPARC64 processor.
19 * COPYRIGHT (c) 2010. Gedare Bloom.
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions
23 * are met:
24 * 1. Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * 2. Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
34 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
35 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
36 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
37 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
38 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGE.
41 */
42
43#ifndef _RTEMS_SCORE_CPU_H
44#define _RTEMS_SCORE_CPU_H
45
46#ifdef __cplusplus
47extern "C" {
48#endif
49
51#include <rtems/score/sparc64.h>
52
53/* conditional compilation parameters */
54
55/*
56 * Does the CPU follow the simple vectored interrupt model?
57 *
58 * If TRUE, then RTEMS allocates the vector table it internally manages.
59 * If FALSE, then the BSP is assumed to allocate and manage the vector
60 * table
61 *
62 * SPARC Specific Information:
63 *
64 * XXX document implementation including references if appropriate
65 */
66#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
67
68/*
69 * Does the RTEMS invoke the user's ISR with the vector number and
70 * a pointer to the saved interrupt frame (1) or just the vector
71 * number (0)?
72 */
73
74#define CPU_ISR_PASSES_FRAME_POINTER FALSE
75
76/*
77 * Does the CPU have hardware floating point?
78 *
79 * If TRUE, then the FLOATING_POINT task attribute is supported.
80 * If FALSE, then the FLOATING_POINT task attribute is ignored.
81 */
82
83#if ( SPARC_HAS_FPU == 1 )
84#define CPU_HARDWARE_FP TRUE
85#else
86#define CPU_HARDWARE_FP FALSE
87#endif
88#define CPU_SOFTWARE_FP FALSE
89
90/*
91 * Are all tasks FLOATING_POINT tasks implicitly?
92 *
93 * If TRUE, then the FLOATING_POINT task attribute is assumed.
94 * If FALSE, then the FLOATING_POINT task attribute is followed.
95 */
96
97#define CPU_ALL_TASKS_ARE_FP FALSE
98
99/*
100 * Should the IDLE task have a floating point context?
101 *
102 * If TRUE, then the IDLE task is created as a FLOATING_POINT task
103 * and it has a floating point context which is switched in and out.
104 * If FALSE, then the IDLE task does not have a floating point context.
105 */
106
107#define CPU_IDLE_TASK_IS_FP FALSE
108
109/*
110 * Should the saving of the floating point registers be deferred
111 * until a context switch is made to another different floating point
112 * task?
113 *
114 * If TRUE, then the floating point context will not be stored until
115 * necessary. It will remain in the floating point registers and not
116 * disturned until another floating point task is switched to.
117 *
118 * If FALSE, then the floating point context is saved when a floating
119 * point task is switched out and restored when the next floating point
120 * task is restored. The state of the floating point registers between
121 * those two operations is not specified.
122 */
123
124#define CPU_USE_DEFERRED_FP_SWITCH TRUE
125
126#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
127
128/*
129 * Does the stack grow up (toward higher addresses) or down
130 * (toward lower addresses)?
131 *
132 * If TRUE, then the grows upward.
133 * If FALSE, then the grows toward smaller addresses.
134 *
135 * The stack grows to lower addresses on the SPARC.
136 */
137
138#define CPU_STACK_GROWS_UP FALSE
139
140/* FIXME: Is this the right value? */
141#define CPU_CACHE_LINE_BYTES 32
142
143/*
144 * The following is the variable attribute used to force alignment
145 * of critical data structures. On some processors it may make
146 * sense to have these aligned on tighter boundaries than
147 * the minimum requirements of the compiler in order to have as
148 * much of the critical data area as possible in a cache line.
149 *
150 * The SPARC does not appear to have particularly strict alignment
151 * requirements. This value (16) was chosen to take advantages of caches.
152 *
153 * SPARC 64 requirements on floating point alignment is at least 8,
154 * and is 16 if quad-word fp instructions are available (e.g. LDQF).
155 */
156
157#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( 16 )
158
159/*
160 * The following defines the number of bits actually used in the
161 * interrupt field of the task mode. How those bits map to the
162 * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
163 *
164 * The SPARC v9 has 16 interrupt levels in the PIL field of the PSR.
165 */
166
167#define CPU_MODES_INTERRUPT_MASK 0x0000000F
168
169#define CPU_MAXIMUM_PROCESSORS 32
170
171/*
172 * This structure represents the organization of the minimum stack frame
173 * for the SPARC. More framing information is required in certain situaions
174 * such as when there are a large number of out parameters or when the callee
175 * must save floating point registers.
176 */
177
178#ifndef ASM
179
180typedef struct {
181 uint64_t l0;
182 uint64_t l1;
183 uint64_t l2;
184 uint64_t l3;
185 uint64_t l4;
186 uint64_t l5;
187 uint64_t l6;
188 uint64_t l7;
189 uint64_t i0;
190 uint64_t i1;
191 uint64_t i2;
192 uint64_t i3;
193 uint64_t i4;
194 uint64_t i5;
195 uint64_t i6_fp;
196 uint64_t i7;
197 void *structure_return_address;
198 /*
199 * The following are for the callee to save the register arguments in
200 * should this be necessary.
201 */
202 uint64_t saved_arg0;
203 uint64_t saved_arg1;
204 uint64_t saved_arg2;
205 uint64_t saved_arg3;
206 uint64_t saved_arg4;
207 uint64_t saved_arg5;
208 uint64_t pad0;
210
211#endif /* !ASM */
212
213#define CPU_STACK_FRAME_L0_OFFSET 0x00
214#define CPU_STACK_FRAME_L1_OFFSET 0x08
215#define CPU_STACK_FRAME_L2_OFFSET 0x10
216#define CPU_STACK_FRAME_L3_OFFSET 0x18
217#define CPU_STACK_FRAME_L4_OFFSET 0x20
218#define CPU_STACK_FRAME_L5_OFFSET 0x28
219#define CPU_STACK_FRAME_L6_OFFSET 0x30
220#define CPU_STACK_FRAME_L7_OFFSET 0x38
221#define CPU_STACK_FRAME_I0_OFFSET 0x40
222#define CPU_STACK_FRAME_I1_OFFSET 0x48
223#define CPU_STACK_FRAME_I2_OFFSET 0x50
224#define CPU_STACK_FRAME_I3_OFFSET 0x58
225#define CPU_STACK_FRAME_I4_OFFSET 0x60
226#define CPU_STACK_FRAME_I5_OFFSET 0x68
227#define CPU_STACK_FRAME_I6_FP_OFFSET 0x70
228#define CPU_STACK_FRAME_I7_OFFSET 0x78
229#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x80
230#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x88
231#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x90
232#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x98
233#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0xA0
234#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0xA8
235#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0xB0
236#define CPU_STACK_FRAME_PAD0_OFFSET 0xB8
237
238#define SPARC64_MINIMUM_STACK_FRAME_SIZE 0xC0
239
240/*
241 * Contexts
242 *
243 * Generally there are 2 types of context to save.
244 * 1. Interrupt registers to save
245 * 2. Task level registers to save
246 *
247 * This means we have the following 3 context items:
248 * 1. task level context stuff:: Context_Control
249 * 2. floating point task stuff:: Context_Control_fp
250 * 3. special interrupt level context :: Context_Control_interrupt
251 *
252 * On the SPARC, we are relatively conservative in that we save most
253 * of the CPU state in the context area. The ET (enable trap) bit and
254 * the CWP (current window pointer) fields of the PSR are considered
255 * system wide resources and are not maintained on a per-thread basis.
256 */
257
258#ifndef ASM
259
260typedef struct {
261 uint64_t g1;
262 uint64_t g2;
263 uint64_t g3;
264 uint64_t g4;
265 uint64_t g5;
266 uint64_t g6;
267 uint64_t g7;
268
269 uint64_t l0;
270 uint64_t l1;
271 uint64_t l2;
272 uint64_t l3;
273 uint64_t l4;
274 uint64_t l5;
275 uint64_t l6;
276 uint64_t l7;
277
278 uint64_t i0;
279 uint64_t i1;
280 uint64_t i2;
281 uint64_t i3;
282 uint64_t i4;
283 uint64_t i5;
284 uint64_t i6_fp;
285 uint64_t i7;
286
287 uint64_t o0;
288 uint64_t o1;
289 uint64_t o2;
290 uint64_t o3;
291 uint64_t o4;
292 uint64_t o5;
293 uint64_t o6_sp;
294 uint64_t o7;
295
296 uint32_t isr_dispatch_disable;
297 uint32_t pad;
299
300#define _CPU_Context_Get_SP( _context ) \
301 (_context)->o6_sp
302
303#endif /* ASM */
304
305/*
306 * Offsets of fields with Context_Control for assembly routines.
307 */
308
309#define G1_OFFSET 0x00
310#define G2_OFFSET 0x08
311#define G3_OFFSET 0x10
312#define G4_OFFSET 0x18
313#define G5_OFFSET 0x20
314#define G6_OFFSET 0x28
315#define G7_OFFSET 0x30
316
317#define L0_OFFSET 0x38
318#define L1_OFFSET 0x40
319#define L2_OFFSET 0x48
320#define L3_OFFSET 0x50
321#define L4_OFFSET 0x58
322#define L5_OFFSET 0x60
323#define L6_OFFSET 0x68
324#define L7_OFFSET 0x70
325
326#define I0_OFFSET 0x78
327#define I1_OFFSET 0x80
328#define I2_OFFSET 0x88
329#define I3_OFFSET 0x90
330#define I4_OFFSET 0x98
331#define I5_OFFSET 0xA0
332#define I6_FP_OFFSET 0xA8
333#define I7_OFFSET 0xB0
334
335#define O0_OFFSET 0xB8
336#define O1_OFFSET 0xC0
337#define O2_OFFSET 0xC8
338#define O3_OFFSET 0xD0
339#define O4_OFFSET 0xD8
340#define O5_OFFSET 0xE0
341#define O6_SP_OFFSET 0xE8
342#define O7_OFFSET 0xF0
343
344#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0xF8
345#define ISR_PAD_OFFSET 0xFC
346
347/*
348 * The floating point context area.
349 */
350
351#ifndef ASM
352
353typedef struct {
354 double f0; /* f0-f1 */
355 double f2; /* f2-f3 */
356 double f4; /* f4-f5 */
357 double f6; /* f6-f7 */
358 double f8; /* f8-f9 */
359 double f10; /* f10-f11 */
360 double f12; /* f12-f13 */
361 double f14; /* f14-f15 */
362 double f16; /* f16-f17 */
363 double f18; /* f18-f19 */
364 double f20; /* f20-f21 */
365 double f22; /* f22-f23 */
366 double f24; /* f24-f25 */
367 double f26; /* f26-f27 */
368 double f28; /* f28-f29 */
369 double f30; /* f30-f31 */
370 double f32;
371 double f34;
372 double f36;
373 double f38;
374 double f40;
375 double f42;
376 double f44;
377 double f46;
378 double f48;
379 double f50;
380 double f52;
381 double f54;
382 double f56;
383 double f58;
384 double f60;
385 double f62;
386 uint64_t fsr;
388
389#endif /* !ASM */
390
391/*
392 * Offsets of fields with Context_Control_fp for assembly routines.
393 */
394
395#define FO_OFFSET 0x00
396#define F2_OFFSET 0x08
397#define F4_OFFSET 0x10
398#define F6_OFFSET 0x18
399#define F8_OFFSET 0x20
400#define F1O_OFFSET 0x28
401#define F12_OFFSET 0x30
402#define F14_OFFSET 0x38
403#define F16_OFFSET 0x40
404#define F18_OFFSET 0x48
405#define F2O_OFFSET 0x50
406#define F22_OFFSET 0x58
407#define F24_OFFSET 0x60
408#define F26_OFFSET 0x68
409#define F28_OFFSET 0x70
410#define F3O_OFFSET 0x78
411#define F32_OFFSET 0x80
412#define F34_OFFSET 0x88
413#define F36_OFFSET 0x90
414#define F38_OFFSET 0x98
415#define F4O_OFFSET 0xA0
416#define F42_OFFSET 0xA8
417#define F44_OFFSET 0xB0
418#define F46_OFFSET 0xB8
419#define F48_OFFSET 0xC0
420#define F5O_OFFSET 0xC8
421#define F52_OFFSET 0xD0
422#define F54_OFFSET 0xD8
423#define F56_OFFSET 0xE0
424#define F58_OFFSET 0xE8
425#define F6O_OFFSET 0xF0
426#define F62_OFFSET 0xF8
427#define FSR_OFFSET 0x100
428
429#define CONTEXT_CONTROL_FP_SIZE 0x108
430
431#ifndef ASM
432
433/*
434 * Context saved on stack for an interrupt.
435 *
436 * NOTE: The tstate, tpc, and tnpc are saved in this structure
437 * to allow resetting the TL while still being able to return
438 * from a trap later. The PIL is saved because
439 * if this is an external interrupt, we will mask lower
440 * priority interrupts until finishing. Even though the y register
441 * is deprecated, gcc still uses it.
442 */
443
444typedef struct {
445 SPARC64_Minimum_stack_frame Stack_frame;
446 uint64_t tstate;
447 uint64_t tpc;
448 uint64_t tnpc;
449 uint64_t pil;
450 uint64_t y;
451 uint64_t g1;
452 uint64_t g2;
453 uint64_t g3;
454 uint64_t g4;
455 uint64_t g5;
456 uint64_t g6;
457 uint64_t g7;
458 uint64_t o0;
459 uint64_t o1;
460 uint64_t o2;
461 uint64_t o3;
462 uint64_t o4;
463 uint64_t o5;
464 uint64_t o6_sp;
465 uint64_t o7;
466 uint64_t tvec;
468
469#endif /* ASM */
470
471/*
472 * Offsets of fields with CPU_Interrupt_frame for assembly routines.
473 */
474
475#define ISF_TSTATE_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x00
476#define ISF_TPC_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x08
477#define ISF_TNPC_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x10
478#define ISF_PIL_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x18
479#define ISF_Y_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x20
480#define ISF_G1_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x28
481#define ISF_G2_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x30
482#define ISF_G3_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x38
483#define ISF_G4_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x40
484#define ISF_G5_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x48
485#define ISF_G6_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x50
486#define ISF_G7_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x58
487#define ISF_O0_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x60
488#define ISF_O1_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x68
489#define ISF_O2_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x70
490#define ISF_O3_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x78
491#define ISF_O4_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x80
492#define ISF_O5_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x88
493#define ISF_O6_SP_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x90
494#define ISF_O7_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x98
495#define ISF_TVEC_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0xA0
496
497#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE SPARC64_MINIMUM_STACK_FRAME_SIZE + 0xA8
498#ifndef ASM
499/*
500 * This variable is contains the initialize context for the FP unit.
501 * It is filled in by _CPU_Initialize and copied into the task's FP
502 * context area during _CPU_Context_Initialize.
503 */
504
505extern Context_Control_fp _CPU_Null_fp_context;
506
507/*
508 * This flag is context switched with each thread. It indicates
509 * that THIS thread has an interrupt stack frame on its stack.
510 * By using this flag, we can avoid nesting more interrupt dispatching
511 * attempts on a previously interrupted thread's stack.
512 */
513
514extern volatile uint32_t _CPU_ISR_Dispatch_disable;
515
516/*
517 * The following type defines an entry in the SPARC's trap table.
518 *
519 * NOTE: The instructions chosen are RTEMS dependent although one is
520 * obligated to use two of the four instructions to perform a
521 * long jump. The other instructions load one register with the
522 * trap type (a.k.a. vector) and another with the psr.
523 */
524/* For SPARC V9, we must use 6 of these instructions to perform a long
525 * jump, because the _handler value is now 64-bits. We also need to store
526 * temporary values in the global register set at this trap level. Because
527 * the handler runs at TL > 0 with GL > 0, it should be OK to use g2 and g3
528 * to pass parameters to ISR_Handler.
529 *
530 * The instruction sequence is now more like:
531 * rdpr %tstate, %g4
532 * setx _handler, %g2, %g3
533 * jmp %g3+0
534 * mov _vector, %g2
535 */
536typedef struct {
537 uint32_t rdpr_tstate_g4; /* rdpr %tstate, %g4 */
538 uint32_t sethi_of_hh_handler_to_g2; /* sethi %hh(_handler), %g2 */
539 uint32_t or_g2_hm_handler_to_g2; /* or %l3, %hm(_handler), %g2 */
540 uint32_t sllx_g2_by_32_to_g2; /* sllx %g2, 32, %g2 */
541 uint32_t sethi_of_handler_to_g3; /* sethi %hi(_handler), %g3 */
542 uint32_t or_g3_g2_to_g3; /* or %g3, %g2, %g3 */
543 uint32_t jmp_to_low_of_handler_plus_g3; /* jmp %g3 + %lo(_handler) */
544 uint32_t mov_vector_g2; /* mov _vector, %g2 */
546
547/*
548 * This is the set of opcodes for the instructions loaded into a trap
549 * table entry. The routine which installs a handler is responsible
550 * for filling in the fields for the _handler address and the _vector
551 * trap type.
552 *
553 * The constants following this structure are masks for the fields which
554 * must be filled in when the handler is installed.
555 */
556
558
559/*
560 * The size of the floating point context area.
561 */
562
563#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
564
565#endif
566
567/*
568 * Amount of extra stack (above minimum stack size) required by
569 * MPCI receive server thread. Remember that in a multiprocessor
570 * system this thread must exist and be able to process all directives.
571 */
572
573#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
574
575/*
576 * This defines the number of entries in the ISR_Vector_table managed
577 * by the executive.
578 *
579 * On the SPARC, there are really only 256 vectors. However, the executive
580 * has no easy, fast, reliable way to determine which traps are synchronous
581 * and which are asynchronous. By default, synchronous traps return to the
582 * instruction which caused the interrupt. So if you install a software
583 * trap handler as an executive interrupt handler (which is desirable since
584 * RTEMS takes care of window and register issues), then the executive needs
585 * to know that the return address is to the trap rather than the instruction
586 * following the trap.
587 *
588 * So vectors 0 through 255 are treated as regular asynchronous traps which
589 * provide the "correct" return address. Vectors 256 through 512 are assumed
590 * by the executive to be synchronous and to require that the return address
591 * be fudged.
592 *
593 * If you use this mechanism to install a trap handler which must reexecute
594 * the instruction which caused the trap, then it should be installed as
595 * an asynchronous trap. This will avoid the executive changing the return
596 * address.
597 */
598/* On SPARC v9, there are 512 vectors. The same philosophy applies to
599 * vector installation and use, we just provide a larger table.
600 */
601#define CPU_INTERRUPT_NUMBER_OF_VECTORS 512
602#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 1023
603
604#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x200
605#define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap)
606#define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 512 )
607
608#define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 512)
609
610/*
611 * This is defined if the port has a special way to report the ISR nesting
612 * level. Most ports maintain the variable _ISR_Nest_level.
613 */
614
615#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
616
617/*
618 * Should be large enough to run all tests. This ensures
619 * that a "reasonable" small application should not have any problems.
620 *
621 * This appears to be a fairly generous number for the SPARC since
622 * represents a call depth of about 20 routines based on the minimum
623 * stack frame.
624 */
625
626#define CPU_STACK_MINIMUM_SIZE (1024*8)
627
628#define CPU_SIZEOF_POINTER 8
629
630/*
631 * CPU's worst alignment requirement for data types on a byte boundary. This
632 * alignment does not take into account the requirements for the stack.
633 *
634 * On the SPARC, this is required for double word loads and stores.
635 *
636 * Note: quad-word loads/stores need alignment of 16, but currently supported
637 * architectures do not provide HW implemented quad-word operations.
638 */
639
640#define CPU_ALIGNMENT 8
641
642/*
643 * This number corresponds to the byte alignment requirement for the
644 * heap handler. This alignment requirement may be stricter than that
645 * for the data types alignment specified by CPU_ALIGNMENT. It is
646 * common for the heap to follow the same alignment requirement as
647 * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap,
648 * then this should be set to CPU_ALIGNMENT.
649 *
650 * NOTE: This does not have to be a power of 2. It does have to
651 * be greater or equal to than CPU_ALIGNMENT.
652 */
653
654#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
655
656/*
657 * The alignment restrictions for the SPARC are not that strict but this
658 * should unsure that the stack is always sufficiently alignment that the
659 * window overflow, underflow, and flush routines can use double word loads
660 * and stores.
661 */
662
663#define CPU_STACK_ALIGNMENT 16
664
665#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
666
667#ifndef ASM
668
669/*
670 * ISR handler macros
671 */
672
673/*
674 * Disable all interrupts for a critical section. The previous
675 * level is returned in _level.
676 */
677
678 #define _CPU_ISR_Disable( _level ) \
679 (_level) = sparc_disable_interrupts()
680
681/*
682 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
683 * This indicates the end of a critical section. The parameter
684 * _level is not modified.
685 */
686
687#define _CPU_ISR_Enable( _level ) \
688 sparc_enable_interrupts( _level )
689
690/*
691 * This temporarily restores the interrupt to _level before immediately
692 * disabling them again. This is used to divide long critical
693 * sections into two or more parts. The parameter _level is not
694 * modified.
695 */
696
697#define _CPU_ISR_Flash( _level ) \
698 sparc_flash_interrupts( _level )
699
700static inline bool _CPU_ISR_Is_enabled( uint32_t level )
701{
702 return ( level & SPARC_PSTATE_IE_MASK ) != 0;
703}
704
705/*
706 * Map interrupt level in task mode onto the hardware that the CPU
707 * actually provides. Currently, interrupt levels which do not
708 * map onto the CPU in a straight fashion are undefined.
709 */
710
711#define _CPU_ISR_Set_level( _newlevel ) \
712 sparc_enable_interrupts( _newlevel)
713
714uint32_t _CPU_ISR_Get_level( void );
715
716/* end of ISR handler macros */
717
718/* Context handler macros */
719
720/*
721 * Initialize the context to a state suitable for starting a
722 * task after a context restore operation. Generally, this
723 * involves:
724 *
725 * - setting a starting address
726 * - preparing the stack
727 * - preparing the stack and frame pointers
728 * - setting the proper interrupt level in the context
729 * - initializing the floating point context
730 *
731 * NOTE: Implemented as a subroutine for the SPARC port.
732 */
733
734void _CPU_Context_Initialize(
735 Context_Control *the_context,
736 void *stack_base,
737 uint32_t size,
738 uint32_t new_level,
739 void *entry_point,
740 bool is_fp,
741 void *tls_area
742);
743
744/*
745 * This macro is invoked from _Thread_Handler to do whatever CPU
746 * specific magic is required that must be done in the context of
747 * the thread when it starts.
748 *
749 * On the SPARC, this is setting the frame pointer so GDB is happy.
750 * Make GDB stop unwinding at _Thread_Handler, previous register window
751 * Frame pointer is 0 and calling address must be a function with starting
752 * with a SAVE instruction. If return address is leaf-function (no SAVE)
753 * GDB will not look at prev reg window fp.
754 *
755 * _Thread_Handler is known to start with SAVE.
756 */
757
758#define _CPU_Context_Initialization_at_thread_begin() \
759 do { \
760 __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \
761 } while (0)
762
763/*
764 * This routine is responsible for somehow restarting the currently
765 * executing task.
766 *
767 * On the SPARC, this is is relatively painless but requires a small
768 * amount of wrapper code before using the regular restore code in
769 * of the context switch.
770 */
771
772#define _CPU_Context_Restart_self( _the_context ) \
773 _CPU_Context_restore( (_the_context) );
774
775/*
776 * This routine initializes the FP context area passed to it to.
777 *
778 * The SPARC allows us to use the simple initialization model
779 * in which an "initial" FP context was saved into _CPU_Null_fp_context
780 * at CPU initialization and it is simply copied into the destination
781 * context.
782 */
783
784#define _CPU_Context_Initialize_fp( _destination ) \
785 do { \
786 *(*(_destination)) = _CPU_Null_fp_context; \
787 } while (0)
788
789/* end of Context handler macros */
790
791#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
792
793/* Bitfield handler macros */
794
795/*
796 * The SPARC port uses the generic C algorithm for bitfield scan if the
797 * CPU model does not have a scan instruction.
798 */
799
800#if ( SPARC_HAS_BITSCAN == 0 )
801#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
802#else
803#error "scan instruction not currently supported by RTEMS!!"
804#endif
805
806/* end of Bitfield handler macros */
807
808/* Priority handler handler macros */
809
810/*
811 * The SPARC port uses the generic C algorithm for bitfield scan if the
812 * CPU model does not have a scan instruction.
813 */
814
815#if ( SPARC_HAS_BITSCAN == 1 )
816#error "scan instruction not currently supported by RTEMS!!"
817#endif
818
819/* end of Priority handler macros */
820
821/* functions */
822
823/*
824 * _CPU_Initialize
825 *
826 * This routine performs CPU dependent initialization.
827 */
828
829void _CPU_Initialize(void);
830
831typedef void ( *CPU_ISR_raw_handler )( void );
832
834 uint32_t vector,
835 CPU_ISR_raw_handler new_handler,
836 CPU_ISR_raw_handler *old_handler
837);
838
839typedef void ( *CPU_ISR_handler )( uint32_t );
840
842 uint32_t vector,
843 CPU_ISR_handler new_handler,
844 CPU_ISR_handler *old_handler
845);
846
847RTEMS_NO_RETURN void *_CPU_Thread_Idle_body( uintptr_t ignored );
848
849/*
850 * _CPU_Context_switch
851 *
852 * This routine switches from the run context to the heir context.
853 */
854
856 Context_Control *run,
857 Context_Control *heir
858);
859
860/*
861 * _CPU_Context_restore
862 *
863 * This routine is generally used only to restart self in an
864 * efficient manner.
865 */
866
867RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context );
868
869/*
870 * _CPU_Context_save_fp
871 *
872 * This routine saves the floating point context passed to it.
873 */
874
876 Context_Control_fp **fp_context_ptr
877);
878
879/*
880 * _CPU_Context_restore_fp
881 *
882 * This routine restores the floating point context passed to it.
883 */
884
886 Context_Control_fp **fp_context_ptr
887);
888
889/* FIXME */
891
893
894/*
895 * CPU_swap_u32
896 *
897 * The following routine swaps the endian format of an unsigned int.
898 * It must be static because it is referenced indirectly.
899 *
900 * This version will work on any processor, but if you come across a better
901 * way for the SPARC PLEASE use it. The most common way to swap a 32-bit
902 * entity as shown below is not any more efficient on the SPARC.
903 *
904 * swap least significant two bytes with 16-bit rotate
905 * swap upper and lower 16-bits
906 * swap most significant two bytes with 16-bit rotate
907 *
908 * It is not obvious how the SPARC can do significantly better than the
909 * generic code. gcc 2.7.0 only generates about 12 instructions for the
910 * following code at optimization level four (i.e. -O4).
911 */
912
913static inline uint32_t CPU_swap_u32(
914 uint32_t value
915)
916{
917 uint32_t byte1, byte2, byte3, byte4, swapped;
918
919 byte4 = (value >> 24) & 0xff;
920 byte3 = (value >> 16) & 0xff;
921 byte2 = (value >> 8) & 0xff;
922 byte1 = value & 0xff;
923
924 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
925 return( swapped );
926}
927
928#define CPU_swap_u16( value ) \
929 (((value&0xff) << 8) | ((value >> 8)&0xff))
930
931typedef uint32_t CPU_Counter_ticks;
932
933uint32_t _CPU_Counter_frequency( void );
934
935CPU_Counter_ticks _CPU_Counter_read( void );
936
938typedef uintptr_t CPU_Uint32ptr;
939
940#endif /* ASM */
941
942#ifdef __cplusplus
943}
944#endif
945
946#endif
This header file provides basic definitions used by the API and the implementation.
void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.c:100
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
Information Required to Build RTEMS for a Particular Member of the SPARC Family.
const CPU_Trap_table_entry _CPU_Trap_slot_template
Definition: sparc-isr-install.c:54
#define _CPU_Context_restore_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:901
#define _CPU_Context_save_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:895
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
Definition: cpu.h:646
SPARC basic context.
Definition: cpu.h:213
Thread register context.
Definition: cpu.h:173
Definition: cpu.h:180