21#ifndef _RTEMS_SCORE_CPU_H
22#define _RTEMS_SCORE_CPU_H
44#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
55#define CPU_ISR_PASSES_FRAME_POINTER TRUE
57#define CPU_HARDWARE_FP FALSE
59#define CPU_SOFTWARE_FP FALSE
61#define CPU_ALL_TASKS_ARE_FP FALSE
63#define CPU_IDLE_TASK_IS_FP FALSE
65#define CPU_USE_DEFERRED_FP_SWITCH FALSE
67#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
80#define CPU_STACK_GROWS_UP FALSE
83#define CPU_CACHE_LINE_BYTES 32
85#define CPU_STRUCTURE_ALIGNMENT
97#define CPU_MODES_INTERRUPT_MASK 0x00000001
99#define CPU_MAXIMUM_PROCESSORS 32
167 uint32_t register_r4;
168 uint32_t register_r5;
169 uint32_t register_r6;
170 uint32_t register_r7;
172 uint32_t register_p3;
173 uint32_t register_p4;
174 uint32_t register_p5;
175 uint32_t register_fp;
176 uint32_t register_sp;
178 uint32_t register_rets;
183#define _CPU_Context_Get_SP( _context ) \
184 (_context)->register_sp
221#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
232#define CPU_INTERRUPT_NUMBER_OF_VECTORS 16
238#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
245#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
256#define CPU_STACK_MINIMUM_SIZE (1024*8)
258#define CPU_SIZEOF_POINTER 4
268#define CPU_ALIGNMENT 8
293#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
295#define CPU_STACK_ALIGNMENT 8
297#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
320#define _CPU_ISR_Disable( _level ) \
322 __asm__ volatile ("cli %0; csync \n" : "=d" (_level) ); \
337#define _CPU_ISR_Enable( _level ) { \
338 __asm__ __volatile__ ("sti %0; csync \n" : : "d" (_level) ); \
353#define _CPU_ISR_Flash( _level ) { \
354 __asm__ __volatile__ ("sti %0; csync; cli r0; csync" \
355 : : "d"(_level) : "R0" ); \
358static inline bool _CPU_ISR_Is_enabled( uint32_t level )
378#define _CPU_ISR_Set_level( _new_level ) \
380 __asm__ __volatile__ ( "sti %0; csync" : : "d"(_new_level ? 0 : 0xffff) ); \
433void _CPU_Context_Initialize(
435 uint32_t *stack_base,
458#define _CPU_Context_Restart_self( _the_context ) \
459 _CPU_Context_restore( (_the_context) );
463#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
465#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
479typedef void ( *CPU_ISR_raw_handler )( void );
483 CPU_ISR_raw_handler new_handler,
484 CPU_ISR_raw_handler *old_handler
487typedef void ( *CPU_ISR_handler )( uint32_t );
491 CPU_ISR_handler new_handler,
492 CPU_ISR_handler *old_handler
576static inline uint32_t CPU_swap_u32(
580 uint32_t byte1, byte2, byte3, byte4, swapped;
582 byte4 = (value >> 24) & 0xff;
583 byte3 = (value >> 16) & 0xff;
584 byte2 = (value >> 8) & 0xff;
585 byte1 = value & 0xff;
587 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
597#define CPU_swap_u16( value ) \
598 (((value&0xff) << 8) | ((value >> 8)&0xff))
602typedef uint32_t CPU_Counter_ticks;
This header file provides basic definitions used by the API and the implementation.
void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.c:100
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
Blackfin Set up Basic CPU Dependency Settings Based on Compiler Settings.
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
Thread register context.
Definition: cpu.h:173