RTEMS 6.1-rc7
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Macros
ADC Extended Private Macros

Macros

#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)    (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
 Test if conversion trigger of injected group is software start or external trigger.
 
#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__)
 Check if conversion is on going on regular or injected groups.
 
#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__)    (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance))
 Check if conversion is on going on injected group.
 
#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__)   ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
 Set the selected injected Channel rank.
 
#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__)   ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
 Configure ADC injected context queue.
 
#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__)   ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
 Configure ADC discontinuous conversion mode for injected group.
 
#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__)   ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
 Configure ADC discontinuous conversion mode for regular group.
 
#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__)   (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
 Configure the number of discontinuous conversions for regular group.
 
#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__)   ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
 Configure the ADC auto delay mode.
 
#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__)   ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
 Configure ADC continuous conversion mode.
 
#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__)   ((__DMACONTREQ_MODE__))
 Enable the ADC DMA continuous request.
 
#define ADC_OFR_CHANNEL(__CHANNEL__)   ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos)
 Configure the channel number into offset OFRx register.
 
#define ADC_DIFSEL_CHANNEL(__CHANNEL__)   (1UL << (__CHANNEL__))
 Configure the channel number into differential mode selection register.
 
#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__)   (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos)
 Configure calibration factor in differential mode to be set into calibration register.
 
#define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__)   ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos)
 Calibration factor in differential mode to be retrieved from calibration register.
 
#define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__)   ((__THRESHOLD__) << 16UL)
 Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
 
#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__)   ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)
 Configure the ADC DMA continuous request for ADC multimode.
 
#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__)
 Shift the offset in function of the selected ADC resolution.
 
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)
 Shift the AWD1 threshold in function of the selected ADC resolution.
 
#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)
 Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.
 
#define ADC12_COMMON_REGISTER(__HANDLE__)   (ADC12_COMMON)
 Clear Common Control Register.
 
#define ADC_MASTER_REGISTER(__HANDLE__)   ( (ADC1))
 Report Master Instance.
 
#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__)
 Check whether or not dual regular conversions are enabled.
 
#define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)
 Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master.
 
#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__)
 Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled.
 
#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__)
 Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled.
 
#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__)
 
#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__)    ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
 Set handle instance of the ADC slave associated to the ADC master.
 
#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__)   (((__HANDLE__)->Instance) == ADC2)
 Verify the ADC instance connected to the temperature sensor.
 
#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)   (((__HANDLE__)->Instance) == ADC2)
 Verify the ADC instance connected to the battery voltage VBAT.
 
#define ADC_VREFINT_INSTANCE(__HANDLE__)   (((__HANDLE__)->Instance) == ADC2)
 Verify the ADC instance connected to the internal voltage reference VREFINT.
 
#define IS_ADC_INJECTED_NB_CONV(__LENGTH__)   (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
 Verify the length of scheduled injected conversions group.
 
#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__)   ((__CALIBRATION_FACTOR__) <= (0x7FFU))
 Calibration factor size verification (11 bits maximum).
 
#define IS_ADC_CHANNEL(__CHANNEL__)
 Verify the ADC channel setting.
 
#define IS_ADC1_DIFF_CHANNEL(__CHANNEL__)
 Verify the ADC channel setting in differential mode for ADC1.
 
#define IS_ADC2_DIFF_CHANNEL(__CHANNEL__)
 Verify the ADC channel setting in differential mode for ADC2.
 
#define IS_ADC3_DIFF_CHANNEL(__CHANNEL__)
 Verify the ADC channel setting in differential mode for ADC3.
 
#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__)
 Verify the ADC single-ended input or differential mode setting.
 
#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__)
 Verify the ADC offset management setting.
 
#define IS_ADC_INJECTED_RANK(__CHANNEL__)
 Verify the ADC injected channel setting.
 
#define IS_ADC_EXTTRIGINJEC(__INJTRIG__)
 Verify the ADC injected conversions external trigger.
 
#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__)
 Verify the ADC edge trigger setting for injected group.
 
#define IS_ADC_MULTIMODE(__MODE__)
 Verify the ADC multimode setting.
 
#define IS_ADC_DUAL_DATA_MODE(MODE)
 Verify the ADC dual data mode setting.
 
#define IS_ADC_SAMPLING_DELAY(__DELAY__)
 Verify the ADC multimode delay setting.
 
#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__)
 Verify the ADC analog watchdog setting.
 
#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__)
 Verify the ADC analog watchdog mode setting.
 
#define IS_ADC_CONVERSION_GROUP(__CONVERSION__)
 Verify the ADC conversion (regular or injected or both).
 
#define IS_ADC_EVENT_TYPE(__EVENT__)
 Verify the ADC event type.
 
#define IS_ADC_OVERSAMPLING_RATIO(RATIO)   (((RATIO) >= 1UL) && ((RATIO) <= 1024UL))
 Verify the ADC oversampling ratio.
 
#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)
 Verify the ADC oversampling shift.
 
#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__)
 Verify the ADC oversampling triggered mode.
 
#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__)
 Verify the ADC oversampling regular conversion resumed or continued mode.
 
#define IS_ADC_DFSDMCFG_MODE(__HANDLE__)   (SET)
 Verify the DFSDM mode configuration.
 
#define ADC_CFGR_DFSDM(__HANDLE__)   (0x0UL)
 Return the DFSDM configuration mode.
 

Detailed Description

Macro Definition Documentation

◆ ADC12_COMMON_REGISTER

#define ADC12_COMMON_REGISTER (   __HANDLE__)    (ADC12_COMMON)

Clear Common Control Register.

Parameters
__HANDLE__ADC handle.
Return values
None

Report common register to ADC1 and ADC2

Parameters
__HANDLE__ADC handle
Return values
Commoncontrol register

◆ ADC12_NONMULTIMODE_OR_MULTIMODEMASTER

#define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER (   __HANDLE__)
Value:
( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2) \
)? \
SET \
: \
((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET) \
)
#define ADC1
Definition: MIMXRT1052.h:1656
#define ADC2
Definition: MIMXRT1052.h:1660
#define ADC_CCR_DUAL
Definition: stm32h723xx.h:4062

Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master.

Parameters
__HANDLE__ADC handle
Return values
SET(non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode)

◆ ADC_AWD1THRESHOLD_SHIFT_RESOLUTION

#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION (   __HANDLE__,
  __THRESHOLD__ 
)
Value:
(((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \
? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
: \
((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \
? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
: \
((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
)
#define ADC_CFGR_RES
Definition: stm32h723xx.h:2866
#define ADC_CFGR_RES_2
Definition: stm32h723xx.h:2869

Shift the AWD1 threshold in function of the selected ADC resolution.

Note
Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0. If resolution 16 bits, no shift. If resolution 14 bits, shift of 2 ranks on the left. If resolution 12 bits, shift of 4 ranks on the left. If resolution 10 bits, shift of 6 ranks on the left. If resolution 8 bits, shift of 8 ranks on the left. therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2))
Parameters
__HANDLE__ADC handle
__THRESHOLD__Value to be shifted
Return values
None

◆ ADC_AWD23THRESHOLD_SHIFT_RESOLUTION

#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION (   __HANDLE__,
  __THRESHOLD__ 
)
Value:
(((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \
? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
: \
((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \
? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
: \
((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
)

Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.

Note
Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0. If resolution 16 bits, no shift. If resolution 14 bits, shift of 2 ranks on the left. If resolution 12 bits, shift of 4 ranks on the left. If resolution 10 bits, shift of 6 ranks on the left. If resolution 8 bits, shift of 8 ranks on the left. therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2))
Parameters
__HANDLE__ADC handle
__THRESHOLD__Value to be shifted
Return values
None

◆ ADC_BATTERY_VOLTAGE_INSTANCE

#define ADC_BATTERY_VOLTAGE_INSTANCE (   __HANDLE__)    (((__HANDLE__)->Instance) == ADC2)

Verify the ADC instance connected to the battery voltage VBAT.

Parameters
__HANDLE__ADC handle.
Return values
SET(ADC instance is valid) or RESET (ADC instance is invalid)

◆ ADC_CALFACT_DIFF_GET

#define ADC_CALFACT_DIFF_GET (   __CALIBRATION_FACTOR__)    ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos)

Calibration factor in differential mode to be retrieved from calibration register.

Parameters
__CALIBRATION_FACTOR__Calibration factor value.
Return values
None

◆ ADC_CALFACT_DIFF_SET

#define ADC_CALFACT_DIFF_SET (   __CALIBRATION_FACTOR__)    (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos)

Configure calibration factor in differential mode to be set into calibration register.

Parameters
__CALIBRATION_FACTOR__Calibration factor value.
Return values
None

◆ ADC_CCR_MULTI_DMACONTREQ

#define ADC_CCR_MULTI_DMACONTREQ (   __DMACONTREQ_MODE__)    ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)

Configure the ADC DMA continuous request for ADC multimode.

Parameters
__DMACONTREQ_MODE__DMA continuous request mode.
Return values
None

◆ ADC_CFGR_AUTOWAIT

#define ADC_CFGR_AUTOWAIT (   __AUTOWAIT__)    ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)

Configure the ADC auto delay mode.

Parameters
__AUTOWAIT__Auto delay bit enable or disable.
Return values
None

◆ ADC_CFGR_CONTINUOUS

#define ADC_CFGR_CONTINUOUS (   __CONTINUOUS_MODE__)    ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)

Configure ADC continuous conversion mode.

Parameters
__CONTINUOUS_MODE__Continuous mode.
Return values
None

◆ ADC_CFGR_DFSDM

#define ADC_CFGR_DFSDM (   __HANDLE__)    (0x0UL)

Return the DFSDM configuration mode.

Parameters
__HANDLE__ADC handle.
Note
When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). For this reason, the input parameter is the ADC handle and not the configuration parameter directly.
Return values
DFSDMconfiguration mode

◆ ADC_CFGR_DISCONTINUOUS_NUM

#define ADC_CFGR_DISCONTINUOUS_NUM (   __NBR_DISCONTINUOUS_CONV__)    (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)

Configure the number of discontinuous conversions for regular group.

Parameters
__NBR_DISCONTINUOUS_CONV__Number of discontinuous conversions.
Return values
None

◆ ADC_CFGR_DMACONTREQ

#define ADC_CFGR_DMACONTREQ (   __DMACONTREQ_MODE__)    ((__DMACONTREQ_MODE__))

Enable the ADC DMA continuous request.

Parameters
__DMACONTREQ_MODE__DMA continuous request mode.
Return values
None

◆ ADC_CFGR_INJECT_CONTEXT_QUEUE

#define ADC_CFGR_INJECT_CONTEXT_QUEUE (   __INJECT_CONTEXT_QUEUE_MODE__)    ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)

Configure ADC injected context queue.

Parameters
__INJECT_CONTEXT_QUEUE_MODE__Injected context queue mode.
Return values
None

◆ ADC_CFGR_INJECT_DISCCONTINUOUS

#define ADC_CFGR_INJECT_DISCCONTINUOUS (   __INJECT_DISCONTINUOUS_MODE__)    ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)

Configure ADC discontinuous conversion mode for injected group.

Parameters
__INJECT_DISCONTINUOUS_MODE__Injected discontinuous mode.
Return values
None

◆ ADC_CFGR_REG_DISCONTINUOUS

#define ADC_CFGR_REG_DISCONTINUOUS (   __REG_DISCONTINUOUS_MODE__)    ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)

Configure ADC discontinuous conversion mode for regular group.

Parameters
__REG_DISCONTINUOUS_MODE__Regular discontinuous mode.
Return values
None

◆ ADC_CLEAR_COMMON_CONTROL_REGISTER

#define ADC_CLEAR_COMMON_CONTROL_REGISTER (   __HANDLE__)
Value:
CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \
#define ADC_CCR_CKMODE
Definition: stm32h723xx.h:4086
#define ADC_CCR_PRESC
Definition: stm32h723xx.h:4092
#define ADC_CCR_DELAY
Definition: stm32h723xx.h:4071
#define ADC_CCR_DAMDF
Definition: stm32h723xx.h:4080
#define ADC_CCR_VBATEN
Definition: stm32h723xx.h:4106
#define ADC_CCR_TSEN
Definition: stm32h723xx.h:4103
#define ADC_CCR_VREFEN
Definition: stm32h723xx.h:4100

◆ ADC_DIFSEL_CHANNEL

#define ADC_DIFSEL_CHANNEL (   __CHANNEL__)    (1UL << (__CHANNEL__))

Configure the channel number into differential mode selection register.

Parameters
__CHANNEL__ADC Channel.
Return values
None

◆ ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE

#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE (   __HANDLE__)
Value:
( ( ((__HANDLE__)->Instance == ADC1) \
)? \
SET \
: \
( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \
((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
#define ADC_DUALMODE_INTERL
Definition: stm32h7xx_hal_adc_ex.h:331
#define ADC_DUALMODE_REGSIMULT
Definition: stm32h7xx_hal_adc_ex.h:330
#define ADC_MODE_INDEPENDENT
Definition: stm32h7xx_hal_adc_ex.h:329

Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled.

Parameters
__HANDLE__ADC handle
Return values
SET(non-MultiMode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled)

◆ ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE

#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE (   __HANDLE__)
Value:
( ( ((__HANDLE__)->Instance == ADC1) \
)? \
SET \
: \
( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
#define ADC_DUALMODE_ALTERTRIG
Definition: stm32h7xx_hal_adc_ex.h:333
#define ADC_DUALMODE_INJECSIMULT
Definition: stm32h7xx_hal_adc_ex.h:332

Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled.

Parameters
__HANDLE__ADC handle
Return values
SET(Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled)

◆ ADC_IS_CONVERSION_ONGOING_INJECTED

#define ADC_IS_CONVERSION_ONGOING_INJECTED (   __HANDLE__)     (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance))

Check if conversion is on going on injected group.

Parameters
__HANDLE__ADC handle.
Return values
Value"0" (no conversion is on going) or value "1" (conversion is on going)

◆ ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED

#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED (   __HANDLE__)
Value:
(( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == 0UL \
) ? RESET : SET)
#define ADC_CR_ADSTART
Definition: stm32h723xx.h:2808
#define ADC_CR_JADSTART
Definition: stm32h723xx.h:2811

Check if conversion is on going on regular or injected groups.

Parameters
__HANDLE__ADC handle.
Return values
SET(conversion is on going) or RESET (no conversion is on going).

◆ ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE

#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE (   __HANDLE__)
Value:
( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
)? \
( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \
((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \
((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \
: \
RESET \
)

Check whether or not dual regular conversions are enabled.

Parameters
__HANDLE__ADC handle
Return values
SET(dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)

◆ ADC_IS_SOFTWARE_START_INJECTED

#define ADC_IS_SOFTWARE_START_INJECTED (   __HANDLE__)     (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)

Test if conversion trigger of injected group is software start or external trigger.

Parameters
__HANDLE__ADC handle.
Return values
SET(software start) or RESET (external trigger).

◆ ADC_JSQR_RK

#define ADC_JSQR_RK (   __CHANNELNB__,
  __RANKNB__ 
)    ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))

Set the selected injected Channel rank.

Parameters
__CHANNELNB__Channel number.
__RANKNB__Rank number.
Return values
None

◆ ADC_MASTER_REGISTER

#define ADC_MASTER_REGISTER (   __HANDLE__)    ( (ADC1))

Report Master Instance.

Parameters
__HANDLE__ADC handle
Note
return same instance if ADC of input handle is independent ADC
Return values
MasterInstance

◆ ADC_MULTI_SLAVE

#define ADC_MULTI_SLAVE (   __HANDLE_MASTER__,
  __HANDLE_SLAVE__ 
)     ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )

Set handle instance of the ADC slave associated to the ADC master.

Parameters
__HANDLE_MASTER__ADC master handle.
__HANDLE_SLAVE__ADC slave handle.
Note
if HANDLE_MASTER is the handle of a slave ADC (ADC2) or an independent ADC, HANDLE_SLAVE instance is set to NULL.
Return values
None

◆ ADC_OFFSET_SHIFT_RESOLUTION

#define ADC_OFFSET_SHIFT_RESOLUTION (   __HANDLE__,
  __OFFSET__ 
)
Value:
(((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \
? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
: \
((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \
? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
: \
((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
)

Shift the offset in function of the selected ADC resolution.

Note
Offset has to be left-aligned on bit 15, the LSB (right bits) are set to 0 If resolution 16 bits, no shift. If resolution 14 bits, shift of 2 ranks on the left. If resolution 12 bits, shift of 4 ranks on the left. If resolution 10 bits, shift of 6 ranks on the left. If resolution 8 bits, shift of 8 ranks on the left. therefore, shift = (16 - resolution) = 16 - (16 - (((RES[2:0]) >> 2)*2))
Parameters
__HANDLE__ADC handle
__OFFSET__Value to be shifted
Return values
None

◆ ADC_OFR_CHANNEL

#define ADC_OFR_CHANNEL (   __CHANNEL__)    ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos)

Configure the channel number into offset OFRx register.

Parameters
__CHANNEL__ADC Channel.
Return values
None

◆ ADC_TEMPERATURE_SENSOR_INSTANCE

#define ADC_TEMPERATURE_SENSOR_INSTANCE (   __HANDLE__)    (((__HANDLE__)->Instance) == ADC2)

Verify the ADC instance connected to the temperature sensor.

Parameters
__HANDLE__ADC handle.
Return values
SET(ADC instance is valid) or RESET (ADC instance is invalid)

◆ ADC_TRX_HIGHTHRESHOLD

#define ADC_TRX_HIGHTHRESHOLD (   __THRESHOLD__)    ((__THRESHOLD__) << 16UL)

Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.

Parameters
__THRESHOLD__Threshold value.
Return values
None

◆ ADC_VREFINT_INSTANCE

#define ADC_VREFINT_INSTANCE (   __HANDLE__)    (((__HANDLE__)->Instance) == ADC2)

Verify the ADC instance connected to the internal voltage reference VREFINT.

Parameters
__HANDLE__ADC handle.
Return values
SET(ADC instance is valid) or RESET (ADC instance is invalid)

◆ IS_ADC1_DIFF_CHANNEL

#define IS_ADC1_DIFF_CHANNEL (   __CHANNEL__)
Value:
(((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) ||\
((__CHANNEL__) == ADC_CHANNEL_3) ||\
((__CHANNEL__) == ADC_CHANNEL_4) ||\
((__CHANNEL__) == ADC_CHANNEL_5) ||\
((__CHANNEL__) == ADC_CHANNEL_10) ||\
((__CHANNEL__) == ADC_CHANNEL_11) ||\
((__CHANNEL__) == ADC_CHANNEL_12) ||\
((__CHANNEL__) == ADC_CHANNEL_16) ||\
((__CHANNEL__) == ADC_CHANNEL_18) )
#define ADC_CHANNEL_18
Definition: stm32h7xx_hal_adc.h:738
#define ADC_CHANNEL_16
Definition: stm32h7xx_hal_adc.h:736

Verify the ADC channel setting in differential mode for ADC1.

Parameters
__CHANNEL__programmed ADC channel.
Return values
SET(CHANNEL is valid) or RESET (CHANNEL is invalid)

◆ IS_ADC2_DIFF_CHANNEL

#define IS_ADC2_DIFF_CHANNEL (   __CHANNEL__)
Value:
(((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) || \
((__CHANNEL__) == ADC_CHANNEL_4) || \
((__CHANNEL__) == ADC_CHANNEL_5) || \
((__CHANNEL__) == ADC_CHANNEL_10) || \
((__CHANNEL__) == ADC_CHANNEL_11) || \
((__CHANNEL__) == ADC_CHANNEL_12) || \
((__CHANNEL__) == ADC_CHANNEL_18) )

Verify the ADC channel setting in differential mode for ADC2.

Parameters
__CHANNEL__programmed ADC channel.
Return values
SET(CHANNEL is valid) or RESET (CHANNEL is invalid)

◆ IS_ADC3_DIFF_CHANNEL

#define IS_ADC3_DIFF_CHANNEL (   __CHANNEL__)
Value:
(((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) || \
((__CHANNEL__) == ADC_CHANNEL_4) || \
((__CHANNEL__) == ADC_CHANNEL_5) || \
((__CHANNEL__) == ADC_CHANNEL_10) || \
((__CHANNEL__) == ADC_CHANNEL_11) || \
((__CHANNEL__) == ADC_CHANNEL_13) || \
((__CHANNEL__) == ADC_CHANNEL_14) || \
((__CHANNEL__) == ADC_CHANNEL_15) )

Verify the ADC channel setting in differential mode for ADC3.

Parameters
__CHANNEL__programmed ADC channel.
Return values
SET(CHANNEL is valid) or RESET (CHANNEL is invalid)

◆ IS_ADC_ANALOG_WATCHDOG_MODE

#define IS_ADC_ANALOG_WATCHDOG_MODE (   __WATCHDOG_MODE__)
Value:
(((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC
Definition: stm32h7xx_hal_adc.h:798
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC
Definition: stm32h7xx_hal_adc.h:802
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC
Definition: stm32h7xx_hal_adc.h:799
#define ADC_ANALOGWATCHDOG_ALL_INJEC
Definition: stm32h7xx_hal_adc.h:801
#define ADC_ANALOGWATCHDOG_NONE
Definition: stm32h7xx_hal_adc.h:796
#define ADC_ANALOGWATCHDOG_SINGLE_REG
Definition: stm32h7xx_hal_adc.h:797
#define ADC_ANALOGWATCHDOG_ALL_REG
Definition: stm32h7xx_hal_adc.h:800

Verify the ADC analog watchdog mode setting.

Parameters
__WATCHDOG_MODE__programmed ADC analog watchdog mode setting.
Return values
SET(WATCHDOG_MODE is valid) or RESET (WATCHDOG_MODE is invalid)

◆ IS_ADC_ANALOG_WATCHDOG_NUMBER

#define IS_ADC_ANALOG_WATCHDOG_NUMBER (   __WATCHDOG__)
Value:
(((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) )
#define ADC_ANALOGWATCHDOG_2
Definition: stm32h7xx_hal_adc.h:768
#define ADC_ANALOGWATCHDOG_1
Definition: stm32h7xx_hal_adc.h:767
#define ADC_ANALOGWATCHDOG_3
Definition: stm32h7xx_hal_adc.h:769

Verify the ADC analog watchdog setting.

Parameters
__WATCHDOG__programmed ADC analog watchdog setting.
Return values
SET(WATCHDOG is valid) or RESET (WATCHDOG is invalid)

◆ IS_ADC_CALFACT

#define IS_ADC_CALFACT (   __CALIBRATION_FACTOR__)    ((__CALIBRATION_FACTOR__) <= (0x7FFU))

Calibration factor size verification (11 bits maximum).

Parameters
__CALIBRATION_FACTOR__Calibration factor value.
Return values
SET(CALIBRATION_FACTOR is within the authorized size) or RESET (CALIBRATION_FACTOR is too large)

◆ IS_ADC_CHANNEL

#define IS_ADC_CHANNEL (   __CHANNEL__)
Value:
(((__CHANNEL__) == ADC_CHANNEL_0) || \
((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) || \
((__CHANNEL__) == ADC_CHANNEL_4) || \
((__CHANNEL__) == ADC_CHANNEL_5) || \
((__CHANNEL__) == ADC_CHANNEL_6) || \
((__CHANNEL__) == ADC_CHANNEL_7) || \
((__CHANNEL__) == ADC_CHANNEL_8) || \
((__CHANNEL__) == ADC_CHANNEL_9) || \
((__CHANNEL__) == ADC_CHANNEL_10) || \
((__CHANNEL__) == ADC_CHANNEL_11) || \
((__CHANNEL__) == ADC_CHANNEL_12) || \
((__CHANNEL__) == ADC_CHANNEL_13) || \
((__CHANNEL__) == ADC_CHANNEL_14) || \
((__CHANNEL__) == ADC_CHANNEL_15) || \
((__CHANNEL__) == ADC_CHANNEL_16) || \
((__CHANNEL__) == ADC_CHANNEL_17) || \
((__CHANNEL__) == ADC_CHANNEL_18) || \
((__CHANNEL__) == ADC_CHANNEL_19) || \
((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2)|| \
((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2)|| \
((__CHANNEL__) == ADC_CHANNEL_VREFINT) )
#define ADC_CHANNEL_DAC1CH1_ADC2
Definition: stm32h7xx_hal_adc.h:743
#define ADC_CHANNEL_VREFINT
Definition: stm32h7xx_hal_adc.h:740
#define ADC_CHANNEL_19
Definition: stm32h7xx_hal_adc.h:739
#define ADC_CHANNEL_VBAT
Definition: stm32h7xx_hal_adc.h:742
#define ADC_CHANNEL_TEMPSENSOR
Definition: stm32h7xx_hal_adc.h:741
#define ADC_CHANNEL_17
Definition: stm32h7xx_hal_adc.h:737
#define ADC_CHANNEL_DAC1CH2_ADC2
Definition: stm32h7xx_hal_adc.h:744

Verify the ADC channel setting.

Parameters
__CHANNEL__programmed ADC channel.
Return values
SET(CHANNEL is valid) or RESET (CHANNEL is invalid)

◆ IS_ADC_CONVERSION_GROUP

#define IS_ADC_CONVERSION_GROUP (   __CONVERSION__)
Value:
(((__CONVERSION__) == ADC_REGULAR_GROUP) || \
((__CONVERSION__) == ADC_INJECTED_GROUP) || \
((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) )
#define ADC_REGULAR_INJECTED_GROUP
Definition: stm32h7xx_hal_adc_ex.h:376
#define ADC_REGULAR_GROUP
Definition: stm32h7xx_hal_adc_ex.h:374
#define ADC_INJECTED_GROUP
Definition: stm32h7xx_hal_adc_ex.h:375

Verify the ADC conversion (regular or injected or both).

Parameters
__CONVERSION__ADC conversion group.
Return values
SET(CONVERSION is valid) or RESET (CONVERSION is invalid)

◆ IS_ADC_DFSDMCFG_MODE

#define IS_ADC_DFSDMCFG_MODE (   __HANDLE__)    (SET)

Verify the DFSDM mode configuration.

Parameters
__HANDLE__ADC handle.
Note
When DMSDFM configuration is not supported, the macro systematically reports SET. For this reason, the input parameter is the ADC handle and not the configuration parameter directly.
Return values
SET(DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)

◆ IS_ADC_DUAL_DATA_MODE

#define IS_ADC_DUAL_DATA_MODE (   MODE)
Value:
#define ADC_DUALMODEDATAFORMAT_8_BITS
Definition: stm32h7xx_hal_adc_ex.h:344
#define ADC_DUALMODEDATAFORMAT_DISABLED
Definition: stm32h7xx_hal_adc_ex.h:342
#define ADC_DUALMODEDATAFORMAT_32_10_BITS
Definition: stm32h7xx_hal_adc_ex.h:343

Verify the ADC dual data mode setting.

Parameters
MODEprogrammed ADC dual mode setting.
Return values
SET(MODE is valid) or RESET (MODE is invalid)

◆ IS_ADC_EVENT_TYPE

#define IS_ADC_EVENT_TYPE (   __EVENT__)
Value:
(((__EVENT__) == ADC_EOSMP_EVENT) || \
((__EVENT__) == ADC_AWD_EVENT) || \
((__EVENT__) == ADC_AWD2_EVENT) || \
((__EVENT__) == ADC_AWD3_EVENT) || \
((__EVENT__) == ADC_OVR_EVENT) || \
((__EVENT__) == ADC_JQOVF_EVENT) )
#define ADC_AWD3_EVENT
Definition: stm32h7xx_hal_adc.h:898
#define ADC_EOSMP_EVENT
Definition: stm32h7xx_hal_adc.h:895
#define ADC_JQOVF_EVENT
Definition: stm32h7xx_hal_adc.h:900
#define ADC_OVR_EVENT
Definition: stm32h7xx_hal_adc.h:899
#define ADC_AWD2_EVENT
Definition: stm32h7xx_hal_adc.h:897
#define ADC_AWD_EVENT
Definition: stm32h7xx_hal_adc.h:904

Verify the ADC event type.

Parameters
__EVENT__ADC event.
Return values
SET(EVENT is valid) or RESET (EVENT is invalid)

◆ IS_ADC_EXTTRIGINJEC

#define IS_ADC_EXTTRIGINJEC (   __INJTRIG__)
Value:
(((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_OUT) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_OUT) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_OUT) || \
\
((__INJTRIG__) == ADC_SOFTWARE_START) )
#define ADC_EXTERNALTRIGINJEC_T3_CC4
Definition: stm32h7xx_hal_adc_ex.h:243
#define ADC_EXTERNALTRIGINJEC_T3_CC3
Definition: stm32h7xx_hal_adc_ex.h:250
#define ADC_EXTERNALTRIGINJEC_EXT_IT15
Definition: stm32h7xx_hal_adc_ex.h:245
#define ADC_EXTERNALTRIGINJEC_T8_CC4
Definition: stm32h7xx_hal_adc_ex.h:246
#define ADC_EXTERNALTRIGINJEC_LPTIM1_OUT
Definition: stm32h7xx_hal_adc_ex.h:259
#define ADC_EXTERNALTRIGINJEC_T8_TRGO
Definition: stm32h7xx_hal_adc_ex.h:248
#define ADC_EXTERNALTRIGINJEC_T1_CC4
Definition: stm32h7xx_hal_adc_ex.h:240
#define ADC_EXTERNALTRIGINJEC_T3_TRGO
Definition: stm32h7xx_hal_adc_ex.h:251
#define ADC_EXTERNALTRIGINJEC_T8_TRGO2
Definition: stm32h7xx_hal_adc_ex.h:249
#define ADC_EXTERNALTRIGINJEC_T15_TRGO
Definition: stm32h7xx_hal_adc_ex.h:254
#define ADC_EXTERNALTRIGINJEC_T2_CC1
Definition: stm32h7xx_hal_adc_ex.h:242
#define ADC_EXTERNALTRIGINJEC_LPTIM2_OUT
Definition: stm32h7xx_hal_adc_ex.h:260
#define ADC_EXTERNALTRIGINJEC_T4_TRGO
Definition: stm32h7xx_hal_adc_ex.h:244
#define ADC_EXTERNALTRIGINJEC_T1_TRGO
Definition: stm32h7xx_hal_adc_ex.h:239
#define ADC_EXTERNALTRIGINJEC_T6_TRGO
Definition: stm32h7xx_hal_adc_ex.h:253
#define ADC_EXTERNALTRIGINJEC_T3_CC1
Definition: stm32h7xx_hal_adc_ex.h:252
#define ADC_EXTERNALTRIGINJEC_T1_TRGO2
Definition: stm32h7xx_hal_adc_ex.h:247
#define ADC_EXTERNALTRIGINJEC_LPTIM3_OUT
Definition: stm32h7xx_hal_adc_ex.h:261
#define ADC_EXTERNALTRIGINJEC_T2_TRGO
Definition: stm32h7xx_hal_adc_ex.h:241
#define ADC_SOFTWARE_START
Definition: stm32h7xx_hal_adc.h:563

Verify the ADC injected conversions external trigger.

Parameters
__INJTRIG__programmed ADC injected conversions external trigger.
Return values
SET(INJTRIG is a valid value) or RESET (INJTRIG is invalid)

◆ IS_ADC_EXTTRIGINJEC_EDGE

#define IS_ADC_EXTTRIGINJEC_EDGE (   __EDGE__)
Value:
#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING
Definition: stm32h7xx_hal_adc_ex.h:272
#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE
Definition: stm32h7xx_hal_adc_ex.h:270
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING
Definition: stm32h7xx_hal_adc_ex.h:271
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING
Definition: stm32h7xx_hal_adc_ex.h:273

Verify the ADC edge trigger setting for injected group.

Parameters
__EDGE__programmed ADC edge trigger setting.
Return values
SET(EDGE is a valid value) or RESET (EDGE is invalid)

◆ IS_ADC_INJECTED_NB_CONV

#define IS_ADC_INJECTED_NB_CONV (   __LENGTH__)    (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))

Verify the length of scheduled injected conversions group.

Parameters
__LENGTH__number of programmed conversions.
Return values
SET(LENGTH is within the maximum number of possible programmable injected conversions) or RESET (LENGTH is null or too large)

◆ IS_ADC_INJECTED_RANK

#define IS_ADC_INJECTED_RANK (   __CHANNEL__)
Value:
(((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
((__CHANNEL__) == ADC_INJECTED_RANK_4) )
#define ADC_INJECTED_RANK_3
Definition: stm32h7xx_hal_adc_ex.h:319
#define ADC_INJECTED_RANK_1
Definition: stm32h7xx_hal_adc_ex.h:317
#define ADC_INJECTED_RANK_2
Definition: stm32h7xx_hal_adc_ex.h:318
#define ADC_INJECTED_RANK_4
Definition: stm32h7xx_hal_adc_ex.h:320

Verify the ADC injected channel setting.

Parameters
__CHANNEL__programmed ADC injected channel.
Return values
SET(CHANNEL is valid) or RESET (CHANNEL is invalid)

◆ IS_ADC_MULTIMODE

#define IS_ADC_MULTIMODE (   __MODE__)
Value:
(((__MODE__) == ADC_MODE_INDEPENDENT) || \
((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \
((__MODE__) == ADC_DUALMODE_REGSIMULT) || \
((__MODE__) == ADC_DUALMODE_INTERL) || \
((__MODE__) == ADC_DUALMODE_ALTERTRIG) )
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG
Definition: stm32h7xx_hal_adc_ex.h:335
#define ADC_DUALMODE_REGINTERL_INJECSIMULT
Definition: stm32h7xx_hal_adc_ex.h:336
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT
Definition: stm32h7xx_hal_adc_ex.h:334

Verify the ADC multimode setting.

Parameters
__MODE__programmed ADC multimode setting.
Return values
SET(MODE is valid) or RESET (MODE is invalid)

◆ IS_ADC_OFFSET_NUMBER

#define IS_ADC_OFFSET_NUMBER (   __OFFSET_NUMBER__)
Value:
(((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \
((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \
((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \
((__OFFSET_NUMBER__) == ADC_OFFSET_4) )
#define ADC_OFFSET_3
Definition: stm32h7xx_hal_adc_ex.h:295
#define ADC_OFFSET_4
Definition: stm32h7xx_hal_adc_ex.h:296
#define ADC_OFFSET_2
Definition: stm32h7xx_hal_adc_ex.h:294
#define ADC_OFFSET_NONE
Definition: stm32h7xx_hal_adc_ex.h:292
#define ADC_OFFSET_1
Definition: stm32h7xx_hal_adc_ex.h:293

Verify the ADC offset management setting.

Parameters
__OFFSET_NUMBER__ADC offset management.
Return values
SET(OFFSET_NUMBER is valid) or RESET (OFFSET_NUMBER is invalid)

◆ IS_ADC_OVERSAMPLING_RATIO

#define IS_ADC_OVERSAMPLING_RATIO (   RATIO)    (((RATIO) >= 1UL) && ((RATIO) <= 1024UL))

Verify the ADC oversampling ratio.

Parameters
RATIOprogrammed ADC oversampling ratio.
Return values
SET(RATIO is a valid value) or RESET (RATIO is invalid)

◆ IS_ADC_REGOVERSAMPLING_MODE

#define IS_ADC_REGOVERSAMPLING_MODE (   __MODE__)
Value:
(((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
#define ADC_REGOVERSAMPLING_CONTINUED_MODE
Definition: stm32h7xx_hal_adc.h:884
#define ADC_REGOVERSAMPLING_RESUMED_MODE
Definition: stm32h7xx_hal_adc.h:885

Verify the ADC oversampling regular conversion resumed or continued mode.

Parameters
__MODE__programmed ADC oversampling regular conversion resumed or continued mode.
Return values
SET(MODE is valid) or RESET (MODE is invalid)

◆ IS_ADC_RIGHT_BIT_SHIFT

#define IS_ADC_RIGHT_BIT_SHIFT (   __SHIFT__)
Value:
(((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_9 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_10 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_11 ))
#define ADC_RIGHTBITSHIFT_5
Definition: stm32h7xx_hal_adc.h:835
#define ADC_RIGHTBITSHIFT_6
Definition: stm32h7xx_hal_adc.h:836
#define ADC_RIGHTBITSHIFT_2
Definition: stm32h7xx_hal_adc.h:832
#define ADC_RIGHTBITSHIFT_10
Definition: stm32h7xx_hal_adc.h:840
#define ADC_RIGHTBITSHIFT_4
Definition: stm32h7xx_hal_adc.h:834
#define ADC_RIGHTBITSHIFT_NONE
Definition: stm32h7xx_hal_adc.h:830
#define ADC_RIGHTBITSHIFT_9
Definition: stm32h7xx_hal_adc.h:839
#define ADC_RIGHTBITSHIFT_11
Definition: stm32h7xx_hal_adc.h:841
#define ADC_RIGHTBITSHIFT_1
Definition: stm32h7xx_hal_adc.h:831
#define ADC_RIGHTBITSHIFT_7
Definition: stm32h7xx_hal_adc.h:837
#define ADC_RIGHTBITSHIFT_3
Definition: stm32h7xx_hal_adc.h:833
#define ADC_RIGHTBITSHIFT_8
Definition: stm32h7xx_hal_adc.h:838

Verify the ADC oversampling shift.

Parameters
__SHIFT__programmed ADC oversampling shift.
Return values
SET(SHIFT is a valid value) or RESET (SHIFT is invalid)

◆ IS_ADC_SAMPLING_DELAY

#define IS_ADC_SAMPLING_DELAY (   __DELAY__)
Value:
(((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) )
#define ADC_TWOSAMPLINGDELAY_6CYCLES
Definition: stm32h7xx_hal_adc_ex.h:358
#define ADC_TWOSAMPLINGDELAY_3CYCLES
Definition: stm32h7xx_hal_adc_ex.h:355
#define ADC_TWOSAMPLINGDELAY_8CYCLES
Definition: stm32h7xx_hal_adc_ex.h:360
#define ADC_TWOSAMPLINGDELAY_9CYCLES
Definition: stm32h7xx_hal_adc_ex.h:361
#define ADC_TWOSAMPLINGDELAY_7CYCLES
Definition: stm32h7xx_hal_adc_ex.h:359
#define ADC_TWOSAMPLINGDELAY_1CYCLE
Definition: stm32h7xx_hal_adc_ex.h:353
#define ADC_TWOSAMPLINGDELAY_4CYCLES
Definition: stm32h7xx_hal_adc_ex.h:356
#define ADC_TWOSAMPLINGDELAY_2CYCLES
Definition: stm32h7xx_hal_adc_ex.h:354
#define ADC_TWOSAMPLINGDELAY_5CYCLES
Definition: stm32h7xx_hal_adc_ex.h:357

Verify the ADC multimode delay setting.

Parameters
__DELAY__programmed ADC multimode delay setting.
Return values
SET(DELAY is a valid value) or RESET (DELAY is invalid)

◆ IS_ADC_SINGLE_DIFFERENTIAL

#define IS_ADC_SINGLE_DIFFERENTIAL (   __SING_DIFF__)
Value:
(((__SING_DIFF__) == ADC_SINGLE_ENDED) || \
((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) )
#define ADC_SINGLE_ENDED
Definition: stm32h7xx_hal_adc_ex.h:282
#define ADC_DIFFERENTIAL_ENDED
Definition: stm32h7xx_hal_adc_ex.h:283

Verify the ADC single-ended input or differential mode setting.

Parameters
__SING_DIFF__programmed channel setting.
Return values
SET(SING_DIFF is valid) or RESET (SING_DIFF is invalid)

◆ IS_ADC_TRIGGERED_OVERSAMPLING_MODE

#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE (   __MODE__)
Value:
(((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
#define ADC_TRIGGEREDMODE_MULTI_TRIGGER
Definition: stm32h7xx_hal_adc.h:875
#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER
Definition: stm32h7xx_hal_adc.h:874

Verify the ADC oversampling triggered mode.

Parameters
__MODE__programmed ADC oversampling triggered mode.
Return values
SET(MODE is valid) or RESET (MODE is invalid)