RTEMS 6.1-rc7
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irq.h
1/*
2 * RTEMS generic MPC5200 BSP
3 *
4 * This file contains declarations for the irq controller handler.
5 *
6 * References: MPC8260ads CPU interrupt header file.
7 * Comment for that:
8 *
9 * This code is heavilly inspired by the public specification of
10 * STREAM V2 that can be found at:
11 *
12 * <http://www.chorus.com/Documentation/index.html> by following
13 * the STREAM API Specification Document link.
14 *
15 * The interrupt handling on the mpc8260 seems quite different from
16 * the 860 (I don't know the 860 well). Although some interrupts
17 * are routed via the CPM irq and some are direct to the SIU they
18 * all appear logically the same.Therefore I removed the distinction
19 * between SIU and CPM interrupts.
20 */
21
22/*
23 * Copyright (C) 1999 valette@crf.canon.fr
24 *
25 * Modified for mpc8260 by Andy Dachs <a.dachs@sstl.co.uk>
26 * Surrey Satellite Technology Limited
27 *
28 * Copyright (c) 2003 IPR Engineering
29 *
30 * Copyright (C) 2005, 2010 embedded brains GmbH & Co. KG
31 *
32 * The license and distribution terms for this file may be
33 * found in the file LICENSE in this distribution or at
34 * http://www.rtems.org/license/LICENSE.
35 */
36
37#ifndef LIBBSP_POWERPC_GEN5200_IRQ_H
38#define LIBBSP_POWERPC_GEN5200_IRQ_H
39
40#define PMCE_CE_SHADOW (1U << (31 - 31))
41#define PMCE_CSE_STICKY (1U << (31 - 21))
42#define PMCE_MSE_STICKY (1U << (31 - 10))
43#define PMCE_PSE_STICKY (1U << (31 - 2))
44#define PMCE_CSE_SOURCE(_pmce) (((_pmce) >> 8) & 0x3U)
45#define PMCE_MSE_SOURCE(_pmce) (((_pmce) >> 16) & 0x1fU)
46#define PMCE_PSE_SOURCE(_pmce) (((_pmce) >> 24) & 0x1fU)
47
48/*
49 * Peripheral IRQ handlers related definitions
50 */
51#define BSP_PER_IRQ_NUMBER 22
52#define BSP_PER_IRQ_LOWEST_OFFSET 0
53#define BSP_PER_IRQ_MAX_OFFSET \
54 (BSP_PER_IRQ_LOWEST_OFFSET + BSP_PER_IRQ_NUMBER - 1) /* 21 */
55/*
56 * Main IRQ handlers related definitions
57 */
58#define BSP_MAIN_IRQ_NUMBER 17
59#define BSP_MAIN_IRQ_LOWEST_OFFSET BSP_PER_IRQ_MAX_OFFSET + 1 /* 22 */
60#define BSP_MAIN_IRQ_MAX_OFFSET \
61 (BSP_MAIN_IRQ_LOWEST_OFFSET + BSP_MAIN_IRQ_NUMBER - 1) /* 38 */
62/*
63 * Critical IRQ handlers related definitions
64 */
65#define BSP_CRIT_IRQ_NUMBER 4
66#define BSP_CRIT_IRQ_LOWEST_OFFSET BSP_MAIN_IRQ_MAX_OFFSET + 1 /* 39 */
67#define BSP_CRIT_IRQ_MAX_OFFSET \
68 (BSP_CRIT_IRQ_LOWEST_OFFSET + BSP_CRIT_IRQ_NUMBER - 1) /* 42 */
69/*
70 * Summary of SIU interrupts
71 */
72#define BSP_SIU_IRQ_NUMBER BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 43 */
73#define BSP_SIU_IRQ_LOWEST_OFFSET BSP_PER_IRQ_LOWEST_OFFSET /* 0 */
74#define BSP_SIU_IRQ_MAX_OFFSET BSP_CRIT_IRQ_MAX_OFFSET /* 42 */
75/*
76 * Processor IRQ handlers related definitions
77 */
78#define BSP_PROCESSOR_IRQ_NUMBER 3
79#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 44 */
80#define BSP_PROCESSOR_IRQ_MAX_OFFSET \
81 (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) /* 46 */
82/*
83 * Summary
84 */
85#define BSP_IRQ_NUMBER BSP_PROCESSOR_IRQ_MAX_OFFSET + 1 /* 47 */
86#define BSP_LOWEST_OFFSET BSP_PER_IRQ_LOWEST_OFFSET /* 0 */
87#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET /* 46 */
88
89#ifndef ASM
90
91#include <rtems.h>
92#include <rtems/irq.h>
93#include <rtems/irq-extension.h>
94
95/*
96 * index table for the module specific handlers, a few entries are only placeholders
97 */
98typedef enum {
99 BSP_SIU_IRQ_SMARTCOMM = BSP_PER_IRQ_LOWEST_OFFSET + 0,
100 BSP_SIU_IRQ_PSC1 = BSP_PER_IRQ_LOWEST_OFFSET + 1,
101 BSP_SIU_IRQ_PSC2 = BSP_PER_IRQ_LOWEST_OFFSET + 2,
102 BSP_SIU_IRQ_PSC3 = BSP_PER_IRQ_LOWEST_OFFSET + 3,
103 BSP_SIU_IRQ_PSC6 = BSP_PER_IRQ_LOWEST_OFFSET + 4,
104 BSP_SIU_IRQ_ETH = BSP_PER_IRQ_LOWEST_OFFSET + 5,
105 BSP_SIU_IRQ_USB = BSP_PER_IRQ_LOWEST_OFFSET + 6,
106 BSP_SIU_IRQ_ATA = BSP_PER_IRQ_LOWEST_OFFSET + 7,
107 BSP_SIU_IRQ_PCI_CRT = BSP_PER_IRQ_LOWEST_OFFSET + 8,
108 BSP_SIU_IRQ_PCI_SC_RX = BSP_PER_IRQ_LOWEST_OFFSET + 9,
109 BSP_SIU_IRQ_PCI_SC_TX = BSP_PER_IRQ_LOWEST_OFFSET + 10,
110 BSP_SIU_IRQ_PSC4 = BSP_PER_IRQ_LOWEST_OFFSET + 11,
111 BSP_SIU_IRQ_PSC5 = BSP_PER_IRQ_LOWEST_OFFSET + 12,
112 BSP_SIU_IRQ_SPI_MODF = BSP_PER_IRQ_LOWEST_OFFSET + 13,
113 BSP_SIU_IRQ_SPI_SPIF = BSP_PER_IRQ_LOWEST_OFFSET + 14,
114 BSP_SIU_IRQ_I2C1 = BSP_PER_IRQ_LOWEST_OFFSET + 15,
115 BSP_SIU_IRQ_I2C2 = BSP_PER_IRQ_LOWEST_OFFSET + 16,
116 BSP_SIU_IRQ_MSCAN1 = BSP_PER_IRQ_LOWEST_OFFSET + 17,
117 BSP_SIU_IRQ_MSCAN2 = BSP_PER_IRQ_LOWEST_OFFSET + 18,
118 BSP_SIU_IRQ_IR_RX = BSP_PER_IRQ_LOWEST_OFFSET + 19,
119 BSP_SIU_IRQ_IR_TX = BSP_PER_IRQ_LOWEST_OFFSET + 20,
120 BSP_SIU_IRQ_XLB_ARB = BSP_PER_IRQ_LOWEST_OFFSET + 21,
121
122 /* SL_TIMER1 -- handler entry only used in case of SMI */
123 BSP_SIU_IRQ_SL_TIMER1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 0,
124 BSP_SIU_IRQ_IRQ1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 1,
125 BSP_SIU_IRQ_IRQ2 = BSP_MAIN_IRQ_LOWEST_OFFSET + 2,
126 BSP_SIU_IRQ_IRQ3 = BSP_MAIN_IRQ_LOWEST_OFFSET + 3,
127 /* LO_INT -- handler entry never used (only placeholder) */
128 BSP_SIU_IRQ_LO_INT = BSP_MAIN_IRQ_LOWEST_OFFSET + 4,
129 BSP_SIU_IRQ_RTC_PER = BSP_MAIN_IRQ_LOWEST_OFFSET + 5,
130 BSP_SIU_IRQ_RTC_STW = BSP_MAIN_IRQ_LOWEST_OFFSET + 6,
131 BSP_SIU_IRQ_GPIO_STD = BSP_MAIN_IRQ_LOWEST_OFFSET + 7,
132 BSP_SIU_IRQ_GPIO_WKUP = BSP_MAIN_IRQ_LOWEST_OFFSET + 8,
133 BSP_SIU_IRQ_TMR0 = BSP_MAIN_IRQ_LOWEST_OFFSET + 9,
134 BSP_SIU_IRQ_TMR1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 10,
135 BSP_SIU_IRQ_TMR2 = BSP_MAIN_IRQ_LOWEST_OFFSET + 1,
136 BSP_SIU_IRQ_TMR3 = BSP_MAIN_IRQ_LOWEST_OFFSET + 12,
137 BSP_SIU_IRQ_TMR4 = BSP_MAIN_IRQ_LOWEST_OFFSET + 13,
138 BSP_SIU_IRQ_TMR5 = BSP_MAIN_IRQ_LOWEST_OFFSET + 14,
139 BSP_SIU_IRQ_TMR6 = BSP_MAIN_IRQ_LOWEST_OFFSET + 15,
140 BSP_SIU_IRQ_TMR7 = BSP_MAIN_IRQ_LOWEST_OFFSET + 16,
141
142 BSP_SIU_IRQ_IRQ0 = BSP_CRIT_IRQ_LOWEST_OFFSET + 0,
143 BSP_SIU_IRQ_SL_TIMER0 = BSP_CRIT_IRQ_LOWEST_OFFSET + 1,
144 /* HI_INT -- handler entry never used (only placeholder) */
145 BSP_SIU_IRQ_HI_INT = BSP_CRIT_IRQ_LOWEST_OFFSET + 2,
146 BSP_SIU_IRQ_CSS_WKUP = BSP_CRIT_IRQ_LOWEST_OFFSET + 3,
147
148 BSP_DECREMENTER = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0,
149 BSP_SYSMGMT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1,
150 BSP_EXT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2
151} rtems_irq_symbolic_name;
152
153#define BSP_CRIT_IRQ_PRIO_LEVELS 4
154#define BSP_PERIODIC_TIMER BSP_SIU_IRQ_TMR6
155
156#define BSP_INTERRUPT_VECTOR_COUNT (BSP_MAX_OFFSET + 1)
157
158#endif
159
160#endif /* LIBBSP_POWERPC_GEN5200_IRQ_H */
This header file is provided for backward compatiblility.
This header file defines the RTEMS Classic API.