RTEMS 6.1-rc7
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cpu.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * COPYRIGHT (c) 1989-2012.
13 * On-Line Applications Research Corporation (OAR).
14 *
15 * COPYRIGHT (c) 1995 i-cubed ltd.
16 *
17 * To anyone who acknowledges that this file is provided "AS IS"
18 * without any express or implied warranty:
19 * permission to use, copy, modify, and distribute this file
20 * for any purpose is hereby granted without fee, provided that
21 * the above copyright notice and this notice appears in all
22 * copies, and that the name of i-cubed limited not be used in
23 * advertising or publicity pertaining to distribution of the
24 * software without specific, written prior permission.
25 * i-cubed limited makes no representations about the suitability
26 * of this software for any purpose.
27 *
28 * Copyright (c) 2001 Andy Dachs <a.dachs@sstl.co.uk>.
29 *
30 * Copyright (c) 2001 Surrey Satellite Technology Limited (SSTL).
31 *
32 * Copyright (C) 2010, 2020 embedded brains GmbH & Co. KG
33 *
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
36 * are met:
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
44 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
45 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
46 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
47 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
53 * POSSIBILITY OF SUCH DAMAGE.
54 */
55
56#ifndef _RTEMS_SCORE_CPU_H
57#define _RTEMS_SCORE_CPU_H
58
60#if defined(RTEMS_PARAVIRT)
61#include <rtems/score/paravirt.h>
62#endif
63#include <rtems/score/powerpc.h>
65
66#ifndef ASM
67 #include <string.h> /* for memset() */
68#endif
69
70#ifdef __cplusplus
71extern "C" {
72#endif
73
74/* conditional compilation parameters */
75
76/*
77 * Does the stack grow up (toward higher addresses) or down
78 * (toward lower addresses)?
79 *
80 * If TRUE, then the grows upward.
81 * If FALSE, then the grows toward smaller addresses.
82 */
83
84#define CPU_STACK_GROWS_UP FALSE
85
86#define CPU_CACHE_LINE_BYTES PPC_STRUCTURE_ALIGNMENT
87
88#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
89
90/*
91 * Does the CPU have hardware floating point?
92 *
93 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
94 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
95 *
96 * If there is a FP coprocessor such as the i387 or mc68881, then
97 * the answer is TRUE.
98 *
99 * The macro name "PPC_HAS_FPU" should be made CPU specific.
100 * It indicates whether or not this CPU model has FP support. For
101 * example, it would be possible to have an i386_nofp CPU model
102 * which set this to false to indicate that you have an i386 without
103 * an i387 and wish to leave floating point support out of RTEMS.
104 */
105
106#if ( PPC_HAS_FPU == 1 )
107#define CPU_HARDWARE_FP TRUE
108#define CPU_SOFTWARE_FP FALSE
109#else
110#define CPU_HARDWARE_FP FALSE
111#define CPU_SOFTWARE_FP FALSE
112#endif
113
114/*
115 * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
116 *
117 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
118 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
119 *
120 * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
121 *
122 * PowerPC Note: It appears the GCC can implicitly generate FPU
123 * and Altivec instructions when you least expect them. So make
124 * all tasks floating point.
125 */
126
127#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP
128
129/*
130 * Should the IDLE task have a floating point context?
131 *
132 * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
133 * and it has a floating point context which is switched in and out.
134 * If FALSE, then the IDLE task does not have a floating point context.
135 *
136 * Setting this to TRUE negatively impacts the time required to preempt
137 * the IDLE task from an interrupt because the floating point context
138 * must be saved as part of the preemption.
139 */
140
141#define CPU_IDLE_TASK_IS_FP FALSE
142
143#define CPU_MAXIMUM_PROCESSORS 32
144
145/*
146 * Processor defined structures required for cpukit/score.
147 */
148
149/*
150 * Contexts
151 *
152 * Generally there are 2 types of context to save.
153 * 1. Interrupt registers to save
154 * 2. Task level registers to save
155 *
156 * This means we have the following 3 context items:
157 * 1. task level context stuff:: Context_Control
158 * 2. floating point task stuff:: Context_Control_fp
159 * 3. special interrupt level context :: Context_Control_interrupt
160 *
161 * On some processors, it is cost-effective to save only the callee
162 * preserved registers during a task context switch. This means
163 * that the ISR code needs to save those registers which do not
164 * persist across function calls. It is not mandatory to make this
165 * distinctions between the caller/callee saves registers for the
166 * purpose of minimizing context saved during task switch and on interrupts.
167 * If the cost of saving extra registers is minimal, simplicity is the
168 * choice. Save the same context on interrupt entry as for tasks in
169 * this case.
170 *
171 * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
172 * care should be used in designing the context area.
173 *
174 * On some CPUs with hardware floating point support, the Context_Control_fp
175 * structure will not be used or it simply consist of an array of a
176 * fixed number of bytes. This is done when the floating point context
177 * is dumped by a "FP save context" type instruction and the format
178 * is not really defined by the CPU. In this case, there is no need
179 * to figure out the exact format -- only the size. Of course, although
180 * this is enough information for RTEMS, it is probably not enough for
181 * a debugger such as gdb. But that is another problem.
182 */
183
184#ifndef __SPE__
185 #define PPC_GPR_TYPE uintptr_t
186 #if defined(__powerpc64__)
187 #define PPC_GPR_SIZE 8
188 #define PPC_GPR_LOAD ld
189 #define PPC_GPR_STORE std
190 #else
191 #define PPC_GPR_SIZE 4
192 #define PPC_GPR_LOAD lwz
193 #define PPC_GPR_STORE stw
194 #endif
195#else
196 #define PPC_GPR_TYPE uint64_t
197 #define PPC_GPR_SIZE 8
198 #define PPC_GPR_LOAD evldd
199 #define PPC_GPR_STORE evstdd
200#endif
201
202#if defined(__powerpc64__)
203 #define PPC_REG_SIZE 8
204 #define PPC_REG_LOAD ld
205 #define PPC_REG_STORE std
206 #define PPC_REG_STORE_UPDATE stdu
207 #define PPC_REG_CMP cmpd
208#else
209 #define PPC_REG_SIZE 4
210 #define PPC_REG_LOAD lwz
211 #define PPC_REG_STORE stw
212 #define PPC_REG_STORE_UPDATE stwu
213 #define PPC_REG_CMP cmpw
214#endif
215
216#ifndef ASM
217
218/*
219 * Non-volatile context according to E500ABIUG, EABI and 32-bit TLS (according
220 * to "Power Architecture 32-bit Application Binary Interface Supplement 1.0 -
221 * Linux and Embedded")
222 */
223typedef struct {
224 uint32_t msr;
225 uint32_t cr;
226 uintptr_t gpr1;
227 uintptr_t lr;
228 PPC_GPR_TYPE gpr14;
229 PPC_GPR_TYPE gpr15;
230 PPC_GPR_TYPE gpr16;
231 PPC_GPR_TYPE gpr17;
232 PPC_GPR_TYPE gpr18;
233 PPC_GPR_TYPE gpr19;
234 PPC_GPR_TYPE gpr20;
235 PPC_GPR_TYPE gpr21;
236 PPC_GPR_TYPE gpr22;
237 PPC_GPR_TYPE gpr23;
238 PPC_GPR_TYPE gpr24;
239 PPC_GPR_TYPE gpr25;
240 PPC_GPR_TYPE gpr26;
241 PPC_GPR_TYPE gpr27;
242 PPC_GPR_TYPE gpr28;
243 PPC_GPR_TYPE gpr29;
244 PPC_GPR_TYPE gpr30;
245 PPC_GPR_TYPE gpr31;
246 uint32_t isr_dispatch_disable;
247 uint32_t reserved_for_alignment;
248 #if defined(PPC_MULTILIB_ALTIVEC)
249 #if !defined(__powerpc64__)
250 uint32_t reserved_for_alignment_2[4];
251 #endif
252 uint32_t vrsave;
253 uint32_t reserved_for_alignment_3[2];
254 /* This field must take stvewx/lvewx requirements into account */
255 uint32_t vscr;
256 uint8_t v20[16];
257 uint8_t v21[16];
258 uint8_t v22[16];
259 uint8_t v23[16];
260 uint8_t v24[16];
261 uint8_t v25[16];
262 uint8_t v26[16];
263 uint8_t v27[16];
264 uint8_t v28[16];
265 uint8_t v29[16];
266 uint8_t v30[16];
267 uint8_t v31[16];
268 #elif defined(__ALTIVEC__)
269 /*
270 * 12 non-volatile vector registers, cache-aligned area for vscr/vrsave
271 * and padding to ensure cache-alignment. Unfortunately, we can't verify
272 * the cache line size here in the cpukit but altivec support code will
273 * produce an error if this is ever different from 32 bytes.
274 *
275 * Note: it is the BSP/CPU-support's responsibility to save/restore
276 * volatile vregs across interrupts and exceptions.
277 */
278 uint8_t altivec[16*12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE];
279 #endif
280 #if defined(PPC_MULTILIB_FPU)
281 double f14;
282 double f15;
283 double f16;
284 double f17;
285 double f18;
286 double f19;
287 double f20;
288 double f21;
289 double f22;
290 double f23;
291 double f24;
292 double f25;
293 double f26;
294 double f27;
295 double f28;
296 double f29;
297 double f30;
298 double f31;
299 #endif
300 /*
301 * The following items are at the structure end, so that we can use dcbz for
302 * the previous items to optimize the context switch. We must not set the
303 * following items to zero via the dcbz.
304 */
305 uintptr_t tp;
306 #if defined(RTEMS_SMP)
307 volatile uint32_t is_executing;
308 #endif
310
311typedef struct {
312 uint8_t context [
313 PPC_DEFAULT_CACHE_LINE_SIZE
314 + sizeof(ppc_context)
315 + (sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE == 0
316 ? 0
317 : PPC_DEFAULT_CACHE_LINE_SIZE
318 - sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE)
319 ];
321
322static inline ppc_context *ppc_get_context( const Context_Control *context )
323{
324 uintptr_t clsz = PPC_DEFAULT_CACHE_LINE_SIZE;
325 uintptr_t mask = clsz - 1;
326 uintptr_t addr = (uintptr_t) context;
327
328 return (ppc_context *) ((addr & ~mask) + clsz);
329}
330
331#define _CPU_Context_Get_SP( _context ) \
332 ppc_get_context(_context)->gpr1
333
334#ifdef RTEMS_SMP
335 static inline bool _CPU_Context_Get_is_executing(
337 )
338 {
339 return ppc_get_context(context)->is_executing;
340 }
341
342 static inline void _CPU_Context_Set_is_executing(
344 bool is_executing
345 )
346 {
347 ppc_get_context(context)->is_executing = is_executing;
348 }
349#endif
350#endif /* ASM */
351
352#define PPC_CONTEXT_OFFSET_MSR (PPC_DEFAULT_CACHE_LINE_SIZE)
353#define PPC_CONTEXT_OFFSET_CR (PPC_DEFAULT_CACHE_LINE_SIZE + 4)
354#define PPC_CONTEXT_OFFSET_GPR1 (PPC_DEFAULT_CACHE_LINE_SIZE + 8)
355#define PPC_CONTEXT_OFFSET_LR (PPC_DEFAULT_CACHE_LINE_SIZE + PPC_REG_SIZE + 8)
356
357#define PPC_CONTEXT_GPR_OFFSET( gpr ) \
358 (((gpr) - 14) * PPC_GPR_SIZE + \
359 PPC_DEFAULT_CACHE_LINE_SIZE + 8 + 2 * PPC_REG_SIZE)
360
361#define PPC_CONTEXT_OFFSET_GPR14 PPC_CONTEXT_GPR_OFFSET( 14 )
362#define PPC_CONTEXT_OFFSET_GPR15 PPC_CONTEXT_GPR_OFFSET( 15 )
363#define PPC_CONTEXT_OFFSET_GPR16 PPC_CONTEXT_GPR_OFFSET( 16 )
364#define PPC_CONTEXT_OFFSET_GPR17 PPC_CONTEXT_GPR_OFFSET( 17 )
365#define PPC_CONTEXT_OFFSET_GPR18 PPC_CONTEXT_GPR_OFFSET( 18 )
366#define PPC_CONTEXT_OFFSET_GPR19 PPC_CONTEXT_GPR_OFFSET( 19 )
367#define PPC_CONTEXT_OFFSET_GPR20 PPC_CONTEXT_GPR_OFFSET( 20 )
368#define PPC_CONTEXT_OFFSET_GPR21 PPC_CONTEXT_GPR_OFFSET( 21 )
369#define PPC_CONTEXT_OFFSET_GPR22 PPC_CONTEXT_GPR_OFFSET( 22 )
370#define PPC_CONTEXT_OFFSET_GPR23 PPC_CONTEXT_GPR_OFFSET( 23 )
371#define PPC_CONTEXT_OFFSET_GPR24 PPC_CONTEXT_GPR_OFFSET( 24 )
372#define PPC_CONTEXT_OFFSET_GPR25 PPC_CONTEXT_GPR_OFFSET( 25 )
373#define PPC_CONTEXT_OFFSET_GPR26 PPC_CONTEXT_GPR_OFFSET( 26 )
374#define PPC_CONTEXT_OFFSET_GPR27 PPC_CONTEXT_GPR_OFFSET( 27 )
375#define PPC_CONTEXT_OFFSET_GPR28 PPC_CONTEXT_GPR_OFFSET( 28 )
376#define PPC_CONTEXT_OFFSET_GPR29 PPC_CONTEXT_GPR_OFFSET( 29 )
377#define PPC_CONTEXT_OFFSET_GPR30 PPC_CONTEXT_GPR_OFFSET( 30 )
378#define PPC_CONTEXT_OFFSET_GPR31 PPC_CONTEXT_GPR_OFFSET( 31 )
379#define PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE PPC_CONTEXT_GPR_OFFSET( 32 )
380
381#ifdef PPC_MULTILIB_ALTIVEC
382 #ifdef __powerpc64__
383 #define PPC_CONTEXT_OFFSET_VRSAVE \
384 ( PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8 )
385 #else
386 #define PPC_CONTEXT_OFFSET_VRSAVE \
387 ( PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 24 )
388 #endif
389 #define PPC_CONTEXT_OFFSET_VSCR ( PPC_CONTEXT_OFFSET_VRSAVE + 12 )
390 #define PPC_CONTEXT_OFFSET_V( v ) \
391 ( ( ( v ) - 20 ) * 16 + PPC_CONTEXT_OFFSET_VRSAVE + 16)
392 #define PPC_CONTEXT_OFFSET_V20 PPC_CONTEXT_OFFSET_V( 20 )
393 #define PPC_CONTEXT_OFFSET_V21 PPC_CONTEXT_OFFSET_V( 21 )
394 #define PPC_CONTEXT_OFFSET_V22 PPC_CONTEXT_OFFSET_V( 22 )
395 #define PPC_CONTEXT_OFFSET_V23 PPC_CONTEXT_OFFSET_V( 23 )
396 #define PPC_CONTEXT_OFFSET_V24 PPC_CONTEXT_OFFSET_V( 24 )
397 #define PPC_CONTEXT_OFFSET_V25 PPC_CONTEXT_OFFSET_V( 25 )
398 #define PPC_CONTEXT_OFFSET_V26 PPC_CONTEXT_OFFSET_V( 26 )
399 #define PPC_CONTEXT_OFFSET_V27 PPC_CONTEXT_OFFSET_V( 27 )
400 #define PPC_CONTEXT_OFFSET_V28 PPC_CONTEXT_OFFSET_V( 28 )
401 #define PPC_CONTEXT_OFFSET_V29 PPC_CONTEXT_OFFSET_V( 29 )
402 #define PPC_CONTEXT_OFFSET_V30 PPC_CONTEXT_OFFSET_V( 30 )
403 #define PPC_CONTEXT_OFFSET_V31 PPC_CONTEXT_OFFSET_V( 31 )
404 #define PPC_CONTEXT_OFFSET_F( f ) \
405 ( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_V( 32 ) )
406#else
407 #define PPC_CONTEXT_OFFSET_F( f ) \
408 ( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8 )
409#endif
410
411#ifdef PPC_MULTILIB_FPU
412 #define PPC_CONTEXT_OFFSET_F14 PPC_CONTEXT_OFFSET_F( 14 )
413 #define PPC_CONTEXT_OFFSET_F15 PPC_CONTEXT_OFFSET_F( 15 )
414 #define PPC_CONTEXT_OFFSET_F16 PPC_CONTEXT_OFFSET_F( 16 )
415 #define PPC_CONTEXT_OFFSET_F17 PPC_CONTEXT_OFFSET_F( 17 )
416 #define PPC_CONTEXT_OFFSET_F18 PPC_CONTEXT_OFFSET_F( 18 )
417 #define PPC_CONTEXT_OFFSET_F19 PPC_CONTEXT_OFFSET_F( 19 )
418 #define PPC_CONTEXT_OFFSET_F20 PPC_CONTEXT_OFFSET_F( 20 )
419 #define PPC_CONTEXT_OFFSET_F21 PPC_CONTEXT_OFFSET_F( 21 )
420 #define PPC_CONTEXT_OFFSET_F22 PPC_CONTEXT_OFFSET_F( 22 )
421 #define PPC_CONTEXT_OFFSET_F23 PPC_CONTEXT_OFFSET_F( 23 )
422 #define PPC_CONTEXT_OFFSET_F24 PPC_CONTEXT_OFFSET_F( 24 )
423 #define PPC_CONTEXT_OFFSET_F25 PPC_CONTEXT_OFFSET_F( 25 )
424 #define PPC_CONTEXT_OFFSET_F26 PPC_CONTEXT_OFFSET_F( 26 )
425 #define PPC_CONTEXT_OFFSET_F27 PPC_CONTEXT_OFFSET_F( 27 )
426 #define PPC_CONTEXT_OFFSET_F28 PPC_CONTEXT_OFFSET_F( 28 )
427 #define PPC_CONTEXT_OFFSET_F29 PPC_CONTEXT_OFFSET_F( 29 )
428 #define PPC_CONTEXT_OFFSET_F30 PPC_CONTEXT_OFFSET_F( 30 )
429 #define PPC_CONTEXT_OFFSET_F31 PPC_CONTEXT_OFFSET_F( 31 )
430#endif
431
432#if defined(PPC_MULTILIB_FPU)
433 #define PPC_CONTEXT_VOLATILE_SIZE PPC_CONTEXT_OFFSET_F( 32 )
434#elif defined(PPC_MULTILIB_ALTIVEC)
435 #define PPC_CONTEXT_VOLATILE_SIZE PPC_CONTEXT_OFFSET_V( 33 )
436#elif defined(__ALTIVEC__)
437 #define PPC_CONTEXT_VOLATILE_SIZE \
438 (PPC_CONTEXT_GPR_OFFSET( 32 ) + 8 \
439 + 16 * 12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE)
440#else
441 #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_GPR_OFFSET( 32 ) + 8)
442#endif
443
444#define PPC_CONTEXT_OFFSET_TP PPC_CONTEXT_VOLATILE_SIZE
445
446#ifdef RTEMS_SMP
447 #define PPC_CONTEXT_OFFSET_IS_EXECUTING \
448 (PPC_CONTEXT_OFFSET_TP + PPC_REG_SIZE)
449#endif
450
451#ifndef ASM
452#if (PPC_HAS_FPU == 1)
453typedef struct {
454 /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
455 * procedure calls. However, this would mean that the interrupt
456 * frame had to hold f0-f13, and the fpscr. And as the majority
457 * of tasks will not have an FP context, we will save the whole
458 * context here.
459 */
460#if (PPC_HAS_DOUBLE == 1)
461 double f[32];
462 uint64_t fpscr;
463#else
464 float f[32];
465 uint32_t fpscr;
466#endif
468#endif /* (PPC_HAS_FPU == 1) */
469#endif /* ASM */
470
471/*
472 * Does the CPU follow the simple vectored interrupt model?
473 *
474 * If TRUE, then RTEMS allocates the vector table it internally manages.
475 * If FALSE, then the BSP is assumed to allocate and manage the vector
476 * table
477 *
478 * PowerPC Specific Information:
479 *
480 * The PowerPC and x86 were the first to use the PIC interrupt model.
481 * They do not use the simple vectored interrupt model.
482 */
483#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
484
485/*
486 * Does the RTEMS invoke the user's ISR with the vector number and
487 * a pointer to the saved interrupt frame (1) or just the vector
488 * number (0)?
489 */
490
491#define CPU_ISR_PASSES_FRAME_POINTER FALSE
492
493/*
494 * Should the saving of the floating point registers be deferred
495 * until a context switch is made to another different floating point
496 * task?
497 *
498 * If TRUE, then the floating point context will not be stored until
499 * necessary. It will remain in the floating point registers and not
500 * disturned until another floating point task is switched to.
501 *
502 * If FALSE, then the floating point context is saved when a floating
503 * point task is switched out and restored when the next floating point
504 * task is restored. The state of the floating point registers between
505 * those two operations is not specified.
506 *
507 * If the floating point context does NOT have to be saved as part of
508 * interrupt dispatching, then it should be safe to set this to TRUE.
509 *
510 * Setting this flag to TRUE results in using a different algorithm
511 * for deciding when to save and restore the floating point context.
512 * The deferred FP switch algorithm minimizes the number of times
513 * the FP context is saved and restored. The FP context is not saved
514 * until a context switch is made to another, different FP task.
515 * Thus in a system with only one FP task, the FP context will never
516 * be saved or restored.
517 *
518 * Note, however that compilers may use floating point registers/
519 * instructions for optimization or they may save/restore FP registers
520 * on the stack. You must not use deferred switching in these cases
521 * and on the PowerPC attempting to do so will raise a "FP unavailable"
522 * exception.
523 */
524/*
525 * ACB Note: This could make debugging tricky..
526 */
527
528/* conservative setting (FALSE); probably doesn't affect performance too much */
529#define CPU_USE_DEFERRED_FP_SWITCH FALSE
530
531#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
532
533/*
534 * Processor defined structures required for cpukit/score.
535 */
536
537#ifndef ASM
538
539/*
540 * This variable is optional. It is used on CPUs on which it is difficult
541 * to generate an "uninitialized" FP context. It is filled in by
542 * _CPU_Initialize and copied into the task's FP context area during
543 * _CPU_Context_Initialize.
544 */
545
546/* EXTERN Context_Control_fp _CPU_Null_fp_context; */
547
548#endif /* ndef ASM */
549
550/*
551 * This defines the number of levels and the mask used to pick those
552 * bits out of a thread mode.
553 */
554
555#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */
556
557/*
558 * The size of the floating point context area. On some CPUs this
559 * will not be a "sizeof" because the format of the floating point
560 * area is not defined -- only the size is. This is usually on
561 * CPUs with a "floating point save context" instruction.
562 */
563
564#if (PPC_HAS_FPU == 1)
565#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
566#endif
567
568/*
569 * (Optional) # of bytes for libmisc/stackchk to check
570 * If not specifed, then it defaults to something reasonable
571 * for most architectures.
572 */
573
574#define CPU_STACK_CHECK_PATTERN_INITIALIZER \
575 { 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
576 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
577 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
578 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
579 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
580 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
581 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
582 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06 }
583
584/*
585 * Amount of extra stack (above minimum stack size) required by
586 * MPCI receive server thread. Remember that in a multiprocessor
587 * system this thread must exist and be able to process all directives.
588 */
589
590#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
591
592/*
593 * This is defined if the port has a special way to report the ISR nesting
594 * level. Most ports maintain the variable _ISR_Nest_level. Note that
595 * this is not an option - RTEMS/score _relies_ on _ISR_Nest_level
596 * being maintained (e.g. watchdog queues).
597 */
598
599#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
600
601/*
602 * ISR handler macros
603 */
604
605/*
606 * Disable all interrupts for an RTEMS critical section. The previous
607 * level is returned in _isr_cookie.
608 */
609
610#ifndef ASM
611
612static inline bool _CPU_ISR_Is_enabled( uint32_t level )
613{
614 return ( level & MSR_EE ) != 0;
615}
616
617#if !defined(PPC_DISABLE_INLINE_ISR_DISABLE_ENABLE)
618
619static inline uint32_t _CPU_ISR_Get_level( void )
620{
621 uint32_t msr;
622 _CPU_MSR_GET(msr);
623 if (msr & MSR_EE) return 0;
624 else return 1;
625}
626
627static inline void _CPU_ISR_Set_level( uint32_t level )
628{
629 uint32_t msr;
630 _CPU_MSR_GET(msr);
631 if (!(level & CPU_MODES_INTERRUPT_MASK)) {
632 msr |= ppc_interrupt_get_disable_mask();
633 }
634 else {
635 msr &= ~ppc_interrupt_get_disable_mask();
636 }
637 _CPU_MSR_SET(msr);
638}
639#else
640/* disable, enable, etc. are in registers.h */
641uint32_t ppc_get_interrupt_level( void );
642void ppc_set_interrupt_level( uint32_t level );
643#define _CPU_ISR_Get_level( _new_level ) ppc_get_interrupt_level()
644#define _CPU_ISR_Set_level( _new_level ) ppc_set_interrupt_level(_new_level)
645#endif
646
647#endif /* ASM */
648
649/*
650 * Should be large enough to run all RTEMS tests. This ensures
651 * that a "reasonable" small application should not have any problems.
652 */
653
654#define CPU_STACK_MINIMUM_SIZE (1024*8)
655
656#if defined(__powerpc64__)
657#define CPU_SIZEOF_POINTER 8
658#else
659#define CPU_SIZEOF_POINTER 4
660#endif
661
662/*
663 * CPU's worst alignment requirement for data types on a byte boundary. This
664 * alignment does not take into account the requirements for the stack.
665 */
666
667#define CPU_ALIGNMENT (PPC_ALIGNMENT)
668
669/*
670 * This number corresponds to the byte alignment requirement for the
671 * heap handler. This alignment requirement may be stricter than that
672 * for the data types alignment specified by CPU_ALIGNMENT. It is
673 * common for the heap to follow the same alignment requirement as
674 * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap,
675 * then this should be set to CPU_ALIGNMENT.
676 *
677 * NOTE: This does not have to be a power of 2. It does have to
678 * be greater or equal to than CPU_ALIGNMENT.
679 */
680
681#define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT)
682
683#define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT)
684
685#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
686
687#ifndef ASM
688/* The following routine swaps the endian format of an unsigned int.
689 * It must be static because it is referenced indirectly.
690 *
691 * This version will work on any processor, but if there is a better
692 * way for your CPU PLEASE use it. The most common way to do this is to:
693 *
694 * swap least significant two bytes with 16-bit rotate
695 * swap upper and lower 16-bits
696 * swap most significant two bytes with 16-bit rotate
697 *
698 * Some CPUs have special instructions which swap a 32-bit quantity in
699 * a single instruction (e.g. i486). It is probably best to avoid
700 * an "endian swapping control bit" in the CPU. One good reason is
701 * that interrupts would probably have to be disabled to ensure that
702 * an interrupt does not try to access the same "chunk" with the wrong
703 * endian. Another good reason is that on some CPUs, the endian bit
704 * endianness for ALL fetches -- both code and data -- so the code
705 * will be fetched incorrectly.
706 */
707
708static inline uint32_t CPU_swap_u32(
709 uint32_t value
710)
711{
712 uint32_t swapped;
713
714 __asm__ volatile("rlwimi %0,%1,8,24,31;"
715 "rlwimi %0,%1,24,16,23;"
716 "rlwimi %0,%1,8,8,15;"
717 "rlwimi %0,%1,24,0,7;" :
718 "=&r" ((swapped)) : "r" ((value)));
719
720 return( swapped );
721}
722
723#define CPU_swap_u16( value ) \
724 (((value&0xff) << 8) | ((value >> 8)&0xff))
725
726typedef uint32_t CPU_Counter_ticks;
727
728uint32_t _CPU_Counter_frequency( void );
729
730static inline CPU_Counter_ticks _CPU_Counter_read( void )
731{
732 CPU_Counter_ticks value;
733
734#if defined(__PPC_CPU_E6500__)
735 /* Use Alternate Time Base */
736 __asm__ volatile( "mfspr %0, 526" : "=r" (value) );
737#elif defined(mpc860)
738 __asm__ volatile( "mftb %0" : "=r" (value) );
739#else
740 __asm__ volatile( "mfspr %0, 268" : "=r" (value) );
741#endif
742
743 return value;
744}
745
746#endif /* ASM */
747
748
749#ifndef ASM
750/* Context handler macros */
751
752/*
753 * Initialize the context to a state suitable for starting a
754 * task after a context restore operation. Generally, this
755 * involves:
756 *
757 * - setting a starting address
758 * - preparing the stack
759 * - preparing the stack and frame pointers
760 * - setting the proper interrupt level in the context
761 * - initializing the floating point context
762 *
763 * This routine generally does not set any unnecessary register
764 * in the context. The state of the "general data" registers is
765 * undefined at task start time.
766 */
767
768void _CPU_Context_Initialize(
769 Context_Control *the_context,
770 void *stack_base,
771 size_t size,
772 uint32_t new_level,
773 void *entry_point,
774 bool is_fp,
775 void *tls_area
776);
777
778/*
779 * This routine is responsible for somehow restarting the currently
780 * executing task. If you are lucky, then all that is necessary
781 * is restoring the context. Otherwise, there will need to be
782 * a special assembly routine which does something special in this
783 * case. Context_Restore should work most of the time. It will
784 * not work if restarting self conflicts with the stack frame
785 * assumptions of restoring a context.
786 */
787
788#define _CPU_Context_Restart_self( _the_context ) \
789 _CPU_Context_restore( (_the_context) );
790
791/*
792 * This routine initializes the FP context area passed to it to.
793 * There are a few standard ways in which to initialize the
794 * floating point context. The code included for this macro assumes
795 * that this is a CPU in which a "initial" FP context was saved into
796 * _CPU_Null_fp_context and it simply copies it to the destination
797 * context passed to it.
798 *
799 * Other models include (1) not doing anything, and (2) putting
800 * a "null FP status word" in the correct place in the FP context.
801 */
802
803#define _CPU_Context_Initialize_fp( _destination ) \
804 memset( *(_destination), 0, sizeof( **(_destination) ) )
805
806/* end of Context handler macros */
807#endif /* ASM */
808
809#ifndef ASM
810
811#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
812
813/* Bitfield handler macros */
814
815#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
816
817/*
818 * This routine sets _output to the bit number of the first bit
819 * set in _value. _value is of CPU dependent type Priority_bit_map_Word.
820 * This type may be either 16 or 32 bits wide although only the 16
821 * least significant bits will be used.
822 *
823 * There are a number of variables in using a "find first bit" type
824 * instruction.
825 *
826 * (1) What happens when run on a value of zero?
827 * (2) Bits may be numbered from MSB to LSB or vice-versa.
828 * (3) The numbering may be zero or one based.
829 * (4) The "find first bit" instruction may search from MSB or LSB.
830 *
831 * RTEMS guarantees that (1) will never happen so it is not a concern.
832 * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
833 * _CPU_Priority_Bits_index(). These three form a set of routines
834 * which must logically operate together. Bits in the _value are
835 * set and cleared based on masks built by _CPU_Priority_mask().
836 * The basic major and minor values calculated by _Priority_Major()
837 * and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
838 * to properly range between the values returned by the "find first bit"
839 * instruction. This makes it possible for _Priority_Get_highest() to
840 * calculate the major and directly index into the minor table.
841 * This mapping is necessary to ensure that 0 (a high priority major/minor)
842 * is the first bit found.
843 *
844 * This entire "find first bit" and mapping process depends heavily
845 * on the manner in which a priority is broken into a major and minor
846 * components with the major being the 4 MSB of a priority and minor
847 * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
848 * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next
849 * to the lowest priority.
850 *
851 * If your CPU does not have a "find first bit" instruction, then
852 * there are ways to make do without it. Here are a handful of ways
853 * to implement this in software:
854 *
855 * - a series of 16 bit test instructions
856 * - a "binary search using if's"
857 * - _number = 0
858 * if _value > 0x00ff
859 * _value >>=8
860 * _number = 8;
861 *
862 * if _value > 0x0000f
863 * _value >=8
864 * _number += 4
865 *
866 * _number += bit_set_table[ _value ]
867 *
868 * where bit_set_table[ 16 ] has values which indicate the first
869 * bit set
870 */
871
872#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
873 { \
874 __asm__ volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
875 "1" ((_value))); \
876 (_output) = (_output) - 16; \
877 }
878
879/* end of Bitfield handler macros */
880
881/*
882 * This routine builds the mask which corresponds to the bit fields
883 * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion
884 * for that routine.
885 */
886
887#define _CPU_Priority_Mask( _bit_number ) \
888 ( 0x8000u >> (_bit_number) )
889
890/*
891 * This routine translates the bit numbers returned by
892 * _CPU_Bitfield_Find_first_bit() into something suitable for use as
893 * a major or minor component of a priority. See the discussion
894 * for that routine.
895 */
896
897#define _CPU_Priority_bits_index( _priority ) \
898 (_priority)
899
900/* end of Priority handler macros */
901#endif /* ASM */
902
903/* functions */
904
905#ifndef ASM
906
907/*
908 * _CPU_Initialize
909 *
910 * This routine performs CPU dependent initialization.
911 */
912
913void _CPU_Initialize(void);
914
915RTEMS_NO_RETURN void *_CPU_Thread_Idle_body( uintptr_t ignored );
916
917/*
918 * _CPU_Context_switch
919 *
920 * This routine switches from the run context to the heir context.
921 */
922
924 Context_Control *run,
925 Context_Control *heir
926);
927
928RTEMS_NO_RETURN void _CPU_Context_switch_no_return(
929 Context_Control *executing,
930 Context_Control *heir
931);
932
933/*
934 * _CPU_Context_restore
935 *
936 * This routine is generallu used only to restart self in an
937 * efficient manner. It may simply be a label in _CPU_Context_switch.
938 *
939 * NOTE: May be unnecessary to reload some registers.
940 */
941
942RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context );
943
944#if (PPC_HAS_FPU == 1)
945/*
946 * _CPU_Context_save_fp
947 *
948 * This routine saves the floating point context passed to it.
949 */
950
952 Context_Control_fp **fp_context_ptr
953);
954
955/*
956 * _CPU_Context_restore_fp
957 *
958 * This routine restores the floating point context passed to it.
959 */
960
962 Context_Control_fp **fp_context_ptr
963);
964#endif
965
966#ifdef RTEMS_SMP
967 uint32_t _CPU_SMP_Initialize( void );
968
969 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
970
971 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
972
973 void _CPU_SMP_Prepare_start_multitasking( void );
974
975 static inline uint32_t _CPU_SMP_Get_current_processor( void )
976 {
977 uint32_t pir;
978
979 /* Use Book E Processor ID Register (PIR) */
980 __asm__ volatile (
981 "mfspr %[pir], 286"
982 : [pir] "=&r" (pir)
983 );
984
985 return pir;
986 }
987
988 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
989#endif
990
991typedef struct {
992 uintptr_t EXC_SRR0;
993 uintptr_t EXC_SRR1;
994 uint32_t _EXC_number;
995 uint32_t RESERVED_FOR_ALIGNMENT_0;
996 uint32_t EXC_CR;
997 uint32_t EXC_XER;
998 uintptr_t EXC_CTR;
999 uintptr_t EXC_LR;
1000 uintptr_t RESERVED_FOR_ALIGNMENT_1;
1001 #ifdef __SPE__
1002 uint32_t EXC_SPEFSCR;
1003 uint64_t EXC_ACC;
1004 #endif
1005 PPC_GPR_TYPE GPR0;
1006 PPC_GPR_TYPE GPR1;
1007 PPC_GPR_TYPE GPR2;
1008 PPC_GPR_TYPE GPR3;
1009 PPC_GPR_TYPE GPR4;
1010 PPC_GPR_TYPE GPR5;
1011 PPC_GPR_TYPE GPR6;
1012 PPC_GPR_TYPE GPR7;
1013 PPC_GPR_TYPE GPR8;
1014 PPC_GPR_TYPE GPR9;
1015 PPC_GPR_TYPE GPR10;
1016 PPC_GPR_TYPE GPR11;
1017 PPC_GPR_TYPE GPR12;
1018 PPC_GPR_TYPE GPR13;
1019 PPC_GPR_TYPE GPR14;
1020 PPC_GPR_TYPE GPR15;
1021 PPC_GPR_TYPE GPR16;
1022 PPC_GPR_TYPE GPR17;
1023 PPC_GPR_TYPE GPR18;
1024 PPC_GPR_TYPE GPR19;
1025 PPC_GPR_TYPE GPR20;
1026 PPC_GPR_TYPE GPR21;
1027 PPC_GPR_TYPE GPR22;
1028 PPC_GPR_TYPE GPR23;
1029 PPC_GPR_TYPE GPR24;
1030 PPC_GPR_TYPE GPR25;
1031 PPC_GPR_TYPE GPR26;
1032 PPC_GPR_TYPE GPR27;
1033 PPC_GPR_TYPE GPR28;
1034 PPC_GPR_TYPE GPR29;
1035 PPC_GPR_TYPE GPR30;
1036 PPC_GPR_TYPE GPR31;
1037 uintptr_t RESERVED_FOR_ALIGNMENT_2;
1038 #ifdef PPC_MULTILIB_ALTIVEC
1039 uint32_t VRSAVE;
1040 uint32_t RESERVED_FOR_ALIGNMENT_3[3];
1041
1042 /* This field must take stvewx/lvewx requirements into account */
1043 uint32_t RESERVED_FOR_ALIGNMENT_4[3];
1044 uint32_t VSCR;
1045
1046 uint8_t V0[16];
1047 uint8_t V1[16];
1048 uint8_t V2[16];
1049 uint8_t V3[16];
1050 uint8_t V4[16];
1051 uint8_t V5[16];
1052 uint8_t V6[16];
1053 uint8_t V7[16];
1054 uint8_t V8[16];
1055 uint8_t V9[16];
1056 uint8_t V10[16];
1057 uint8_t V11[16];
1058 uint8_t V12[16];
1059 uint8_t V13[16];
1060 uint8_t V14[16];
1061 uint8_t V15[16];
1062 uint8_t V16[16];
1063 uint8_t V17[16];
1064 uint8_t V18[16];
1065 uint8_t V19[16];
1066 uint8_t V20[16];
1067 uint8_t V21[16];
1068 uint8_t V22[16];
1069 uint8_t V23[16];
1070 uint8_t V24[16];
1071 uint8_t V25[16];
1072 uint8_t V26[16];
1073 uint8_t V27[16];
1074 uint8_t V28[16];
1075 uint8_t V29[16];
1076 uint8_t V30[16];
1077 uint8_t V31[16];
1078 #endif
1079 #ifdef PPC_MULTILIB_FPU
1080 double F0;
1081 double F1;
1082 double F2;
1083 double F3;
1084 double F4;
1085 double F5;
1086 double F6;
1087 double F7;
1088 double F8;
1089 double F9;
1090 double F10;
1091 double F11;
1092 double F12;
1093 double F13;
1094 double F14;
1095 double F15;
1096 double F16;
1097 double F17;
1098 double F18;
1099 double F19;
1100 double F20;
1101 double F21;
1102 double F22;
1103 double F23;
1104 double F24;
1105 double F25;
1106 double F26;
1107 double F27;
1108 double F28;
1109 double F29;
1110 double F30;
1111 double F31;
1112 uint64_t FPSCR;
1113 uint64_t RESERVED_FOR_ALIGNMENT_5;
1114 #endif
1116
1118
1119/*
1120 * _CPU_Initialize_altivec()
1121 *
1122 * Global altivec-related initialization.
1123 */
1124void
1125_CPU_Initialize_altivec(void);
1126
1127/*
1128 * _CPU_Context_switch_altivec
1129 *
1130 * This routine switches the altivec contexts passed to it.
1131 */
1132
1133void
1134_CPU_Context_switch_altivec(
1135 ppc_context *from,
1136 ppc_context *to
1137);
1138
1139/*
1140 * _CPU_Context_restore_altivec
1141 *
1142 * This routine restores the altivec context passed to it.
1143 */
1144
1145void
1146_CPU_Context_restore_altivec(
1148);
1149
1150/*
1151 * _CPU_Context_initialize_altivec
1152 *
1153 * This routine initializes the altivec context passed to it.
1154 */
1155
1156void
1157_CPU_Context_initialize_altivec(
1159);
1160
1161void _CPU_Fatal_error(
1162 uint32_t _error
1163);
1164
1166typedef uintptr_t CPU_Uint32ptr;
1167
1168#endif /* ASM */
1169
1170#ifdef __cplusplus
1171}
1172#endif
1173
1174#endif /* _RTEMS_SCORE_CPU_H */
This header file provides basic definitions used by the API and the implementation.
IBM/Motorola PowerPC Definitions.
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
#define _CPU_ISR_Set_level(_new_level)
Definition: cpu.h:378
rtems_termios_device_context * context
Definition: console-config.c:62
#define _CPU_Context_restore_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:901
#define _CPU_Context_save_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:895
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
SPARC basic context.
Definition: cpu.h:213
Thread register context.
Definition: cpu.h:173
Definition: bootldr.h:45
Definition: cpu.h:223