RTEMS 6.1-rc7
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Data Fields

FMC SDRAM Configuration Structure definition. More...

#include <stm32h7xx_ll_fmc.h>

Data Fields

uint32_t SDBank
 
uint32_t ColumnBitsNumber
 
uint32_t RowBitsNumber
 
uint32_t MemoryDataWidth
 
uint32_t InternalBankNumber
 
uint32_t CASLatency
 
uint32_t WriteProtection
 
uint32_t SDClockPeriod
 
uint32_t ReadBurst
 
uint32_t ReadPipeDelay
 

Detailed Description

FMC SDRAM Configuration Structure definition.

Field Documentation

◆ CASLatency

uint32_t FMC_SDRAM_InitTypeDef::CASLatency

Defines the SDRAM CAS latency in number of memory clock cycles. This parameter can be a value of FMC SDRAM CAS Latency.

◆ ColumnBitsNumber

uint32_t FMC_SDRAM_InitTypeDef::ColumnBitsNumber

Defines the number of bits of column address. This parameter can be a value of FMC SDRAM Column Bits number.

◆ InternalBankNumber

uint32_t FMC_SDRAM_InitTypeDef::InternalBankNumber

Defines the number of the device's internal banks. This parameter can be of FMC SDRAM Internal Banks Number.

◆ MemoryDataWidth

uint32_t FMC_SDRAM_InitTypeDef::MemoryDataWidth

Defines the memory device width. This parameter can be a value of FMC SDRAM Memory Bus Width.

◆ ReadBurst

uint32_t FMC_SDRAM_InitTypeDef::ReadBurst

This bit enable the SDRAM controller to anticipate the next read commands during the CAS latency and stores data in the Read FIFO. This parameter can be a value of FMC SDRAM Read Burst.

◆ ReadPipeDelay

uint32_t FMC_SDRAM_InitTypeDef::ReadPipeDelay

Define the delay in system clock cycles on read data path. This parameter can be a value of FMC SDRAM Read Pipe Delay.

◆ RowBitsNumber

uint32_t FMC_SDRAM_InitTypeDef::RowBitsNumber

Defines the number of bits of column address. This parameter can be a value of FMC SDRAM Row Bits number.

◆ SDBank

uint32_t FMC_SDRAM_InitTypeDef::SDBank

Specifies the SDRAM memory device that will be used. This parameter can be a value of FMC SDRAM Bank

◆ SDClockPeriod

uint32_t FMC_SDRAM_InitTypeDef::SDClockPeriod

Define the SDRAM Clock Period for both SDRAM devices and they allow to disable the clock before changing frequency. This parameter can be a value of FMC SDRAM Clock Period.

◆ WriteProtection

uint32_t FMC_SDRAM_InitTypeDef::WriteProtection

Enables the SDRAM device to be accessed in write mode. This parameter can be a value of FMC SDRAM Write Protection.


The documentation for this struct was generated from the following file: