RTEMS 6.1-rc7
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cpuimpl.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
13 * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _RTEMS_SCORE_CPUIMPL_H
38#define _RTEMS_SCORE_CPUIMPL_H
39
40#include <rtems/score/cpu.h>
41
52#define CPU_PER_CPU_CONTROL_SIZE 0
53
54#define CPU_INTERRUPT_FRAME_SIZE 0x2E0
55
56#define CPU_THREAD_LOCAL_STORAGE_VARIANT 11
57
58#ifndef ASM
59
60#ifdef __cplusplus
61extern "C" {
62#endif
63
64typedef struct {
65 uint64_t x0;
66 uint64_t register_lr_original;
67 uint64_t register_lr;
68 uint64_t x1;
69 uint64_t x2;
70 uint64_t x3;
71 uint64_t x4;
72 uint64_t x5;
73 uint64_t x6;
74 uint64_t x7;
75 uint64_t x8;
76 uint64_t x9;
77 uint64_t x10;
78 uint64_t x11;
79 uint64_t x12;
80 uint64_t x13;
81 uint64_t x14;
82 uint64_t x15;
83 uint64_t x16;
84 uint64_t x17;
85 uint64_t x18;
86 uint64_t x19;
87 uint64_t x20;
88 uint64_t x21;
89#ifdef AARCH64_MULTILIB_VFP
90 uint128_t q0;
91 uint128_t q1;
92 uint128_t q2;
93 uint128_t q3;
94 uint128_t q4;
95 uint128_t q5;
96 uint128_t q6;
97 uint128_t q7;
98 uint128_t q8;
99 uint128_t q9;
100 uint128_t q10;
101 uint128_t q11;
102 uint128_t q12;
103 uint128_t q13;
104 uint128_t q14;
105 uint128_t q15;
106 uint128_t q16;
107 uint128_t q17;
108 uint128_t q18;
109 uint128_t q19;
110 uint128_t q20;
111 uint128_t q21;
112 uint128_t q22;
113 uint128_t q23;
114 uint128_t q24;
115 uint128_t q25;
116 uint128_t q26;
117 uint128_t q27;
118 uint128_t q28;
119 uint128_t q29;
120 uint128_t q30;
121 uint128_t q31;
122#endif /* AARCH64_MULTILIB_VFP */
123 uint64_t register_elr;
124 uint64_t register_spsr;
125 uint64_t register_fpsr;
126 uint64_t register_fpcr;
128
129#ifdef RTEMS_SMP
130
131static inline
132struct Per_CPU_Control *_AARCH64_Get_current_per_CPU_control( void )
133{
134 struct Per_CPU_Control *cpu_self;
135 uint64_t value;
136
137 __asm__ volatile (
138 "mrs %0, TPIDR_EL1" : "=&r" ( value ) : : "memory"
139 );
140
141 /* Use EL1 Thread ID Register (TPIDR_EL1) */
142 cpu_self = (struct Per_CPU_Control *)(uintptr_t)value;
143
144 return cpu_self;
145}
146
147#define _CPU_Get_current_per_CPU_control() \
148 _AARCH64_Get_current_per_CPU_control()
149
161uint64_t _AArch64_Get_current_processor_for_system_start( void );
162
163#endif /* RTEMS_SMP */
164
165void _CPU_Context_volatile_clobber( uintptr_t pattern );
166
167void _CPU_Context_validate( uintptr_t pattern );
168
169static inline void _CPU_Instruction_illegal( void )
170{
171 __asm__ volatile ( ".inst 0x0" );
172}
173
174static inline void _CPU_Instruction_no_operation( void )
175{
176 __asm__ volatile ( "nop" );
177}
178
179static inline void _CPU_Use_thread_local_storage(
181)
182{
183 __asm__ volatile (
184 "msr TPIDR_EL0, %0" : : "r" ( context->thread_id ) : "memory"
185 );
186}
187
188static inline void *_CPU_Get_TLS_thread_pointer(
190)
191{
192 return (void *)(uintptr_t) context->thread_id;
193}
194
195#ifdef __cplusplus
196}
197#endif
198
199#endif /* ASM */
200
203#endif /* _RTEMS_SCORE_CPUIMPL_H */
rtems_termios_device_context * context
Definition: console-config.c:62
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
Thread register context.
Definition: cpu.h:173
Per CPU Core Structure.
Definition: percpu.h:384