RTEMS 6.1-rc7
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cpu.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
9/*
10 * This include file contains macros pertaining to the Opencores
11 * or1k processor family.
12 *
13 * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com>
14 * COPYRIGHT (c) 1989-1999.
15 * On-Line Applications Research Corporation (OAR).
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
30 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 *
38 * This file adapted from no_cpu example of the RTEMS distribution.
39 * The body has been modified for the Opencores OR1k implementation by
40 * Chris Ziomkowski. <chris@asics.ws>
41 *
42 */
43
44#ifndef _OR1K_CPU_H
45#define _OR1K_CPU_H
46
47#ifdef __cplusplus
48extern "C" {
49#endif
50
51
52#include <rtems/score/or1k.h> /* pick up machine definitions */
55
56/* conditional compilation parameters */
57
58/*
59 * Does the RTEMS invoke the user's ISR with the vector number and
60 * a pointer to the saved interrupt frame (1) or just the vector
61 * number (0)?
62 *
63 */
64
65#define CPU_ISR_PASSES_FRAME_POINTER TRUE
66
67#define CPU_HARDWARE_FP FALSE
68
69#define CPU_SOFTWARE_FP FALSE
70
71#define CPU_ALL_TASKS_ARE_FP FALSE
72
73#define CPU_IDLE_TASK_IS_FP FALSE
74
75#define CPU_USE_DEFERRED_FP_SWITCH TRUE
76
77#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
78
79/*
80 * Does the stack grow up (toward higher addresses) or down
81 * (toward lower addresses)?
82 *
83 * If TRUE, then the grows upward.
84 * If FALSE, then the grows toward smaller addresses.
85 *
86 */
87
88#define CPU_STACK_GROWS_UP FALSE
89
90/* FIXME: Is this the right value? */
91#define CPU_CACHE_LINE_BYTES 32
92
93#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
94
95/*
96 * The following defines the number of bits actually used in the
97 * interrupt field of the task mode. How those bits map to the
98 * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
99 *
100 */
101
102#define CPU_MODES_INTERRUPT_MASK 0x00000001
103
104/*
105 * Processor defined structures required for cpukit/score.
106 */
107
108
109/*
110 * Contexts
111 *
112 * Generally there are 2 types of context to save.
113 * 1. Interrupt registers to save
114 * 2. Task level registers to save
115 *
116 * This means we have the following 3 context items:
117 * 1. task level context stuff:: Context_Control
118 * 2. floating point task stuff:: Context_Control_fp
119 * 3. special interrupt level context :: Context_Control_interrupt
120 *
121 * On some processors, it is cost-effective to save only the callee
122 * preserved registers during a task context switch. This means
123 * that the ISR code needs to save those registers which do not
124 * persist across function calls. It is not mandatory to make this
125 * distinctions between the caller/callee saves registers for the
126 * purpose of minimizing context saved during task switch and on interrupts.
127 * If the cost of saving extra registers is minimal, simplicity is the
128 * choice. Save the same context on interrupt entry as for tasks in
129 * this case.
130 *
131 * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
132 * care should be used in designing the context area.
133 *
134 * On some CPUs with hardware floating point support, the Context_Control_fp
135 * structure will not be used or it simply consist of an array of a
136 * fixed number of bytes. This is done when the floating point context
137 * is dumped by a "FP save context" type instruction and the format
138 * is not really defined by the CPU. In this case, there is no need
139 * to figure out the exact format -- only the size. Of course, although
140 * this is enough information for RTEMS, it is probably not enough for
141 * a debugger such as gdb. But that is another problem.
142 *
143 *
144 */
145#ifndef ASM
146#ifdef OR1K_64BIT_ARCH
147#define or1kreg uint64_t
148#else
149#define or1kreg uint32_t
150#endif
151
152typedef struct {
153 uint32_t r1; /* Stack pointer */
154 uint32_t r2; /* Frame pointer */
155 uint32_t r3;
156 uint32_t r4;
157 uint32_t r5;
158 uint32_t r6;
159 uint32_t r7;
160 uint32_t r8;
161 uint32_t r9;
162 uint32_t r10;
163 uint32_t r11;
164 uint32_t r12;
165 uint32_t r13;
166 uint32_t r14;
167 uint32_t r15;
168 uint32_t r16;
169 uint32_t r17;
170 uint32_t r18;
171 uint32_t r19;
172 uint32_t r20;
173 uint32_t r21;
174 uint32_t r22;
175 uint32_t r23;
176 uint32_t r24;
177 uint32_t r25;
178 uint32_t r26;
179 uint32_t r27;
180 uint32_t r28;
181 uint32_t r29;
182 uint32_t r30;
183 uint32_t r31;
184
185 uint32_t sr; /* Current supervision register non persistent values */
186 uint32_t epcr;
187 uint32_t eear;
188 uint32_t esr;
190
191#define _CPU_Context_Get_SP( _context ) \
192 (_context)->r1
193
195
196/*
197 * Amount of extra stack (above minimum stack size) required by
198 * MPCI receive server thread. Remember that in a multiprocessor
199 * system this thread must exist and be able to process all directives.
200 *
201 */
202
203#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
204
205/*
206 * Should be large enough to run all RTEMS tests. This insures
207 * that a "reasonable" small application should not have any problems.
208 *
209 */
210
211#define CPU_STACK_MINIMUM_SIZE 4096
212
213/*
214 * CPU's worst alignment requirement for data types on a byte boundary. This
215 * alignment does not take into account the requirements for the stack.
216 *
217 */
218
219#define CPU_ALIGNMENT 8
220
221/*
222 * This is defined if the port has a special way to report the ISR nesting
223 * level. Most ports maintain the variable _ISR_Nest_level.
224 */
225#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
226
234#define CPU_SIZEOF_POINTER 4
235
236/*
237 * This number corresponds to the byte alignment requirement for the
238 * heap handler. This alignment requirement may be stricter than that
239 * for the data types alignment specified by CPU_ALIGNMENT. It is
240 * common for the heap to follow the same alignment requirement as
241 * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap,
242 * then this should be set to CPU_ALIGNMENT.
243 *
244 * NOTE: This does not have to be a power of 2 although it should be
245 * a multiple of 2 greater than or equal to 2. The requirement
246 * to be a multiple of 2 is because the heap uses the least
247 * significant field of the front and back flags to indicate
248 * that a block is in use or free. So you do not want any odd
249 * length blocks really putting length data in that bit.
250 *
251 * On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will
252 * have to be greater or equal to than CPU_ALIGNMENT to ensure that
253 * elements allocated from the heap meet all restrictions.
254 *
255 */
256
257#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
258
259#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
260
261#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
262
263/* ISR handler macros */
264
265/*
266 * Disable all interrupts for an RTEMS critical section. The previous
267 * level is returned in _level.
268 *
269 */
270
271static inline uint32_t or1k_interrupt_disable( void )
272{
273 uint32_t sr;
274 sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
275
276 _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_IEE));
277
278 return sr;
279}
280
281static inline void or1k_interrupt_enable(uint32_t level)
282{
283 uint32_t sr;
284
285 /* Enable interrupts and restore rs */
286 sr = level | CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE;
287 _OR1K_mtspr(CPU_OR1K_SPR_SR, sr);
288
289}
290
291#define _CPU_ISR_Disable( _level ) \
292 _level = or1k_interrupt_disable()
293
294
295/*
296 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
297 * This indicates the end of an RTEMS critical section. The parameter
298 * _level is not modified.
299 *
300 */
301
302#define _CPU_ISR_Enable( _level ) \
303 or1k_interrupt_enable( _level )
304
305/*
306 * This temporarily restores the interrupt to _level before immediately
307 * disabling them again. This is used to divide long RTEMS critical
308 * sections into two or more parts. The parameter _level is not
309 * modified.
310 *
311 */
312
313#define _CPU_ISR_Flash( _level ) \
314 do{ \
315 _CPU_ISR_Enable( _level ); \
316 _OR1K_mtspr(CPU_OR1K_SPR_SR, (_level & ~CPU_OR1K_SPR_SR_IEE)); \
317 } while(0)
318
319static inline bool _CPU_ISR_Is_enabled( uint32_t level )
320{
321 return ( level & CPU_OR1K_SPR_SR ) != 0;
322}
323
324/*
325 * Map interrupt level in task mode onto the hardware that the CPU
326 * actually provides. Currently, interrupt levels which do not
327 * map onto the CPU in a generic fashion are undefined. Someday,
328 * it would be nice if these were "mapped" by the application
329 * via a callout. For example, m68k has 8 levels 0 - 7, levels
330 * 8 - 255 would be available for bsp/application specific meaning.
331 * This could be used to manage a programmable interrupt controller
332 * via the rtems_task_mode directive.
333 *
334 * The get routine usually must be implemented as a subroutine.
335 *
336 */
337
338void _CPU_ISR_Set_level( uint32_t level );
339
340uint32_t _CPU_ISR_Get_level( void );
341
342/* end of ISR handler macros */
343
344/* Context handler macros */
345
346#define OR1K_FAST_CONTEXT_SWITCH_ENABLED FALSE
347/*
348 * Initialize the context to a state suitable for starting a
349 * task after a context restore operation. Generally, this
350 * involves:
351 *
352 * - setting a starting address
353 * - preparing the stack
354 * - preparing the stack and frame pointers
355 * - setting the proper interrupt level in the context
356 * - initializing the floating point context
357 *
358 * This routine generally does not set any unnecessary register
359 * in the context. The state of the "general data" registers is
360 * undefined at task start time.
361 *
362 * NOTE: This is_fp parameter is TRUE if the thread is to be a floating
363 * point thread. This is typically only used on CPUs where the
364 * FPU may be easily disabled by software such as on the SPARC
365 * where the PSR contains an enable FPU bit.
366 *
367 */
368
386void _CPU_Context_Initialize(
388 void *stack_area_begin,
389 size_t stack_area_size,
390 uint32_t new_level,
391 void (*entry_point)( void ),
392 bool is_fp,
393 void *tls_area
394);
395
396/*
397 * This routine is responsible for somehow restarting the currently
398 * executing task. If you are lucky, then all that is necessary
399 * is restoring the context. Otherwise, there will need to be
400 * a special assembly routine which does something special in this
401 * case. Context_Restore should work most of the time. It will
402 * not work if restarting self conflicts with the stack frame
403 * assumptions of restoring a context.
404 *
405 */
406
407#define _CPU_Context_Restart_self( _the_context ) \
408 _CPU_Context_restore( (_the_context) );
409
410/* end of Context handler macros */
411
412#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
413
414#define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE
415
416#endif /* ASM */
417
418#define CPU_SIZEOF_POINTER 4
419
420#define CPU_MAXIMUM_PROCESSORS 32
421
422#ifndef ASM
423typedef struct {
424 uint32_t r[32];
425
426 /* The following registers must be saved if we have
427 fast context switch disabled and nested interrupt
428 levels are enabled.
429 */
430#if !OR1K_FAST_CONTEXT_SWITCH_ENABLED
431 uint32_t epcr; /* exception PC register */
432 uint32_t eear; /* exception effective address register */
433 uint32_t esr; /* exception supervision register */
434#endif
435
437
444
445
446/* end of Priority handler macros */
447
448/* functions */
449
450/*
451 * _CPU_Initialize
452 *
453 * This routine performs CPU dependent initialization.
454 *
455 */
456
457void _CPU_Initialize(
458 void
459);
460
461typedef void ( *CPU_ISR_raw_handler )( uint32_t, CPU_Exception_frame * );
462
464 uint32_t vector,
465 CPU_ISR_raw_handler new_handler,
466 CPU_ISR_raw_handler *old_handler
467);
468
469typedef void ( *CPU_ISR_handler )( uint32_t );
470
471static inline void _CPU_ISR_install_vector(
472 uint32_t vector,
473 CPU_ISR_handler new_handler,
474 CPU_ISR_handler *old_handler
475)
476{
478 vector,
479 (CPU_ISR_raw_handler) new_handler,
480 (CPU_ISR_raw_handler *) old_handler
481 );
482}
483
484RTEMS_NO_RETURN void *_CPU_Thread_Idle_body( uintptr_t ignored );
485
486/*
487 * _CPU_Context_switch
488 *
489 * This routine switches from the run context to the heir context.
490 *
491 * Or1k Specific Information:
492 *
493 * Please see the comments in the .c file for a description of how
494 * this function works. There are several things to be aware of.
495 */
496
498 Context_Control *run,
499 Context_Control *heir
500);
501
502/*
503 * _CPU_Context_restore
504 *
505 * This routine is generally used only to restart self in an
506 * efficient manner. It may simply be a label in _CPU_Context_switch.
507 *
508 * NOTE: May be unnecessary to reload some registers.
509 *
510 */
511
512RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context );
513
514/*
515 * _CPU_Context_save_fp
516 *
517 * This routine saves the floating point context passed to it.
518 *
519 */
520
522 void **fp_context_ptr
523);
524
525/*
526 * _CPU_Context_restore_fp
527 *
528 * This routine restores the floating point context passed to it.
529 *
530 */
531
533 void **fp_context_ptr
534);
535
536/* The following routine swaps the endian format of an unsigned int.
537 * It must be static because it is referenced indirectly.
538 *
539 * This version will work on any processor, but if there is a better
540 * way for your CPU PLEASE use it. The most common way to do this is to:
541 *
542 * swap least significant two bytes with 16-bit rotate
543 * swap upper and lower 16-bits
544 * swap most significant two bytes with 16-bit rotate
545 *
546 * Some CPUs have special instructions which swap a 32-bit quantity in
547 * a single instruction (e.g. i486). It is probably best to avoid
548 * an "endian swapping control bit" in the CPU. One good reason is
549 * that interrupts would probably have to be disabled to insure that
550 * an interrupt does not try to access the same "chunk" with the wrong
551 * endian. Another good reason is that on some CPUs, the endian bit
552 * endianness for ALL fetches -- both code and data -- so the code
553 * will be fetched incorrectly.
554 *
555 */
556
557static inline unsigned int CPU_swap_u32(
558 unsigned int value
559)
560{
561 uint32_t byte1, byte2, byte3, byte4, swapped;
562
563 byte4 = (value >> 24) & 0xff;
564 byte3 = (value >> 16) & 0xff;
565 byte2 = (value >> 8) & 0xff;
566 byte1 = value & 0xff;
567
568 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
569 return( swapped );
570}
571
572#define CPU_swap_u16( value ) \
573 (((value&0xff) << 8) | ((value >> 8)&0xff))
574
575typedef uint32_t CPU_Counter_ticks;
576
577uint32_t _CPU_Counter_frequency( void );
578
579CPU_Counter_ticks _CPU_Counter_read( void );
580
582typedef uintptr_t CPU_Uint32ptr;
583
584#endif /* ASM */
585
586#ifdef __cplusplus
587}
588#endif
589
590#endif
This header file provides basic definitions used by the API and the implementation.
void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.c:100
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
#define _CPU_ISR_Set_level(_new_level)
Definition: cpu.h:378
OR1K utility.
rtems_termios_device_context * context
Definition: console-config.c:62
#define _CPU_Context_restore_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:901
#define _CPU_Context_save_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:895
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
Thread register context.
Definition: cpu.h:173