RTEMS 6.1-rc7
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Data Fields

High resolution Timer (HRTIM) More...

#include <stm32h742xx.h>

Data Fields

__IO uint32_t MCR
 
__IO uint32_t MISR
 
__IO uint32_t MICR
 
__IO uint32_t MDIER
 
__IO uint32_t MCNTR
 
__IO uint32_t MPER
 
__IO uint32_t MREP
 
__IO uint32_t MCMP1R
 
uint32_t RESERVED0
 
__IO uint32_t MCMP2R
 
__IO uint32_t MCMP3R
 
__IO uint32_t MCMP4R
 
uint32_t RESERVED1 [20]
 

Detailed Description

High resolution Timer (HRTIM)

Field Documentation

◆ MCMP1R

__IO uint32_t HRTIM_Master_TypeDef::MCMP1R

HRTIM Master Timer compare 1 register, Address offset: 0x1C

◆ MCMP2R

__IO uint32_t HRTIM_Master_TypeDef::MCMP2R

HRTIM Master Timer compare 2 register, Address offset: 0x24

◆ MCMP3R

__IO uint32_t HRTIM_Master_TypeDef::MCMP3R

HRTIM Master Timer compare 3 register, Address offset: 0x28

◆ MCMP4R

__IO uint32_t HRTIM_Master_TypeDef::MCMP4R

HRTIM Master Timer compare 4 register, Address offset: 0x2C

◆ MCNTR

__IO uint32_t HRTIM_Master_TypeDef::MCNTR

HRTIM Master Timer counter register, Address offset: 0x10

◆ MCR

__IO uint32_t HRTIM_Master_TypeDef::MCR

HRTIM Master Timer control register, Address offset: 0x00

◆ MDIER

__IO uint32_t HRTIM_Master_TypeDef::MDIER

HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C

◆ MICR

__IO uint32_t HRTIM_Master_TypeDef::MICR

HRTIM Master Timer interrupt clear register, Address offset: 0x08

◆ MISR

__IO uint32_t HRTIM_Master_TypeDef::MISR

HRTIM Master Timer interrupt status register, Address offset: 0x04

◆ MPER

__IO uint32_t HRTIM_Master_TypeDef::MPER

HRTIM Master Timer period register, Address offset: 0x14

◆ MREP

__IO uint32_t HRTIM_Master_TypeDef::MREP

HRTIM Master Timer repetition register, Address offset: 0x18

◆ RESERVED0

uint32_t HRTIM_Master_TypeDef::RESERVED0

Reserved, 0x20

◆ RESERVED1

uint32_t HRTIM_Master_TypeDef::RESERVED1

Reserved, 0x30..0x7C


The documentation for this struct was generated from the following files: