32#ifndef _RTEMS_SCORE_CPUIMPL_H
33#define _RTEMS_SCORE_CPUIMPL_H
35#include <rtems/score/cpu.h>
47#if defined(__riscv_atomic) && __riscv_xlen == 64
48#define CPU_PER_CPU_CONTROL_SIZE 48
49#elif defined(__riscv_atomic) && __riscv_xlen == 32
50#define CPU_PER_CPU_CONTROL_SIZE 32
51#elif __riscv_xlen == 64
52#define CPU_PER_CPU_CONTROL_SIZE 32
53#elif __riscv_xlen == 32
54#define CPU_PER_CPU_CONTROL_SIZE 16
57#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
60#define RISCV_CONTEXT_IS_EXECUTING 0
63#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 4
67#define RISCV_CONTEXT_RA 8
68#define RISCV_CONTEXT_SP 12
69#define RISCV_CONTEXT_TP 16
70#define RISCV_CONTEXT_S0 20
71#define RISCV_CONTEXT_S1 24
72#define RISCV_CONTEXT_S2 28
73#define RISCV_CONTEXT_S3 32
74#define RISCV_CONTEXT_S4 36
75#define RISCV_CONTEXT_S5 40
76#define RISCV_CONTEXT_S6 44
77#define RISCV_CONTEXT_S7 48
78#define RISCV_CONTEXT_S8 52
79#define RISCV_CONTEXT_S9 56
80#define RISCV_CONTEXT_S10 60
81#define RISCV_CONTEXT_S11 64
83#define RISCV_INTERRUPT_FRAME_MSTATUS 0
84#define RISCV_INTERRUPT_FRAME_MEPC 4
85#define RISCV_INTERRUPT_FRAME_A2 8
86#define RISCV_INTERRUPT_FRAME_S0 12
87#define RISCV_INTERRUPT_FRAME_S1 16
88#define RISCV_INTERRUPT_FRAME_RA 20
89#define RISCV_INTERRUPT_FRAME_A3 24
90#define RISCV_INTERRUPT_FRAME_A4 28
91#define RISCV_INTERRUPT_FRAME_A5 32
92#define RISCV_INTERRUPT_FRAME_A6 36
93#define RISCV_INTERRUPT_FRAME_A7 40
94#define RISCV_INTERRUPT_FRAME_T0 44
95#define RISCV_INTERRUPT_FRAME_T1 48
96#define RISCV_INTERRUPT_FRAME_T2 52
97#define RISCV_INTERRUPT_FRAME_T3 56
98#define RISCV_INTERRUPT_FRAME_T4 60
99#define RISCV_INTERRUPT_FRAME_T5 64
100#define RISCV_INTERRUPT_FRAME_T6 68
104#define RISCV_INTERRUPT_FRAME_A0 72
105#define RISCV_INTERRUPT_FRAME_A1 76
107#define CPU_INTERRUPT_FRAME_SIZE 80
109#elif __riscv_flen == 32
111#define RISCV_CONTEXT_FCSR 68
113#define RISCV_CONTEXT_F( x ) ( 72 + 4 * x )
115#define RISCV_INTERRUPT_FRAME_FCSR 72
117#define RISCV_INTERRUPT_FRAME_F( x ) ( 76 + 4 * x )
119#define RISCV_INTERRUPT_FRAME_A0 156
120#define RISCV_INTERRUPT_FRAME_A1 160
122#define CPU_INTERRUPT_FRAME_SIZE 176
124#elif __riscv_flen == 64
126#define RISCV_CONTEXT_FCSR 68
128#define RISCV_CONTEXT_F( x ) ( 72 + 8 * x )
130#define RISCV_INTERRUPT_FRAME_FCSR 72
132#define RISCV_INTERRUPT_FRAME_F( x ) ( 80 + 8 * x )
134#define RISCV_INTERRUPT_FRAME_A0 240
135#define RISCV_INTERRUPT_FRAME_A1 244
137#define CPU_INTERRUPT_FRAME_SIZE 256
141#define RISCV_EXCEPTION_FRAME_X( x ) ( CPU_INTERRUPT_FRAME_SIZE + 4 * x )
143#elif __riscv_xlen == 64
145#define RISCV_CONTEXT_RA 8
146#define RISCV_CONTEXT_SP 16
147#define RISCV_CONTEXT_TP 24
148#define RISCV_CONTEXT_S0 32
149#define RISCV_CONTEXT_S1 40
150#define RISCV_CONTEXT_S2 48
151#define RISCV_CONTEXT_S3 56
152#define RISCV_CONTEXT_S4 64
153#define RISCV_CONTEXT_S5 72
154#define RISCV_CONTEXT_S6 80
155#define RISCV_CONTEXT_S7 88
156#define RISCV_CONTEXT_S8 96
157#define RISCV_CONTEXT_S9 104
158#define RISCV_CONTEXT_S10 112
159#define RISCV_CONTEXT_S11 120
161#define RISCV_INTERRUPT_FRAME_MSTATUS 0
162#define RISCV_INTERRUPT_FRAME_MEPC 8
163#define RISCV_INTERRUPT_FRAME_A2 16
164#define RISCV_INTERRUPT_FRAME_S0 24
165#define RISCV_INTERRUPT_FRAME_S1 32
166#define RISCV_INTERRUPT_FRAME_RA 40
167#define RISCV_INTERRUPT_FRAME_A3 48
168#define RISCV_INTERRUPT_FRAME_A4 56
169#define RISCV_INTERRUPT_FRAME_A5 64
170#define RISCV_INTERRUPT_FRAME_A6 72
171#define RISCV_INTERRUPT_FRAME_A7 80
172#define RISCV_INTERRUPT_FRAME_T0 88
173#define RISCV_INTERRUPT_FRAME_T1 96
174#define RISCV_INTERRUPT_FRAME_T2 104
175#define RISCV_INTERRUPT_FRAME_T3 112
176#define RISCV_INTERRUPT_FRAME_T4 120
177#define RISCV_INTERRUPT_FRAME_T5 128
178#define RISCV_INTERRUPT_FRAME_T6 136
182#define RISCV_INTERRUPT_FRAME_A0 144
183#define RISCV_INTERRUPT_FRAME_A1 152
185#define CPU_INTERRUPT_FRAME_SIZE 160
187#elif __riscv_flen == 32
189#define RISCV_CONTEXT_FCSR 128
191#define RISCV_CONTEXT_F( x ) ( 132 + 4 * x )
193#define RISCV_INTERRUPT_FRAME_FCSR 144
195#define RISCV_INTERRUPT_FRAME_F( x ) ( 148 + 4 * x )
197#define RISCV_INTERRUPT_FRAME_A0 232
198#define RISCV_INTERRUPT_FRAME_A1 240
200#define CPU_INTERRUPT_FRAME_SIZE 256
202#elif __riscv_flen == 64
204#define RISCV_CONTEXT_FCSR 128
206#define RISCV_CONTEXT_F( x ) ( 136 + 8 * x )
208#define RISCV_INTERRUPT_FRAME_FCSR 144
210#define RISCV_INTERRUPT_FRAME_F( x ) ( 152 + 8 * x )
212#define RISCV_INTERRUPT_FRAME_A0 312
213#define RISCV_INTERRUPT_FRAME_A1 320
215#define CPU_INTERRUPT_FRAME_SIZE 336
219#define RISCV_EXCEPTION_FRAME_X( x ) ( CPU_INTERRUPT_FRAME_SIZE + 8 * x )
223#define RISCV_EXCEPTION_FRAME_MCAUSE RISCV_EXCEPTION_FRAME_X( 0 )
224#define RISCV_EXCEPTION_FRAME_SP RISCV_EXCEPTION_FRAME_X( 1 )
225#define RISCV_EXCEPTION_FRAME_GP RISCV_EXCEPTION_FRAME_X( 2 )
226#define RISCV_EXCEPTION_FRAME_TP RISCV_EXCEPTION_FRAME_X( 3 )
227#define RISCV_EXCEPTION_FRAME_S2 RISCV_EXCEPTION_FRAME_X( 4 )
228#define RISCV_EXCEPTION_FRAME_S3 RISCV_EXCEPTION_FRAME_X( 5 )
229#define RISCV_EXCEPTION_FRAME_S4 RISCV_EXCEPTION_FRAME_X( 6 )
230#define RISCV_EXCEPTION_FRAME_S5 RISCV_EXCEPTION_FRAME_X( 7 )
231#define RISCV_EXCEPTION_FRAME_S6 RISCV_EXCEPTION_FRAME_X( 8 )
232#define RISCV_EXCEPTION_FRAME_S7 RISCV_EXCEPTION_FRAME_X( 9 )
233#define RISCV_EXCEPTION_FRAME_S8 RISCV_EXCEPTION_FRAME_X( 10 )
234#define RISCV_EXCEPTION_FRAME_S9 RISCV_EXCEPTION_FRAME_X( 11 )
235#define RISCV_EXCEPTION_FRAME_S10 RISCV_EXCEPTION_FRAME_X( 12 )
236#define RISCV_EXCEPTION_FRAME_S11 RISCV_EXCEPTION_FRAME_X( 13 )
240#define RISCV_CONTEXT_FS0 RISCV_CONTEXT_F( 0 )
241#define RISCV_CONTEXT_FS1 RISCV_CONTEXT_F( 1 )
242#define RISCV_CONTEXT_FS2 RISCV_CONTEXT_F( 2 )
243#define RISCV_CONTEXT_FS3 RISCV_CONTEXT_F( 3 )
244#define RISCV_CONTEXT_FS4 RISCV_CONTEXT_F( 4 )
245#define RISCV_CONTEXT_FS5 RISCV_CONTEXT_F( 5 )
246#define RISCV_CONTEXT_FS6 RISCV_CONTEXT_F( 6 )
247#define RISCV_CONTEXT_FS7 RISCV_CONTEXT_F( 7 )
248#define RISCV_CONTEXT_FS8 RISCV_CONTEXT_F( 8 )
249#define RISCV_CONTEXT_FS9 RISCV_CONTEXT_F( 9 )
250#define RISCV_CONTEXT_FS10 RISCV_CONTEXT_F( 10 )
251#define RISCV_CONTEXT_FS11 RISCV_CONTEXT_F( 11 )
253#define RISCV_INTERRUPT_FRAME_FT0 RISCV_INTERRUPT_FRAME_F( 0 )
254#define RISCV_INTERRUPT_FRAME_FT1 RISCV_INTERRUPT_FRAME_F( 1 )
255#define RISCV_INTERRUPT_FRAME_FT2 RISCV_INTERRUPT_FRAME_F( 2 )
256#define RISCV_INTERRUPT_FRAME_FT3 RISCV_INTERRUPT_FRAME_F( 3 )
257#define RISCV_INTERRUPT_FRAME_FT4 RISCV_INTERRUPT_FRAME_F( 4 )
258#define RISCV_INTERRUPT_FRAME_FT5 RISCV_INTERRUPT_FRAME_F( 5 )
259#define RISCV_INTERRUPT_FRAME_FT6 RISCV_INTERRUPT_FRAME_F( 6 )
260#define RISCV_INTERRUPT_FRAME_FT7 RISCV_INTERRUPT_FRAME_F( 7 )
261#define RISCV_INTERRUPT_FRAME_FT8 RISCV_INTERRUPT_FRAME_F( 8 )
262#define RISCV_INTERRUPT_FRAME_FT9 RISCV_INTERRUPT_FRAME_F( 9 )
263#define RISCV_INTERRUPT_FRAME_FT10 RISCV_INTERRUPT_FRAME_F( 10 )
264#define RISCV_INTERRUPT_FRAME_FT11 RISCV_INTERRUPT_FRAME_F( 11 )
265#define RISCV_INTERRUPT_FRAME_FA0 RISCV_INTERRUPT_FRAME_F( 12 )
266#define RISCV_INTERRUPT_FRAME_FA1 RISCV_INTERRUPT_FRAME_F( 13 )
267#define RISCV_INTERRUPT_FRAME_FA2 RISCV_INTERRUPT_FRAME_F( 14 )
268#define RISCV_INTERRUPT_FRAME_FA3 RISCV_INTERRUPT_FRAME_F( 15 )
269#define RISCV_INTERRUPT_FRAME_FA4 RISCV_INTERRUPT_FRAME_F( 16 )
270#define RISCV_INTERRUPT_FRAME_FA5 RISCV_INTERRUPT_FRAME_F( 17 )
271#define RISCV_INTERRUPT_FRAME_FA6 RISCV_INTERRUPT_FRAME_F( 18 )
272#define RISCV_INTERRUPT_FRAME_FA7 RISCV_INTERRUPT_FRAME_F( 19 )
274#if __riscv_flen == 32
275#define RISCV_EXCEPTION_FRAME_F( x ) ( RISCV_EXCEPTION_FRAME_X( 14 ) + 4 * x )
276#elif __riscv_flen == 64
277#define RISCV_EXCEPTION_FRAME_F( x ) ( RISCV_EXCEPTION_FRAME_X( 14 ) + 8 * x )
280#define RISCV_EXCEPTION_FRAME_FS0 RISCV_EXCEPTION_FRAME_F( 0 )
281#define RISCV_EXCEPTION_FRAME_FS1 RISCV_EXCEPTION_FRAME_F( 1 )
282#define RISCV_EXCEPTION_FRAME_FS2 RISCV_EXCEPTION_FRAME_F( 2 )
283#define RISCV_EXCEPTION_FRAME_FS3 RISCV_EXCEPTION_FRAME_F( 3 )
284#define RISCV_EXCEPTION_FRAME_FS4 RISCV_EXCEPTION_FRAME_F( 4 )
285#define RISCV_EXCEPTION_FRAME_FS5 RISCV_EXCEPTION_FRAME_F( 5 )
286#define RISCV_EXCEPTION_FRAME_FS6 RISCV_EXCEPTION_FRAME_F( 6 )
287#define RISCV_EXCEPTION_FRAME_FS7 RISCV_EXCEPTION_FRAME_F( 7 )
288#define RISCV_EXCEPTION_FRAME_FS8 RISCV_EXCEPTION_FRAME_F( 8 )
289#define RISCV_EXCEPTION_FRAME_FS9 RISCV_EXCEPTION_FRAME_F( 9 )
290#define RISCV_EXCEPTION_FRAME_FS10 RISCV_EXCEPTION_FRAME_F( 10 )
291#define RISCV_EXCEPTION_FRAME_FS11 RISCV_EXCEPTION_FRAME_F( 11 )
301static inline uint32_t _RISCV_Map_hardid_to_cpu_index( uint32_t hardid )
303 return hardid - RISCV_BOOT_HARTID;
306static inline uint32_t _RISCV_Map_cpu_index_to_hardid( uint32_t cpu_index )
308 return cpu_index + RISCV_BOOT_HARTID;
321 uint32_t reserved_8000[4094];
323 uint32_t reserved_c000[4096];
328#define RISCV_PLIC_MAX_INTERRUPTS 1024
331 uint32_t priority_threshold;
332 uint32_t claim_complete;
333 uint32_t reserved_8[1022];
337 uint32_t priority[RISCV_PLIC_MAX_INTERRUPTS];
338 uint32_t pending[1024];
339 uint32_t enable[16320][32];
345 uint64_t clear_reservations;
346 uint32_t reserved_for_alignment_of_interrupt_frame[ 2 ];
349 volatile uint32_t *plic_m_ie;
351 volatile uint32_t *clint_msip;
356void _RISCV_Interrupt_dispatch(
361static inline uint32_t _RISCV_Read_FCSR(
void )
365 __asm__
volatile (
"frcsr %0" :
"=&r" ( fcsr ) );
400extern volatile uint32_t *_RISCV_Counter_mutable;
406extern volatile uint32_t _RISCV_Counter_register;
410static inline struct Per_CPU_Control *_RISCV_Get_current_per_CPU_control(
void )
416 ".option arch, +zicsr\n"
417 "csrr %0, mscratch\n"
425#define _CPU_Get_current_per_CPU_control() _RISCV_Get_current_per_CPU_control()
429void _CPU_Context_volatile_clobber( uintptr_t pattern );
431void _CPU_Context_validate( uintptr_t pattern );
433static inline void _CPU_Instruction_illegal(
void )
435 __asm__
volatile (
"unimp" );
438static inline void _CPU_Instruction_no_operation(
void )
440 __asm__
volatile (
"nop" );
443static inline void _CPU_Use_thread_local_storage(
447 register uintptr_t tp __asm__(
"tp" );
452 __asm__
volatile (
"" : :
"r" ( tp ) );
455static inline void *_CPU_Get_TLS_thread_pointer(
rtems_termios_device_context * context
Definition: console-config.c:62
The CPU specific per-CPU control.
Definition: cpuimpl.h:91
Thread register context.
Definition: cpu.h:173
Per CPU Core Structure.
Definition: percpu.h:384
Definition: cpuimpl.h:318
Definition: cpuimpl.h:330
Definition: cpuimpl.h:336
Definition: cpuimpl.h:313