RTEMS 6.1-rc7
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sc16is752.h
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/*
4 * Copyright (c) 2016 embedded brains GmbH & Co. KG
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#ifndef _DEV_SERIAL_SC16IS752_H
29#define _DEV_SERIAL_SC16IS752_H
30
31#include <sys/ioccom.h>
32
33#include <rtems/termiostypes.h>
34
35#ifdef __cplusplus
36extern "C" {
37#endif /* __cplusplus */
38
45typedef enum {
46 SC16IS752_MODE_RS232,
47
48 /* Enable RS485 mode */
49 SC16IS752_MODE_RS485,
50
51 /* Enable RS485 mode, enable the transmitter to control the #RTS pin */
52 SC16IS752_MODE_RS485_RTS,
53
54 /*
55 * Enable RS485 mode, enable the transmitter to control the #RTS pin, invert
56 * RTS signal (#RTS = 1 during transmission and #RTS = 0 during reception)
57 */
58 SC16IS752_MODE_RS485_RTS_INV
59} sc16is752_mode;
60
62
68
74 int (*write_reg)(
76 uint8_t addr,
77 const uint8_t *data,
78 size_t len
79 );
80
86 int (*read_reg)(
88 uint8_t addr,
89 uint8_t *data,
90 size_t len
91 );
92
98 int (*read_2_reg)(
100 uint8_t addr_0,
101 uint8_t addr_1,
102 uint8_t data[2]
103 );
104
111
118
125
132
138 sc16is752_mode mode;
139
147
154
160 uint8_t ier;
161
168
175
181 uint8_t lcr;
182
188 uint8_t efcr;
189};
190
194typedef struct {
196
202 int fd;
203
209 uint8_t cs;
210
216 uint32_t speed_hz;
217
223 const char *spi_path;
225
229typedef struct {
231
237 int fd;
238
244 const char *bus_path;
246
247extern const rtems_termios_device_handler sc16is752_termios_handler;
248
254void sc16is752_interrupt_handler(void *arg);
255
265rtems_status_code sc16is752_spi_create(
267 const char *device_path
268);
269
275#define SC16IS752_SET_SLEEP_MODE _IOW('d', 0, int)
276
283#define SC16IS752_SET_IOCONTROL _IOW('d', 1, uint8_t)
284
288#define SC16IS752_SET_IODIR _IOW('d', 2, uint8_t)
289
293#define SC16IS752_SET_IOSTATE _IOW('d', 3, uint8_t)
294
298#define SC16IS752_SET_EFCR _IOW('d', 4, uint8_t)
299
303#define SC16IS752_GET_SLEEP_MODE _IOR('d', 0, int)
304
308#define SC16IS752_GET_IOCONTROL _IOR('d', 1, uint8_t)
309
313#define SC16IS752_GET_IODIR _IOR('d', 2, uint8_t)
314
318#define SC16IS752_GET_IOSTATE _IOR('d', 3, uint8_t)
319
323#define SC16IS752_GET_EFCR _IOR('d', 4, uint8_t)
324
329#define SC16IS752_IOCONTROL_SRESET (1u << 3)
330#define SC16IS752_IOCONTROL_GPIO_3_0_OR_MODEM (1u << 2)
331#define SC16IS752_IOCONTROL_GPIO_7_4_OR_MODEM (1u << 1)
332#define SC16IS752_IOCONTROL_IOLATCH (1u << 0)
337#ifdef __cplusplus
338}
339#endif /* __cplusplus */
340
341#endif /* _DEV_SERIAL_SC16IS752_H */
rtems_status_code
This enumeration provides status codes for directives of the Classic API.
Definition: status.h:85
Termios device context.
Definition: termiosdevice.h:68
Termios device handler.
Definition: termiosdevice.h:100
Definition: termiostypes.h:94
SC16IS752 device context.
Definition: sc16is752.h:66
uint8_t ier
Shadow Interrupt Enable Register (IER).
Definition: sc16is752.h:160
uint32_t input_frequency
Input frequency in Hertz (dependent on crystal, see XTAL1 and XTAL2 pins).
Definition: sc16is752.h:146
rtems_termios_tty * tty
Corresponding Termios structure.
Definition: sc16is752.h:153
uint8_t tx_fifo_free
Count of free characters in the transmit FIFO.
Definition: sc16is752.h:174
void(* last_close)(sc16is752_context *ctx)
Last close.
Definition: sc16is752.h:117
int(* write_reg)(sc16is752_context *ctx, uint8_t addr, const uint8_t *data, size_t len)
Writes a register.
Definition: sc16is752.h:74
int(* read_2_reg)(sc16is752_context *ctx, uint8_t addr_0, uint8_t addr_1, uint8_t data[2])
Reads two registers.
Definition: sc16is752.h:98
int(* read_reg)(sc16is752_context *ctx, uint8_t addr, uint8_t *data, size_t len)
Reads a register.
Definition: sc16is752.h:86
uint8_t tx_in_progress
Characters placed into transmit FIFO.
Definition: sc16is752.h:167
void(* remove_irq)(sc16is752_context *ctx)
Shall remove the interrupt handler.
Definition: sc16is752.h:131
bool(* install_irq)(sc16is752_context *ctx)
Shall install the interrupt handler.
Definition: sc16is752.h:124
sc16is752_mode mode
Device mode.
Definition: sc16is752.h:138
bool(* first_open)(sc16is752_context *ctx)
First open.
Definition: sc16is752.h:110
uint8_t lcr
Shadow Line Control Register (LCR).
Definition: sc16is752.h:181
uint8_t efcr
Shadow Extra Features Control Register (EFCR).
Definition: sc16is752.h:188
SC16IS752 I2C context.
Definition: sc16is752.h:229
const char * bus_path
The I2C bus device path.
Definition: sc16is752.h:244
int fd
The I2C bus device file descriptor.
Definition: sc16is752.h:237
SC16IS752 SPI context.
Definition: sc16is752.h:194
const char * spi_path
The SPI bus device path.
Definition: sc16is752.h:223
uint32_t speed_hz
The SPI bus speed in Hertz.
Definition: sc16is752.h:216
uint8_t cs
The SPI device chip select.
Definition: sc16is752.h:209
int fd
The SPI bus device file descriptor.
Definition: sc16is752.h:202