11#include "fsl_common.h"
23#ifndef FSL_COMPONENT_ID
24#define FSL_COMPONENT_ID "platform.drivers.nic301"
30#define FSL_NIC301_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
33#define GPV0_BASE (0x41000000UL)
34#define GPV1_BASE (0x41100000UL)
35#define GPV4_BASE (0x41400000UL)
37#define NIC_FN_MOD2_OFFSET (0x024UL)
38#define NIC_FN_MOD_AHB_OFFSET (0x028UL)
39#define NIC_WR_TIDEMARK_OFFSET (0x040UL)
40#define NIC_READ_QOS_OFFSET (0x100UL)
41#define NIC_WRITE_QOS_OFFSET (0x104UL)
42#define NIC_FN_MOD_OFFSET (0x108UL)
44#define NIC_LCD_BASE (GPV0_BASE + 0x44000)
45#define NIC_CSI_BASE (GPV0_BASE + 0x45000)
46#define NIC_PXP_BASE (GPV0_BASE + 0x46000)
48#define NIC_DCP_BASE (GPV1_BASE + 0x42000)
49#define NIC_ENET_BASE (GPV1_BASE + 0x43000)
50#define NIC_USBO2_BASE (GPV1_BASE + 0x44000)
51#define NIC_USDHC1_BASE (GPV1_BASE + 0x45000)
52#define NIC_USDHC2_BASE (GPV1_BASE + 0x46000)
53#define NIC_TestPort_BASE (GPV1_BASE + 0x47000)
55#define NIC_CM7_BASE (GPV4_BASE + 0x42000)
56#define NIC_DMA_BASE (GPV4_BASE + 0x43000)
58#define NIC_QOS_MASK (0xF)
59#define NIC_WR_TIDEMARK_MASK (0x7)
60#define NIC_FN_MOD_AHB_MASK (0x7)
61#define NIC_FN_MOD_MASK (0x1)
62#define NIC_FN_MOD2_MASK (0x1)
67 kNIC_REG_READ_QOS_LCD = NIC_LCD_BASE + NIC_READ_QOS_OFFSET,
68 kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET,
69 kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET,
70 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
71 kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
72 kNIC_REG_READ_QOS_USBO2 = NIC_USBO2_BASE + NIC_READ_QOS_OFFSET,
73 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
74 kNIC_REG_READ_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_READ_QOS_OFFSET,
75 kNIC_REG_READ_QOS_TestPort = NIC_TestPort_BASE + NIC_READ_QOS_OFFSET,
76 kNIC_REG_READ_QOS_CM7 = NIC_CM7_BASE + NIC_READ_QOS_OFFSET,
77 kNIC_REG_READ_QOS_DMA = NIC_DMA_BASE + NIC_READ_QOS_OFFSET,
80 kNIC_REG_WRITE_QOS_LCD = NIC_LCD_BASE + NIC_WRITE_QOS_OFFSET,
81 kNIC_REG_WRITE_QOS_CSI = NIC_CSI_BASE + NIC_WRITE_QOS_OFFSET,
82 kNIC_REG_WRITE_QOS_PXP = NIC_PXP_BASE + NIC_WRITE_QOS_OFFSET,
83 kNIC_REG_WRITE_QOS_DCP = NIC_DCP_BASE + NIC_WRITE_QOS_OFFSET,
84 kNIC_REG_WRITE_QOS_ENET = NIC_ENET_BASE + NIC_WRITE_QOS_OFFSET,
85 kNIC_REG_WRITE_QOS_USBO2 = NIC_USBO2_BASE + NIC_WRITE_QOS_OFFSET,
86 kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
87 kNIC_REG_WRITE_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_WRITE_QOS_OFFSET,
88 kNIC_REG_WRITE_QOS_TestPort = NIC_TestPort_BASE + NIC_WRITE_QOS_OFFSET,
89 kNIC_REG_WRITE_QOS_CM7 = NIC_CM7_BASE + NIC_WRITE_QOS_OFFSET,
90 kNIC_REG_WRITE_QOS_DMA = NIC_DMA_BASE + NIC_WRITE_QOS_OFFSET,
93 kNIC_REG_FN_MOD_LCD = NIC_LCD_BASE + NIC_FN_MOD_OFFSET,
94 kNIC_REG_FN_MOD_CSI = NIC_CSI_BASE + NIC_FN_MOD_OFFSET,
95 kNIC_REG_FN_MOD_PXP = NIC_PXP_BASE + NIC_FN_MOD_OFFSET,
96 kNIC_REG_FN_MOD_DCP = NIC_DCP_BASE + NIC_FN_MOD_OFFSET,
97 kNIC_REG_FN_MOD_ENET = NIC_ENET_BASE + NIC_FN_MOD_OFFSET,
98 kNIC_REG_FN_MOD_USBO2 = NIC_USBO2_BASE + NIC_FN_MOD_OFFSET,
99 kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,
100 kNIC_REG_FN_MOD_USDHC2 = NIC_USDHC2_BASE + NIC_FN_MOD_OFFSET,
101 kNIC_REG_FN_MOD_TestPort = NIC_TestPort_BASE + NIC_FN_MOD_OFFSET,
102 kNIC_REG_FN_MOD_CM7 = NIC_CM7_BASE + NIC_FN_MOD_OFFSET,
103 kNIC_REG_FN_MOD_DMA = NIC_DMA_BASE + NIC_FN_MOD_OFFSET,
106 kNIC_REG_FN_MOD2_DCP = NIC_ENET_BASE + NIC_FN_MOD2_OFFSET,
109 kNIC_REG_FN_MOD_AHB_ENET = NIC_ENET_BASE + NIC_FN_MOD_AHB_OFFSET,
110 kNIC_REG_FN_MOD_AHB_TestPort = NIC_TestPort_BASE + NIC_FN_MOD_AHB_OFFSET,
111 kNIC_REG_FN_MOD_AHB_DMA = NIC_DMA_BASE + NIC_FN_MOD_AHB_OFFSET,
114 kNIC_REG_WR_TIDEMARK_CM7 = NIC_CM7_BASE + NIC_WR_TIDEMARK_OFFSET,
118typedef enum _nic_fn_mod2
120 kNIC_FN_MOD2_ENABLE = 0,
125typedef enum _nic_fn_mod_ahb
127 kNIC_FN_MOD_AHB_RD_INCR_OVERRIDE = 0,
128 kNIC_FN_MOD_AHB_WR_INCR_OVERRIDE,
129 kNIC_FN_MOD_AHB_LOCK_OVERRIDE,
133typedef enum _nic_fn_mod
135 kNIC_FN_MOD_ReadIssue = 0,
136 kNIC_FN_MOD_WriteIssue,
163#if defined(__cplusplus)
173static inline void NIC_SetReadQos(nic_reg_t base, nic_qos_t value)
175 *(
volatile uint32_t *)(base) = (value & NIC_QOS_MASK);
185static inline nic_qos_t NIC_GetReadQos(nic_reg_t base)
187 return (nic_qos_t)((*(
volatile uint32_t *)(base)) & NIC_QOS_MASK);
196static void inline NIC_SetWriteQos(nic_reg_t base, nic_qos_t value)
198 *(
volatile uint32_t *)(base) = (value & NIC_QOS_MASK);
208static inline nic_qos_t NIC_GetWriteQos(nic_reg_t base)
210 return (nic_qos_t)((*(
volatile uint32_t *)(base)) & NIC_QOS_MASK);
219static inline void NIC_SetFnModAhb(nic_reg_t base, nic_fn_mod_ahb_t v)
221 *(
volatile uint32_t *)(base) = v;
231static inline nic_fn_mod_ahb_t NIC_GetFnModAhb(nic_reg_t base)
233 return (nic_fn_mod_ahb_t)((*(
volatile uint32_t *)(base)) & NIC_FN_MOD_AHB_MASK);
242static inline void NIC_SetWrTideMark(nic_reg_t base, uint8_t value)
244 *(
volatile uint32_t *)(base) = (value & NIC_WR_TIDEMARK_MASK);
254static inline uint8_t NIC_GetWrTideMark(nic_reg_t base)
256 return (uint8_t)((*(
volatile uint32_t *)(base)) & NIC_WR_TIDEMARK_MASK);
265static inline void NIC_SetFnMod(nic_reg_t base, nic_fn_mod_t value)
267 *(
volatile uint32_t *)(base) = value;
277static inline nic_fn_mod_t NIC_GetFnMod(nic_reg_t base)
279 return (nic_fn_mod_t)((*(
volatile uint32_t *)(base)) & NIC_FN_MOD_MASK);
288static inline void NIC_SetFnMod2(nic_reg_t base, nic_fn_mod_t value)
290 *(
volatile uint32_t *)(base) = value;
300static inline nic_fn_mod2_t NIC_GetFnMod2(nic_reg_t base)
302 return (nic_fn_mod2_t)((*(
volatile uint32_t *)(base)) & NIC_FN_MOD2_MASK);
305#if defined(__cplusplus)
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:286