47#define RISCV_MSTATUS_MIE 0x8
49#define CPU_ISR_PASSES_FRAME_POINTER FALSE
51#define CPU_HARDWARE_FP FALSE
52#define CPU_SOFTWARE_FP FALSE
53#define CPU_ALL_TASKS_ARE_FP FALSE
54#define CPU_IDLE_TASK_IS_FP FALSE
55#define CPU_USE_DEFERRED_FP_SWITCH FALSE
57#define CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE
59#define CPU_STACK_GROWS_UP FALSE
61#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (64)))
62#define CPU_BIG_ENDIAN FALSE
63#define CPU_LITTLE_ENDIAN TRUE
64#define CPU_MODES_INTERRUPT_MASK 0x0000000000000001
66#define CPU_CACHE_LINE_BYTES 64
70#define CPU_SIZEOF_POINTER 4
72#define CPU_STACK_MINIMUM_SIZE 4096
74#elif __riscv_xlen == 64
76#define CPU_SIZEOF_POINTER 8
78#define CPU_STACK_MINIMUM_SIZE 8192
83#define CPU_ALIGNMENT 16
85#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
88#define CPU_STACK_ALIGNMENT 16
90#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
99typedef float RISCV_Float;
100#elif __riscv_flen == 64
101typedef double RISCV_Float;
106 volatile uint32_t is_executing;
110 uint32_t isr_dispatch_disable;
143#define _CPU_Context_Get_SP( _context ) \
146#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
148#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
150static inline uint32_t riscv_interrupt_disable(
void )
152 unsigned long mstatus;
156 ".option arch, +zicsr\n"
157 "csrrc %0, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE )
"\n"
162 return mstatus & RISCV_MSTATUS_MIE;
165static inline void riscv_interrupt_enable( uint32_t level )
169 ".option arch, +zicsr\n"
170 "csrrs zero, mstatus, %0\n"
177#define _CPU_ISR_Disable( _level ) \
178 _level = riscv_interrupt_disable()
180#define _CPU_ISR_Enable( _level ) \
181 riscv_interrupt_enable( _level )
183#define _CPU_ISR_Flash( _level ) \
185 _CPU_ISR_Enable( _level ); \
186 riscv_interrupt_disable(); \
189static inline bool _CPU_ISR_Is_enabled(
unsigned long level )
191 return ( level & RISCV_MSTATUS_MIE ) != 0;
205 ".option arch, +zicsr\n"
206 "csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE )
"\n"
215void _CPU_Context_Initialize(
217 void *stack_area_begin,
218 size_t stack_area_size,
220 void ( *entry_point )(
void ),
225#define _CPU_Context_Restart_self( _the_context ) \
226 _CPU_Context_restore( (_the_context) )
228#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
230#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
232#define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE
234#define CPU_MAXIMUM_PROCESSORS 32
236typedef uint16_t Priority_bit_map_Word;
244 RISCV_INTERRUPT_SOFTWARE_USER = 0,
245 RISCV_INTERRUPT_SOFTWARE_SUPERVISOR = 1,
246 RISCV_INTERRUPT_SOFTWARE_MACHINE = 3,
247 RISCV_INTERRUPT_TIMER_USER = 4,
248 RISCV_INTERRUPT_TIMER_SUPERVISOR = 5,
249 RISCV_INTERRUPT_TIMER_MACHINE = 7,
250 RISCV_INTERRUPT_EXTERNAL_USER = 8,
251 RISCV_INTERRUPT_EXTERNAL_SUPERVISOR = 9,
252 RISCV_INTERRUPT_EXTERNAL_MACHINE = 11
253} RISCV_Interrupt_code;
261 RISCV_EXCEPTION_INSTRUCTION_ADDRESS_MISALIGNED = 0,
262 RISCV_EXCEPTION_INSTRUCTION_ACCESS_FAULT = 1,
263 RISCV_EXCEPTION_ILLEGAL_INSTRUCTION = 2,
264 RISCV_EXCEPTION_BREAKPOINT = 3,
265 RISCV_EXCEPTION_LOAD_ADDRESS_MISALIGNED = 4,
266 RISCV_EXCEPTION_LOAD_ACCESS_FAULT = 5,
267 RISCV_EXCEPTION_STORE_OR_AMO_ADDRESS_MISALIGNED = 6,
268 RISCV_EXCEPTION_STORE_OR_AMO_ACCESS_FAULT = 7,
269 RISCV_EXCEPTION_ENVIRONMENT_CALL_FROM_U_MODE = 8,
270 RISCV_EXCEPTION_ENVIRONMENT_CALL_FROM_S_MODE = 9,
271 RISCV_EXCEPTION_ENVIRONMENT_CALL_FROM_M_MODE = 11,
272 RISCV_EXCEPTION_INSTRUCTION_PAGE_FAULT = 12,
273 RISCV_EXCEPTION_LOAD_PAGE_FAULT = 13,
274 RISCV_EXCEPTION_STORE_OR_AMO_PAGE_FAULT = 15
275} RISCV_Exception_code;
434static inline uint32_t CPU_swap_u32(
438 uint32_t byte1, byte2, byte3, byte4, swapped;
440 byte4 = (value >> 24) & 0xff;
441 byte3 = (value >> 16) & 0xff;
442 byte2 = (value >> 8) & 0xff;
443 byte1 = value & 0xff;
445 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
449#define CPU_swap_u16( value ) \
450 (((value&0xff) << 8) | ((value >> 8)&0xff))
452typedef uint32_t CPU_Counter_ticks;
456extern volatile uint32_t *
const _RISCV_Counter;
462uint32_t _CPU_SMP_Initialize(
void );
464bool _CPU_SMP_Start_processor( uint32_t cpu_index );
466void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
468void _CPU_SMP_Prepare_start_multitasking(
void );
470static inline uint32_t _CPU_SMP_Get_current_processor(
void )
472 unsigned long mhartid;
476 ".option arch, +zicsr\n"
482 return (uint32_t) mhartid - RISCV_BOOT_HARTID;
485void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
487static inline bool _CPU_Context_Get_is_executing(
494static inline void _CPU_Context_Set_is_executing(
499 context->is_executing = is_executing;
504#define _CPU_Start_multitasking( _heir ) _RISCV_Start_multitasking( _heir )
This header file provides basic definitions used by the API and the implementation.
#define RTEMS_XSTRING(...)
Stringifies the expansion of the arguments.
Definition: basedefs.h:987
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
#define _CPU_ISR_Set_level(_new_level)
Definition: cpu.h:378
#define ra
return address */
Definition: regs.h:66
#define sp
stack-pointer */
Definition: regs.h:64
#define gp
global data pointer */
Definition: regs.h:63
rtems_termios_device_context * context
Definition: console-config.c:62
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
Thread register context.
Definition: cpu.h:173