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RTEMS 6.1-rc7
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11#ifndef _RTEMS_TMTEST27
12#error "This is an RTEMS internal file you must not include directly."
24#define MUST_WAIT_FOR_INTERRUPT 1
26#define Install_tm27_vector( handler ) \
27 rtems_interrupt_handler_install( \
28 TX3904_IRQ_TMR0, "benchmark", 0, \
31#define Cause_tm27_intr() \
33 uint32_t _clicks = 20; \
34 TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \
35 TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CPRA, _clicks ); \
36 TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \
37 TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x8001 ); \
38 TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TCR, 0xC0 ); \
39 *((volatile uint32_t*) 0xFFFFC01C) = 0x00000700; \
42#define Clear_tm27_intr() \
44 TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x0001 ); \
45 TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \
46 TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \
49#define Lower_tm27_intr() \
50 mips_enable_in_interrupt_mask( 0xff01 );