RTEMS 6.1-rc7
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tm27.h
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/* @file
4 *
5 * @ingroup RTEMSBSPsARMLPC32XX
6 *
7 * @brief Implementations of interrupt mechanisms for Time Test 27
8 */
9
10/*
11 * Copyright (c) 2010 embedded brains GmbH & Co. KG
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _RTEMS_TMTEST27
36#error "This is an RTEMS internal file you must not include directly."
37#endif
38
39#ifndef __tm27_h
40#define __tm27_h
41
42#include <rtems.h>
43
44#include <bsp/lpc32xx.h>
45#include <bsp/irq.h>
46#include <bsp/irq-generic.h>
47
48#define MUST_WAIT_FOR_INTERRUPT 1
49
50#define LPC32XX_TM27_TIMER (&lpc32xx.timer_2)
51
52#define LPC32XX_TM27_IRQ LPC32XX_IRQ_TIMER_2
53
54static inline void Install_tm27_vector( rtems_interrupt_handler handler )
55{
57 volatile lpc_timer *timer = LPC32XX_TM27_TIMER;
58
59 LPC32XX_TIMCLK_CTRL1 |= 1U << 4;
60
61 timer->tcr = LPC_TIMER_TCR_RST;
62 timer->ctcr = 0x0;
63 timer->pr = 0x0;
64 timer->ir = 0xff;
65 timer->mcr = LPC_TIMER_MCR_MR0_INTR | LPC_TIMER_MCR_MR0_STOP |
66 LPC_TIMER_MCR_MR0_RST;
67 timer->ccr = 0x0;
68 timer->emr = 0x0;
69 timer->mr0 = 0x1;
70
71 rtems_interrupt_entry_initialize(
72 &entry,
73 handler,
74 NULL,
75 "tm27"
76 );
78 LPC32XX_TM27_IRQ,
80 &entry
81 );
82}
83
84static inline void Cause_tm27_intr(void)
85{
86 volatile lpc_timer *timer = LPC32XX_TM27_TIMER;
87
88 timer->tcr = LPC_TIMER_TCR_EN;
89}
90
91static inline void Clear_tm27_intr(void)
92{
93 volatile lpc_timer *timer = LPC32XX_TM27_TIMER;
94
95 timer->ir = LPC_TIMER_IR_MR0;
97 LPC32XX_TM27_IRQ,
98 LPC32XX_IRQ_PRIORITY_LOWEST
99 );
100}
101
102static inline void Lower_tm27_intr(void)
103{
104 bsp_interrupt_vector_enable(LPC32XX_TM27_IRQ);
106 LPC32XX_TM27_IRQ,
107 LPC32XX_IRQ_PRIORITY_HIGHEST
108 );
109}
110
111#endif /* __tm27_h */
rtems_status_code rtems_interrupt_entry_install(rtems_vector_number vector, rtems_option options, rtems_interrupt_entry *entry)
Installs the interrupt entry at the interrupt vector.
Definition: irq-generic.c:264
#define RTEMS_INTERRUPT_SHARED
This interrupt handler install option allows that the interrupt handler may share the interrupt vecto...
Definition: intr.h:960
void(* rtems_interrupt_handler)(void *)
Interrupt handler routines shall have this type.
Definition: intr.h:1030
rtems_status_code rtems_interrupt_set_priority(rtems_vector_number vector, uint32_t priority)
Sets the priority of the interrupt vector.
Definition: irq-priority.c:39
rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
Enables the interrupt vector.
Definition: irq.c:140
This header file provides interfaces of the Interrupt Manager implementation.
Register base addresses.
This header file defines the RTEMS Classic API.
Definition: mmu-config.c:53
Timer control block.
Definition: lpc-timer.h:147
This structure represents an interrupt entry.
Definition: intr.h:1070