RTEMS 6.1-rc7
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cpu.h
Go to the documentation of this file.
1
10/*
11 * COPYRIGHT (c) 1989-2006.
12 * On-Line Applications Research Corporation (OAR).
13 * adapted to Blackfin by Alain Schaefer <alain.schaefer@easc.ch>
14 * and Antonio Giovanini <antonio@atos.com.br>
15 *
16 * The license and distribution terms for this file may be
17 * found in the file LICENSE in this distribution or at
18 * http://www.rtems.org/license/LICENSE.
19 */
20
21#ifndef _RTEMS_SCORE_CPU_H
22#define _RTEMS_SCORE_CPU_H
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
29#include <rtems/score/bfin.h>
30
31/* conditional compilation parameters */
32
33/*
34 * Does the CPU follow the simple vectored interrupt model?
35 *
36 * If TRUE, then RTEMS allocates the vector table it internally manages.
37 * If FALSE, then the BSP is assumed to allocate and manage the vector
38 * table
39 *
40 * BFIN Specific Information:
41 *
42 * XXX document implementation including references if appropriate
43 */
44#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
45
55#define CPU_ISR_PASSES_FRAME_POINTER TRUE
56
57#define CPU_HARDWARE_FP FALSE
58
59#define CPU_SOFTWARE_FP FALSE
60
61#define CPU_ALL_TASKS_ARE_FP FALSE
62
63#define CPU_IDLE_TASK_IS_FP FALSE
64
65#define CPU_USE_DEFERRED_FP_SWITCH FALSE
66
67#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
68
80#define CPU_STACK_GROWS_UP FALSE
81
82/* FIXME: Is this the right value? */
83#define CPU_CACHE_LINE_BYTES 32
84
85#define CPU_STRUCTURE_ALIGNMENT
86
97#define CPU_MODES_INTERRUPT_MASK 0x00000001
98
99#define CPU_MAXIMUM_PROCESSORS 32
100
101/*
102 * Processor defined structures required for cpukit/score.
103 *
104 * Port Specific Information:
105 *
106 * XXX document implementation including references if appropriate
107 */
108
109/* may need to put some structures here. */
110
111#ifndef ASM
112
164/* make sure this stays in sync with the assembly function
165 __CPU_Context_switch in cpu_asm.S */
166typedef struct {
167 uint32_t register_r4;
168 uint32_t register_r5;
169 uint32_t register_r6;
170 uint32_t register_r7;
171
172 uint32_t register_p3;
173 uint32_t register_p4;
174 uint32_t register_p5;
175 uint32_t register_fp;
176 uint32_t register_sp;
177
178 uint32_t register_rets;
179
180 uint32_t imask;
182
183#define _CPU_Context_Get_SP( _context ) \
184 (_context)->register_sp
185
191typedef struct {
196 /*uint32_t special_interrupt_register;*/
198
209#endif /* ASM */
210
221#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
222
232#define CPU_INTERRUPT_NUMBER_OF_VECTORS 16
233
238#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
239
245#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
246
256#define CPU_STACK_MINIMUM_SIZE (1024*8)
257
258#define CPU_SIZEOF_POINTER 4
259
268#define CPU_ALIGNMENT 8
269
293#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
294
295#define CPU_STACK_ALIGNMENT 8
296
297#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
298
299#ifndef ASM
300
301/*
302 * ISR handler macros
303 */
304
320#define _CPU_ISR_Disable( _level ) \
321 { \
322 __asm__ volatile ("cli %0; csync \n" : "=d" (_level) ); \
323 }
324
325
337#define _CPU_ISR_Enable( _level ) { \
338 __asm__ __volatile__ ("sti %0; csync \n" : : "d" (_level) ); \
339 }
340
353#define _CPU_ISR_Flash( _level ) { \
354 __asm__ __volatile__ ("sti %0; csync; cli r0; csync" \
355 : : "d"(_level) : "R0" ); \
356 }
357
358static inline bool _CPU_ISR_Is_enabled( uint32_t level )
359{
360 return level != 0;
361}
362
378#define _CPU_ISR_Set_level( _new_level ) \
379 { \
380 __asm__ __volatile__ ( "sti %0; csync" : : "d"(_new_level ? 0 : 0xffff) ); \
381 }
382
393uint32_t _CPU_ISR_Get_level( void );
394
395/* end of ISR handler macros */
396
399/* Context handler macros */
400
433void _CPU_Context_Initialize(
434 Context_Control *the_context,
435 uint32_t *stack_base,
436 uint32_t size,
437 uint32_t new_level,
438 void *entry_point,
439 bool is_fp,
440 void *tls_area
441);
442
458#define _CPU_Context_Restart_self( _the_context ) \
459 _CPU_Context_restore( (_the_context) );
460
461/* end of Context handler macros */
462
463#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
464
465#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
466
467/* functions */
468
477void _CPU_Initialize(void);
478
479typedef void ( *CPU_ISR_raw_handler )( void );
480
482 uint32_t vector,
483 CPU_ISR_raw_handler new_handler,
484 CPU_ISR_raw_handler *old_handler
485);
486
487typedef void ( *CPU_ISR_handler )( uint32_t );
488
490 uint32_t vector,
491 CPU_ISR_handler new_handler,
492 CPU_ISR_handler *old_handler
493);
494
495RTEMS_NO_RETURN void *_CPU_Thread_Idle_body( uintptr_t ignored );
496
513 Context_Control *run,
514 Context_Control *heir
515);
516
529RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context );
530
533/* FIXME */
535
537
547/*
548 *
549 * The following routine swaps the endian format of an unsigned int.
550 * It must be static because it is referenced indirectly.
551 *
552 * This version will work on any processor, but if there is a better
553 * way for your CPU PLEASE use it. The most common way to do this is to:
554 *
555 * swap least significant two bytes with 16-bit rotate
556 * swap upper and lower 16-bits
557 * swap most significant two bytes with 16-bit rotate
558 *
559 * Some CPUs have special instructions which swap a 32-bit quantity in
560 * a single instruction (e.g. i486). It is probably best to avoid
561 * an "endian swapping control bit" in the CPU. One good reason is
562 * that interrupts would probably have to be disabled to ensure that
563 * an interrupt does not try to access the same "chunk" with the wrong
564 * endian. Another good reason is that on some CPUs, the endian bit
565 * endianness for ALL fetches -- both code and data -- so the code
566 * will be fetched incorrectly.
567 *
568 * @param[in] value is the value to be swapped
569 * @return the value after being endian swapped
570 *
571 * Port Specific Information:
572 *
573 * XXX document implementation including references if appropriate
574 */
575
576static inline uint32_t CPU_swap_u32(
577 uint32_t value
578)
579{
580 uint32_t byte1, byte2, byte3, byte4, swapped;
581
582 byte4 = (value >> 24) & 0xff;
583 byte3 = (value >> 16) & 0xff;
584 byte2 = (value >> 8) & 0xff;
585 byte1 = value & 0xff;
586
587 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
588 return( swapped );
589}
590
597#define CPU_swap_u16( value ) \
598 (((value&0xff) << 8) | ((value >> 8)&0xff))
599
602typedef uint32_t CPU_Counter_ticks;
603
604uint32_t _CPU_Counter_frequency( void );
605
606CPU_Counter_ticks _CPU_Counter_read( void );
607
609typedef uintptr_t CPU_Uint32ptr;
610
611#endif /* ASM */
612
613#ifdef __cplusplus
614}
615#endif
616
617#endif
This header file provides basic definitions used by the API and the implementation.
void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.c:100
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
Blackfin Set up Basic CPU Dependency Settings Based on Compiler Settings.
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
Thread register context.
Definition: cpu.h:173