RTEMS 6.1-rc7
Loading...
Searching...
No Matches
irq.h
Go to the documentation of this file.
1
7/*
8 * SPDX-License-Identifier: BSD-2-Clause
9 *
10 * Copyright (C) 2013 embedded brains GmbH & Co. KG
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#ifndef LIBBSP_ARM_XILINX_ZYNQ_IRQ_H
35#define LIBBSP_ARM_XILINX_ZYNQ_IRQ_H
36
37#ifndef ASM
38
39#include <rtems/irq-extension.h>
40
42#include <dev/irq/arm-gic-irq.h>
43
44#ifdef __cplusplus
45extern "C" {
46#endif /* __cplusplus */
47
55#define ZYNQ_IRQ_CPU_0 32
56#define ZYNQ_IRQ_CPU_1 33
57#define ZYNQ_IRQ_L2_CACHE 34
58#define ZYNQ_IRQ_OCM 35
59#define ZYNQ_IRQ_PMU_0 37
60#define ZYNQ_IRQ_PMU_1 38
61#define ZYNQ_IRQ_XADC 39
62#define ZYNQ_IRQ_DVI 40
63#define ZYNQ_IRQ_SWDT 41
64#define ZYNQ_IRQ_TTC_0_0 42
65#define ZYNQ_IRQ_TTC_1_0 43
66#define ZYNQ_IRQ_TTC_2_0 44
67#define ZYNQ_IRQ_DMAC_ABORT 45
68#define ZYNQ_IRQ_DMAC_0 46
69#define ZYNQ_IRQ_DMAC_1 47
70#define ZYNQ_IRQ_DMAC_2 48
71#define ZYNQ_IRQ_DMAC_3 49
72#define ZYNQ_IRQ_SMC 50
73#define ZYNQ_IRQ_QUAD_SPI 51
74#define ZYNQ_IRQ_GPIO 52
75#define ZYNQ_IRQ_USB_0 53
76#define ZYNQ_IRQ_ETHERNET_0 54
77#define ZYNQ_IRQ_ETHERNET_0_WAKEUP 55
78#define ZYNQ_IRQ_SDIO_0 56
79#define ZYNQ_IRQ_I2C_0 57
80#define ZYNQ_IRQ_SPI_0 58
81#define ZYNQ_IRQ_UART_0 59
82#define ZYNQ_IRQ_CAN_0 60
83#define ZYNQ_IRQ_FPGA_0 61
84#define ZYNQ_IRQ_FPGA_1 62
85#define ZYNQ_IRQ_FPGA_2 63
86#define ZYNQ_IRQ_FPGA_3 64
87#define ZYNQ_IRQ_FPGA_4 65
88#define ZYNQ_IRQ_FPGA_5 66
89#define ZYNQ_IRQ_FPGA_6 67
90#define ZYNQ_IRQ_FPGA_7 68
91#define ZYNQ_IRQ_TTC_0_1 69
92#define ZYNQ_IRQ_TTC_1_1 70
93#define ZYNQ_IRQ_TTC_2_1 71
94#define ZYNQ_IRQ_DMAC_4 72
95#define ZYNQ_IRQ_DMAC_5 73
96#define ZYNQ_IRQ_DMAC_6 74
97#define ZYNQ_IRQ_DMAC_7 75
98#define ZYNQ_IRQ_USB_1 76
99#define ZYNQ_IRQ_ETHERNET_1 77
100#define ZYNQ_IRQ_ETHERNET_1_WAKEUP 78
101#define ZYNQ_IRQ_SDIO_1 79
102#define ZYNQ_IRQ_I2C_1 80
103#define ZYNQ_IRQ_SPI_1 81
104#define ZYNQ_IRQ_UART_1 82
105#define ZYNQ_IRQ_CAN_1 83
106#define ZYNQ_IRQ_FPGA_8 84
107#define ZYNQ_IRQ_FPGA_9 85
108#define ZYNQ_IRQ_FPGA_10 86
109#define ZYNQ_IRQ_FPGA_11 87
110#define ZYNQ_IRQ_FPGA_12 88
111#define ZYNQ_IRQ_FPGA_13 89
112#define ZYNQ_IRQ_FPGA_14 90
113#define ZYNQ_IRQ_FPGA_15 91
114#define ZYNQ_IRQ_PARITY 92
115
116#define BSP_INTERRUPT_VECTOR_COUNT 93
117
120#ifdef __cplusplus
121}
122#endif /* __cplusplus */
123
124#endif /* ASM */
125
126#endif /* LIBBSP_ARM_XILINX_ZYNQ_IRQ_H */
This header file provides the interfaces of the Cortex-A9 MPCore Support.
This header file provides interfaces of the ARM Generic Interrupt Controller (GIC) support.
This header file is provided for backward compatiblility.