65#define CPU_ISR_PASSES_FRAME_POINTER TRUE
67#define CPU_HARDWARE_FP FALSE
69#define CPU_SOFTWARE_FP FALSE
71#define CPU_ALL_TASKS_ARE_FP FALSE
73#define CPU_IDLE_TASK_IS_FP FALSE
75#define CPU_USE_DEFERRED_FP_SWITCH TRUE
77#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
88#define CPU_STACK_GROWS_UP FALSE
91#define CPU_CACHE_LINE_BYTES 32
93#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
102#define CPU_MODES_INTERRUPT_MASK 0x00000001
146#ifdef OR1K_64BIT_ARCH
147#define or1kreg uint64_t
149#define or1kreg uint32_t
191#define _CPU_Context_Get_SP( _context ) \
203#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
211#define CPU_STACK_MINIMUM_SIZE 4096
219#define CPU_ALIGNMENT 8
225#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
234#define CPU_SIZEOF_POINTER 4
257#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
259#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
261#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
271static inline uint32_t or1k_interrupt_disable(
void )
274 sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
276 _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_IEE));
281static inline void or1k_interrupt_enable(uint32_t level)
286 sr = level | CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE;
287 _OR1K_mtspr(CPU_OR1K_SPR_SR, sr);
291#define _CPU_ISR_Disable( _level ) \
292 _level = or1k_interrupt_disable()
302#define _CPU_ISR_Enable( _level ) \
303 or1k_interrupt_enable( _level )
313#define _CPU_ISR_Flash( _level ) \
315 _CPU_ISR_Enable( _level ); \
316 _OR1K_mtspr(CPU_OR1K_SPR_SR, (_level & ~CPU_OR1K_SPR_SR_IEE)); \
319static inline bool _CPU_ISR_Is_enabled( uint32_t level )
321 return ( level & CPU_OR1K_SPR_SR ) != 0;
346#define OR1K_FAST_CONTEXT_SWITCH_ENABLED FALSE
386void _CPU_Context_Initialize(
388 void *stack_area_begin,
389 size_t stack_area_size,
391 void (*entry_point)(
void ),
407#define _CPU_Context_Restart_self( _the_context ) \
408 _CPU_Context_restore( (_the_context) );
412#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
414#define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE
418#define CPU_SIZEOF_POINTER 4
420#define CPU_MAXIMUM_PROCESSORS 32
430#if !OR1K_FAST_CONTEXT_SWITCH_ENABLED
465 CPU_ISR_raw_handler new_handler,
466 CPU_ISR_raw_handler *old_handler
469typedef void ( *CPU_ISR_handler )( uint32_t );
473 CPU_ISR_handler new_handler,
474 CPU_ISR_handler *old_handler
479 (CPU_ISR_raw_handler) new_handler,
480 (CPU_ISR_raw_handler *) old_handler
522 void **fp_context_ptr
533 void **fp_context_ptr
557static inline unsigned int CPU_swap_u32(
561 uint32_t byte1, byte2, byte3, byte4, swapped;
563 byte4 = (value >> 24) & 0xff;
564 byte3 = (value >> 16) & 0xff;
565 byte2 = (value >> 8) & 0xff;
566 byte1 = value & 0xff;
568 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
572#define CPU_swap_u16( value ) \
573 (((value&0xff) << 8) | ((value >> 8)&0xff))
575typedef uint32_t CPU_Counter_ticks;
This header file provides basic definitions used by the API and the implementation.
void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.c:100
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
#define _CPU_ISR_Set_level(_new_level)
Definition: cpu.h:378
rtems_termios_device_context * context
Definition: console-config.c:62
#define _CPU_Context_restore_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:901
#define _CPU_Context_save_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:895
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
Thread register context.
Definition: cpu.h:173