RTEMS 6.1-rc7
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bsp.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2009, 2011 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#ifndef LIBBSP_ARM_LPC32XX_BSP_H
37#define LIBBSP_ARM_LPC32XX_BSP_H
38
49#include <bspopts.h>
50
51#define BSP_FEATURE_IRQ_EXTENSION
52
53#ifndef ASM
54
55#include <rtems.h>
56
57#include <bsp/lpc32xx.h>
59
60#ifdef __cplusplus
61extern "C" {
62#endif /* __cplusplus */
63
64struct rtems_bsdnet_ifconfig;
65
70 struct rtems_bsdnet_ifconfig *config,
71 int attaching
72);
73
77#define RTEMS_BSP_NETWORK_DRIVER_ATTACH lpc_eth_attach_detach
78
82#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0"
83
104void *lpc32xx_idle(uintptr_t ignored);
105
106#define LPC32XX_STANDARD_TIMER (&lpc32xx.timer_1)
107
108static inline unsigned lpc32xx_timer(void)
109{
110 volatile lpc_timer *timer = LPC32XX_STANDARD_TIMER;
111
112 return timer->tc;
113}
114
115static inline void lpc32xx_micro_seconds_delay(unsigned us)
116{
117 unsigned start = lpc32xx_timer();
118 unsigned delay = us * (LPC32XX_PERIPH_CLK / 1000000);
119 unsigned elapsed = 0;
120
121 do {
122 elapsed = lpc32xx_timer() - start;
123 } while (elapsed < delay);
124}
125
126#if LPC32XX_OSCILLATOR_MAIN == 13000000U
127 #define LPC32XX_HCLKPLL_CTRL_INIT_VALUE \
128 (HCLK_PLL_POWER | HCLK_PLL_DIRECT | HCLK_PLL_M(16 - 1))
129 #define LPC32XX_HCLKDIV_CTRL_INIT_VALUE \
130 (HCLK_DIV_HCLK(2 - 1) | HCLK_DIV_PERIPH_CLK(16 - 1) | HCLK_DIV_DDRAM_CLK(0))
131#else
132 #error "unexpected main oscillator frequency"
133#endif
134
135bool lpc32xx_start_pll_setup(
136 uint32_t hclkpll_ctrl,
137 uint32_t hclkdiv_ctrl,
138 bool force
139);
140
141uint32_t lpc32xx_sysclk(void);
142
143uint32_t lpc32xx_hclkpll_clk(void);
144
145uint32_t lpc32xx_periph_clk(void);
146
147uint32_t lpc32xx_hclk(void);
148
149uint32_t lpc32xx_arm_clk(void);
150
151uint32_t lpc32xx_ddram_clk(void);
152
153typedef enum {
154 LPC32XX_NAND_CONTROLLER_NONE,
155 LPC32XX_NAND_CONTROLLER_MLC,
156 LPC32XX_NAND_CONTROLLER_SLC
157} lpc32xx_nand_controller;
158
159void lpc32xx_select_nand_controller(lpc32xx_nand_controller nand_controller);
160
161void bsp_restart(void *addr);
162
163void *bsp_idle_thread(uintptr_t arg);
164
165#define BSP_IDLE_TASK_BODY bsp_idle_thread
166
167#define BSP_CONSOLE_UART_BASE LPC32XX_BASE_UART_5
168
174extern uint32_t lpc32xx_magic_zero_begin [];
175
181extern uint32_t lpc32xx_magic_zero_end [];
182
188extern uint32_t lpc32xx_magic_zero_size [];
189
190#ifdef LPC32XX_SCRATCH_AREA_SIZE
196 extern uint8_t lpc32xx_scratch_area [LPC32XX_SCRATCH_AREA_SIZE]
197 __attribute__((aligned(32)));
198#endif
199
200#define LPC32XX_DO_STOP_GPDMA \
201 do { \
202 if ((LPC32XX_DMACLK_CTRL & 0x1) != 0) { \
203 if ((lpc32xx.dma.cfg & DMA_CFG_E) != 0) { \
204 int i = 0; \
205 for (i = 0; i < 8; ++i) { \
206 lpc32xx.dma.channels [i].cfg = 0; \
207 } \
208 lpc32xx.dma.cfg &= ~DMA_CFG_E; \
209 } \
210 LPC32XX_DMACLK_CTRL = 0; \
211 } \
212 } while (0)
213
214#define LPC32XX_DO_STOP_ETHERNET \
215 do { \
216 if ((LPC32XX_MAC_CLK_CTRL & 0x7) == 0x7) { \
217 lpc32xx.eth.command = 0x38; \
218 lpc32xx.eth.mac1 = 0xcf00; \
219 lpc32xx.eth.mac1 = 0; \
220 LPC32XX_MAC_CLK_CTRL = 0; \
221 } \
222 } while (0)
223
224#define LPC32XX_DO_STOP_USB \
225 do { \
226 if ((LPC32XX_USB_CTRL & 0x010e8000) != 0) { \
227 LPC32XX_OTG_CLK_CTRL = 0; \
228 LPC32XX_USB_CTRL = 0x80000; \
229 } \
230 } while (0)
231
232#define LPC32XX_DO_RESTART(addr) \
233 do { \
234 ARM_SWITCH_REGISTERS; \
235 rtems_interrupt_level level; \
236 uint32_t ctrl = 0; \
237 \
238 rtems_interrupt_disable(level); \
239 (void) level; /* avoid set but not used warning */ \
240 \
241 arm_cp15_data_cache_test_and_clean(); \
242 arm_cp15_instruction_cache_invalidate(); \
243 \
244 ctrl = arm_cp15_get_control(); \
245 ctrl &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M); \
246 arm_cp15_set_control(ctrl); \
247 \
248 __asm__ volatile ( \
249 ARM_SWITCH_TO_ARM \
250 "mov pc, %[addr]\n" \
251 ARM_SWITCH_BACK \
252 : ARM_SWITCH_OUTPUT \
253 : [addr] "r" (addr) \
254 ); \
255 } while (0)
256
257#ifdef __cplusplus
258}
259#endif /* __cplusplus */
260
261#endif /* ASM */
262
265#endif /* LIBBSP_ARM_LPC32XX_BSP_H */
This header file provides the default definition of BSP_INITIAL_EXTENSION.
void * bsp_idle_thread(uintptr_t ignored)
Optimized idle task.
Definition: bspidle.c:39
int lpc_eth_attach_detach(struct rtems_bsdnet_ifconfig *config, int attaching)
Network driver attach and detach function.
uint32_t lpc32xx_magic_zero_begin[]
Begin of magic zero area.
void * lpc32xx_idle(uintptr_t ignored)
Optimized idle task.
uint32_t lpc32xx_magic_zero_end[]
End of magic zero area.
uint32_t lpc32xx_magic_zero_size[]
Size of magic zero area.
Register base addresses.
This header file defines the RTEMS Classic API.
Definition: xnandpsu_onfi.h:185
Definition: deflate.c:114
Timer control block.
Definition: lpc-timer.h:147