RTEMS 6.1-rc7
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fsl_dcdc.h
1/*
2 * Copyright 2017-2021, NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef __FSL_DCDC_H__
10#define __FSL_DCDC_H__
11
12#include "fsl_common.h"
13
19/*******************************************************************************
20 * Definitions
21 ******************************************************************************/
23#define FSL_DCDC_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
29{
30 kDCDC_LockedOKStatus = (1U << 0U),
31};
32
37{
43
48{
54
59{
67
72{
76
81{
87
92{
97
98#if (defined(FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT) && (FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT == 2))
102typedef enum _dcdc_voltage_output_sel
103{
107#endif /* FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT */
108
109#if defined(FSL_FEATURE_DCDC_HAS_CTRL_REG) && FSL_FEATURE_DCDC_HAS_CTRL_REG
113typedef enum _dcdc_low_power_mode
114{
115 kDCDC_StandbyMode = 0U,
116 kDCDC_LowPowerMode = 1U,
117 kDCDC_GpcStandbyLowPowerMode = 2U,
118} dcdc_low_power_mode_t;
119
123typedef enum _dcdc_control_mode
124{
128
132typedef enum _dcdc_trim_input_mode
133{
137
138#if defined(DCDC_REG4_ENABLE_SP_MASK) && DCDC_REG4_ENABLE_SP_MASK
143{
144 kDCDC_SetPoint0 = 1UL << 0UL,
145 kDCDC_SetPoint1 = 1UL << 1UL,
146 kDCDC_SetPoint2 = 1UL << 2UL,
147 kDCDC_SetPoint3 = 1UL << 3UL,
148 kDCDC_SetPoint4 = 1UL << 4UL,
149 kDCDC_SetPoint5 = 1UL << 5UL,
150 kDCDC_SetPoint6 = 1UL << 6UL,
151 kDCDC_SetPoint7 = 1UL << 7UL,
152 kDCDC_SetPoint8 = 1UL << 8UL,
153 kDCDC_SetPoint9 = 1UL << 9UL,
154 kDCDC_SetPoint10 = 1UL << 10UL,
155 kDCDC_SetPoint11 = 1UL << 11UL,
156 kDCDC_SetPoint12 = 1UL << 12UL,
157 kDCDC_SetPoint13 = 1UL << 13UL,
158 kDCDC_SetPoint14 = 1UL << 14UL,
159 kDCDC_SetPoint15 = 1UL << 15UL
160};
161#endif /* DCDC_REG4_ENABLE_SP_MASK */
162
166typedef struct _dcdc_config
167{
170 bool enableDcdcTimeout;
173#endif /* FSL_FEATURE_DCDC_HAS_CTRL_REGp */
174
178typedef struct _dcdc_detection_config
179{
181#if (defined(FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT) && (FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT == 2))
184#else
186#endif /* FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT */
195
199typedef struct _dcdc_loop_control_config
200{
204#if defined(FSL_FEATURE_DCDC_HAS_SWITCHING_CONVERTER_DIFFERENTIAL_MODE) && \
205 FSL_FEATURE_DCDC_HAS_SWITCHING_CONVERTER_DIFFERENTIAL_MODE
211#endif /* FSL_FEATURE_DCDC_HAS_SWITCHING_CONVERTER_DIFFERENTIAL_MODE */
214 uint32_t enableRCScaleCircuit;
225typedef struct _dcdc_low_power_config
226{
227#if !(defined(FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS) && FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS)
231#endif /* FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS */
239
244{
248 uint32_t feedbackPoint;
250
254typedef struct _dcdc_min_power_config
255{
258
259#if defined(DCDC_REG4_ENABLE_SP_MASK) && DCDC_REG4_ENABLE_SP_MASK
263typedef struct _dcdc_setpoint_config
264{
265 uint32_t enableDCDCMap;
267 uint32_t enableDigLogicMap;
269 uint32_t lowpowerMap;
271 uint32_t standbyMap;
273 uint32_t standbyLowpowerMap;
276 uint8_t *buckVDD1P8TargetVoltage;
278 uint8_t *buckVDD1P0TargetVoltage;
285
286#endif /* DCDC_REG4_ENABLE_SP_MASK */
287
288#if defined(__cplusplus)
289extern "C" {
290#endif
291
292/*******************************************************************************
293 * API
294 ******************************************************************************/
300#if defined(FSL_FEATURE_DCDC_HAS_CTRL_REG) && FSL_FEATURE_DCDC_HAS_CTRL_REG
308#else
314void DCDC_Init(DCDC_Type *base);
315#endif /* FSL_FEATURE_DCDC_HAS_CTRL_REG */
316
322void DCDC_Deinit(DCDC_Type *base);
323
324#if defined(FSL_FEATURE_DCDC_HAS_CTRL_REG) && FSL_FEATURE_DCDC_HAS_CTRL_REG
339#endif /* FSL_FEATURE_DCDC_HAS_CTRL_REGp */
340
341/* @} */
342
354uint32_t DCDC_GetstatusFlags(DCDC_Type *base);
355
356/* @} */
357
363#if defined(FSL_FEATURE_DCDC_HAS_CTRL_REG) && FSL_FEATURE_DCDC_HAS_CTRL_REG
370void DCDC_EnterLowPowerMode(DCDC_Type *base, dcdc_low_power_mode_t mode);
371#endif /* FSL_FEATURE_DCDC_HAS_CTRL_REG */
372
381static inline void DCDC_EnableOutputRangeComparator(DCDC_Type *base, bool enable)
382{
383 if (enable)
384 {
385 base->REG0 &= ~DCDC_REG0_PWD_CMP_OFFSET_MASK;
386 }
387 else
388 {
389 base->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK;
390 }
391}
392
399void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource);
400
420
428
444
452
459void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable);
460
467static inline void DCDC_SetBandgapVoltageTrimValue(DCDC_Type *base, uint32_t trimValue)
468{
469 base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK;
470 base->REG1 |= DCDC_REG1_VBG_TRIM(trimValue);
471}
472
490
498
506
513static inline void DCDC_SetLPComparatorBiasValue(DCDC_Type *base, dcdc_comparator_current_bias_t biasVaule)
514{
515 base->REG1 &= ~DCDC_REG1_LP_CMP_ISRC_SEL_MASK;
516 base->REG1 |= DCDC_REG1_LP_CMP_ISRC_SEL(biasVaule);
517}
518
519#if (defined(FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT) && (FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT == 2))
525static inline void DCDC_LockVdd1p0TargetVoltage(DCDC_Type *base)
526{
527 base->REG3 |= DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
528}
529
535static inline void DCDC_LockVdd1p8TargetVoltage(DCDC_Type *base)
536{
537 base->REG3 |= DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK;
538}
539
555void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby, dcdc_voltage_output_sel_t sel);
556
569void DCDC_AdjustRunTargetVoltage(DCDC_Type *base, uint32_t VDDRun, dcdc_voltage_output_sel_t sel);
570
583void DCDC_AdjustLowPowerTargetVoltage(DCDC_Type *base, uint32_t VDDStandby, dcdc_voltage_output_sel_t sel);
584#else
585
591static inline void DCDC_LockTargetVoltage(DCDC_Type *base)
592{
593 base->REG3 |= DCDC_REG3_DISABLE_STEP_MASK;
594}
595
610void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby);
611
623void DCDC_AdjustRunTargetVoltage(DCDC_Type *base, uint32_t VDDRun);
624
636void DCDC_AdjustLowPowerTargetVoltage(DCDC_Type *base, uint32_t VDDStandby);
637#endif /* FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT */
638
646
654static inline void DCDC_EnableImproveTransition(DCDC_Type *base, bool enable)
655{
656 if (enable)
657 {
658 base->REG2 |= DCDC_REG2_DCM_SET_CTRL_MASK;
659 }
660 else
661 {
662 base->REG2 &= ~DCDC_REG2_DCM_SET_CTRL_MASK;
663 }
664}
665
666/* @} */
667
668#if defined(DCDC_REG4_ENABLE_SP_MASK) && DCDC_REG4_ENABLE_SP_MASK
683
691static inline void DCDC_SetPointDeinit(DCDC_Type *base, uint32_t setpointMap)
692{
693 base->REG4 &= ~setpointMap;
694}
695
696/* @} */
697#endif /* DCDC_REG4_ENABLE_SP_MASK */
698
714void DCDC_BootIntoDCM(DCDC_Type *base);
715
725void DCDC_BootIntoCCM(DCDC_Type *base);
726
727/* @} */
728
729#if defined(__cplusplus)
730}
731#endif
732
733/* @} */
734
735#endif /* __FSL_DCDC_H__ */
#define DCDC_REG1_LP_CMP_ISRC_SEL(x)
Definition: MIMXRT1052.h:12222
#define DCDC_REG1_VBG_TRIM(x)
Definition: MIMXRT1052.h:12244
void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config)
Configures for the min power.
Definition: fsl_dcdc.c:404
void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config)
Gets the default setting for low power configuration.
Definition: fsl_dcdc.c:280
void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config)
Configures the DCDC low power.
Definition: fsl_dcdc.c:295
enum _dcdc_trim_input_mode dcdc_trim_input_mode_t
DCDC trim input mode, including sample trim input and hold trim input.
enum _dcdc_voltage_output_sel dcdc_voltage_output_sel_t
Voltage output option.
void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config)
Configures the DCDC internal regulator.
Definition: fsl_dcdc.c:424
struct _dcdc_min_power_config dcdc_min_power_config_t
Configuration for min power setting.
void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config)
Gets the default setting for loop control configuration.
Definition: fsl_dcdc.c:328
void DCDC_GetDefaultConfig(dcdc_config_t *config)
Gets the default setting for DCDC, such as control mode, etc.
Definition: fsl_dcdc.c:139
_dcdc_control_mode
DCDC control mode, including setpoint control mode and static control mode.
Definition: fsl_dcdc.h:90
struct _dcdc_internal_regulator_config dcdc_internal_regulator_config_t
Configuration for DCDC internal regulator.
void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource)
Configures the DCDC clock source.
Definition: fsl_dcdc.c:242
void DCDC_Init(DCDC_Type *base, const dcdc_config_t *config)
Initializes the basic resource of DCDC module, such as control mode, etc.
Definition: fsl_dcdc.c:88
_dcdc_clock_source
Oscillator clock option.
Definition: fsl_dcdc.h:320
void DCDC_SetPointInit(DCDC_Type *base, const dcdc_setpoint_config_t *config)
Initializes DCDC module when the control mode selected as setpoint mode.
Definition: fsl_dcdc.c:444
_dcdc_peak_current_threshold
The threshold if peak current detection.
Definition: fsl_dcdc.h:305
enum _dcdc_clock_source dcdc_clock_source_t
Oscillator clock option.
void DCDC_Deinit(DCDC_Type *base)
De-initializes the DCDC module.
Definition: fsl_dcdc.c:116
struct _dcdc_config dcdc_config_t
Configuration for DCDC.
void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config)
Configures the DCDC detection.
Definition: fsl_dcdc.c:193
_dcdc_comparator_current_bias
The current bias of low power comparator.
Definition: fsl_dcdc.h:294
_dcdc_setpoint_map
System setpoints enumeration.
Definition: fsl_dcdc.h:67
enum _dcdc_control_mode dcdc_control_mode_t
DCDC control mode, including setpoint control mode and static control mode.
void DCDC_BootIntoDCM(DCDC_Type *base)
Boots DCDC into DCM(discontinous conduction mode).
Definition: fsl_dcdc.c:495
void DCDC_BootIntoCCM(DCDC_Type *base)
Boots DCDC into CCM(continous conduction mode).
Definition: fsl_dcdc.c:514
void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config)
Gets the default setting for detection configuration.
Definition: fsl_dcdc.c:170
enum _dcdc_comparator_current_bias dcdc_comparator_current_bias_t
The current bias of low power comparator.
_dcdc_trim_input_mode
DCDC trim input mode, including sample trim input and hold trim input.
Definition: fsl_dcdc.h:99
struct _dcdc_loop_control_config dcdc_loop_control_config_t
Configuration for the loop control.
struct _dcdc_setpoint_config dcdc_setpoint_config_t
DCDC configuration in set point mode.
struct _dcdc_detection_config dcdc_detection_config_t
Configuration for DCDC detection.
enum _dcdc_peak_current_threshold dcdc_peak_current_threshold_t
The threshold if peak current detection.
void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config)
Configures the DCDC loop control.
Definition: fsl_dcdc.c:351
_dcdc_voltage_output_sel
Voltage output option.
Definition: fsl_dcdc.h:330
struct _dcdc_low_power_config dcdc_low_power_config_t
Configuration for DCDC low power.
@ kDCDC_StaticControl
Definition: fsl_dcdc.h:91
@ kDCDC_SetPointControl
Definition: fsl_dcdc.h:92
@ kDCDC_SetPoint11
Definition: fsl_dcdc.h:79
@ kDCDC_SetPoint2
Definition: fsl_dcdc.h:70
@ kDCDC_SetPoint14
Definition: fsl_dcdc.h:82
@ kDCDC_SetPoint10
Definition: fsl_dcdc.h:78
@ kDCDC_SetPoint3
Definition: fsl_dcdc.h:71
@ kDCDC_SetPoint4
Definition: fsl_dcdc.h:72
@ kDCDC_SetPoint7
Definition: fsl_dcdc.h:75
@ kDCDC_SetPoint6
Definition: fsl_dcdc.h:74
@ kDCDC_SetPoint15
Definition: fsl_dcdc.h:83
@ kDCDC_SetPoint1
Definition: fsl_dcdc.h:69
@ kDCDC_SetPoint9
Definition: fsl_dcdc.h:77
@ kDCDC_SetPoint12
Definition: fsl_dcdc.h:80
@ kDCDC_SetPoint8
Definition: fsl_dcdc.h:76
@ kDCDC_SetPoint0
Definition: fsl_dcdc.h:68
@ kDCDC_SetPoint5
Definition: fsl_dcdc.h:73
@ kDCDC_SetPoint13
Definition: fsl_dcdc.h:81
@ kDCDC_SampleTrimInput
Definition: fsl_dcdc.h:100
@ kDCDC_HoldTrimInput
Definition: fsl_dcdc.h:101
@ kDCDC_VoltageOutput1P8
Definition: fsl_dcdc.h:331
@ kDCDC_VoltageOutput1P0
Definition: fsl_dcdc.h:332
enum _dcdc_count_charging_time_threshold dcdc_count_charging_time_threshold_t
The threshold of the counting number of charging times.
enum _dcdc_count_charging_time_period dcdc_count_charging_time_period_t
The period of counting the charging times in power save mode.
void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable)
Reset current alert signal. Alert signal is generate by peak current detection.
Definition: fsl_dcdc.c:423
_dcdc_count_charging_time_period
The period of counting the charging times in power save mode.
Definition: fsl_dcdc.h:72
uint32_t DCDC_GetstatusFlags(DCDC_Type *base)
Get DCDC status flags.
Definition: fsl_dcdc.c:404
dcdc_count_charging_time_period_t countChargingTimePeriod
Definition: fsl_dcdc.h:234
void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby)
Adjust the target voltage of VDD_SOC in run mode and low power mode.
Definition: fsl_dcdc.c:718
bool enableUseHalfFreqForContinuous
Definition: fsl_dcdc.h:351
void DCDC_AdjustLowPowerTargetVoltage(DCDC_Type *base, uint32_t VDDStandby)
Adjust the target voltage of VDD_SOC in low power mode.
Definition: fsl_dcdc.c:780
dcdc_peak_current_threshold_t PeakCurrentThreshold
Definition: fsl_dcdc.h:367
bool enableRCThresholdDetection
Definition: fsl_dcdc.h:384
bool powerDownZeroCrossDetection
Definition: fsl_dcdc.h:365
void DCDC_AdjustRunTargetVoltage(DCDC_Type *base, uint32_t VDDRun)
Adjust the target voltage of VDD_SOC in run mode.
Definition: fsl_dcdc.c:749
bool powerDownOverCurrentDetection
Definition: fsl_dcdc.h:363
bool enableCommonThresholdDetection
Definition: fsl_dcdc.h:377
bool powerDownPeakCurrentDetection
Definition: fsl_dcdc.h:364
bool enableLoadResistor
Definition: fsl_dcdc.h:245
uint32_t feedbackPoint
Definition: fsl_dcdc.h:404
dcdc_count_charging_time_threshold_t countChargingTimeThreshold
Definition: fsl_dcdc.h:236
bool enableOverloadDetection
Definition: fsl_dcdc.h:228
dcdc_over_current_threshold_t OverCurrentThreshold
Definition: fsl_dcdc.h:192
_dcdc_count_charging_time_threshold
The threshold of the counting number of charging times.
Definition: fsl_dcdc.h:81
bool enableAdjustHystereticValue
Definition: fsl_dcdc.h:412
bool enableXtalokDetection
Definition: fsl_dcdc.h:359
bool enableCommonHysteresis
Definition: fsl_dcdc.h:375
_dcdc_over_current_threshold
The threshold of over current detection.
Definition: fsl_dcdc.h:48
uint32_t enableRCScaleCircuit
Definition: fsl_dcdc.h:385
bool enableInvertHysteresisSign
Definition: fsl_dcdc.h:383
bool powerDownLowVlotageDetection
Definition: fsl_dcdc.h:187
_dcdc_status_flags_t
DCDC status flags.
Definition: fsl_dcdc.h:29
enum _dcdc_peak_current_threshold dcdc_peak_current_threshold_t
The threshold if peak current detection.
uint32_t complementFeedForwardStep
Definition: fsl_dcdc.h:387
bool powerDownOverVoltageDetection
Definition: fsl_dcdc.h:185
enum _dcdc_over_current_threshold dcdc_over_current_threshold_t
The threshold of over current detection.
@ kDCDC_CountChargingTimePeriod16Cycle
Definition: fsl_dcdc.h:74
@ kDCDC_CountChargingTimePeriod8Cycle
Definition: fsl_dcdc.h:73
@ kDCDC_ClockAutoSwitch
Definition: fsl_dcdc.h:321
@ kDCDC_ClockInternalOsc
Definition: fsl_dcdc.h:322
@ kDCDC_ClockExternalOsc
Definition: fsl_dcdc.h:323
@ kDCDC_PeakCurrentThresholdAlt1
Definition: fsl_dcdc.h:61
@ kDCDC_PeakCurrentThresholdAlt5
Definition: fsl_dcdc.h:65
@ kDCDC_PeakCurrentThresholdAlt2
Definition: fsl_dcdc.h:62
@ kDCDC_PeakCurrentThresholdAlt4
Definition: fsl_dcdc.h:64
@ kDCDC_PeakCurrentThresholdAlt0
Definition: fsl_dcdc.h:60
@ kDCDC_PeakCurrentThresholdAlt3
Definition: fsl_dcdc.h:63
@ kDCDC_ComparatorCurrentBias400nA
Definition: fsl_dcdc.h:298
@ kDCDC_ComparatorCurrentBias50nA
Definition: fsl_dcdc.h:295
@ kDCDC_ComparatorCurrentBias200nA
Definition: fsl_dcdc.h:297
@ kDCDC_ComparatorCurrentBias100nA
Definition: fsl_dcdc.h:296
@ kDCDC_CountChargingTimeThreshold16
Definition: fsl_dcdc.h:84
@ kDCDC_CountChargingTimeThreshold64
Definition: fsl_dcdc.h:83
@ kDCDC_CountChargingTimeThreshold8
Definition: fsl_dcdc.h:85
@ kDCDC_CountChargingTimeThreshold32
Definition: fsl_dcdc.h:82
@ kDCDC_OverCurrentThresholdAlt0
Definition: fsl_dcdc.h:49
@ kDCDC_OverCurrentThresholdAlt1
Definition: fsl_dcdc.h:50
@ kDCDC_OverCurrentThresholdAlt3
Definition: fsl_dcdc.h:52
@ kDCDC_OverCurrentThresholdAlt2
Definition: fsl_dcdc.h:51
@ kDCDC_LockedOKStatus
Definition: fsl_dcdc.h:30
Definition: MIMXRT1052.h:12013
Configuration for DCDC.
Definition: fsl_dcdc.h:339
bool enableDcdcTimeout
Definition: fsl_dcdc.h:342
dcdc_control_mode_t controlMode
Definition: fsl_dcdc.h:340
bool enableSwitchingConverterOutput
Definition: fsl_dcdc.h:343
dcdc_trim_input_mode_t trimInputMode
Definition: fsl_dcdc.h:341
Configuration for DCDC detection.
Definition: fsl_dcdc.h:358
bool powerDownOverVoltageVdd1P0Detection
Definition: fsl_dcdc.h:361
bool powerDownOverVoltageVdd1P8Detection
Definition: fsl_dcdc.h:360
Configuration for DCDC internal regulator.
Definition: fsl_dcdc.h:403
Configuration for the loop control.
Definition: fsl_dcdc.h:374
bool enableDifferentialThresholdDetection
Definition: fsl_dcdc.h:381
bool enableDifferentialHysteresis
Definition: fsl_dcdc.h:378
Configuration for DCDC low power.
Definition: fsl_dcdc.h:411
Configuration for min power setting.
Definition: fsl_dcdc.h:350
DCDC configuration in set point mode.
Definition: fsl_dcdc.h:419
uint32_t standbyLowpowerMap
Definition: fsl_dcdc.h:428
uint32_t standbyMap
Definition: fsl_dcdc.h:426
uint32_t enableDigLogicMap
Definition: fsl_dcdc.h:422
dcdc_buck_mode_1P0_target_vol_t * buckVDD1P0TargetVoltage
Definition: fsl_dcdc.h:434
uint32_t lowpowerMap
Definition: fsl_dcdc.h:424
dcdc_buck_mode_1P8_target_vol_t * buckVDD1P8TargetVoltage
Definition: fsl_dcdc.h:430
dcdc_standby_mode_1P0_target_vol_t * standbyVDD1P0TargetVoltage
Definition: fsl_dcdc.h:442
dcdc_standby_mode_1P8_target_vol_t * standbyVDD1P8TargetVoltage
Definition: fsl_dcdc.h:438
uint32_t enableDCDCMap
Definition: fsl_dcdc.h:420
Definition: deflate.c:114