43#ifndef _RTEMS_SCORE_CPU_H
44#define _RTEMS_SCORE_CPU_H
66#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
74#define CPU_ISR_PASSES_FRAME_POINTER FALSE
83#if ( SPARC_HAS_FPU == 1 )
84#define CPU_HARDWARE_FP TRUE
86#define CPU_HARDWARE_FP FALSE
88#define CPU_SOFTWARE_FP FALSE
97#define CPU_ALL_TASKS_ARE_FP FALSE
107#define CPU_IDLE_TASK_IS_FP FALSE
124#define CPU_USE_DEFERRED_FP_SWITCH TRUE
126#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
138#define CPU_STACK_GROWS_UP FALSE
141#define CPU_CACHE_LINE_BYTES 32
157#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( 16 )
167#define CPU_MODES_INTERRUPT_MASK 0x0000000F
169#define CPU_MAXIMUM_PROCESSORS 32
197 void *structure_return_address;
213#define CPU_STACK_FRAME_L0_OFFSET 0x00
214#define CPU_STACK_FRAME_L1_OFFSET 0x08
215#define CPU_STACK_FRAME_L2_OFFSET 0x10
216#define CPU_STACK_FRAME_L3_OFFSET 0x18
217#define CPU_STACK_FRAME_L4_OFFSET 0x20
218#define CPU_STACK_FRAME_L5_OFFSET 0x28
219#define CPU_STACK_FRAME_L6_OFFSET 0x30
220#define CPU_STACK_FRAME_L7_OFFSET 0x38
221#define CPU_STACK_FRAME_I0_OFFSET 0x40
222#define CPU_STACK_FRAME_I1_OFFSET 0x48
223#define CPU_STACK_FRAME_I2_OFFSET 0x50
224#define CPU_STACK_FRAME_I3_OFFSET 0x58
225#define CPU_STACK_FRAME_I4_OFFSET 0x60
226#define CPU_STACK_FRAME_I5_OFFSET 0x68
227#define CPU_STACK_FRAME_I6_FP_OFFSET 0x70
228#define CPU_STACK_FRAME_I7_OFFSET 0x78
229#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x80
230#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x88
231#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x90
232#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x98
233#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0xA0
234#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0xA8
235#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0xB0
236#define CPU_STACK_FRAME_PAD0_OFFSET 0xB8
238#define SPARC64_MINIMUM_STACK_FRAME_SIZE 0xC0
296 uint32_t isr_dispatch_disable;
300#define _CPU_Context_Get_SP( _context ) \
309#define G1_OFFSET 0x00
310#define G2_OFFSET 0x08
311#define G3_OFFSET 0x10
312#define G4_OFFSET 0x18
313#define G5_OFFSET 0x20
314#define G6_OFFSET 0x28
315#define G7_OFFSET 0x30
317#define L0_OFFSET 0x38
318#define L1_OFFSET 0x40
319#define L2_OFFSET 0x48
320#define L3_OFFSET 0x50
321#define L4_OFFSET 0x58
322#define L5_OFFSET 0x60
323#define L6_OFFSET 0x68
324#define L7_OFFSET 0x70
326#define I0_OFFSET 0x78
327#define I1_OFFSET 0x80
328#define I2_OFFSET 0x88
329#define I3_OFFSET 0x90
330#define I4_OFFSET 0x98
331#define I5_OFFSET 0xA0
332#define I6_FP_OFFSET 0xA8
333#define I7_OFFSET 0xB0
335#define O0_OFFSET 0xB8
336#define O1_OFFSET 0xC0
337#define O2_OFFSET 0xC8
338#define O3_OFFSET 0xD0
339#define O4_OFFSET 0xD8
340#define O5_OFFSET 0xE0
341#define O6_SP_OFFSET 0xE8
342#define O7_OFFSET 0xF0
344#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0xF8
345#define ISR_PAD_OFFSET 0xFC
395#define FO_OFFSET 0x00
396#define F2_OFFSET 0x08
397#define F4_OFFSET 0x10
398#define F6_OFFSET 0x18
399#define F8_OFFSET 0x20
400#define F1O_OFFSET 0x28
401#define F12_OFFSET 0x30
402#define F14_OFFSET 0x38
403#define F16_OFFSET 0x40
404#define F18_OFFSET 0x48
405#define F2O_OFFSET 0x50
406#define F22_OFFSET 0x58
407#define F24_OFFSET 0x60
408#define F26_OFFSET 0x68
409#define F28_OFFSET 0x70
410#define F3O_OFFSET 0x78
411#define F32_OFFSET 0x80
412#define F34_OFFSET 0x88
413#define F36_OFFSET 0x90
414#define F38_OFFSET 0x98
415#define F4O_OFFSET 0xA0
416#define F42_OFFSET 0xA8
417#define F44_OFFSET 0xB0
418#define F46_OFFSET 0xB8
419#define F48_OFFSET 0xC0
420#define F5O_OFFSET 0xC8
421#define F52_OFFSET 0xD0
422#define F54_OFFSET 0xD8
423#define F56_OFFSET 0xE0
424#define F58_OFFSET 0xE8
425#define F6O_OFFSET 0xF0
426#define F62_OFFSET 0xF8
427#define FSR_OFFSET 0x100
429#define CONTEXT_CONTROL_FP_SIZE 0x108
475#define ISF_TSTATE_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x00
476#define ISF_TPC_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x08
477#define ISF_TNPC_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x10
478#define ISF_PIL_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x18
479#define ISF_Y_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x20
480#define ISF_G1_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x28
481#define ISF_G2_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x30
482#define ISF_G3_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x38
483#define ISF_G4_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x40
484#define ISF_G5_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x48
485#define ISF_G6_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x50
486#define ISF_G7_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x58
487#define ISF_O0_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x60
488#define ISF_O1_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x68
489#define ISF_O2_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x70
490#define ISF_O3_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x78
491#define ISF_O4_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x80
492#define ISF_O5_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x88
493#define ISF_O6_SP_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x90
494#define ISF_O7_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x98
495#define ISF_TVEC_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0xA0
497#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE SPARC64_MINIMUM_STACK_FRAME_SIZE + 0xA8
514extern volatile uint32_t _CPU_ISR_Dispatch_disable;
537 uint32_t rdpr_tstate_g4;
538 uint32_t sethi_of_hh_handler_to_g2;
539 uint32_t or_g2_hm_handler_to_g2;
540 uint32_t sllx_g2_by_32_to_g2;
541 uint32_t sethi_of_handler_to_g3;
542 uint32_t or_g3_g2_to_g3;
543 uint32_t jmp_to_low_of_handler_plus_g3;
544 uint32_t mov_vector_g2;
563#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
573#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
601#define CPU_INTERRUPT_NUMBER_OF_VECTORS 512
602#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 1023
604#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x200
605#define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap)
606#define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 512 )
608#define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 512)
615#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
626#define CPU_STACK_MINIMUM_SIZE (1024*8)
628#define CPU_SIZEOF_POINTER 8
640#define CPU_ALIGNMENT 8
654#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
663#define CPU_STACK_ALIGNMENT 16
665#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
678 #define _CPU_ISR_Disable( _level ) \
679 (_level) = sparc_disable_interrupts()
687#define _CPU_ISR_Enable( _level ) \
688 sparc_enable_interrupts( _level )
697#define _CPU_ISR_Flash( _level ) \
698 sparc_flash_interrupts( _level )
700static inline bool _CPU_ISR_Is_enabled( uint32_t level )
702 return ( level & SPARC_PSTATE_IE_MASK ) != 0;
711#define _CPU_ISR_Set_level( _newlevel ) \
712 sparc_enable_interrupts( _newlevel)
734void _CPU_Context_Initialize(
758#define _CPU_Context_Initialization_at_thread_begin() \
760 __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \
772#define _CPU_Context_Restart_self( _the_context ) \
773 _CPU_Context_restore( (_the_context) );
784#define _CPU_Context_Initialize_fp( _destination ) \
786 *(*(_destination)) = _CPU_Null_fp_context; \
791#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
800#if ( SPARC_HAS_BITSCAN == 0 )
801#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
803#error "scan instruction not currently supported by RTEMS!!"
815#if ( SPARC_HAS_BITSCAN == 1 )
816#error "scan instruction not currently supported by RTEMS!!"
831typedef void ( *CPU_ISR_raw_handler )( void );
835 CPU_ISR_raw_handler new_handler,
836 CPU_ISR_raw_handler *old_handler
839typedef void ( *CPU_ISR_handler )( uint32_t );
843 CPU_ISR_handler new_handler,
844 CPU_ISR_handler *old_handler
913static inline uint32_t CPU_swap_u32(
917 uint32_t byte1, byte2, byte3, byte4, swapped;
919 byte4 = (value >> 24) & 0xff;
920 byte3 = (value >> 16) & 0xff;
921 byte2 = (value >> 8) & 0xff;
922 byte1 = value & 0xff;
924 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
928#define CPU_swap_u16( value ) \
929 (((value&0xff) << 8) | ((value >> 8)&0xff))
931typedef uint32_t CPU_Counter_ticks;
This header file provides basic definitions used by the API and the implementation.
void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.c:100
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
Information Required to Build RTEMS for a Particular Member of the SPARC Family.
const CPU_Trap_table_entry _CPU_Trap_slot_template
Definition: sparc-isr-install.c:54
#define _CPU_Context_restore_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:901
#define _CPU_Context_save_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:895
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
SPARC basic context.
Definition: cpu.h:213
Thread register context.
Definition: cpu.h:173