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RTEMS 6.1-rc7
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Macros | |
#define | IOMUXC_SNVS_GPR_GPR_COUNT (32U) |
#define | IOMUXC_SNVS_GPR_GPR_COUNT (32U) |
GPR3 - GPR3 General Purpose Register | |
#define | IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U) |
#define | IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U) |
#define | IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK) |
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U) |
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U) |
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK) |
#define | IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU) |
#define | IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U) |
#define | IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK) |
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U) |
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U) |
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U) |
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U) |
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK) |
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK (0x40000U) |
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U) |
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U) |
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U) |
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK) |
GPR - GPR0 General Purpose Register | |
#define | IOMUXC_SNVS_GPR_GPR_GPR_MASK (0xFFFFFFFFU) |
#define | IOMUXC_SNVS_GPR_GPR_GPR_SHIFT (0U) |
#define | IOMUXC_SNVS_GPR_GPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR_GPR_MASK) |
GPR32 - GPR32 General Purpose Register | |
#define | IOMUXC_SNVS_GPR_GPR32_GPR_MASK (0xFFFEU) |
#define | IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT (1U) |
#define | IOMUXC_SNVS_GPR_GPR32_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_GPR_MASK) |
#define | IOMUXC_SNVS_GPR_GPR32_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT (16U) |
#define | IOMUXC_SNVS_GPR_GPR32_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK) |
GPR33 - GPR33 General Purpose Register | |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK (0x2U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT (1U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK) |
#define | IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK (0x4U) |
#define | IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT (2U) |
#define | IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK (0x10000U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT (16U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK (0x20000U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT (17U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK (0x40000U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT (18U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK (0x80000U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT (19U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK) |
#define | IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK (0x100000U) |
#define | IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT (20U) |
#define | IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK) |
GPR34 - GPR34 General Purpose Register | |
#define | IOMUXC_SNVS_GPR_GPR34_LOCK_MASK (0x1U) |
#define | IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT (0U) |
#define | IOMUXC_SNVS_GPR_GPR34_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_LOCK_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK (0x2U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT (1U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK (0xCU) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT (2U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK (0x80U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT (7U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK (0xFF00U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT (8U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK (0x30000U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT (16U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK (0xC0000U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT (18U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK (0x800000U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT (23U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK (0xF000000U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT (24U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK) |
GPR35 - GPR35 General Purpose Register | |
#define | IOMUXC_SNVS_GPR_GPR35_LOCK_MASK (0x1U) |
#define | IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT (0U) |
#define | IOMUXC_SNVS_GPR_GPR35_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_LOCK_MASK) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK (0x8U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT (3U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK (0xFF0U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT (4U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK (0x8000U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT (15U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK (0xFFF0000U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT (16U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK (0x30000000U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT (28U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK (0xC0000000U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT (30U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK) |
GPR36 - GPR36 General Purpose Register | |
#define | IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK (0x800000U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT (23U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK (0x4000000U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT (26U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK (0x8000000U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT (27U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK (0x10000000U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT (28U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK (0x20000000U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT (29U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK (0x40000000U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT (30U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK (0x80000000U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT (31U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK) |
GPR37 - GPR37 General Purpose Register | |
#define | IOMUXC_SNVS_GPR_GPR37_LOCK_MASK (0x1U) |
#define | IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT (0U) |
#define | IOMUXC_SNVS_GPR_GPR37_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_LOCK_MASK) |
#define | IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK (0x7FEU) |
#define | IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT (1U) |
#define | IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK) |
#define | IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK (0x1FF800U) |
#define | IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT (11U) |
#define | IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK) |
GPR - GPR0 General Purpose Register | |
#define | IOMUXC_SNVS_GPR_GPR_GPR_MASK (0xFFFFFFFFU) |
#define | IOMUXC_SNVS_GPR_GPR_GPR_SHIFT (0U) |
#define | IOMUXC_SNVS_GPR_GPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR_GPR_MASK) |
GPR32 - GPR32 General Purpose Register | |
#define | IOMUXC_SNVS_GPR_GPR32_GPR_MASK (0xFFFEU) |
#define | IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT (1U) |
#define | IOMUXC_SNVS_GPR_GPR32_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_GPR_MASK) |
#define | IOMUXC_SNVS_GPR_GPR32_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT (16U) |
#define | IOMUXC_SNVS_GPR_GPR32_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK) |
GPR33 - GPR33 General Purpose Register | |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK (0x2U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT (1U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK) |
#define | IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK (0x4U) |
#define | IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT (2U) |
#define | IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK (0x10000U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT (16U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK (0x20000U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT (17U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK (0x40000U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT (18U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK (0x80000U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT (19U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK) |
#define | IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK (0x100000U) |
#define | IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT (20U) |
#define | IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK) |
GPR34 - GPR34 General Purpose Register | |
#define | IOMUXC_SNVS_GPR_GPR34_LOCK_MASK (0x1U) |
#define | IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT (0U) |
#define | IOMUXC_SNVS_GPR_GPR34_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_LOCK_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK (0x2U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT (1U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK (0xCU) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT (2U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK (0x80U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT (7U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK (0xFF00U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT (8U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK (0x30000U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT (16U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK (0xC0000U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT (18U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK (0x800000U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT (23U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK (0xF000000U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT (24U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK) |
GPR35 - GPR35 General Purpose Register | |
#define | IOMUXC_SNVS_GPR_GPR35_LOCK_MASK (0x1U) |
#define | IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT (0U) |
#define | IOMUXC_SNVS_GPR_GPR35_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_LOCK_MASK) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK (0x8U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT (3U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK (0xFF0U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT (4U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK (0x8000U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT (15U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK (0xFFF0000U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT (16U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK (0x30000000U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT (28U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK (0xC0000000U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT (30U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK) |
GPR36 - GPR36 General Purpose Register | |
#define | IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK (0x800000U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT (23U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK (0x4000000U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT (26U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK (0x8000000U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT (27U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK (0x10000000U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT (28U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK (0x20000000U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT (29U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK (0x40000000U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT (30U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK (0x80000000U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT (31U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK) |
GPR37 - GPR37 General Purpose Register | |
#define | IOMUXC_SNVS_GPR_GPR37_LOCK_MASK (0x1U) |
#define | IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT (0U) |
#define | IOMUXC_SNVS_GPR_GPR37_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_LOCK_MASK) |
#define | IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK (0x7FEU) |
#define | IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT (1U) |
#define | IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK) |
#define | IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK (0x1FF800U) |
#define | IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT (11U) |
#define | IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK) |
#define IOMUXC_SNVS_GPR_GPR32_GPR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_GPR_MASK) |
GPR - General purpose bits
#define IOMUXC_SNVS_GPR_GPR32_GPR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_GPR_MASK) |
GPR - General purpose bits
#define IOMUXC_SNVS_GPR_GPR32_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK) |
LOCK - Lock the write to bit 15:0
#define IOMUXC_SNVS_GPR_GPR32_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK) |
LOCK - Lock the write to bit 15:0
#define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK) |
DCDC_IN_LOW_VOL - DCDC_IN low voltage detect 0b1..Voltage on DCDC_IN is lower than 2.6V 0b0..Voltage on DCDC_IN is higher than 2.6V
#define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK) |
DCDC_IN_LOW_VOL - DCDC_IN low voltage detect 0b1..Voltage on DCDC_IN is lower than 2.6V 0b0..Voltage on DCDC_IN is higher than 2.6V
#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK) |
DCDC_OVER_CUR - DCDC output over current alert 0b1..Overcurrent on DCDC output 0b0..No Overcurrent on DCDC output
#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK) |
DCDC_OVER_CUR - DCDC output over current alert 0b1..Overcurrent on DCDC output 0b0..No Overcurrent on DCDC output
#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK) |
DCDC_OVER_VOL - DCDC output over voltage alert 0b1..Overvoltage on DCDC VDDLP0 or VDDLP8 output 0b0..No Overvoltage on DCDC VDDLP0 or VDDLP8 output
#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK) |
DCDC_OVER_VOL - DCDC output over voltage alert 0b1..Overvoltage on DCDC VDDLP0 or VDDLP8 output 0b0..No Overvoltage on DCDC VDDLP0 or VDDLP8 output
#define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK) |
DCDC_STATUS_CAPT_CLR - DCDC captured status clear 0b0..No change 0b1..Clear the 3 bits of DCDC captured status: DCDC_OVER_VOL, DCDC_OVER_CUR, and DCDC_IN_LOW_VOL
#define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK) |
DCDC_STATUS_CAPT_CLR - DCDC captured status clear 0b0..No change 0b1..Clear the 3 bits of DCDC captured status: DCDC_OVER_VOL, DCDC_OVER_CUR, and DCDC_IN_LOW_VOL
#define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK) |
DCDC_STS_DC_OK - DCDC status OK 0b0..DCDC is settling 0b1..DCDC already settled
#define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK) |
DCDC_STS_DC_OK - DCDC status OK 0b0..DCDC is settling 0b1..DCDC already settled
#define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK) |
SNVS_BYPASS_EN - SNVS LDO_SNVS_ANA bypass enable 0b1..Enable bypass 0b0..Disable bypass
#define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK) |
SNVS_BYPASS_EN - SNVS LDO_SNVS_ANA bypass enable 0b1..Enable bypass 0b0..Disable bypass
#define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK) |
SNVS_XTAL_CLK_OK - 32K OSC ok flag 0b1..32K oscillator is stable into normal operation 0b0..32K oscillator is NOT stable into normal operation
#define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK) |
SNVS_XTAL_CLK_OK - 32K OSC ok flag 0b1..32K oscillator is stable into normal operation 0b0..32K oscillator is NOT stable into normal operation
#define IOMUXC_SNVS_GPR_GPR34_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b0..Write access is not blocked 0b1..Write access is blocked
#define IOMUXC_SNVS_GPR_GPR34_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b0..Write access is not blocked 0b1..Write access is blocked
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK) |
SNVS_CAP_TRIM_SEL - SNVS OSC load capacitor trim select 0b0..The trimming codes are selected from eFuse 0b1..The trimming codes are used from SNVS_OSC_CAP_TRIM (osc32k's load capacitor)
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK) |
SNVS_CAP_TRIM_SEL - SNVS OSC load capacitor trim select 0b0..The trimming codes are selected from eFuse 0b1..The trimming codes are used from SNVS_OSC_CAP_TRIM (osc32k's load capacitor)
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK) |
SNVS_CLK_DET_OFFSET_HIGH - SNVS clock detect offset of high boundary frequency 0b00..No change (Default) 0b01..Add +5 to the Trim 0b10..Add +10 to the trim 0b11..Add -5 to the Trim
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK) |
SNVS_CLK_DET_OFFSET_HIGH - SNVS clock detect offset of high boundary frequency 0b00..No change (Default) 0b01..Add +5 to the Trim 0b10..Add +10 to the trim 0b11..Add -5 to the Trim
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK) |
SNVS_CLK_DET_OFFSET_LOW - SNVS clock detect offset of low boundary frequency 0b00..No change (Default) 0b01..Add +5 to the Trim 0b10..Add +10 to the trim 0b11..Add -5 to the Trim
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK) |
SNVS_CLK_DET_OFFSET_LOW - SNVS clock detect offset of low boundary frequency 0b00..No change (Default) 0b01..Add +5 to the Trim 0b10..Add +10 to the trim 0b11..Add -5 to the Trim
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK) |
SNVS_CLK_DET_TRIM - SNVS clock detect trim bits
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK) |
SNVS_CLK_DET_TRIM - SNVS clock detect trim bits
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK) |
SNVS_CLK_DET_TRIM_SEL - SNVS clock detect trim select 0b0..The trimming codes are selected from eFuse 0b1..The trimming codes of clock detector used to change the boundary frequencies are selected from SNVS_CLK_DET_TRIM
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK) |
SNVS_CLK_DET_TRIM_SEL - SNVS clock detect trim select 0b0..The trimming codes are selected from eFuse 0b1..The trimming codes of clock detector used to change the boundary frequencies are selected from SNVS_CLK_DET_TRIM
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK) |
SNVS_CORE_VOLT_DET_TRIM - SNVS core voltage detect trim
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK) |
SNVS_CORE_VOLT_DET_TRIM - SNVS core voltage detect trim
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK) |
SNVS_CORE_VOLT_DET_TRIM_SEL - SNVS core voltage detect trim select 0b0..The trimming codes are selected from eFuse 0b1..The trimming codes of core voltage detectors used to change the voltage falling trip point are selected from SNVS_CORE_VOLT_DET_TRIM
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK) |
SNVS_CORE_VOLT_DET_TRIM_SEL - SNVS core voltage detect trim select 0b0..The trimming codes are selected from eFuse 0b1..The trimming codes of core voltage detectors used to change the voltage falling trip point are selected from SNVS_CORE_VOLT_DET_TRIM
#define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK) |
SNVS_OSC_CAP_TRIM - SNVS OSC load capacitor trim
#define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK) |
SNVS_OSC_CAP_TRIM - SNVS OSC load capacitor trim
#define IOMUXC_SNVS_GPR_GPR35_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b0..Write access is not blocked 0b1..Write access is blocked
#define IOMUXC_SNVS_GPR_GPR35_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b0..Write access is not blocked 0b1..Write access is blocked
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK) |
SNVS_TEMP_DET_OFFSET_HIGH - SNVS temperature detect offset of high temperature boundary 0b00..No change (Default) 0b01..Add +5 to the Trim 0b10..Add +10 to the trim 0b11..Add -5 to the Trim
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK) |
SNVS_TEMP_DET_OFFSET_HIGH - SNVS temperature detect offset of high temperature boundary 0b00..No change (Default) 0b01..Add +5 to the Trim 0b10..Add +10 to the trim 0b11..Add -5 to the Trim
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK) |
SNVS_TEMP_DET_OFFSET_LOW - SNVS temperature detect offset of low temperature boundary 0b00..No change (Default) 0b01..Add +5 to the Trim 0b10..Add +10 to the trim 0b11..Add -5 to the Trim
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK) |
SNVS_TEMP_DET_OFFSET_LOW - SNVS temperature detect offset of low temperature boundary 0b00..No change (Default) 0b01..Add +5 to the Trim 0b10..Add +10 to the trim 0b11..Add -5 to the Trim
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK) |
SNVS_TEMP_DET_TRIM - SNVS temperature detect trim
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK) |
SNVS_TEMP_DET_TRIM - SNVS temperature detect trim
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK) |
SNVS_TEMP_DET_TRIM_SEL - SNVS temperature detect trim select 0b0..The trimming codes are selected from eFuse 0b1..The trimming codes to define the temperature boundaries of temperature detector are selected from SNVS_TEMP_DET_TRIM
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK) |
SNVS_TEMP_DET_TRIM_SEL - SNVS temperature detect trim select 0b0..The trimming codes are selected from eFuse 0b1..The trimming codes to define the temperature boundaries of temperature detector are selected from SNVS_TEMP_DET_TRIM
#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK) |
SNVS_VOLT_DET_TRIM - SNVS voltage detect trim
#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK) |
SNVS_VOLT_DET_TRIM - SNVS voltage detect trim
#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK) |
SNVS_VOLT_DET_TRIM_SEL - SNVS voltage detect trim select 0b0..The trimming codes are selected from eFuse 0b1..The trimming codes of voltage detectors to change the voltage boundaries in battery voltage detecting are selected from SNVS_VOLT_DET_TRIM
#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK) |
SNVS_VOLT_DET_TRIM_SEL - SNVS voltage detect trim select 0b0..The trimming codes are selected from eFuse 0b1..The trimming codes of voltage detectors to change the voltage boundaries in battery voltage detecting are selected from SNVS_VOLT_DET_TRIM
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK) |
SNVS_SRAM_PSWLARGE - SNVS SRAM large switch control bit 0b1..Switch off SNVS SRAM power for peripheral and array 0b0..Switch on SNVS SRAM power for peripheral and array
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK) |
SNVS_SRAM_PSWLARGE - SNVS SRAM large switch control bit 0b1..Switch off SNVS SRAM power for peripheral and array 0b0..Switch on SNVS SRAM power for peripheral and array
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK) |
SNVS_SRAM_PSWLARGEMP_FORCE - SNVS SRAM large switch control bit for peripheral 0b1..Switch off SNVS SRAM power for peripheral (SRAM array power is not impacted, and data can be retained) 0b0..Switch on SNVS SRAM power for peripheral
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK) |
SNVS_SRAM_PSWLARGEMP_FORCE - SNVS SRAM large switch control bit for peripheral 0b1..Switch off SNVS SRAM power for peripheral (SRAM array power is not impacted, and data can be retained) 0b0..Switch on SNVS SRAM power for peripheral
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK) |
SNVS_SRAM_PSWSMALL - SNVS SRAM small switch control bit 0b1..Switch off SNVS SRAM power for peripheral and array 0b0..Switch on SNVS SRAM power for peripheral and array
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK) |
SNVS_SRAM_PSWSMALL - SNVS SRAM small switch control bit 0b1..Switch off SNVS SRAM power for peripheral and array 0b0..Switch on SNVS SRAM power for peripheral and array
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK) |
SNVS_SRAM_PSWSMALLMP_FORCE - SNVS SRAM small switch control bit for peripheral 0b1..Switch off SNVS SRAM power for peripheral (SRAM array power is not impacted, and data can be retained) 0b0..Switch on SNVS SRAM power for peripheral
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK) |
SNVS_SRAM_PSWSMALLMP_FORCE - SNVS SRAM small switch control bit for peripheral 0b1..Switch off SNVS SRAM power for peripheral (SRAM array power is not impacted, and data can be retained) 0b0..Switch on SNVS SRAM power for peripheral
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK) |
SNVS_SRAM_SLEEP - SNVS SRAM power-down enable bit 0b0..Enable SRAM access (It should be cleared after LDO_SNVS_DIG is enabled) 0b1..SNVS SRAM can go in Shutdown/ Periphery Off Array On/ Periphery On Array Off mode. In addition, this bit ensures power-up without stuck-at /high DC current states and hence must be held to 1 during wake-up, so this bit is default high.
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK) |
SNVS_SRAM_SLEEP - SNVS SRAM power-down enable bit 0b0..Enable SRAM access (It should be cleared after LDO_SNVS_DIG is enabled) 0b1..SNVS SRAM can go in Shutdown/ Periphery Off Array On/ Periphery On Array Off mode. In addition, this bit ensures power-up without stuck-at /high DC current states and hence must be held to 1 during wake-up, so this bit is default high.
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK) |
SNVS_SRAM_STDBY - SNVS SRAM standby enable bit 0b1..SNVS SRAM enters low leakage state and large drivers are switched OFF 0b0..SNVS SRAM does not enter low leakage state
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK) |
SNVS_SRAM_STDBY - SNVS SRAM standby enable bit 0b1..SNVS SRAM enters low leakage state and large drivers are switched OFF 0b0..SNVS SRAM does not enter low leakage state
#define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK) |
SNVSDIG_SNVS1P8_ISO_EN - SNVS RAM isolation enable bit 0b1..Enable the isolation to avoid extra leakage power before SNVS SRAM peripheral power or LDO_SNVS_DIG is switched off 0b0..Enable SRAM access (It should be cleared after LDO_SNVS_DIG and SNVS SRAM peripheral power is back)
#define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK) |
SNVSDIG_SNVS1P8_ISO_EN - SNVS RAM isolation enable bit 0b1..Enable the isolation to avoid extra leakage power before SNVS SRAM peripheral power or LDO_SNVS_DIG is switched off 0b0..Enable SRAM access (It should be cleared after LDO_SNVS_DIG and SNVS SRAM peripheral power is back)
#define IOMUXC_SNVS_GPR_GPR37_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b0..Write access is not blocked 0b1..Write access is blocked
#define IOMUXC_SNVS_GPR_GPR37_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_LOCK_MASK) |
LOCK - Lock the write to bit 31:1 0b0..Write access is not blocked 0b1..Write access is blocked
#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK) |
SNVS_TAMPER_PUE - SNVS tamper detect pin pull enable bit
#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK) |
SNVS_TAMPER_PUE - SNVS tamper detect pin pull enable bit
#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK) |
SNVS_TAMPER_PUS - SNVS tamper detect pin pull selection bit
#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK) |
SNVS_TAMPER_PUS - SNVS tamper detect pin pull selection bit
#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK) |
DCDC_IN_LOW_VOL 0b0..DCDC_IN is ok 0b1..DCDC_IN is too low
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK) |
DCDC_OVER_CUR 0b0..No over current detected 0b1..Over current detected
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK) |
DCDC_OVER_VOL 0b0..No over voltage detected 0b1..Over voltage detected
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK) |
DCDC_STATUS_CAPT_CLR - DCDC captured status clear
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK) |
DCDC_STS_DC_OK 0b0..DCDC is ramping up and not ready 0b1..DCDC is ready
#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK) |
LPSR_MODE_ENABLE 0b0..SNVS domain will reset when system reset happens 0b1..SNVS domain will only reset with SNVS POR
#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK) |
POR_PULL_TYPE 0b00..100 Ohm pull up enabled for POR_B always 0b01..Disable pull in SNVS mode, 100 Ohm pull up enabled otherwise 0b10..Disable pull of POR_B always 0b11..100 Ohm pull down enabled in SNVS mode, 100 Ohm pull up enabled otherwise
#define IOMUXC_SNVS_GPR_GPR_GPR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR_GPR_MASK) |
GPR - General purpose bits
#define IOMUXC_SNVS_GPR_GPR_GPR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR_GPR_MASK) |
GPR - General purpose bits