RTEMS 6.1-rc7
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stm32h7xx_hal_flash_ex.h
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1
18/* Define to prevent recursive inclusion -------------------------------------*/
19#ifndef STM32H7xx_HAL_FLASH_EX_H
20#define STM32H7xx_HAL_FLASH_EX_H
21
22#ifdef __cplusplus
23 extern "C" {
24#endif
25
26/* Includes ------------------------------------------------------------------*/
27#include "stm32h7xx_hal_def.h"
28
37/* Exported types ------------------------------------------------------------*/
46typedef struct
47{
48 uint32_t TypeErase;
51 uint32_t Banks;
54 uint32_t Sector;
57 uint32_t NbSectors;
60 uint32_t VoltageRange;
64
65
69typedef struct
70{
71 uint32_t OptionType;
74 uint32_t WRPState;
77 uint32_t WRPSector;
80 uint32_t RDPLevel;
83 uint32_t BORLevel;
86 uint32_t USERType;
89 uint32_t USERConfig;
92 uint32_t Banks;
95 uint32_t PCROPConfig;
99 uint32_t PCROPStartAddr;
102 uint32_t PCROPEndAddr;
105 uint32_t BootConfig;
108 uint32_t BootAddr0;
111 uint32_t BootAddr1;
113#if defined(DUAL_CORE)
114 uint32_t CM4BootConfig;
118 uint32_t CM4BootAddr0;
121 uint32_t CM4BootAddr1;
123#endif /*DUAL_CORE*/
124
135#if defined (FLASH_OTPBL_LOCKBL)
136 uint32_t OTPBlockLock;
138#endif /* FLASH_OTPBL_LOCKBL */
139
140#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
141 uint32_t SharedRamConfig;
143#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
144
145#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
146 uint32_t FreqBoostState;
148#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
149
151
155typedef struct
156{
157 uint32_t TypeCRC;
160 uint32_t BurstSize;
163 uint32_t Bank;
166 uint32_t Sector;
169 uint32_t NbSectors;
172 uint32_t CRCStartAddr;
175 uint32_t CRCEndAddr;
179
180#if (USE_FLASH_ECC == 1U)
184typedef struct
185{
186 uint32_t Area;
189 uint32_t Address;
191} FLASH_EccInfoTypeDef;
192#endif /* USE_FLASH_ECC */
193
197/* Exported constants --------------------------------------------------------*/
198
208#define FLASH_TYPEERASE_SECTORS 0x00U
209#define FLASH_TYPEERASE_MASSERASE 0x01U
214#if defined (FLASH_CR_PSIZE)
219#define FLASH_VOLTAGE_RANGE_1 0x00000000U
220#define FLASH_VOLTAGE_RANGE_2 FLASH_CR_PSIZE_0
221#define FLASH_VOLTAGE_RANGE_3 FLASH_CR_PSIZE_1
222#define FLASH_VOLTAGE_RANGE_4 FLASH_CR_PSIZE
226#endif /* FLASH_CR_PSIZE */
227
232#define OB_WRPSTATE_DISABLE 0x00000000U
233#define OB_WRPSTATE_ENABLE 0x00000001U
238#if (USE_FLASH_ECC == 1U)
243#define FLASH_ECC_AREA_USER_BANK1 0x00000000U
244#define FLASH_ECC_AREA_USER_BANK2 0x00000001U
248#endif /* USE_FLASH_ECC */
249
254#define OPTIONBYTE_WRP 0x01U
255#define OPTIONBYTE_RDP 0x02U
256#define OPTIONBYTE_USER 0x04U
257#define OPTIONBYTE_PCROP 0x08U
258#define OPTIONBYTE_BOR 0x10U
259#define OPTIONBYTE_SECURE_AREA 0x20U
260#if defined (DUAL_CORE)
261#define OPTIONBYTE_CM7_BOOTADD 0x40U
262#define OPTIONBYTE_CM4_BOOTADD 0x80U
263#define OPTIONBYTE_BOOTADD OPTIONBYTE_CM7_BOOTADD
264#else /* Single core */
265#define OPTIONBYTE_BOOTADD 0x40U
266#endif /*DUAL_CORE*/
267#if defined (FLASH_OTPBL_LOCKBL)
268#define OPTIONBYTE_OTP_LOCK 0x80U
269#endif /* FLASH_OTPBL_LOCKBL */
270#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
271#define OPTIONBYTE_SHARED_RAM 0x100U
272#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
273#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
274#define OPTIONBYTE_FREQ_BOOST 0x200U
275#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
276
277#if defined (DUAL_CORE)
278#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
279 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
280 OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD)
281#elif defined (FLASH_OTPBL_LOCKBL)
282#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
283 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
284 OPTIONBYTE_BOOTADD | OPTIONBYTE_OTP_LOCK)
285#elif defined (FLASH_OPTSR2_TCM_AXI_SHARED)
286#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
287 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
288 OPTIONBYTE_BOOTADD | OPTIONBYTE_SHARED_RAM | OPTIONBYTE_FREQ_BOOST)
289#else
290#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
291 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
292 OPTIONBYTE_BOOTADD)
293#endif /* DUAL_CORE */
302#define OB_RDP_LEVEL_0 0xAA00U
303#define OB_RDP_LEVEL_1 0x5500U
304#define OB_RDP_LEVEL_2 0xCC00U
314#define OB_IWDG_SW OB_IWDG1_SW
315#define OB_IWDG_HW OB_IWDG1_HW
324#define OB_STOP_NO_RST 0x40U
325#define OB_STOP_RST 0x00U
334#define OB_STDBY_NO_RST 0x80U
335#define OB_STDBY_RST 0x00U
344#define OB_IWDG_STOP_FREEZE 0x00000000U
345#define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP
354#define OB_IWDG_STDBY_FREEZE 0x00000000U
355#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY
364#define OB_BOR_LEVEL0 0x00000000U
365#define OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0
366#define OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1
367#define OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0)
378#define OB_BOOTADDR_ITCM_RAM 0x0000U
379#define OB_BOOTADDR_SYSTEM 0x0040U
380#define OB_BOOTADDR_ITCM_FLASH 0x0080U
381#define OB_BOOTADDR_AXIM_FLASH 0x2000U
382#define OB_BOOTADDR_DTCM_RAM 0x8000U
383#define OB_BOOTADDR_SRAM1 0x8004U
384#define OB_BOOTADDR_SRAM2 0x8013U
393#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
394#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
395#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
396#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
397#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
398#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
399#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
400#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS
402/* Unused FLASH Latency defines */
403#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS
404#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS
405#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS
406#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS
407#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS
408#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS
409#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS
410#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS
419#define FLASH_BANK_1 0x01U
420#if defined (DUAL_BANK)
421#define FLASH_BANK_2 0x02U
422#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2)
423#endif /* DUAL_BANK */
432#define OB_PCROP_RDP_NOT_ERASE 0x00000000U
434#define OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP
445#if (FLASH_SECTOR_TOTAL == 128)
446#define OB_WRP_SECTOR_0TO3 0x00000001U
447#define OB_WRP_SECTOR_4TO7 0x00000002U
448#define OB_WRP_SECTOR_8TO11 0x00000004U
449#define OB_WRP_SECTOR_12TO15 0x00000008U
450#define OB_WRP_SECTOR_16TO19 0x00000010U
451#define OB_WRP_SECTOR_20TO23 0x00000020U
452#define OB_WRP_SECTOR_24TO27 0x00000040U
453#define OB_WRP_SECTOR_28TO31 0x00000080U
454#define OB_WRP_SECTOR_32TO35 0x00000100U
455#define OB_WRP_SECTOR_36TO39 0x00000200U
456#define OB_WRP_SECTOR_40TO43 0x00000400U
457#define OB_WRP_SECTOR_44TO47 0x00000800U
458#define OB_WRP_SECTOR_48TO51 0x00001000U
459#define OB_WRP_SECTOR_52TO55 0x00002000U
460#define OB_WRP_SECTOR_56TO59 0x00004000U
461#define OB_WRP_SECTOR_60TO63 0x00008000U
462#define OB_WRP_SECTOR_64TO67 0x00010000U
463#define OB_WRP_SECTOR_68TO71 0x00020000U
464#define OB_WRP_SECTOR_72TO75 0x00040000U
465#define OB_WRP_SECTOR_76TO79 0x00080000U
466#define OB_WRP_SECTOR_80TO83 0x00100000U
467#define OB_WRP_SECTOR_84TO87 0x00200000U
468#define OB_WRP_SECTOR_88TO91 0x00400000U
469#define OB_WRP_SECTOR_92TO95 0x00800000U
470#define OB_WRP_SECTOR_96TO99 0x01000000U
471#define OB_WRP_SECTOR_100TO103 0x02000000U
472#define OB_WRP_SECTOR_104TO107 0x04000000U
473#define OB_WRP_SECTOR_108TO111 0x08000000U
474#define OB_WRP_SECTOR_112TO115 0x10000000U
475#define OB_WRP_SECTOR_116TO119 0x20000000U
476#define OB_WRP_SECTOR_120TO123 0x40000000U
477#define OB_WRP_SECTOR_124TO127 0x80000000U
478#define OB_WRP_SECTOR_ALL 0xFFFFFFFFU
479#else
480#define OB_WRP_SECTOR_0 0x00000001U
481#define OB_WRP_SECTOR_1 0x00000002U
482#define OB_WRP_SECTOR_2 0x00000004U
483#define OB_WRP_SECTOR_3 0x00000008U
484#define OB_WRP_SECTOR_4 0x00000010U
485#define OB_WRP_SECTOR_5 0x00000020U
486#define OB_WRP_SECTOR_6 0x00000040U
487#define OB_WRP_SECTOR_7 0x00000080U
488#define OB_WRP_SECTOR_ALL 0x000000FFU
489#endif /* FLASH_SECTOR_TOTAL == 128 */
498#define OB_SECURITY_DISABLE 0x00000000U
499#define OB_SECURITY_ENABLE FLASH_OPTSR_SECURITY
508#define OB_ST_RAM_SIZE_2KB 0x00000000U
509#define OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0
510#define OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1
511#define OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE
516#if defined(DUAL_CORE)
521#define OB_BCM7_DISABLE 0x00000000U
522#define OB_BCM7_ENABLE FLASH_OPTSR_BCM7
532#define OB_BCM4_DISABLE 0x00000000U
533#define OB_BCM4_ENABLE FLASH_OPTSR_BCM4
537#endif /* DUAL_CORE */
538
543#define OB_IWDG1_SW FLASH_OPTSR_IWDG1_SW
544#define OB_IWDG1_HW 0x00000000U
549#if defined(DUAL_CORE)
554#define OB_IWDG2_SW FLASH_OPTSR_IWDG2_SW
555#define OB_IWDG2_HW 0x00000000U
559#endif
560
565#define OB_STOP_RST_D1 0x00000000U
566#define OB_STOP_NO_RST_D1 FLASH_OPTSR_NRST_STOP_D1
575#define OB_STDBY_RST_D1 0x00000000U
576#define OB_STDBY_NO_RST_D1 FLASH_OPTSR_NRST_STBY_D1
581#if defined (FLASH_OPTSR_NRST_STOP_D2)
586#define OB_STOP_RST_D2 0x00000000U
587#define OB_STOP_NO_RST_D2 FLASH_OPTSR_NRST_STOP_D2
596#define OB_STDBY_RST_D2 0x00000000U
597#define OB_STDBY_NO_RST_D2 FLASH_OPTSR_NRST_STBY_D2
601#endif /* FLASH_OPTSR_NRST_STOP_D2 */
602
603#if defined (DUAL_BANK)
608#define OB_SWAP_BANK_DISABLE 0x00000000U
609#define OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK_OPT
613#endif /* DUAL_BANK */
614
619#define OB_IOHSLV_DISABLE 0x00000000U
620#define OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV
625#if defined (FLASH_OPTSR_VDDMMC_HSLV)
630#define OB_VDDMMC_HSLV_DISABLE 0x00000000U
631#define OB_VDDMMC_HSLV_ENABLE FLASH_OPTSR_VDDMMC_HSLV
635#endif /* FLASH_OPTSR_VDDMMC_HSLV */
636
637#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
642#define OB_CPUFREQ_BOOST_DISABLE 0x00000000U
643#define OB_CPUFREQ_BOOST_ENABLE FLASH_OPTSR2_CPUFREQ_BOOST
647#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
648
649#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
654#define OB_TCM_AXI_SHARED_ITCM64KB 0x00000000U
655#define OB_TCM_AXI_SHARED_ITCM128KB FLASH_OPTSR2_TCM_AXI_SHARED_0
656#define OB_TCM_AXI_SHARED_ITCM192KB FLASH_OPTSR2_TCM_AXI_SHARED_1
657#define OB_TCM_AXI_SHARED_ITCM256KB FLASH_OPTSR2_TCM_AXI_SHARED
661#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
662
667#define OB_USER_IWDG1_SW 0x0001U
668#define OB_USER_NRST_STOP_D1 0x0002U
669#define OB_USER_NRST_STDBY_D1 0x0004U
670#define OB_USER_IWDG_STOP 0x0008U
671#define OB_USER_IWDG_STDBY 0x0010U
672#define OB_USER_ST_RAM_SIZE 0x0020U
673#define OB_USER_SECURITY 0x0040U
674#define OB_USER_IOHSLV 0x0080U
675#if defined (DUAL_BANK)
676#define OB_USER_SWAP_BANK 0x0100U
677#endif /* DUAL_BANK */
678#if defined (FLASH_OPTSR_VDDMMC_HSLV)
679#define OB_USER_VDDMMC_HSLV 0x0200U
680#endif /* FLASH_OPTSR_VDDMMC_HSLV */
681#if defined (DUAL_CORE)
682#define OB_USER_IWDG2_SW 0x0200U
683#define OB_USER_BCM4 0x0400U
684#define OB_USER_BCM7 0x0800U
685#endif /*DUAL_CORE*/
686#if defined (FLASH_OPTSR_NRST_STOP_D2)
687#define OB_USER_NRST_STOP_D2 0x1000U
688#define OB_USER_NRST_STDBY_D2 0x2000U
689#endif /* FLASH_OPTSR_NRST_STOP_D2 */
690
691#if defined (DUAL_CORE)
692#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
693 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
694 OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\
695 OB_USER_IWDG2_SW | OB_USER_BCM4 | OB_USER_BCM7 |\
696 OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2)
697#elif defined (FLASH_OPTSR_VDDMMC_HSLV)
698#if defined (DUAL_BANK)
699#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
700 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
701 OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\
702 OB_USER_VDDMMC_HSLV)
703#else
704#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
705 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
706 OB_USER_SECURITY | OB_USER_IOHSLV |\
707 OB_USER_VDDMMC_HSLV)
708#endif /* DUAL_BANK */
709#elif defined (FLASH_OPTSR2_TCM_AXI_SHARED)
710#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
711 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
712 OB_USER_SECURITY | OB_USER_IOHSLV |\
713 OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2)
714#else /* Single core */
715#if defined (DUAL_BANK)
716#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
717 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
718 OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK )
719#else
720#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
721 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
722 OB_USER_SECURITY | OB_USER_IOHSLV )
723#endif /* DUAL_BANK */
724#endif /* DUAL_CORE */
733#define OB_BOOT_ADD0 0x01U
734#define OB_BOOT_ADD1 0x02U
735#define OB_BOOT_ADD_BOTH 0x03U
744#define OB_SECURE_RDP_NOT_ERASE 0x00000000U
746#define OB_SECURE_RDP_ERASE FLASH_SCAR_DMES
756#define FLASH_CRC_ADDR 0x00000000U
757#define FLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT
758#define FLASH_CRC_BANK (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT)
767#define FLASH_CRC_BURST_SIZE_4 0x00000000U
768#define FLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0
769#define FLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1
770#define FLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST
779#define FLASH_PROGRAMMING_DELAY_0 0x00000000U
780#define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0
781#define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1
782#define FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ
787#if defined (FLASH_OTPBL_LOCKBL)
792#define FLASH_OTP_BLOCK_0 0x00000001U
793#define FLASH_OTP_BLOCK_1 0x00000002U
794#define FLASH_OTP_BLOCK_2 0x00000004U
795#define FLASH_OTP_BLOCK_3 0x00000008U
796#define FLASH_OTP_BLOCK_4 0x00000010U
797#define FLASH_OTP_BLOCK_5 0x00000020U
798#define FLASH_OTP_BLOCK_6 0x00000040U
799#define FLASH_OTP_BLOCK_7 0x00000080U
800#define FLASH_OTP_BLOCK_8 0x00000100U
801#define FLASH_OTP_BLOCK_9 0x00000200U
802#define FLASH_OTP_BLOCK_10 0x00000400U
803#define FLASH_OTP_BLOCK_11 0x00000800U
804#define FLASH_OTP_BLOCK_12 0x00001000U
805#define FLASH_OTP_BLOCK_13 0x00002000U
806#define FLASH_OTP_BLOCK_14 0x00004000U
807#define FLASH_OTP_BLOCK_15 0x00008000U
808#define FLASH_OTP_BLOCK_ALL 0x0000FFFFU
812#endif /* FLASH_OTPBL_LOCKBL */
817/* Exported macro ------------------------------------------------------------*/
828#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U)
829
830#if defined (FLASH_CR_PSIZE)
838#if defined (DUAL_BANK)
839#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1) ? \
840 MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \
841 MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__)))
842#else
843#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__))
844#endif /* DUAL_BANK */
845
852#if defined (DUAL_BANK)
853#define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \
854 READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) : \
855 READ_BIT((FLASH->CR2), FLASH_CR_PSIZE))
856#else
857#define __HAL_FLASH_GET_PSIZE(__BANK__) READ_BIT((FLASH->CR1), FLASH_CR_PSIZE)
858#endif /* DUAL_BANK */
859
860#endif /* FLASH_CR_PSIZE */
861
868#define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__))
869
875#define __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ)
880/* Exported functions --------------------------------------------------------*/
888/* Extension Program operation functions *************************************/
889HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
890HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
891HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
892void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
893
894HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void);
895HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void);
896#if defined (DUAL_BANK)
897HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void);
898HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void);
899#endif /* DUAL_BANK */
900
901HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result);
902
907#if (USE_FLASH_ECC == 1U)
911void HAL_FLASHEx_EnableEccCorrectionInterrupt(void);
912void HAL_FLASHEx_DisableEccCorrectionInterrupt(void);
913void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank1(void);
914void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank1(void);
915#if defined (DUAL_BANK)
916void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank2(void);
917void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank2(void);
918#endif /* DUAL_BANK */
919
920void HAL_FLASHEx_EnableEccDetectionInterrupt(void);
921void HAL_FLASHEx_DisableEccDetectionInterrupt(void);
922void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank1(void);
923void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank1(void);
924#if defined (DUAL_BANK)
925void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank2(void);
926void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank2(void);
927#endif /* DUAL_BANK */
928
929void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData);
930void HAL_FLASHEx_BusFault_IRQHandler(void);
931
932__weak void HAL_FLASHEx_EccDetectionCallback(void);
933__weak void HAL_FLASHEx_EccCorrectionCallback(void);
937#endif /* USE_FLASH_ECC */
938
942/* Private types -------------------------------------------------------------*/
943/* Private variables ---------------------------------------------------------*/
944/* Private constants ---------------------------------------------------------*/
945/* Private macros ------------------------------------------------------------*/
956#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
957 ((VALUE) == FLASH_TYPEERASE_MASSERASE))
958
959#if defined (FLASH_CR_PSIZE)
960#define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
961 ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
962 ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
963 ((RANGE) == FLASH_VOLTAGE_RANGE_4))
964#endif /* FLASH_CR_PSIZE */
965
966#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
967 ((VALUE) == OB_WRPSTATE_ENABLE))
968
969#define IS_OPTIONBYTE(VALUE) ((((VALUE) & OPTIONBYTE_ALL) != 0U) && \
970 (((VALUE) & ~OPTIONBYTE_ALL) == 0U))
971
972#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U)
973
974#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
975 ((LEVEL) == OB_RDP_LEVEL_1) ||\
976 ((LEVEL) == OB_RDP_LEVEL_2))
977
978#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
979
980#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
981
982#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
983
984#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
985
986#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
987
988#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \
989 ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3))
990
991#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
992 ((LATENCY) == FLASH_LATENCY_1) || \
993 ((LATENCY) == FLASH_LATENCY_2) || \
994 ((LATENCY) == FLASH_LATENCY_3) || \
995 ((LATENCY) == FLASH_LATENCY_4) || \
996 ((LATENCY) == FLASH_LATENCY_5) || \
997 ((LATENCY) == FLASH_LATENCY_6) || \
998 ((LATENCY) == FLASH_LATENCY_7) || \
999 ((LATENCY) == FLASH_LATENCY_8) || \
1000 ((LATENCY) == FLASH_LATENCY_9) || \
1001 ((LATENCY) == FLASH_LATENCY_10) || \
1002 ((LATENCY) == FLASH_LATENCY_11) || \
1003 ((LATENCY) == FLASH_LATENCY_12) || \
1004 ((LATENCY) == FLASH_LATENCY_13) || \
1005 ((LATENCY) == FLASH_LATENCY_14) || \
1006 ((LATENCY) == FLASH_LATENCY_15))
1007
1008#define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL)
1009
1010#if (FLASH_SECTOR_TOTAL == 8U)
1011#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
1012#else
1013#define IS_OB_WRP_SECTOR(SECTOR) ((SECTOR) != 0x00000000U)
1014#endif /* FLASH_SECTOR_TOTAL == 8U */
1015
1016#define IS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \
1017 ((CONFIG) == OB_PCROP_RDP_ERASE))
1018
1019#define IS_OB_SECURE_RDP(CONFIG) (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \
1020 ((CONFIG) == OB_SECURE_RDP_ERASE))
1021
1022#if defined (DUAL_BANK)
1023#define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))
1024#endif /* DUAL_BANK */
1025
1026#define IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
1027
1028#if defined (FLASH_OPTSR_VDDMMC_HSLV)
1029#define IS_OB_USER_VDDMMC_HSLV(VALUE) (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE))
1030#endif /* FLASH_OPTSR_VDDMMC_HSLV */
1031
1032#define IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))
1033#if defined (DUAL_CORE)
1034#define IS_OB_IWDG2_SOURCE(SOURCE) (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW))
1035#endif /* DUAL_CORE */
1036#define IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))
1037
1038#define IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))
1039
1040#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))
1041
1042#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))
1043
1044#define IS_OB_USER_ST_RAM_SIZE(VALUE) (((VALUE) == OB_ST_RAM_SIZE_2KB) || ((VALUE) == OB_ST_RAM_SIZE_4KB) || \
1045 ((VALUE) == OB_ST_RAM_SIZE_8KB) || ((VALUE) == OB_ST_RAM_SIZE_16KB))
1046
1047#define IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE))
1048
1049#if defined (DUAL_CORE)
1050#define IS_OB_USER_BCM4(VALUE) (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE))
1051
1052#define IS_OB_USER_BCM7(VALUE) (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE))
1053#endif /* DUAL_CORE */
1054
1055#if defined (FLASH_OPTSR_NRST_STOP_D2)
1056#define IS_OB_STOP_D2_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2))
1057
1058#define IS_OB_STDBY_D2_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2))
1059#endif /* FLASH_OPTSR_NRST_STOP_D2 */
1060
1061#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
1062#define IS_OB_USER_TCM_AXI_SHARED(VALUE) (((VALUE) == OB_TCM_AXI_SHARED_ITCM64KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM128KB) || \
1063 ((VALUE) == OB_TCM_AXI_SHARED_ITCM192KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM256KB))
1064#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
1065
1066#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
1067#define IS_OB_USER_CPUFREQ_BOOST(VALUE) (((VALUE) == OB_CPUFREQ_BOOST_DISABLE) || ((VALUE) == OB_CPUFREQ_BOOST_ENABLE))
1068#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
1069
1070#define IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0U) && \
1071 (((TYPE) & ~OB_USER_ALL) == 0U))
1072
1073#define IS_OB_BOOT_ADD_OPTION(VALUE) (((VALUE) == OB_BOOT_ADD0) || \
1074 ((VALUE) == OB_BOOT_ADD1) || \
1075 ((VALUE) == OB_BOOT_ADD_BOTH))
1076
1077#define IS_FLASH_TYPECRC(VALUE) (((VALUE) == FLASH_CRC_ADDR) || \
1078 ((VALUE) == FLASH_CRC_SECTORS) || \
1079 ((VALUE) == FLASH_CRC_BANK))
1080
1081#if defined (FLASH_OTPBL_LOCKBL)
1082#define IS_OTP_BLOCK(VALUE) ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U))
1083#endif /* FLASH_OTPBL_LOCKBL */
1092/* Private functions ---------------------------------------------------------*/
1097void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange);
1110#ifdef __cplusplus
1111}
1112#endif
1113
1114#endif /* STM32H7xx_HAL_FLASH_EX_H */
1115
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
FLASH Erase structure definition.
Definition: stm32h7xx_hal_flash_ex.h:156
uint32_t TypeCRC
Definition: stm32h7xx_hal_flash_ex.h:157
uint32_t BurstSize
Definition: stm32h7xx_hal_flash_ex.h:160
uint32_t CRCStartAddr
Definition: stm32h7xx_hal_flash_ex.h:172
uint32_t Sector
Definition: stm32h7xx_hal_flash_ex.h:166
uint32_t NbSectors
Definition: stm32h7xx_hal_flash_ex.h:169
uint32_t Bank
Definition: stm32h7xx_hal_flash_ex.h:163
uint32_t CRCEndAddr
Definition: stm32h7xx_hal_flash_ex.h:175
FLASH Erase structure definition.
Definition: stm32h7xx_hal_flash_ex.h:47
uint32_t Sector
Definition: stm32h7xx_hal_flash_ex.h:54
uint32_t VoltageRange
Definition: stm32h7xx_hal_flash_ex.h:60
uint32_t TypeErase
Definition: stm32h7xx_hal_flash_ex.h:48
uint32_t Banks
Definition: stm32h7xx_hal_flash_ex.h:51
uint32_t NbSectors
Definition: stm32h7xx_hal_flash_ex.h:57
FLASH Option Bytes Program structure definition.
Definition: stm32h7xx_hal_flash_ex.h:70
uint32_t BootAddr0
Definition: stm32h7xx_hal_flash_ex.h:108
uint32_t RDPLevel
Definition: stm32h7xx_hal_flash_ex.h:80
uint32_t WRPState
Definition: stm32h7xx_hal_flash_ex.h:74
uint32_t BootAddr1
Definition: stm32h7xx_hal_flash_ex.h:111
uint32_t PCROPConfig
Definition: stm32h7xx_hal_flash_ex.h:95
uint32_t SecureAreaConfig
Definition: stm32h7xx_hal_flash_ex.h:125
uint32_t OptionType
Definition: stm32h7xx_hal_flash_ex.h:71
uint32_t BORLevel
Definition: stm32h7xx_hal_flash_ex.h:83
uint32_t Banks
Definition: stm32h7xx_hal_flash_ex.h:92
uint32_t SecureAreaStartAddr
Definition: stm32h7xx_hal_flash_ex.h:129
uint32_t USERType
Definition: stm32h7xx_hal_flash_ex.h:86
uint32_t WRPSector
Definition: stm32h7xx_hal_flash_ex.h:77
uint32_t SecureAreaEndAddr
Definition: stm32h7xx_hal_flash_ex.h:132
uint32_t BootConfig
Definition: stm32h7xx_hal_flash_ex.h:105
uint32_t PCROPStartAddr
Definition: stm32h7xx_hal_flash_ex.h:99
uint32_t PCROPEndAddr
Definition: stm32h7xx_hal_flash_ex.h:102
uint32_t USERConfig
Definition: stm32h7xx_hal_flash_ex.h:89