38#ifndef _RTEMS_SCORE_CPU_H
39#define _RTEMS_SCORE_CPU_H
50#if defined(RTEMS_PARAVIRT)
51#include <rtems/score/paravirt.h>
78#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
86#define CPU_ISR_PASSES_FRAME_POINTER FALSE
94#define CPU_HARDWARE_FP TRUE
95#define CPU_SOFTWARE_FP FALSE
97#define CPU_ALL_TASKS_ARE_FP TRUE
98#define CPU_IDLE_TASK_IS_FP TRUE
99#define CPU_USE_DEFERRED_FP_SWITCH FALSE
102#if ( I386_HAS_FPU == 1 )
103#define CPU_HARDWARE_FP TRUE
105#define CPU_HARDWARE_FP FALSE
107#define CPU_SOFTWARE_FP FALSE
109#define CPU_ALL_TASKS_ARE_FP FALSE
110#define CPU_IDLE_TASK_IS_FP FALSE
111#if defined(RTEMS_SMP)
112 #define CPU_USE_DEFERRED_FP_SWITCH FALSE
114 #define CPU_USE_DEFERRED_FP_SWITCH TRUE
118#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
120#define CPU_STACK_GROWS_UP FALSE
123#define CPU_CACHE_LINE_BYTES 64
125#define CPU_STRUCTURE_ALIGNMENT
127#define CPU_MAXIMUM_PROCESSORS 32
129#define I386_CONTEXT_CONTROL_EFLAGS_OFFSET 0
130#define I386_CONTEXT_CONTROL_ESP_OFFSET 4
131#define I386_CONTEXT_CONTROL_EBP_OFFSET 8
132#define I386_CONTEXT_CONTROL_EBX_OFFSET 12
133#define I386_CONTEXT_CONTROL_ESI_OFFSET 16
134#define I386_CONTEXT_CONTROL_EDI_OFFSET 20
135#define I386_CONTEXT_CONTROL_GS_0_OFFSET 24
136#define I386_CONTEXT_CONTROL_GS_1_OFFSET 28
137#define I386_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 32
140 #define I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 36
158 segment_descriptors gs;
161 volatile bool is_executing;
165#define _CPU_Context_Get_SP( _context ) \
166 (uintptr_t) (_context)->esp
169 static inline bool _CPU_Context_Get_is_executing(
176 static inline void _CPU_Context_Set_is_executing(
181 context->is_executing = is_executing;
214 uint8_t fp_save_area[108];
275 uint8_t xmmregs[8][16];
283extern cpuExcHandlerType _currentExcHandler;
284extern void rtems_exception_init_mngt(
void);
293 uint32_t reserved[3];
310 I386_EXCEPTION_DIVIDE_BY_ZERO = 0,
311 I386_EXCEPTION_DEBUG = 1,
312 I386_EXCEPTION_NMI = 2,
313 I386_EXCEPTION_BREAKPOINT = 3,
314 I386_EXCEPTION_OVERFLOW = 4,
315 I386_EXCEPTION_BOUND = 5,
316 I386_EXCEPTION_ILLEGAL_INSTR = 6,
317 I386_EXCEPTION_MATH_COPROC_UNAVAIL = 7,
318 I386_EXCEPTION_DOUBLE_FAULT = 8,
319 I386_EXCEPTION_I386_COPROC_SEG_ERR = 9,
320 I386_EXCEPTION_INVALID_TSS = 10,
321 I386_EXCEPTION_SEGMENT_NOT_PRESENT = 11,
322 I386_EXCEPTION_STACK_SEGMENT_FAULT = 12,
323 I386_EXCEPTION_GENERAL_PROT_ERR = 13,
324 I386_EXCEPTION_PAGE_FAULT = 14,
325 I386_EXCEPTION_INTEL_RES15 = 15,
326 I386_EXCEPTION_FLOAT_ERROR = 16,
327 I386_EXCEPTION_ALIGN_CHECK = 17,
328 I386_EXCEPTION_MACHINE_CHECK = 18,
329 I386_EXCEPTION_ENTER_RDBG = 50
331} Intel_symbolic_exception_name;
340#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
355#define CPU_MODES_INTERRUPT_MASK 0x00000001
361#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
368#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
374#define CPU_STACK_MINIMUM_SIZE 4096
376#define CPU_SIZEOF_POINTER 4
382#define CPU_ALIGNMENT 4
383#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
394#define CPU_STACK_ALIGNMENT 16
396#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
412#if !defined(I386_DISABLE_INLINE_ISR_DISABLE_ENABLE)
413#define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level )
415#define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level )
417#define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level )
419#define _CPU_ISR_Set_level( _new_level ) \
421 if ( _new_level ) __asm__ volatile ( "cli" ); \
422 else __asm__ volatile ( "sti" ); \
425#define _CPU_ISR_Disable( _level ) _level = i386_disable_interrupts()
426#define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level )
427#define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level )
428#define _CPU_ISR_Set_level( _new_level ) i386_set_interrupt_level(_new_level)
431static inline bool _CPU_ISR_Is_enabled( uint32_t level )
433 return ( level & EFLAGS_INTR_ENABLE ) != 0;
443#define _CPU_Interrupt_stack_setup( _lo, _hi ) \
445 _hi = (void*)(((uintptr_t)(_hi) - 4) & ~ (CPU_STACK_ALIGNMENT - 1)); \
462#define CPU_EFLAGS_INTERRUPTS_ON 0x00003202
463#define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002
467void _CPU_Context_Initialize(
469 void *stack_area_begin,
470 size_t stack_area_size,
472 void (*entry_point)(
void ),
477#define _CPU_Context_Restart_self( _the_context ) \
478 _CPU_Context_restore( (_the_context) );
480#if defined(RTEMS_SMP)
481 uint32_t _CPU_SMP_Initialize(
void );
483 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
485 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
487 void _CPU_SMP_Prepare_start_multitasking(
void );
489 uint32_t _CPU_SMP_Get_current_processor(
void );
491 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
494#define _CPU_Context_Initialize_fp( _fp_area ) \
496 memcpy( *_fp_area, &_CPU_Null_fp_context, CPU_CONTEXT_FP_SIZE ); \
503#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
512#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
514#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
516 uint16_t __value_in_register = ( _value ); \
517 uint16_t __output = 0; \
518 __asm__ volatile ( "bsfw %0,%1 " \
519 : "=r" ( __value_in_register ), "=r" ( __output ) \
520 : "0" ( __value_in_register ), "1" ( __output ) \
522 ( _output ) = __output; \
537#define _CPU_Priority_Mask( _bit_number ) \
538 ( 1 << (_bit_number) )
540#define _CPU_Priority_bits_index( _priority ) \
554typedef void ( *CPU_ISR_handler )( void );
558 CPU_ISR_handler new_handler,
559 CPU_ISR_handler *old_handler
596#define _CPU_Context_save_fp(fp_context_pp) \
598 __asm__ __volatile__( \
600 :"=m"((*(fp_context_pp))->fpucw) \
602 __asm__ __volatile__( \
604 :"=m"((*(fp_context_pp))->mxcsr) \
619#define _CPU_Context_restore_fp(fp_context_pp) \
621 __asm__ __volatile__( \
623 ::"m"((*(fp_context_pp))->fpucw) \
626 __builtin_ia32_ldmxcsr(_Thread_Executing->fp_context->mxcsr); \
635#define _CPU_Context_Initialization_at_thread_begin() \
637 __asm__ __volatile__( \
641 :"st","st(1)","st(2)","st(3)", \
642 "st(4)","st(5)","st(6)","st(7)", \
645 if ( _Thread_Executing->fp_context ) { \
646 _CPU_Context_restore_fp(&_Thread_Executing->fp_context); \
653typedef uint32_t CPU_Counter_ticks;
This header file provides basic definitions used by the API and the implementation.
lpc176x_can_isr_vector isr_vector
Vector of isr for the can_driver .
Definition: can.c:37
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
Intel I386 CPU Dependent Source.
rtems_termios_device_context * context
Definition: console-config.c:62
#define _CPU_Context_restore_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:901
#define _CPU_Context_save_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:895
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
SPARC basic context.
Definition: cpu.h:213
Definition: sse_test.c:126
Thread register context.
Definition: cpu.h:173
uint32_t isr_dispatch_disable
This member is used for the external interrupt controller (EIC) support.
Definition: cpu.h:159
Definition: xnandpsu_onfi.h:185