RTEMS 6.1-rc7
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fsl_clock.h
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1/*
2 * Copyright 2019-2022 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_CLOCK_H_
9#define _FSL_CLOCK_H_
10
11#include "fsl_common.h"
12
18/*******************************************************************************
19 * Configurations
20 ******************************************************************************/
21
32#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
33#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
34#endif
35
36/*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
43#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
44
45/* Definition for delay API in clock driver, users can redefine it to the real application. */
46#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
47#if __CORTEX_M == 7
48#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (600000000UL)
49#else
50#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (240000000UL)
51#endif
52#endif
53
59#define CCSR_OFFSET 0x0C
60#define CBCDR_OFFSET 0x14
61#define CBCMR_OFFSET 0x18
62#define CSCMR1_OFFSET 0x1C
63#define CSCMR2_OFFSET 0x20
64#define CSCDR1_OFFSET 0x24
65#define CDCDR_OFFSET 0x30
66#define CSCDR2_OFFSET 0x38
67#define CSCDR3_OFFSET 0x3C
68#define CACRR_OFFSET 0x10
69#define CS1CDR_OFFSET 0x28
70#define CS2CDR_OFFSET 0x2C
71
75#define ARM_PLL_OFFSET 0x00
76#define PLL_SYS_OFFSET 0x30
77#define PLL_USB1_OFFSET 0x10
78#define PLL_AUDIO_OFFSET 0x70
79#define PLL_VIDEO_OFFSET 0xA0
80#define PLL_ENET_OFFSET 0xE0
81#define PLL_USB2_OFFSET 0x20
82
83#define CCM_TUPLE(reg, shift, mask, busyShift) \
84 (int)((reg & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
85#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU))))
86#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU)
87#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU))))
88#define CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU)
89
90#define CCM_BUSY_WAIT (0x20U)
91
95#define CCM_ANALOG_TUPLE(reg, shift) (((reg & 0xFFFU) << 16U) | (shift))
96#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU)
97#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
98 (*((volatile uint32_t *)((uint32_t)base + (((uint32_t)tuple >> 16U) & 0xFFFU) + off)))
99#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
100
104#define SYS_PLL1_FREQ (1000000000UL)
105#define SYS_PLL2_MFI (22UL)
106#define SYS_PLL2_FREQ (XTAL_FREQ * SYS_PLL2_MFI)
107#define SYS_PLL3_MFI (20UL)
108#define SYS_PLL3_FREQ (XTAL_FREQ * SYS_PLL3_MFI)
109#define XTAL_FREQ (24000000UL)
110
112#define LPADC_CLOCKS \
113 { \
114 kCLOCK_IpInvalid, kCLOCK_Lpadc1, kCLOCK_Lpadc2 \
115 }
116
118#define ADC_ETC_CLOCKS \
119 { \
120 kCLOCK_Adc_Etc \
121 }
122
124#define AOI_CLOCKS \
125 { \
126 kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \
127 }
128
130#define DCDC_CLOCKS \
131 { \
132 kCLOCK_Dcdc \
133 }
134
136#define SRC_CLOCKS \
137 { \
138 kCLOCK_Src \
139 }
140
142#define GPC_CLOCKS \
143 { \
144 kCLOCK_Gpc \
145 }
146
148#define SSARC_CLOCKS \
149 { \
150 kCLOCK_Ssarc \
151 }
152
154#define WDOG_CLOCKS \
155 { \
156 kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3, kCLOCK_Wdog4 \
157 }
158
160#define EWM_CLOCKS \
161 { \
162 kCLOCK_Ewm0 \
163 }
164
166#define SEMA_CLOCKS \
167 { \
168 kCLOCK_Sema \
169 }
170
172#if (__CORTEX_M == 7)
173#define MU_CLOCKS \
174 { \
175 kCLOCK_Mu_A \
176 }
177#else
178#define MU_CLOCKS \
179 { \
180 kCLOCK_Mu_B \
181 }
182#endif
183
185#define EDMA_CLOCKS \
186 { \
187 kCLOCK_Edma, kCLOCK_Edma_Lpsr \
188 }
189
191#define FLEXRAM_CLOCKS \
192 { \
193 kCLOCK_Flexram \
194 }
195
197#define LMEM_CLOCKS \
198 { \
199 kCLOCK_Lmem \
200 }
201
203#define FLEXSPI_CLOCKS \
204 { \
205 kCLOCK_IpInvalid, kCLOCK_Flexspi1, kCLOCK_Flexspi2 \
206 }
207
209#define RDC_CLOCKS \
210 { \
211 kCLOCK_Rdc, kCLOCK_M7_Xrdc, kCLOCK_M4_Xrdc \
212 }
213
215#define DCDC_CLOCKS \
216 { \
217 kCLOCK_Dcdc \
218 }
219
221#define SEMC_CLOCKS \
222 { \
223 kCLOCK_Semc \
224 }
225
227#define XECC_CLOCKS \
228 { \
229 kCLOCK_Xecc \
230 }
231
233#define IEE_CLOCKS \
234 { \
235 kCLOCK_Iee \
236 }
237
239#define KEYMANAGER_CLOCKS \
240 { \
241 kCLOCK_Key_Manager \
242 }
243
245#define PUF_CLOCKS \
246 { \
247 kCLOCK_Puf \
248 }
249
251#define OCOTP_CLOCKS \
252 { \
253 kCLOCK_Ocotp \
254 }
255
257#define CAAM_CLOCKS \
258 { \
259 kCLOCK_Caam \
260 }
261
263#define XBAR_CLOCKS \
264 { \
265 kCLOCK_IpInvalid, kCLOCK_Xbar1, kCLOCK_Xbar2, kCLOCK_Xbar3 \
266 }
267
269#define IOMUXC_CLOCKS \
270 { \
271 kCLOCK_Iomuxc, kCLOCK_Iomuxc_Lpsr \
272 }
273
275#define GPIO_CLOCKS \
276 { \
277 kCLOCK_IpInvalid, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, \
278 kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, \
279 }
280
282#define KPP_CLOCKS \
283 { \
284 kCLOCK_Kpp \
285 }
286
288#define FLEXIO_CLOCKS \
289 { \
290 kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \
291 }
292
294#define DAC_CLOCKS \
295 { \
296 kCLOCK_Dac \
297 }
298
300#define CMP_CLOCKS \
301 { \
302 kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \
303 }
304
306#define PIT_CLOCKS \
307 { \
308 kCLOCK_IpInvalid, kCLOCK_Pit1, kCLOCK_Pit2 \
309 }
310
312#define GPT_CLOCKS \
313 { \
314 kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2, kCLOCK_Gpt3, kCLOCK_Gpt4, kCLOCK_Gpt5, kCLOCK_Gpt6 \
315 }
316
318#define TMR_CLOCKS \
319 { \
320 kCLOCK_IpInvalid, kCLOCK_Qtimer1, kCLOCK_Qtimer2, kCLOCK_Qtimer3, kCLOCK_Qtimer4 \
321 }
322
324#define ENC_CLOCKS \
325 { \
326 kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \
327 }
328
330#define PWM_CLOCKS \
331 { \
332 {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
333 {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, \
334 {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2}, \
335 {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3}, \
336 { \
337 kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4 \
338 } \
339 }
340
342#define FLEXCAN_CLOCKS \
343 { \
344 kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2, kCLOCK_Can3 \
345 }
346
348#define LPUART_CLOCKS \
349 { \
350 kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \
351 kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8, kCLOCK_Lpuart9, kCLOCK_Lpuart10, kCLOCK_Lpuart11, \
352 kCLOCK_Lpuart12 \
353 }
354
356#define LPI2C_CLOCKS \
357 { \
358 kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4, kCLOCK_Lpi2c5, kCLOCK_Lpi2c6 \
359 }
360
362#define LPSPI_CLOCKS \
363 { \
364 kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4, kCLOCK_Lpspi5, kCLOCK_Lpspi6 \
365 }
366
368#define EMVSIM_CLOCKS \
369 { \
370 kCLOCK_IpInvalid, kCLOCK_Sim1, kCLOCK_Sim2 \
371 }
372
374#define ENET_CLOCKS \
375 { \
376 kCLOCK_Enet, kCLOCK_Enet_1g \
377 }
378
380#define USB_CLOCKS \
381 { \
382 kCLOCK_Usb \
383 }
384
386#define CDOG_CLOCKS \
387 { \
388 kCLOCK_Cdog \
389 }
390
392#define USDHC_CLOCKS \
393 { \
394 kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
395 }
396
398#define ASRC_CLOCKS \
399 { \
400 kCLOCK_Asrc \
401 }
402
404#define MQS_CLOCKS \
405 { \
406 kCLOCK_Mqs \
407 }
408
410#define PDM_CLOCKS \
411 { \
412 kCLOCK_Pdm \
413 }
414
416#define SPDIF_CLOCKS \
417 { \
418 kCLOCK_Spdif \
419 }
420
422#define SAI_CLOCKS \
423 { \
424 kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, kCLOCK_Sai4 \
425 }
426
428#define PXP_CLOCKS \
429 { \
430 kCLOCK_Pxp \
431 }
432
434#define GPU2D_CLOCKS \
435 { \
436 kCLOCK_Gpu2d \
437 }
438
440#define LCDIF_CLOCKS \
441 { \
442 kCLOCK_Lcdif \
443 }
444
446#define LCDIFV2_CLOCKS \
447 { \
448 kCLOCK_Lcdifv2 \
449 }
450
452#define MIPI_DSI_HOST_CLOCKS \
453 { \
454 kCLOCK_Mipi_Dsi \
455 }
456
458#define MIPI_CSI2RX_CLOCKS \
459 { \
460 kCLOCK_Mipi_Csi \
461 }
462
464#define CSI_CLOCKS \
465 { \
466 kCLOCK_Csi \
467 }
468
470#define DCIC_CLOCKS \
471 { \
472 kCLOCK_IpInvalid, kCLOCK_Dcic_Mipi, kCLOCK_Dcic_Lcd \
473 }
474
476#define DMAMUX_CLOCKS \
477 { \
478 kCLOCK_Edma, kCLOCK_Edma_Lpsr \
479 }
480
482#define XBARA_CLOCKS \
483 { \
484 kCLOCK_IpInvalid, kCLOCK_Xbar1 \
485 }
486
488#define XBARB_CLOCKS \
489 { \
490 kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \
491 }
492
496typedef enum _clock_lpcg
497{
637 kCLOCK_IpInvalid,
639
643typedef enum _clock_name
644{
678
679/* Clock OBSERVE SIGNALS */
680#define CCM_OBS_M7_CLK_ROOT 128, 4
681#define CCM_OBS_M4_CLK_ROOT 129, 0
682#define CCM_OBS_BUS_CLK_ROOT 130, 2
683#define CCM_OBS_BUS_LPSR_CLK_ROOT 131, 0
684#define CCM_OBS_SEMC_CLK_ROOT 132, 2
685#define CCM_OBS_CSSYS_CLK_ROOT 133, 2
686#define CCM_OBS_CSTRACE_CLK_ROOT 134, 2
687#define CCM_OBS_M4_SYSTICK_CLK_ROOT 135, 0
688#define CCM_OBS_M7_SYSTICK_CLK_ROOT 136, 2
689#define CCM_OBS_ADC1_CLK_ROOT 137, 2
690#define CCM_OBS_ADC2_CLK_ROOT 138, 2
691#define CCM_OBS_ACMP_CLK_ROOT 139, 2
692#define CCM_OBS_FLEXIO1_CLK_ROOT 140, 2
693#define CCM_OBS_FLEXIO2_CLK_ROOT 141, 2
694#define CCM_OBS_GPT1_CLK_ROOT 142, 2
695#define CCM_OBS_GPT2_CLK_ROOT 143, 2
696#define CCM_OBS_GPT3_CLK_ROOT 144, 2
697#define CCM_OBS_GPT4_CLK_ROOT 145, 2
698#define CCM_OBS_GPT5_CLK_ROOT 146, 2
699#define CCM_OBS_GPT6_CLK_ROOT 147, 2
700#define CCM_OBS_FLEXSPI1_CLK_ROOT 148, 2
701#define CCM_OBS_FLEXSPI2_CLK_ROOT 149, 2
702#define CCM_OBS_CAN1_CLK_ROOT 150, 2
703#define CCM_OBS_CAN2_CLK_ROOT 151, 2
704#define CCM_OBS_CAN3_CLK_ROOT 152, 0
705#define CCM_OBS_LPUART1_CLK_ROOT 153, 2
706#define CCM_OBS_LPUART2_CLK_ROOT 154, 2
707#define CCM_OBS_LPUART3_CLK_ROOT 155, 2
708#define CCM_OBS_LPUART4_CLK_ROOT 156, 2
709#define CCM_OBS_LPUART5_CLK_ROOT 157, 2
710#define CCM_OBS_LPUART6_CLK_ROOT 158, 2
711#define CCM_OBS_LPUART7_CLK_ROOT 159, 2
712#define CCM_OBS_LPUART8_CLK_ROOT 160, 2
713#define CCM_OBS_LPUART9_CLK_ROOT 161, 2
714#define CCM_OBS_LPUART10_CLK_ROOT 162, 2
715#define CCM_OBS_LPUART11_CLK_ROOT 163, 0
716#define CCM_OBS_LPUART12_CLK_ROOT 164, 0
717#define CCM_OBS_LPI2C1_CLK_ROOT 165, 2
718#define CCM_OBS_LPI2C2_CLK_ROOT 166, 2
719#define CCM_OBS_LPI2C3_CLK_ROOT 167, 2
720#define CCM_OBS_LPI2C4_CLK_ROOT 168, 2
721#define CCM_OBS_LPI2C5_CLK_ROOT 169, 0
722#define CCM_OBS_LPI2C6_CLK_ROOT 170, 0
723#define CCM_OBS_LPSPI1_CLK_ROOT 171, 2
724#define CCM_OBS_LPSPI2_CLK_ROOT 172, 2
725#define CCM_OBS_LPSPI3_CLK_ROOT 173, 2
726#define CCM_OBS_LPSPI4_CLK_ROOT 174, 2
727#define CCM_OBS_LPSPI5_CLK_ROOT 175, 0
728#define CCM_OBS_LPSPI6_CLK_ROOT 176, 0
729#define CCM_OBS_EMV1_CLK_ROOT 177, 2
730#define CCM_OBS_EMV2_CLK_ROOT 178, 2
731#define CCM_OBS_ENET1_CLK_ROOT 179, 2
732#define CCM_OBS_ENET2_CLK_ROOT 180, 2
733#define CCM_OBS_ENET_25M_CLK_ROOT 182, 2
734#define CCM_OBS_ENET_TIMER1_CLK_ROOT 183, 2
735#define CCM_OBS_ENET_TIMER2_CLK_ROOT 184, 2
736#define CCM_OBS_USDHC1_CLK_ROOT 186, 2
737#define CCM_OBS_USDHC2_CLK_ROOT 187, 2
738#define CCM_OBS_ASRC_CLK_ROOT 188, 2
739#define CCM_OBS_MQS_CLK_ROOT 189, 2
740#define CCM_OBS_MIC_CLK_ROOT 190, 0
741#define CCM_OBS_SPDIF_CLK_ROOT 191, 2
742#define CCM_OBS_SAI1_CLK_ROOT 192, 2
743#define CCM_OBS_SAI2_CLK_ROOT 193, 2
744#define CCM_OBS_SAI3_CLK_ROOT 194, 2
745#define CCM_OBS_SAI4_CLK_ROOT 195, 0
746#define CCM_OBS_GC355_CLK_ROOT 196, 2
747#define CCM_OBS_LCDIF_CLK_ROOT 197, 2
748#define CCM_OBS_LCDIFV2_CLK_ROOT 198, 2
749#define CCM_OBS_MIPI_REF_CLK_ROOT 199, 2
750#define CCM_OBS_MIPI_ESC_CLK_ROOT 200, 2
751#define CCM_OBS_CSI2_CLK_ROOT 201, 2
752#define CCM_OBS_CSI2_ESC_CLK_ROOT 202, 2
753#define CCM_OBS_CSI2_UI_CLK_ROOT 203, 2
754#define CCM_OBS_CSI_CLK_ROOT 204, 2
755#define CCM_OBS_CCM_CKO1_CLK_ROOT 205, 0
756#define CCM_OBS_CCM_CKO2_CLK_ROOT 206, 2
757#define CCM_OBS_CM7_CORE_STCLKEN 207, 4
758#define CCM_OBS_CCM_FLEXRAM_CLK_ROOT 208, 4
759#define CCM_OBS_MIPI_DSI_TXESC 209, 2
760#define CCM_OBS_MIPI_DSI_RXESC 210, 2
761#define CCM_OBS_OSC_RC_16M 224, 0
762#define CCM_OBS_OSC_RC_48M 225, 0
763#define CCM_OBS_OSC_RC_48M_DIV2 226, 0
764#define CCM_OBS_OSC_RC_400M 227, 0
765#define CCM_OBS_OSC_24M_OUT 229, 0
766#define CCM_OBS_ARM_PLL_OUT 231, 2
767#define CCM_OBS_SYS_PLL2_OUT 233, 2
768#define CCM_OBS_SYS_PLL2_PFD0 234, 2
769#define CCM_OBS_SYS_PLL2_PFD1 235, 2
770#define CCM_OBS_SYS_PLL2_PFD2 236, 2
771#define CCM_OBS_SYS_PLL2_PFD3 237, 2
772#define CCM_OBS_SYS_PLL3_OUT 239, 2
773#define CCM_OBS_SYS_PLL3_DIV2 240, 2
774#define CCM_OBS_SYS_PLL3_PFD0 241, 2
775#define CCM_OBS_SYS_PLL3_PFD1 242, 2
776#define CCM_OBS_SYS_PLL3_PFD2 243, 2
777#define CCM_OBS_SYS_PLL3_PFD3 244, 2
778#define CCM_OBS_SYS_PLL1_OUT 246, 2
779#define CCM_OBS_SYS_PLL1_DIV2 247, 2
780#define CCM_OBS_SYS_PLL1_DIV5 248, 2
781#define CCM_OBS_PLL_AUDIO_OUT 250, 2
782#define CCM_OBS_PLL_VIDEO_OUT 252, 2
783
784#define CCM_OBS_DIV 3
785
786/* Clock Source Definitions */
787/* clang-format off */
788static const clock_name_t s_clockSourceName[][8] = {
789 /*SRC0, SRC1, SRC2, SRC3, SRC4, SRC5, SRC6, SRC7, name index */ \
869};
870/* clang-format on */
871
876typedef enum _clock_root
877{
956
961{
962 /* M7 */
970 /* M4 */
980 /* BUS */
990 /* BUS_LPSR */
1000 /* SEMC */
1010 /* CSSYS */
1020 /* CSTRACE */
1030 /* M4_SYSTICK */
1040 /* M7_SYSTICK */
1050 /* ADC1 */
1060 /* ADC2 */
1070 /* ACMP */
1080 /* FLEXIO1 */
1090 /* FLEXIO2 */
1100 /* GPT1 */
1110 /* GPT2 */
1120 /* GPT3 */
1130 /* GPT4 */
1140 /* GPT5 */
1150 /* GPT6 */
1160 /* FLEXSPI1 */
1170 /* FLEXSPI2 */
1180 /* CAN1 */
1190 /* CAN2 */
1200 /* CAN3 */
1210 /* LPUART1 */
1220 /* LPUART2 */
1230 /* LPUART3 */
1240 /* LPUART4 */
1250 /* LPUART5 */
1260 /* LPUART6 */
1270 /* LPUART7 */
1280 /* LPUART8 */
1290 /* LPUART9 */
1300 /* LPUART10 */
1310 /* LPUART11 */
1320 /* LPUART12 */
1330 /* LPI2C1 */
1340 /* LPI2C2 */
1350 /* LPI2C3 */
1360 /* LPI2C4 */
1370 /* LPI2C5 */
1380 /* LPI2C6 */
1390 /* LPSPI1 */
1400 /* LPSPI2 */
1410 /* LPSPI3 */
1420 /* LPSPI4 */
1430 /* LPSPI5 */
1440 /* LPSPI6 */
1450 /* EMV1 */
1460 /* EMV2 */
1470 /* ENET1 */
1480 /* ENET2 */
1490 /* ENET_25M */
1500 /* ENET_TIMER1 */
1510 /* ENET_TIMER2 */
1520 /* USDHC1 */
1530 /* USDHC2 */
1540 /* ASRC */
1550 /* MQS */
1560 /* MIC */
1570 /* SPDIF */
1580 /* SAI1 */
1590 /* SAI2 */
1600 /* SAI3 */
1610 /* SAI4 */
1620 /* GC355 */
1630 /* LCDIF */
1640 /* LCDIFV2 */
1650 /* MIPI_REF */
1660 /* MIPI_ESC */
1670 /* CSI2 */
1680 /* CSI2_ESC */
1690 /* CSI2_UI */
1700 /* CSI */
1710 /* CKO1 */
1720 /* CKO2 */
1730
1734typedef enum _clock_group
1735{
1740
1745{
1747 uint16_t resetDiv;
1748 uint8_t div0;
1750
1751#define clock_ip_name_t clock_lpcg_t
1752
1753#if (__CORTEX_M == 7)
1754#define CLOCK_GetCpuClkFreq CLOCK_GetM7Freq
1755#else
1756#define CLOCK_GetCpuClkFreq CLOCK_GetM4Freq
1757#endif
1758
1759#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq
1761/* uncomment the following line if want to use OBS to retrieve frequency */
1762/* #define GET_FREQ_FROM_OBS */
1763
1765typedef enum _clock_osc
1766{
1770
1773{
1774 kCLOCK_Off = (int)~CCM_LPCG_DIRECT_ON_MASK,
1775 kCLOCK_On = CCM_LPCG_DIRECT_ON_MASK,
1777
1779typedef enum _clock_mode_t
1780{
1785
1787typedef enum _clock_usb_src
1788{
1790 kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU,
1793
1796{
1799
1802{
1805};
1806
1811{
1815
1825typedef struct _clock_arm_pll_config
1826{
1828 uint32_t loopDivider;
1830
1832typedef struct _clock_usb_pll_config
1833{
1834 uint8_t loopDivider;
1837 uint8_t src;
1840
1843{
1844 uint16_t stop;
1845 uint16_t step;
1847
1850{
1851 uint32_t mfd;
1856
1859{
1866
1868typedef struct _clock_audio_pll_config
1869{
1870 uint8_t loopDivider;
1871 uint8_t postDivider;
1873 uint32_t numerator;
1874 uint32_t denominator;
1879
1884{
1885 uint8_t loopDivider;
1886 uint32_t numerator;
1887 uint32_t denominator;
1892
1894typedef struct _clock_enet_pll_config
1895{
1896 bool enableClkOutput;
1897 bool enableClkOutput25M;
1898 uint8_t loopDivider;
1903 uint8_t src;
1911
1914{
1915 bool clockOff;
1916 uint8_t mux;
1917 uint8_t div;
1919
1922{
1923 uint8_t grade;
1924 bool clockOff;
1925 uint8_t mux;
1926 uint8_t div;
1928
1930typedef enum _clock_pll
1931{
1940
1941#define PLL_PFD_COUNT 4
1943typedef enum _clock_pfd
1944{
1950
1956{
1960
1965{
1970
1975{
1979
1985{
1991
1995typedef enum _clock_level
1996{
2003
2004/*******************************************************************************
2005 * API
2006 ******************************************************************************/
2007
2008#if defined(__cplusplus)
2009extern "C" {
2010#endif /* __cplusplus */
2011
2018static inline void CLOCK_SetRootClockMux(clock_root_t root, uint8_t src)
2019{
2020 assert(src < 8U);
2021 CCM->CLOCK_ROOT[root].CONTROL =
2022 (CCM->CLOCK_ROOT[root].CONTROL & ~(CCM_CLOCK_ROOT_CONTROL_MUX_MASK)) | CCM_CLOCK_ROOT_CONTROL_MUX(src);
2023 __DSB();
2024 __ISB();
2025#if __CORTEX_M == 4
2026 (void)CCM->CLOCK_ROOT[root].CONTROL;
2027#endif
2028}
2029
2036static inline uint32_t CLOCK_GetRootClockMux(clock_root_t root)
2037{
2038 return (CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_MUX_MASK) >> CCM_CLOCK_ROOT_CONTROL_MUX_SHIFT;
2039}
2040
2048static inline clock_name_t CLOCK_GetRootClockSource(clock_root_t root, uint32_t src)
2049{
2050 return s_clockSourceName[root][src];
2051}
2052
2059static inline void CLOCK_SetRootClockDiv(clock_root_t root, uint32_t div)
2060{
2061 assert(div);
2062 CCM->CLOCK_ROOT[root].CONTROL = (CCM->CLOCK_ROOT[root].CONTROL & ~CCM_CLOCK_ROOT_CONTROL_DIV_MASK) |
2063 CCM_CLOCK_ROOT_CONTROL_DIV((uint32_t)div - 1UL);
2064 __DSB();
2065 __ISB();
2066#if __CORTEX_M == 4
2067 (void)CCM->CLOCK_ROOT[root].CONTROL;
2068#endif
2069}
2070
2077static inline uint32_t CLOCK_GetRootClockDiv(clock_root_t root)
2078{
2079 return ((CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_DIV_MASK) >> CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT) +
2080 1UL;
2081}
2082
2088static inline void CLOCK_PowerOffRootClock(clock_root_t root)
2089{
2090 if (0UL == (CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_OFF_MASK))
2091 {
2092 CCM->CLOCK_ROOT[root].CONTROL_SET = CCM_CLOCK_ROOT_CONTROL_OFF_MASK;
2093 __DSB();
2094 __ISB();
2095#if __CORTEX_M == 4
2096 (void)CCM->CLOCK_ROOT[root].CONTROL;
2097#endif
2098 }
2099}
2100
2106static inline void CLOCK_PowerOnRootClock(clock_root_t root)
2107{
2108 CCM->CLOCK_ROOT[root].CONTROL_CLR = CCM_CLOCK_ROOT_CONTROL_OFF_MASK;
2109 __DSB();
2110 __ISB();
2111#if __CORTEX_M == 4
2112 (void)CCM->CLOCK_ROOT[root].CONTROL;
2113#endif
2114}
2115
2122static inline void CLOCK_SetRootClock(clock_root_t root, const clock_root_config_t *config)
2123{
2124 assert(config);
2125 CCM->CLOCK_ROOT[root].CONTROL = CCM_CLOCK_ROOT_CONTROL_MUX(config->mux) |
2126 CCM_CLOCK_ROOT_CONTROL_DIV((uint32_t)config->div - 1UL) |
2127 (config->clockOff ? CCM_CLOCK_ROOT_CONTROL_OFF(config->clockOff) : 0UL);
2128 __DSB();
2129 __ISB();
2130#if __CORTEX_M == 4
2131 (void)CCM->CLOCK_ROOT[root].CONTROL;
2132#endif
2133}
2134
2143static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value)
2144{
2145 if (((uint32_t)value & CCM_LPCG_DIRECT_ON_MASK) != (CCM->LPCG[name].DIRECT & CCM_LPCG_DIRECT_ON_MASK))
2146 {
2147 CCM->LPCG[name].DIRECT = ((uint32_t)value & CCM_LPCG_DIRECT_ON_MASK);
2148 __DSB();
2149 __ISB();
2150
2151 while ((CCM->LPCG[name].STATUS0 & CCM_LPCG_STATUS0_ON_MASK) != ((uint32_t)value & CCM_LPCG_STATUS0_ON_MASK))
2152 {
2153 }
2154 }
2155}
2156
2162static inline void CLOCK_EnableClock(clock_ip_name_t name)
2163{
2164 CLOCK_ControlGate(name, kCLOCK_On);
2165}
2166
2172static inline void CLOCK_DisableClock(clock_ip_name_t name)
2173{
2174 CLOCK_ControlGate(name, kCLOCK_Off);
2175}
2176
2184
2194uint32_t CLOCK_GetFreq(clock_name_t name);
2195
2205static inline uint32_t CLOCK_GetRootClockFreq(clock_root_t root)
2206{
2207 uint32_t freq, mux;
2208 mux = CLOCK_GetRootClockMux(root);
2209 freq = CLOCK_GetFreq(s_clockSourceName[root][mux]) / (CLOCK_GetRootClockDiv(root));
2210 assert(freq);
2211 return freq;
2212}
2213
2219static inline uint32_t CLOCK_GetM7Freq(void)
2220{
2221 return CLOCK_GetRootClockFreq(kCLOCK_Root_M7);
2222}
2223
2229static inline uint32_t CLOCK_GetM4Freq(void)
2230{
2231 return CLOCK_GetRootClockFreq(kCLOCK_Root_M4);
2232}
2233
2242static inline bool CLOCK_IsPllBypassed(clock_pll_t pll)
2243{
2244 if (pll == kCLOCK_PllArm)
2245 {
2246 return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK) >>
2247 ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT);
2248 }
2249 else if (pll == kCLOCK_PllSys2)
2250 {
2251 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >>
2252 ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT);
2253 }
2254 else if (pll == kCLOCK_PllSys3)
2255 {
2256 return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK) >>
2257 ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT);
2258 }
2259 else
2260 {
2261 return false;
2262 }
2263}
2264
2273static inline bool CLOCK_IsPllEnabled(clock_pll_t pll)
2274{
2275 if (pll == kCLOCK_PllArm)
2276 {
2277 return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) >>
2278 ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT);
2279 }
2280 else if (pll == kCLOCK_PllSys2)
2281 {
2282 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >>
2283 ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT);
2284 }
2285 else if (pll == kCLOCK_PllSys3)
2286 {
2287 return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK) >>
2288 ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT);
2289 }
2290 else if (pll == kCLOCK_PllSys1)
2291 {
2292 return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >>
2293 ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT);
2294 }
2295 else if (pll == kCLOCK_PllAudio)
2296 {
2297 return (bool)((ANADIG_PLL->PLL_AUDIO_CTRL & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK) >>
2298 ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT);
2299 }
2300 else if (pll == kCLOCK_PllVideo)
2301 {
2302 return (bool)((ANADIG_PLL->PLL_VIDEO_CTRL & ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK) >>
2303 ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT);
2304 }
2305 else
2306 {
2307 return false;
2308 }
2309}
2310
2321static inline uint32_t CLOCK_GetRtcFreq(void)
2322{
2323 return 32768U;
2324}
2325
2331static inline void CLOCK_OSC_SetOsc48MControlMode(clock_control_mode_t controlMode)
2332{
2333 ANADIG_OSC->OSC_48M_CTRL = (ANADIG_OSC->OSC_48M_CTRL & ~(ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK)) |
2335}
2336
2344static inline void CLOCK_OSC_EnableOsc48M(bool enable)
2345{
2346 if (enable)
2347 {
2348 ANADIG_OSC->OSC_48M_CTRL |= ANADIG_OSC_OSC_48M_CTRL_TEN_MASK;
2349 }
2350 else
2351 {
2352 ANADIG_OSC->OSC_48M_CTRL &= ~ANADIG_OSC_OSC_48M_CTRL_TEN_MASK;
2353 }
2354}
2355
2361static inline void CLOCK_OSC_SetOsc48MDiv2ControlMode(clock_control_mode_t controlMode)
2362{
2363 ANADIG_OSC->OSC_48M_CTRL = (ANADIG_OSC->OSC_48M_CTRL & ~(ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK)) |
2365}
2366
2376static inline void CLOCK_OSC_EnableOsc48MDiv2(bool enable)
2377{
2378 if (enable)
2379 {
2380 ANADIG_OSC->OSC_48M_CTRL |= ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK;
2381 }
2382 else
2383 {
2384 ANADIG_OSC->OSC_48M_CTRL &= ~ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK;
2385 }
2386}
2387
2393static inline void CLOCK_OSC_SetOsc24MControlMode(clock_control_mode_t controlMode)
2394{
2395 ANADIG_OSC->OSC_24M_CTRL = (ANADIG_OSC->OSC_24M_CTRL & ~(ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK)) |
2397}
2398
2403void CLOCK_OSC_EnableOsc24M(void);
2404
2414static inline void CLOCK_OSC_GateOsc24M(bool enableGate)
2415{
2416 if (enableGate)
2417 {
2418 ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK;
2419 }
2420 else
2421 {
2422 ANADIG_OSC->OSC_24M_CTRL &= ~ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK;
2423 }
2424}
2425
2433
2439static inline void CLOCK_OSC_SetOscRc400MControlMode(clock_control_mode_t controlMode)
2440{
2441 ANADIG_OSC->OSC_400M_CTRL1 = (ANADIG_OSC->OSC_400M_CTRL1 & (~ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK)) |
2443}
2444
2449void CLOCK_OSC_EnableOscRc400M(void);
2450
2458static inline void CLOCK_OSC_GateOscRc400M(bool enableGate)
2459{
2460 if (enableGate)
2461 {
2462 ANADIG_OSC->OSC_400M_CTRL1 |= ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK;
2463 }
2464 else
2465 {
2466 ANADIG_OSC->OSC_400M_CTRL1 &= ~ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK;
2467 }
2468}
2469
2477void CLOCK_OSC_TrimOscRc400M(bool enable, bool bypass, uint16_t trim);
2478
2486void CLOCK_OSC_SetOscRc400MRefClkDiv(uint8_t divValue);
2487
2494void CLOCK_OSC_SetOscRc400MFastClkCount(uint16_t targetCount);
2495
2506void CLOCK_OSC_SetOscRc400MHysteresisValue(uint8_t negHysteresis, uint8_t posHysteresis);
2507
2516void CLOCK_OSC_BypassOscRc400MTuneLogic(bool enableBypass);
2517
2525void CLOCK_OSC_EnableOscRc400MTuneLogic(bool enable);
2526
2534void CLOCK_OSC_FreezeOscRc400MTuneValue(bool enableFreeze);
2535
2541void CLOCK_OSC_SetOscRc400MTuneValue(uint8_t tuneValue);
2542
2552
2559void CLOCK_OSC_SetLocked1MHzCount(uint16_t count);
2560
2569
2574
2581
2588
2594static inline void CLOCK_OSC_SetOsc16MControlMode(clock_control_mode_t controlMode)
2595{
2596 ANADIG_OSC->OSC_16M_CTRL = (ANADIG_OSC->OSC_16M_CTRL & (~ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK)) |
2598}
2599
2611void CLOCK_OSC_SetOsc16MConfig(clock_16MOsc_source_t source, bool enablePowerSave, bool enableClockOut);
2612
2613/* @} */
2614
2623
2633
2641status_t CLOCK_InitArmPllWithFreq(uint32_t freqInMhz);
2642
2646void CLOCK_DeinitArmPll(void);
2647
2661void CLOCK_CalcPllSpreadSpectrum(uint32_t factor, uint32_t range, uint32_t mod, clock_pll_ss_config_t *ss);
2662
2671
2675void CLOCK_DeinitSysPll1(void);
2676
2683
2693
2697void CLOCK_DeinitSysPll2(void);
2698
2709
2716void CLOCK_InitSysPll3(void);
2717
2721void CLOCK_DeinitSysPll3(void);
2722
2733
2746void CLOCK_SetPllBypass(clock_pll_t pll, bool bypass);
2747
2758
2769status_t CLOCK_InitAudioPllWithFreq(uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod);
2770
2779
2783void CLOCK_DeinitAudioPll(void);
2784
2791
2802status_t CLOCK_InitVideoPllWithFreq(uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod);
2803
2812
2816void CLOCK_DeinitVideoPll(void);
2817
2832uint32_t CLOCK_GetPllFreq(clock_pll_t pll);
2833
2845void CLOCK_InitPfd(clock_pll_t pll, clock_pfd_t pfd, uint8_t frac);
2846
2854
2864uint32_t CLOCK_GetPfdFreq(clock_pll_t pll, clock_pfd_t pfd);
2865
2866uint32_t CLOCK_GetFreqFromObs(uint32_t obsSigIndex, uint32_t obsIndex);
2867
2879bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
2880
2892bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq);
2893
2903bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
2904
2910
2920bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
2921
2927
2935static inline void CLOCK_OSCPLL_LockControlMode(clock_name_t name)
2936{
2937 CCM->OSCPLL[name].AUTHEN |= CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK;
2938}
2939
2947static inline void CLOCK_OSCPLL_LockWhiteList(clock_name_t name)
2948{
2949 CCM->OSCPLL[name].AUTHEN |= CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK;
2950}
2951
2960static inline void CLOCK_OSCPLL_SetWhiteList(clock_name_t name, uint8_t domainId)
2961{
2962 CCM->OSCPLL[name].AUTHEN =
2963 (CCM->OSCPLL[name].AUTHEN & ~CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK) | CCM_OSCPLL_AUTHEN_WHITE_LIST(domainId);
2964}
2965
2974static inline bool CLOCK_OSCPLL_IsSetPointImplemented(clock_name_t name)
2975{
2976 return (((CCM->OSCPLL[name].CONFIG & CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_MASK) >>
2977 CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_SHIFT) != 0UL);
2978}
2979
2987static inline void CLOCK_OSCPLL_ControlByUnassignedMode(clock_name_t name)
2988{
2989 CCM->OSCPLL[name].AUTHEN &=
2990 ~(CCM_OSCPLL_AUTHEN_CPULPM_MASK | CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK | CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK);
2991}
2992
3006void CLOCK_OSCPLL_ControlBySetPointMode(clock_name_t name, uint16_t spValue, uint16_t stbyValue);
3007
3018 uint8_t domainId,
3019 clock_level_t level0,
3020 clock_level_t level1);
3021
3030static inline void CLOCK_OSCPLL_SetCurrentClockLevel(clock_name_t name, clock_level_t level)
3031{
3032 CCM->OSCPLL[name].DOMAINr =
3033 (CCM->OSCPLL[name].DOMAINr & ~CCM_OSCPLL_DOMAIN_LEVEL_MASK) | CCM_OSCPLL_DOMAIN_LEVEL(level);
3034}
3035
3044static inline void CLOCK_OSCPLL_ControlByDomainMode(clock_name_t name, uint8_t domainId)
3045{
3046 CCM->OSCPLL[name].AUTHEN =
3047 (CCM->OSCPLL[name].AUTHEN &
3048 ~(CCM_OSCPLL_AUTHEN_CPULPM_MASK | CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK | CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK)) |
3049 CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK | CCM_OSCPLL_AUTHEN_WHITE_LIST(domainId);
3050}
3051
3059static inline void CLOCK_ROOT_LockControlMode(clock_root_t name)
3060{
3061 CCM->CLOCK_ROOT[name].AUTHEN |= CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_MASK;
3062}
3063
3071static inline void CLOCK_ROOT_LockWhiteList(clock_root_t name)
3072{
3073 CCM->CLOCK_ROOT[name].AUTHEN |= CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK;
3074}
3075
3084static inline void CLOCK_ROOT_SetWhiteList(clock_root_t name, uint8_t domainId)
3085{
3086 CCM->CLOCK_ROOT[name].AUTHEN = (CCM->CLOCK_ROOT[name].AUTHEN & ~CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK) |
3088}
3089
3098static inline bool CLOCK_ROOT_IsSetPointImplemented(clock_root_t name)
3099{
3100 return (((CCM->CLOCK_ROOT[name].CONFIG & CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_MASK) >>
3101 CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_SHIFT) != 0UL);
3102}
3103
3111static inline void CLOCK_ROOT_ControlByUnassignedMode(clock_root_t name)
3112{
3113 CCM->CLOCK_ROOT[name].AUTHEN &=
3114 ~(CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK | CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK);
3115}
3116
3126static inline void CLOCK_ROOT_ConfigSetPoint(clock_root_t name,
3127 uint16_t spIndex,
3129{
3130 assert(config != NULL);
3131 CCM->CLOCK_ROOT[name].SETPOINT[spIndex] =
3136}
3137
3145static inline void CLOCK_ROOT_EnableSetPointControl(clock_root_t name)
3146{
3147 CCM->CLOCK_ROOT[name].AUTHEN = (CCM->CLOCK_ROOT[name].AUTHEN & ~CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK) |
3148 CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK;
3149}
3150
3161
3170static inline void CLOCK_ROOT_ControlByDomainMode(clock_root_t name, uint8_t domainId)
3171{
3172 CCM->CLOCK_ROOT[name].AUTHEN = (CCM->CLOCK_ROOT[name].AUTHEN & ~(CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK |
3173 CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK)) |
3174 CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK | CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST(domainId);
3175}
3176
3184static inline void CLOCK_LPCG_LockControlMode(clock_lpcg_t name)
3185{
3186 CCM->LPCG[name].AUTHEN |= CCM_LPCG_AUTHEN_LOCK_MODE_MASK;
3187}
3188
3196static inline void CLOCK_LPCG_LockWhiteList(clock_lpcg_t name)
3197{
3198 CCM->LPCG[name].AUTHEN |= CCM_LPCG_AUTHEN_LOCK_LIST_MASK;
3199}
3200
3209static inline void CLOCK_LPCG_SetWhiteList(clock_lpcg_t name, uint8_t domainId)
3210{
3211 CCM->LPCG[name].AUTHEN =
3212 (CCM->LPCG[name].AUTHEN & ~CCM_LPCG_AUTHEN_WHITE_LIST_MASK) | CCM_LPCG_AUTHEN_WHITE_LIST(domainId);
3213}
3214
3223static inline bool CLOCK_LPCG_IsSetPointImplemented(clock_lpcg_t name)
3224{
3225 return (((CCM->LPCG[name].CONFIG & CCM_LPCG_CONFIG_SETPOINT_PRESENT_MASK) >>
3226 CCM_LPCG_CONFIG_SETPOINT_PRESENT_SHIFT) != 0UL);
3227}
3228
3236static inline void CLOCK_LPCG_ControlByUnassignedMode(clock_lpcg_t name)
3237{
3238 CCM->LPCG[name].AUTHEN &=
3239 ~(CCM_LPCG_AUTHEN_CPULPM_MASK | CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK | CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK);
3240}
3241
3255void CLOCK_LPCG_ControlBySetPointMode(clock_lpcg_t name, uint16_t spValue, uint16_t stbyValue);
3256
3267 uint8_t domainId,
3268 clock_level_t level0,
3269 clock_level_t level1);
3270
3279static inline void CLOCK_LPCG_SetCurrentClockLevel(clock_lpcg_t name, clock_level_t level)
3280{
3281 CCM->LPCG[name].DOMAINr = (CCM->LPCG[name].DOMAINr & ~CCM_LPCG_DOMAIN_LEVEL_MASK) | CCM_LPCG_DOMAIN_LEVEL(level);
3282}
3283
3292static inline void CLOCK_LPCG_ControlByDomainMode(clock_lpcg_t name, uint8_t domainId)
3293{
3294 CCM->LPCG[name].AUTHEN =
3295 (CCM->LPCG[name].AUTHEN &
3296 ~(CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK | CCM_LPCG_AUTHEN_CPULPM_MASK | CCM_LPCG_AUTHEN_WHITE_LIST_MASK)) |
3297 CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK | CCM_LPCG_AUTHEN_WHITE_LIST(domainId);
3298}
3299
3300/* @} */
3301
3302#if defined(__cplusplus)
3303}
3304#endif /* __cplusplus */
3305
3308#endif /* _FSL_CLOCK_H_ */
#define ANADIG_OSC
Definition: MIMXRT1166_cm4.h:5211
#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE(x)
Definition: MIMXRT1166_cm4.h:5098
#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE(x)
Definition: MIMXRT1166_cm4.h:5024
#define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE(x)
Definition: MIMXRT1166_cm4.h:5136
#define ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE(x)
Definition: MIMXRT1166_cm4.h:5198
#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE(x)
Definition: MIMXRT1166_cm4.h:5032
#define ANADIG_PLL
Definition: MIMXRT1166_cm4.h:6164
#define CCM
Definition: MIMXRT1052.h:7185
#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE(x)
Definition: MIMXRT1166_cm4.h:21096
#define CCM_CLOCK_ROOT_CONTROL_MUX(x)
Definition: MIMXRT1166_cm4.h:20611
#define CCM_OSCPLL_AUTHEN_WHITE_LIST(x)
Definition: MIMXRT1166_cm4.h:23966
#define CCM_LPCG_AUTHEN_WHITE_LIST(x)
Definition: MIMXRT1166_cm4.h:24371
#define CCM_LPCG_DOMAIN_LEVEL(x)
Definition: MIMXRT1166_cm4.h:24038
#define CCM_CLOCK_ROOT_CONTROL_OFF(x)
Definition: MIMXRT1166_cm4.h:20619
#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF(x)
Definition: MIMXRT1166_cm4.h:21090
#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX(x)
Definition: MIMXRT1166_cm4.h:21082
#define CCM_CLOCK_ROOT_CONTROL_DIV(x)
Definition: MIMXRT1166_cm4.h:20605
#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV(x)
Definition: MIMXRT1166_cm4.h:21076
#define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST(x)
Definition: MIMXRT1166_cm4.h:20866
#define CCM_OSCPLL_DOMAIN_LEVEL(x)
Definition: MIMXRT1166_cm4.h:23569
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:286
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:275
enum _clock_ip_name clock_ip_name_t
CCM CCGR gate control for each module independently.
uint8_t loopDivider
Definition: fsl_clock.h:1251
uint32_t denominator
Definition: fsl_clock.h:1230
enum _clock_1MHzOut_behavior clock_1MHzOut_behavior_t
The enumeration of 1MHz output clock behavior, including disabling 1MHz output, enabling locked 1MHz ...
void CLOCK_CalcPllSpreadSpectrum(uint32_t factor, uint32_t range, uint32_t mod, clock_pll_ss_config_t *ss)
Calculate spread spectrum step and stop.
Definition: fsl_clock.c:184
uint32_t loopDivider
Definition: fsl_clock.h:1195
clock_pll_ss_config_t * ss
Definition: fsl_clock.h:1862
struct _clock_video_pll_config clock_video_pll_config_t
PLL configuration for AUDIO and VIDEO.
uint32_t numerator
Definition: fsl_clock.h:1886
enum _clock_mode_t clock_mode_t
System clock mode.
_clock_name
Clock name used to get clock frequency.
Definition: fsl_clock.h:464
struct _clock_sys_pll2_config clock_sys_pll2_config_t
PLL configure for Sys Pll2.
_clock_24MOsc_mode
The enumeration of 24MHz crystal oscillator mode.
Definition: fsl_clock.h:1965
void CLOCK_InitSysPll1(const clock_sys_pll1_config_t *config)
Initialize the System PLL1.
Definition: fsl_clock.c:1032
_clock_osc
OSC 24M sorce select.
Definition: fsl_clock.h:642
status_t CLOCK_CalcAvPllFreq(clock_av_pll_config_t *config, uint32_t freqInMhz)
Calculate corresponding config values per given frequency.
Definition: fsl_clock.c:806
bool clockOff
Definition: fsl_clock.h:1746
_clock_control_mode
The enumeration of control mode.
Definition: fsl_clock.h:1956
enum _clock_name clock_name_t
Clock name used to get clock frequency.
void CLOCK_OSC_SetOsc24MWorkMode(clock_24MOsc_mode_t workMode)
Set the work mode of 24MHz crystal oscillator, the available modes are high gian mode,...
Definition: fsl_clock.c:1123
_clock_root
The enumerator of clock root.
Definition: fsl_clock.h:1344
struct _clock_audio_pll_gpc_config clock_audio_pll_gpc_config_t
PLL configuration fro AUDIO PLL, SYSTEM PLL1 and VIDEO PLL.
enum _clock_gate_value clock_gate_value_t
Clock gate value.
uint16_t CLOCK_OSC_GetCurrentOscRc400MFastClockCount(void)
Get current count for the fast clock during the tune process.
Definition: fsl_clock.c:1365
void CLOCK_OSC_EnableOscRc400M(void)
Enable OSC RC 400Mhz.
Definition: fsl_clock.c:1614
enum _clock_usb_src clock_usb_src_t
USB clock source definition.
bool enableClkOutput25M
Definition: fsl_clock.h:1250
bool CLOCK_OSC_CheckLocked1MHzErrorFlag(void)
Check the error flag for locked 1MHz clock out.
Definition: fsl_clock.c:1343
bool pllDiv2En
Definition: fsl_clock.h:1860
_clock_pfd
PLL PFD name.
Definition: fsl_clock.h:1279
void CLOCK_OSC_SetOscRc400MFastClkCount(uint16_t targetCount)
Set the target count for the fast clock.
Definition: fsl_clock.c:1179
uint32_t denominator
Definition: fsl_clock.h:1887
bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq)
Enable USB HS clock.
Definition: fsl_clock.c:515
void CLOCK_OSC_ClearLocked1MHzErrorFlag(void)
Clear the error flag for locked 1MHz clock out.
Definition: fsl_clock.c:1355
uint8_t loopDivider1
Definition: fsl_clock.h:1905
struct _clock_root_config_t clock_root_config_t
Clock root configuration.
uint8_t div
Definition: fsl_clock.h:1917
enum _clock_control_mode clock_control_mode_t
The enumeration of control mode.
void CLOCK_InitPfd(clock_pll_t pll, clock_pfd_t pfd, uint8_t frac)
Initialize PLL PFD.
Definition: fsl_clock.c:303
bool enableClkOutput1
Definition: fsl_clock.h:1904
bool pllDiv5En
Definition: fsl_clock.h:1861
enum _clock_usb_phy_src clock_usb_phy_src_t
Source of the USB HS PHY.
uint8_t div0
Definition: fsl_clock.h:1748
enum _clock_root clock_root_t
The enumerator of clock root.
void CLOCK_InitVideoPll(const clock_video_pll_config_t *config)
Initialize the video PLL.
Definition: fsl_clock.c:805
void CLOCK_GPC_SetAudioPllOutputFreq(const clock_audio_pll_gpc_config_t *config)
Set Audio PLL output frequency in GPC mode.
Definition: fsl_clock.c:722
_clock_16MOsc_source
The enumeration of 16MHz RC oscillator clock source.
Definition: fsl_clock.h:1975
struct _clock_audio_pll_config clock_av_pll_config_t
PLL configuration for AUDIO and VIDEO.
void CLOCK_OSC_EnableOscRc400MTuneLogic(bool enable)
Start/Stop the tune logic.
Definition: fsl_clock.c:1235
struct _clock_arm_pll_config clock_arm_pll_config_t
PLL configuration for ARM.
uint16_t resetDiv
Definition: fsl_clock.h:1747
uint16_t stop
Definition: fsl_clock.h:1844
bool CLOCK_IsSysPll3PfdEnabled(clock_pfd_t pfd)
Check if Sys PLL3 PFD is enabled.
Definition: fsl_clock.c:518
void CLOCK_SetPllBypass(clock_pll_t pll, bool bypass)
PLL bypass setting.
Definition: fsl_clock.c:524
void CLOCK_OSC_BypassOscRc400MTuneLogic(bool enableBypass)
Bypass/un-bypass the tune logic.
Definition: fsl_clock.c:1216
void CLOCK_OSC_SetOscRc400MTuneValue(uint8_t tuneValue)
Set the 400MHz RC oscillator tune value when the tune logic is disabled.
Definition: fsl_clock.c:1271
enum _clock_pfd clock_pfd_t
PLL PFD name.
enum _clock_root_mux_source clock_root_mux_source_t
The enumerator of clock roots' clock source mux value.
clock_pll_post_div_t postDivider
Definition: fsl_clock.h:1827
clock_pll_ss_config_t * ss
Definition: fsl_clock.h:1888
void CLOCK_OSCPLL_ControlByCpuLowPowerMode(clock_name_t name, uint8_t domainId, clock_level_t level0, clock_level_t level1)
Set this clock works in CPU Low Power Mode.
Definition: fsl_clock.c:1880
struct _clock_pll_ss_config clock_pll_ss_config_t
Spread specturm configure Pll.
_clock_usb_phy_src
Source of the USB HS PHY.
Definition: fsl_clock.h:1181
enum _clock_lpcg clock_lpcg_t
Clock LPCG index.
void CLOCK_InitSysPll3(void)
Initialize the System PLL3.
Definition: fsl_clock.c:440
_clock_group
Clock group enumeration.
Definition: fsl_clock.h:1735
bool enableClkOutput
Definition: fsl_clock.h:1248
struct _clock_root_setpoint_config_t clock_root_setpoint_config_t
Clock root configuration in SetPoint Mode.
struct _clock_enet_pll_config clock_enet_pll_config_t
PLL configuration for ENET.
void CLOCK_OSC_Set1MHzOutputBehavior(clock_1MHzOut_behavior_t behavior)
Set the behavior of the 1MHz output clock, such as disable the 1MHz clock output, enable the free-run...
Definition: fsl_clock.c:1289
void CLOCK_InitArmPll(const clock_arm_pll_config_t *config)
Initialize the ARM PLL.
Definition: fsl_clock.c:577
struct _clock_usb_pll_config clock_usb_pll_config_t
PLL configuration for USB.
_clock_pll
PLL name.
Definition: fsl_clock.h:1262
uint8_t div
Definition: fsl_clock.h:1926
enum _clock_pll clock_pll_t
PLL name.
uint8_t src
Definition: fsl_clock.h:1205
void CLOCK_OSC_TrimOscRc400M(bool enable, bool bypass, uint16_t trim)
Trims OSC RC 400MHz.
Definition: fsl_clock.c:1602
void CLOCK_OSC_EnableOsc24M(void)
Enable OSC 24Mhz.
Definition: fsl_clock.c:1105
void CLOCK_OSC_SetOscRc400MRefClkDiv(uint8_t divValue)
Set the divide value for ref_clk to generate slow clock.
Definition: fsl_clock.c:1164
_clock_root_mux_source
The enumerator of clock roots' clock source mux value.
Definition: fsl_clock.h:961
void CLOCK_DeinitSysPll2(void)
De-initialize the System PLL2.
Definition: fsl_clock.c:273
struct _clock_sys_pll1_config clock_sys_pll1_config_t
PLL configure for Sys Pll1.
enum _clock_level clock_level_t
The clock dependence level.
void CLOCK_OSCPLL_ControlBySetPointMode(clock_name_t name, uint16_t spValue, uint16_t stbyValue)
Set this clock works in SetPoint control Mode.
Definition: fsl_clock.c:1869
uint8_t mux
Definition: fsl_clock.h:1916
status_t CLOCK_InitVideoPllWithFreq(uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod)
Initializes the Video PLL with Specific Frequency (in Mhz).
Definition: fsl_clock.c:876
enum _clock_24MOsc_mode clock_24MOsc_mode_t
The enumeration of 24MHz crystal oscillator mode.
void CLOCK_LPCG_ControlByCpuLowPowerMode(clock_lpcg_t name, uint8_t domainId, clock_level_t level0, clock_level_t level1)
Set this clock works in CPU Low Power Mode.
Definition: fsl_clock.c:1923
void CLOCK_SetGroupConfig(clock_group_t group, const clock_group_config_t *config)
Set the clock group configuration.
Definition: fsl_clock.c:1593
uint8_t loopDivider
Definition: fsl_clock.h:1202
void CLOCK_OSC_FreezeOscRc400MTuneValue(bool enableFreeze)
Freeze/Unfreeze the tuning value.
Definition: fsl_clock.c:1254
_clock_usb_src
USB clock source definition.
Definition: fsl_clock.h:1173
bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
Enable USB HS PHY PLL clock.
Definition: fsl_clock.c:1336
uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
Get current PLL output frequency.
Definition: fsl_clock.c:939
clock_pll_ss_config_t * ss
Definition: fsl_clock.h:1875
bool ssEnable
Definition: fsl_clock.h:1854
status_t CLOCK_CalcArmPllFreq(clock_arm_pll_config_t *config, uint32_t freqInMhz)
Calculate corresponding config values per given frequency.
Definition: fsl_clock.c:762
status_t CLOCK_InitArmPllWithFreq(uint32_t freqInMhz)
Initializes the Arm PLL with Specific Frequency (in Mhz).
Definition: fsl_clock.c:795
_clock_1MHzOut_behavior
The enumeration of 1MHz output clock behavior, including disabling 1MHz output, enabling locked 1MHz ...
Definition: fsl_clock.h:1985
void CLOCK_InitSysPll2(const clock_sys_pll2_config_t *config)
Initialize the System PLL2.
Definition: fsl_clock.c:193
void CLOCK_OSC_SetOsc16MConfig(clock_16MOsc_source_t source, bool enablePowerSave, bool enableClockOut)
Configure the 16MHz oscillator.
Definition: fsl_clock.c:1145
void CLOCK_DeinitSysPll3(void)
De-initialize the System PLL3.
Definition: fsl_clock.c:498
enum _clock_16MOsc_source clock_16MOsc_source_t
The enumeration of 16MHz RC oscillator clock source.
bool ssEnable
Definition: fsl_clock.h:1890
void CLOCK_GPC_SetVideoPllOutputFreq(const clock_video_pll_gpc_config_t *config)
Set Video PLL output frequency in GPC mode.
Definition: fsl_clock.c:956
void CLOCK_OSC_SetLocked1MHzCount(uint16_t count)
Set the count for the locked 1MHz clock out.
Definition: fsl_clock.c:1316
struct _clock_audio_pll_config clock_audio_pll_config_t
PLL configuration for AUDIO and VIDEO.
enum _clock_group clock_group_t
Clock group enumeration.
status_t CLOCK_InitAudioPllWithFreq(uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod)
Initializes the Audio PLL with Specific Frequency (in Mhz).
Definition: fsl_clock.c:642
bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
Enable USB HS PHY PLL clock.
Definition: fsl_clock.c:540
_clock_pll_post_div
PLL post divider enumeration.
Definition: fsl_clock.h:1811
_clock_level
The clock dependence level.
Definition: fsl_clock.h:1996
clock_pll_ss_config_t * ss
Definition: fsl_clock.h:1852
uint32_t CLOCK_GetFreq(clock_name_t name)
Gets the clock frequency for a specific clock name.
Definition: fsl_clock.c:341
uint32_t mfd
Definition: fsl_clock.h:1851
struct _clock_group_config clock_group_config_t
The structure used to configure clock group.
enum _clock_osc clock_osc_t
OSC 24M sorce select.
void CLOCK_OSC_SetOscRc400MHysteresisValue(uint8_t negHysteresis, uint8_t posHysteresis)
Set the negative and positive hysteresis value for the tuned clock.
Definition: fsl_clock.c:1198
_clock_mode_t
System clock mode.
Definition: fsl_clock.h:657
uint32_t CLOCK_GetPfdFreq(clock_pll_t pll, clock_pfd_t pfd)
Get current PFD output frequency.
Definition: fsl_clock.c:388
uint32_t numerator
Definition: fsl_clock.h:1229
uint8_t postDivider
Definition: fsl_clock.h:1228
void CLOCK_DeinitSysPll1(void)
De-initialize the System PLL1.
Definition: fsl_clock.c:1076
bool CLOCK_IsSysPll2PfdEnabled(clock_pfd_t pfd)
Check if Sys PLL2 PFD is enabled.
Definition: fsl_clock.c:295
uint8_t loopDivider
Definition: fsl_clock.h:1227
uint8_t loopDivider
Definition: fsl_clock.h:1885
bool ssEnable
Definition: fsl_clock.h:1864
uint16_t step
Definition: fsl_clock.h:1845
void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config)
Initializes the Audio PLL.
Definition: fsl_clock.c:718
uint8_t CLOCK_OSC_GetCurrentOscRc400MTuneValue(void)
Get current tune value used by oscillator during tune process.
Definition: fsl_clock.c:1379
_clock_pll_clk_src
PLL clock source, bypass cloco source also.
Definition: fsl_clock.h:1187
enum _clock_pll_post_div clock_pll_post_div_t
PLL post divider enumeration.
void CLOCK_DeinitVideoPll(void)
De-initialize the Video PLL.
Definition: fsl_clock.c:879
uint8_t mux
Definition: fsl_clock.h:1925
void CLOCK_ROOT_ControlBySetPointMode(clock_root_t name, const clock_root_setpoint_config_t *spTable)
Set this clock works in SetPoint controlled Mode.
Definition: fsl_clock.c:1897
void CLOCK_DeinitArmPll(void)
De-initialize the ARM PLL.
Definition: fsl_clock.c:598
bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
Enable USB HS clock.
Definition: fsl_clock.c:488
_clock_gate_value
Clock gate value.
Definition: fsl_clock.h:649
void CLOCK_GPC_SetSysPll1OutputFreq(const clock_sys_pll1_gpc_config_t *config)
Set System PLL1 output frequency in GPC mode.
Definition: fsl_clock.c:1088
bool ssEnable
Definition: fsl_clock.h:1877
void CLOCK_DeinitAudioPll(void)
De-initialize the Audio PLL.
Definition: fsl_clock.c:793
void CLOCK_DisableUsbhs0PhyPllClock(void)
Disable USB HS PHY PLL clock.
Definition: fsl_clock.c:564
uint8_t grade
Definition: fsl_clock.h:1923
void CLOCK_LPCG_ControlBySetPointMode(clock_lpcg_t name, uint16_t spValue, uint16_t stbyValue)
Set this clock works in SetPoint control Mode.
Definition: fsl_clock.c:1912
void CLOCK_DeinitPfd(clock_pll_t pll, clock_pfd_t pfd)
De-initialize selected PLL PFD.
Definition: fsl_clock.c:359
uint8_t src
Definition: fsl_clock.h:1256
_clock_lpcg
Clock LPCG index.
Definition: fsl_clock.h:497
void CLOCK_DisableUsbhs1PhyPllClock(void)
Disable USB HS PHY PLL clock.
Definition: fsl_clock.c:1354
@ kCLOCK_Lpi2c4
Definition: fsl_clock.h:633
@ kCLOCK_Pwm3
Definition: fsl_clock.h:595
@ kCLOCK_Lpspi3
Definition: fsl_clock.h:533
@ kCLOCK_Csi
Definition: fsl_clock.h:550
@ kCLOCK_Lpuart3
Definition: fsl_clock.h:519
@ kCLOCK_Ocram
Definition: fsl_clock.h:581
@ kCLOCK_Pwm2
Definition: fsl_clock.h:594
@ kCLOCK_Usdhc2
Definition: fsl_clock.h:623
@ kCLOCK_Lpi2c1
Definition: fsl_clock.h:552
@ kCLOCK_Lpi2c3
Definition: fsl_clock.h:554
@ kCLOCK_Pwm4
Definition: fsl_clock.h:596
@ kCLOCK_Lpspi4
Definition: fsl_clock.h:534
@ kCLOCK_Can2
Definition: fsl_clock.h:522
@ kCLOCK_Mqs
Definition: fsl_clock.h:515
@ kCLOCK_Ewm0
Definition: fsl_clock.h:574
@ kCLOCK_Iomuxc
Definition: fsl_clock.h:586
@ kCLOCK_Lpuart2
Definition: fsl_clock.h:527
@ kCLOCK_Enc3
Definition: fsl_clock.h:599
@ kCLOCK_Flexio1
Definition: fsl_clock.h:604
@ kCLOCK_Enet
Definition: fsl_clock.h:536
@ kCLOCK_Usdhc1
Definition: fsl_clock.h:622
@ kCLOCK_Acmp3
Definition: fsl_clock.h:579
@ kCLOCK_Flexio2
Definition: fsl_clock.h:567
@ kCLOCK_Anadig
Definition: fsl_clock.h:632
@ kCLOCK_Aoi2
Definition: fsl_clock.h:538
@ kCLOCK_Acmp4
Definition: fsl_clock.h:580
@ kCLOCK_Lpuart7
Definition: fsl_clock.h:616
@ kCLOCK_Pwm1
Definition: fsl_clock.h:593
@ kCLOCK_Dcdc
Definition: fsl_clock.h:624
@ kCLOCK_Acmp2
Definition: fsl_clock.h:578
@ kCLOCK_Gpt1
Definition: fsl_clock.h:541
@ kCLOCK_Enc2
Definition: fsl_clock.h:598
@ kCLOCK_Lpuart1
Definition: fsl_clock.h:615
@ kCLOCK_Acmp1
Definition: fsl_clock.h:577
@ kCLOCK_Pxp
Definition: fsl_clock.h:564
@ kCLOCK_Sai1
Definition: fsl_clock.h:612
@ kCLOCK_Aoi1
Definition: fsl_clock.h:571
@ kCLOCK_Enc1
Definition: fsl_clock.h:597
@ kCLOCK_Kpp
Definition: fsl_clock.h:607
@ kCLOCK_Xbar3
Definition: fsl_clock.h:556
@ kCLOCK_Gpt2
Definition: fsl_clock.h:525
@ kCLOCK_Lpi2c2
Definition: fsl_clock.h:553
@ kCLOCK_Wdog2
Definition: fsl_clock.h:608
@ kCLOCK_Wdog3
Definition: fsl_clock.h:605
@ kCLOCK_Xbar1
Definition: fsl_clock.h:560
@ kCLOCK_Lpspi1
Definition: fsl_clock.h:531
@ kCLOCK_Sai2
Definition: fsl_clock.h:613
@ kCLOCK_Xbar2
Definition: fsl_clock.h:561
@ kCLOCK_Spdif
Definition: fsl_clock.h:610
@ kCLOCK_Lpspi2
Definition: fsl_clock.h:532
@ kCLOCK_Lpuart4
Definition: fsl_clock.h:543
@ kCLOCK_Sai3
Definition: fsl_clock.h:614
@ kCLOCK_Wdog1
Definition: fsl_clock.h:575
@ kCLOCK_Lpuart6
Definition: fsl_clock.h:570
@ kCLOCK_Lpuart8
Definition: fsl_clock.h:628
@ kCLOCK_Semc
Definition: fsl_clock.h:569
@ kCLOCK_Ocotp
Definition: fsl_clock.h:555
@ kCLOCK_Lpuart5
Definition: fsl_clock.h:568
@ kCLOCK_Can1
Definition: fsl_clock.h:520
@ kCLOCK_Enc4
Definition: fsl_clock.h:600
@ kCLOCK_AudioPll
Definition: fsl_clock.h:670
@ kCLOCK_ArmPll
Definition: fsl_clock.h:651
@ kCLOCK_SysPll2Pfd3
Definition: fsl_clock.h:658
@ kCLOCK_SysPll1Out
Definition: fsl_clock.h:667
@ kCLOCK_CpuClk
Definition: fsl_clock.h:465
@ kCLOCK_SysPll3Pfd3
Definition: fsl_clock.h:665
@ kCLOCK_SysPll2Pfd1
Definition: fsl_clock.h:656
@ kCLOCK_CoreSysClk
Definition: fsl_clock.h:675
@ kCLOCK_SysPll2Pfd2
Definition: fsl_clock.h:657
@ kCLOCK_SysPll3Pfd0
Definition: fsl_clock.h:662
@ kCLOCK_OscRc48M
Definition: fsl_clock.h:646
@ kCLOCK_SysPll1Div5
Definition: fsl_clock.h:669
@ kCLOCK_Osc24MOut
Definition: fsl_clock.h:650
@ kCLOCK_VideoPll
Definition: fsl_clock.h:672
@ kCLOCK_SysPll3
Definition: fsl_clock.h:659
@ kCLOCK_SysPll3Pfd1
Definition: fsl_clock.h:663
@ kCLOCK_SysPll2
Definition: fsl_clock.h:653
@ kCLOCK_SysPll3Pfd2
Definition: fsl_clock.h:664
@ kCLOCK_SysPll3Out
Definition: fsl_clock.h:660
@ kCLOCK_SysPll1Div2
Definition: fsl_clock.h:668
@ kCLOCK_SysPll3Div2
Definition: fsl_clock.h:661
@ kCLOCK_OscRc48MDiv2
Definition: fsl_clock.h:647
@ kCLOCK_ArmPllOut
Definition: fsl_clock.h:652
@ kCLOCK_SysPll2Out
Definition: fsl_clock.h:654
@ kCLOCK_SysPll1
Definition: fsl_clock.h:666
@ kCLOCK_Osc24M
Definition: fsl_clock.h:649
@ kCLOCK_VideoPllOut
Definition: fsl_clock.h:673
@ kCLOCK_OscRc16M
Definition: fsl_clock.h:645
@ kCLOCK_OscRc400M
Definition: fsl_clock.h:648
@ kCLOCK_AudioPllOut
Definition: fsl_clock.h:671
@ kCLOCK_SysPll2Pfd0
Definition: fsl_clock.h:655
@ kCLOCK_Reserved
Definition: fsl_clock.h:676
@ kCLOCK_24MOscLowPowerMode
Definition: fsl_clock.h:1968
@ kCLOCK_24MOscBypassMode
Definition: fsl_clock.h:1967
@ kCLOCK_24MOscHighGainMode
Definition: fsl_clock.h:1966
@ kCLOCK_XtalOsc
Definition: fsl_clock.h:644
@ kCLOCK_RcOsc
Definition: fsl_clock.h:643
@ kCLOCK_GpcMode
Definition: fsl_clock.h:1958
@ kCLOCK_SoftwareMode
Definition: fsl_clock.h:1957
@ kCLOCK_Root_Sai2
Definition: fsl_clock.h:941
@ kCLOCK_Root_Acmp
Definition: fsl_clock.h:889
@ kCLOCK_Root_Emv2
Definition: fsl_clock.h:928
@ kCLOCK_Root_Lpuart8
Definition: fsl_clock.h:910
@ kCLOCK_Root_Lcdifv2
Definition: fsl_clock.h:946
@ kCLOCK_Root_Usdhc2
Definition: fsl_clock.h:935
@ kCLOCK_Root_Gc355
Definition: fsl_clock.h:944
@ kCLOCK_Root_Lpuart4
Definition: fsl_clock.h:906
@ kCLOCK_Root_M4_Systick
Definition: fsl_clock.h:885
@ kCLOCK_Root_Csi2
Definition: fsl_clock.h:949
@ kCLOCK_Root_Lpuart10
Definition: fsl_clock.h:912
@ kCLOCK_Root_Sai3
Definition: fsl_clock.h:942
@ kCLOCK_Root_Sai1
Definition: fsl_clock.h:940
@ kCLOCK_Root_Csi
Definition: fsl_clock.h:952
@ kCLOCK_Root_Csi2_Esc
Definition: fsl_clock.h:950
@ kCLOCK_Root_Enet1
Definition: fsl_clock.h:929
@ kCLOCK_Root_Lpi2c2
Definition: fsl_clock.h:916
@ kCLOCK_Root_Flexspi1
Definition: fsl_clock.h:898
@ kCLOCK_Root_Can3
Definition: fsl_clock.h:902
@ kCLOCK_Root_Usdhc1
Definition: fsl_clock.h:934
@ kCLOCK_Root_Lpuart5
Definition: fsl_clock.h:907
@ kCLOCK_Root_Gpt1
Definition: fsl_clock.h:892
@ kCLOCK_Root_Cko1
Definition: fsl_clock.h:953
@ kCLOCK_Root_Lpspi1
Definition: fsl_clock.h:921
@ kCLOCK_Root_Lpi2c4
Definition: fsl_clock.h:918
@ kCLOCK_Root_Spdif
Definition: fsl_clock.h:939
@ kCLOCK_Root_Lpuart2
Definition: fsl_clock.h:904
@ kCLOCK_Root_Can1
Definition: fsl_clock.h:900
@ kCLOCK_Root_Emv1
Definition: fsl_clock.h:927
@ kCLOCK_Root_Sai4
Definition: fsl_clock.h:943
@ kCLOCK_Root_Gpt4
Definition: fsl_clock.h:895
@ kCLOCK_Root_Cko2
Definition: fsl_clock.h:954
@ kCLOCK_Root_Enet_Timer2
Definition: fsl_clock.h:933
@ kCLOCK_Root_Asrc
Definition: fsl_clock.h:936
@ kCLOCK_Root_Flexio1
Definition: fsl_clock.h:890
@ kCLOCK_Root_Adc1
Definition: fsl_clock.h:887
@ kCLOCK_Root_Lpspi5
Definition: fsl_clock.h:925
@ kCLOCK_Root_Cssys
Definition: fsl_clock.h:883
@ kCLOCK_Root_Flexio2
Definition: fsl_clock.h:891
@ kCLOCK_Root_Cstrace
Definition: fsl_clock.h:884
@ kCLOCK_Root_Lpuart6
Definition: fsl_clock.h:908
@ kCLOCK_Root_Lpspi4
Definition: fsl_clock.h:924
@ kCLOCK_Root_Mipi_Esc
Definition: fsl_clock.h:948
@ kCLOCK_Root_Csi2_Ui
Definition: fsl_clock.h:951
@ kCLOCK_Root_Lpi2c1
Definition: fsl_clock.h:915
@ kCLOCK_Root_Mic
Definition: fsl_clock.h:938
@ kCLOCK_Root_Lpuart11
Definition: fsl_clock.h:913
@ kCLOCK_Root_Bus_Lpsr
Definition: fsl_clock.h:881
@ kCLOCK_Root_Lpuart7
Definition: fsl_clock.h:909
@ kCLOCK_Root_Lpuart12
Definition: fsl_clock.h:914
@ kCLOCK_Root_Gpt5
Definition: fsl_clock.h:896
@ kCLOCK_Root_Mipi_Ref
Definition: fsl_clock.h:947
@ kCLOCK_Root_Semc
Definition: fsl_clock.h:882
@ kCLOCK_Root_M4
Definition: fsl_clock.h:879
@ kCLOCK_Root_Lpi2c6
Definition: fsl_clock.h:920
@ kCLOCK_Root_Enet_25m
Definition: fsl_clock.h:931
@ kCLOCK_Root_Gpt3
Definition: fsl_clock.h:894
@ kCLOCK_Root_Mqs
Definition: fsl_clock.h:937
@ kCLOCK_Root_Lpuart3
Definition: fsl_clock.h:905
@ kCLOCK_Root_Lpi2c5
Definition: fsl_clock.h:919
@ kCLOCK_Root_Flexspi2
Definition: fsl_clock.h:899
@ kCLOCK_Root_Lpspi2
Definition: fsl_clock.h:922
@ kCLOCK_Root_Can2
Definition: fsl_clock.h:901
@ kCLOCK_Root_Lpuart9
Definition: fsl_clock.h:911
@ kCLOCK_Root_Lpi2c3
Definition: fsl_clock.h:917
@ kCLOCK_Root_Lpspi3
Definition: fsl_clock.h:923
@ kCLOCK_Root_M7_Systick
Definition: fsl_clock.h:886
@ kCLOCK_Root_Enet_Timer1
Definition: fsl_clock.h:932
@ kCLOCK_Root_Lcdif
Definition: fsl_clock.h:945
@ kCLOCK_Root_Lpuart1
Definition: fsl_clock.h:903
@ kCLOCK_Root_Bus
Definition: fsl_clock.h:880
@ kCLOCK_Root_Gpt6
Definition: fsl_clock.h:897
@ kCLOCK_Root_Gpt2
Definition: fsl_clock.h:893
@ kCLOCK_Root_M7
Definition: fsl_clock.h:878
@ kCLOCK_Root_Lpspi6
Definition: fsl_clock.h:926
@ kCLOCK_Root_Adc2
Definition: fsl_clock.h:888
@ kCLOCK_Root_Enet2
Definition: fsl_clock.h:930
@ kCLOCK_Pfd3
Definition: fsl_clock.h:1283
@ kCLOCK_Pfd2
Definition: fsl_clock.h:1282
@ kCLOCK_Pfd0
Definition: fsl_clock.h:1280
@ kCLOCK_Pfd1
Definition: fsl_clock.h:1281
@ kCLOCK_16MOscSourceFrom16MOsc
Definition: fsl_clock.h:1976
@ kCLOCK_16MOscSourceFrom24MOsc
Definition: fsl_clock.h:1977
@ kCLOCK_Usbphy480M
Definition: fsl_clock.h:1182
@ kCLOCK_Group_MipiDsi
Definition: fsl_clock.h:1737
@ kCLOCK_Group_FlexRAM
Definition: fsl_clock.h:1736
@ kCLOCK_Group_Last
Definition: fsl_clock.h:1738
@ kCLOCK_PllSys1
Definition: fsl_clock.h:1933
@ kCLOCK_PllInvalid
Definition: fsl_clock.h:1938
@ kCLOCK_PllVideo
Definition: fsl_clock.h:1267
@ kCLOCK_PllSys2
Definition: fsl_clock.h:1934
@ kCLOCK_PllSys3
Definition: fsl_clock.h:1935
@ kCLOCK_PllAudio
Definition: fsl_clock.h:1266
@ kCLOCK_PllArm
Definition: fsl_clock.h:1263
@ kCLOCK_LPUART10_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1307
@ kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd0
Definition: fsl_clock.h:1536
@ kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1311
@ kCLOCK_SAI2_ClockRoot_MuxSysPll3Pfd2
Definition: fsl_clock.h:1596
@ kCLOCK_LPUART2_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1221
@ kCLOCK_GPT5_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1145
@ kCLOCK_EMV1_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1454
@ kCLOCK_LPUART9_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1292
@ kCLOCK_MIPI_REF_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1654
@ kCLOCK_CAN2_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1197
@ kCLOCK_EMV2_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1466
@ kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:994
@ kCLOCK_CAN3_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:1206
@ kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll2Pfd1
Definition: fsl_clock.h:1518
@ kCLOCK_CKO2_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1724
@ kCLOCK_CSI_ClockRoot_MuxSysPll3Pfd1
Definition: fsl_clock.h:1707
@ kCLOCK_LPI2C3_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1352
@ kCLOCK_LPUART9_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1297
@ kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1581
@ kCLOCK_GPT3_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1122
@ kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1664
@ kCLOCK_LPUART12_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1327
@ kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div2
Definition: fsl_clock.h:1515
@ kCLOCK_LPUART10_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1305
@ kCLOCK_SAI1_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1588
@ kCLOCK_SAI1_ClockRoot_MuxSysPll3Pfd2
Definition: fsl_clock.h:1586
@ kCLOCK_LPUART4_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1247
@ kCLOCK_ENET_25M_ClockRoot_MuxSysPll2Pfd1
Definition: fsl_clock.h:1498
@ kCLOCK_LPUART5_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1252
@ kCLOCK_LPSPI2_ClockRoot_MuxSysPll3Pfd2
Definition: fsl_clock.h:1405
@ kCLOCK_LPI2C2_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1342
@ kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1097
@ kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1421
@ kCLOCK_LPUART8_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1283
@ kCLOCK_LPUART10_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1303
@ kCLOCK_GPT4_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1135
@ kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1497
@ kCLOCK_LPUART4_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1246
@ kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1491
@ kCLOCK_GPT4_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1134
@ kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1337
@ kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1301
@ kCLOCK_USDHC2_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1534
@ kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div2
Definition: fsl_clock.h:1505
@ kCLOCK_LPSPI5_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1438
@ kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1338
@ kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1028
@ kCLOCK_GPT2_ClockRoot_MuxAudioPllOut
Definition: fsl_clock.h:1117
@ kCLOCK_LPUART10_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1308
@ kCLOCK_ENET2_ClockRoot_MuxSysPll2Pfd1
Definition: fsl_clock.h:1488
@ kCLOCK_LPUART4_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1245
@ kCLOCK_LPUART9_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1295
@ kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1531
@ kCLOCK_BUS_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:984
@ kCLOCK_LPUART9_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1294
@ kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:1168
@ kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1341
@ kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1511
@ kCLOCK_LPUART2_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1225
@ kCLOCK_SPDIF_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1574
@ kCLOCK_MIC_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1564
@ kCLOCK_ENET_25M_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1492
@ kCLOCK_LPI2C5_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1377
@ kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1085
@ kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1271
@ kCLOCK_CSI_ClockRoot_MuxVideoPllOut
Definition: fsl_clock.h:1708
@ kCLOCK_LPI2C2_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1345
@ kCLOCK_CSTRACE_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1025
@ kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1504
@ kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1227
@ kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1141
@ kCLOCK_LPUART3_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1234
@ kCLOCK_LPI2C6_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1388
@ kCLOCK_CAN3_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1203
@ kCLOCK_LPUART6_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1266
@ kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:996
@ kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1181
@ kCLOCK_LPSPI4_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1423
@ kCLOCK_LPUART12_ClockRoot_MuxSysPll3Pfd3
Definition: fsl_clock.h:1325
@ kCLOCK_EMV1_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1457
@ kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1571
@ kCLOCK_LCDIF_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1633
@ kCLOCK_GPT3_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1126
@ kCLOCK_EMV1_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1458
@ kCLOCK_CKO2_ClockRoot_MuxOscRc48M
Definition: fsl_clock.h:1726
@ kCLOCK_LPUART3_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1237
@ kCLOCK_LPUART3_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1238
@ kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3
Definition: fsl_clock.h:975
@ kCLOCK_ASRC_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1548
@ kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2
Definition: fsl_clock.h:1525
@ kCLOCK_LCDIF_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1632
@ kCLOCK_CAN2_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1198
@ kCLOCK_CSI2_ESC_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1682
@ kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd2
Definition: fsl_clock.h:1107
@ kCLOCK_SAI1_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1587
@ kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1683
@ kCLOCK_LPSPI1_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1392
@ kCLOCK_CSI2_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1674
@ kCLOCK_ENET_TIMER2_ClockRoot_MuxAudioPllOut
Definition: fsl_clock.h:1516
@ kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:998
@ kCLOCK_CKO1_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1718
@ kCLOCK_GPT4_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1136
@ kCLOCK_GC355_ClockRoot_MuxVideoPllOut
Definition: fsl_clock.h:1628
@ kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:988
@ kCLOCK_CSTRACE_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1022
@ kCLOCK_ADC2_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1068
@ kCLOCK_CKO1_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1716
@ kCLOCK_GC355_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1625
@ kCLOCK_LPSPI3_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1416
@ kCLOCK_ENET2_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1484
@ kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd2
Definition: fsl_clock.h:1685
@ kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1043
@ kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1044
@ kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1241
@ kCLOCK_EMV2_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1468
@ kCLOCK_LPI2C5_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1378
@ kCLOCK_LPSPI4_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1426
@ kCLOCK_CSI2_ESC_ClockRoot_MuxVideoPllOut
Definition: fsl_clock.h:1688
@ kCLOCK_GPT2_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1116
@ kCLOCK_SAI2_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1597
@ kCLOCK_LPI2C5_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1372
@ kCLOCK_CSSYS_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1016
@ kCLOCK_FLEXIO1_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1082
@ kCLOCK_LPUART8_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1285
@ kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1033
@ kCLOCK_LPUART2_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1228
@ kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1407
@ kCLOCK_M7_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:968
@ kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1503
@ kCLOCK_LPUART8_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1288
@ kCLOCK_MIPI_ESC_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1662
@ kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1171
@ kCLOCK_MQS_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1552
@ kCLOCK_ADC2_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1064
@ kCLOCK_GPT3_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1124
@ kCLOCK_ENET1_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1473
@ kCLOCK_GC355_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1624
@ kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1651
@ kCLOCK_LPUART6_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1263
@ kCLOCK_GPT6_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1152
@ kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1251
@ kCLOCK_SAI3_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1607
@ kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd3
Definition: fsl_clock.h:1138
@ kCLOCK_FLEXIO2_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1096
@ kCLOCK_CSSYS_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1012
@ kCLOCK_SEMC_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1002
@ kCLOCK_MIPI_REF_ClockRoot_MuxVideoPllOut
Definition: fsl_clock.h:1658
@ kCLOCK_CSI2_UI_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1694
@ kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll2Pfd1
Definition: fsl_clock.h:1508
@ kCLOCK_ENET2_ClockRoot_MuxAudioPllOut
Definition: fsl_clock.h:1486
@ kCLOCK_LCDIF_ClockRoot_MuxSysPll3Pfd0
Definition: fsl_clock.h:1637
@ kCLOCK_FLEXSPI1_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1162
@ kCLOCK_GPT4_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1133
@ kCLOCK_LPUART11_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1312
@ kCLOCK_ADC1_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1057
@ kCLOCK_SEMC_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1004
@ kCLOCK_BUS_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:986
@ kCLOCK_LPUART6_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1268
@ kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Pfd0
Definition: fsl_clock.h:1048
@ kCLOCK_ENET1_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1474
@ kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1164
@ kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1111
@ kCLOCK_LPUART11_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1314
@ kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2
Definition: fsl_clock.h:1535
@ kCLOCK_FLEXSPI2_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1172
@ kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1047
@ kCLOCK_GPT6_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1154
@ kCLOCK_M7_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:965
@ kCLOCK_CAN1_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1183
@ kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1291
@ kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Pfd3
Definition: fsl_clock.h:1385
@ kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1261
@ kCLOCK_LPI2C6_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1382
@ kCLOCK_LPUART2_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1226
@ kCLOCK_LPI2C2_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1343
@ kCLOCK_USDHC1_ClockRoot_MuxArmPllOut
Definition: fsl_clock.h:1528
@ kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1041
@ kCLOCK_ENET_25M_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1494
@ kCLOCK_LPUART5_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1258
@ kCLOCK_LPUART11_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1317
@ kCLOCK_CSI_ClockRoot_MuxSysPll2Pfd2
Definition: fsl_clock.h:1705
@ kCLOCK_SAI4_ClockRoot_MuxSysPll3Pfd3
Definition: fsl_clock.h:1615
@ kCLOCK_MQS_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1556
@ kCLOCK_LPI2C6_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1387
@ kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd3
Definition: fsl_clock.h:1158
@ kCLOCK_LPUART12_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:1326
@ kCLOCK_LPUART8_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1286
@ kCLOCK_MIC_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1563
@ kCLOCK_CSSYS_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1013
@ kCLOCK_GPT3_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1125
@ kCLOCK_LPUART5_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1253
@ kCLOCK_CAN2_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1195
@ kCLOCK_GPT2_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1112
@ kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1471
@ kCLOCK_LPSPI5_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1434
@ kCLOCK_MQS_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1554
@ kCLOCK_ENET_TIMER1_ClockRoot_MuxAudioPllOut
Definition: fsl_clock.h:1506
@ kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1011
@ kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1166
@ kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd0
Definition: fsl_clock.h:1687
@ kCLOCK_CSI_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1703
@ kCLOCK_SPDIF_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:1576
@ kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1121
@ kCLOCK_CKO2_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1723
@ kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1174
@ kCLOCK_MIPI_ESC_ClockRoot_MuxVideoPllOut
Definition: fsl_clock.h:1668
@ kCLOCK_CSTRACE_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1026
@ kCLOCK_LPI2C1_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1333
@ kCLOCK_LPSPI3_ClockRoot_MuxSysPll3Pfd2
Definition: fsl_clock.h:1415
@ kCLOCK_LCDIFV2_ClockRoot_MuxVideoPllOut
Definition: fsl_clock.h:1648
@ kCLOCK_GPT5_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1144
@ kCLOCK_CKO1_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1712
@ kCLOCK_LPUART11_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1318
@ kCLOCK_ASRC_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1546
@ kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1501
@ kCLOCK_CKO1_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1714
@ kCLOCK_ADC2_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1066
@ kCLOCK_ADC1_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1056
@ kCLOCK_LPI2C1_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1336
@ kCLOCK_MQS_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1553
@ kCLOCK_GC355_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:1627
@ kCLOCK_ASRC_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1545
@ kCLOCK_LPSPI2_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1404
@ kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2
Definition: fsl_clock.h:1475
@ kCLOCK_CAN1_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1187
@ kCLOCK_USDHC1_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1524
@ kCLOCK_LPUART2_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1223
@ kCLOCK_CAN1_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1184
@ kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1398
@ kCLOCK_MIC_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:1566
@ kCLOCK_SAI2_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1594
@ kCLOCK_LPUART3_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1232
@ kCLOCK_BUS_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:982
@ kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1701
@ kCLOCK_ACMP_ClockRoot_MuxAudioPllOut
Definition: fsl_clock.h:1077
@ kCLOCK_LPSPI4_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1422
@ kCLOCK_MIC_ClockRoot_MuxSysPll3Pfd3
Definition: fsl_clock.h:1565
@ kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1514
@ kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1098
@ kCLOCK_LPUART6_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1262
@ kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1046
@ kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1655
@ kCLOCK_LPI2C2_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1344
@ kCLOCK_LPUART5_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1257
@ kCLOCK_LPUART12_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1323
@ kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1071
@ kCLOCK_LPI2C3_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1356
@ kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd3
Definition: fsl_clock.h:1435
@ kCLOCK_LPUART10_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1304
@ kCLOCK_SAI1_ClockRoot_MuxAudioPllOut
Definition: fsl_clock.h:1585
@ kCLOCK_ASRC_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1542
@ kCLOCK_ACMP_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:1075
@ kCLOCK_LPUART3_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1235
@ kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1671
@ kCLOCK_EMV2_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1467
@ kCLOCK_LPI2C4_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1363
@ kCLOCK_LCDIFV2_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1642
@ kCLOCK_LPUART9_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1296
@ kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1038
@ kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1217
@ kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1095
@ kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1665
@ kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1131
@ kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Pfd0
Definition: fsl_clock.h:1656
@ kCLOCK_LPUART1_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1216
@ kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Pfd2
Definition: fsl_clock.h:1177
@ kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1428
@ kCLOCK_CAN1_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1182
@ kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1561
@ kCLOCK_LPSPI3_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1412
@ kCLOCK_ENET2_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1487
@ kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1591
@ kCLOCK_ADC2_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1065
@ kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1101
@ kCLOCK_CSI2_UI_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:1696
@ kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1631
@ kCLOCK_M7_ClockRoot_MuxArmPllOut
Definition: fsl_clock.h:967
@ kCLOCK_SAI2_ClockRoot_MuxAudioPllOut
Definition: fsl_clock.h:1595
@ kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd2
Definition: fsl_clock.h:1437
@ kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1115
@ kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1427
@ kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1461
@ kCLOCK_SPDIF_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1572
@ kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1281
@ kCLOCK_MIPI_REF_ClockRoot_MuxSysPll3Pfd0
Definition: fsl_clock.h:1657
@ kCLOCK_LCDIF_ClockRoot_MuxVideoPllOut
Definition: fsl_clock.h:1638
@ kCLOCK_LPSPI3_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1414
@ kCLOCK_BUS_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:987
@ kCLOCK_M4_SYSTICK_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1032
@ kCLOCK_CAN3_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1208
@ kCLOCK_SAI1_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1584
@ kCLOCK_M7_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:964
@ kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1
Definition: fsl_clock.h:1007
@ kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:1446
@ kCLOCK_GPT3_ClockRoot_MuxVideoPllOut
Definition: fsl_clock.h:1128
@ kCLOCK_GPT1_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1104
@ kCLOCK_SAI1_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1582
@ kCLOCK_ENET2_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1483
@ kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1551
@ kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1351
@ kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd3
Definition: fsl_clock.h:1148
@ kCLOCK_USDHC2_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1533
@ kCLOCK_SAI1_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1583
@ kCLOCK_LPI2C4_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1364
@ kCLOCK_LPUART7_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1274
@ kCLOCK_ENET1_ClockRoot_MuxAudioPllOut
Definition: fsl_clock.h:1476
@ kCLOCK_ADC1_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1055
@ kCLOCK_SAI4_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:1616
@ kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd3
Definition: fsl_clock.h:1445
@ kCLOCK_LPUART8_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1284
@ kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd2
Definition: fsl_clock.h:1675
@ kCLOCK_CAN2_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1193
@ kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1173
@ kCLOCK_GPT3_ClockRoot_MuxAudioPllOut
Definition: fsl_clock.h:1127
@ kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1541
@ kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1441
@ kCLOCK_LCDIFV2_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1644
@ kCLOCK_LPUART1_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1213
@ kCLOCK_MIC_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1568
@ kCLOCK_GPT1_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1102
@ kCLOCK_GPT6_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1156
@ kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1381
@ kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Pfd3
Definition: fsl_clock.h:995
@ kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1151
@ kCLOCK_BUS_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:981
@ kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1663
@ kCLOCK_CSSYS_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1017
@ kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd0
Definition: fsl_clock.h:1677
@ kCLOCK_LPUART1_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1212
@ kCLOCK_MIPI_REF_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1653
@ kCLOCK_CAN2_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1192
@ kCLOCK_GPT5_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1146
@ kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Pfd3
Definition: fsl_clock.h:1375
@ kCLOCK_SAI4_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1612
@ kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1331
@ kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1042
@ kCLOCK_CKO2_ClockRoot_MuxAudioPllOut
Definition: fsl_clock.h:1728
@ kCLOCK_LPUART2_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1222
@ kCLOCK_LPUART1_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1215
@ kCLOCK_M4_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:978
@ kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1361
@ kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd0
Definition: fsl_clock.h:1175
@ kCLOCK_FLEXIO1_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1084
@ kCLOCK_USDHC1_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1527
@ kCLOCK_USDHC2_ClockRoot_MuxArmPllOut
Definition: fsl_clock.h:1538
@ kCLOCK_LPUART1_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1218
@ kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:1178
@ kCLOCK_LPUART12_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1322
@ kCLOCK_GPT4_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1132
@ kCLOCK_SPDIF_ClockRoot_MuxAudioPllOut
Definition: fsl_clock.h:1575
@ kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1061
@ kCLOCK_LPI2C4_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1365
@ kCLOCK_CSI2_UI_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1692
@ kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Pfd3
Definition: fsl_clock.h:1035
@ kCLOCK_LPUART7_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1276
@ kCLOCK_CKO1_ClockRoot_MuxSysPll3Pfd1
Definition: fsl_clock.h:1717
@ kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1431
@ kCLOCK_ENET_TIMER2_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1512
@ kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1357
@ kCLOCK_GPT5_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1143
@ kCLOCK_MIPI_REF_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1652
@ kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd2
Definition: fsl_clock.h:1147
@ kCLOCK_LPI2C1_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1335
@ kCLOCK_EMV2_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1464
@ kCLOCK_LPUART5_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1254
@ kCLOCK_LPUART4_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1248
@ kCLOCK_SAI4_ClockRoot_MuxAudioPllOut
Definition: fsl_clock.h:1617
@ kCLOCK_CSSYS_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1018
@ kCLOCK_SPDIF_ClockRoot_MuxSysPll3Pfd2
Definition: fsl_clock.h:1577
@ kCLOCK_LPI2C4_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1362
@ kCLOCK_CAN1_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1188
@ kCLOCK_GPT1_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1106
@ kCLOCK_MIC_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1562
@ kCLOCK_LPSPI5_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1433
@ kCLOCK_SEMC_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1006
@ kCLOCK_LPUART8_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1282
@ kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1176
@ kCLOCK_CAN3_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1207
@ kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1601
@ kCLOCK_ENET1_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1472
@ kCLOCK_LPSPI1_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1393
@ kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Pfd0
Definition: fsl_clock.h:1666
@ kCLOCK_ADC2_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1062
@ kCLOCK_LPUART7_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1273
@ kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1031
@ kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1481
@ kCLOCK_ENET2_ClockRoot_MuxSysPll1Div2
Definition: fsl_clock.h:1485
@ kCLOCK_LPSPI6_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1443
@ kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div2
Definition: fsl_clock.h:1495
@ kCLOCK_LPI2C5_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1374
@ kCLOCK_CAN2_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1196
@ kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1087
@ kCLOCK_LPUART9_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1293
@ kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Pfd2
Definition: fsl_clock.h:1167
@ kCLOCK_GPT1_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1103
@ kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1611
@ kCLOCK_M4_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:973
@ kCLOCK_FLEXIO2_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1094
@ kCLOCK_SEMC_ClockRoot_MuxSysPll3Pfd0
Definition: fsl_clock.h:1008
@ kCLOCK_LPSPI6_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1444
@ kCLOCK_SAI2_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1592
@ kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd2
Definition: fsl_clock.h:1157
@ kCLOCK_USDHC2_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1532
@ kCLOCK_ACMP_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1078
@ kCLOCK_LPUART8_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1287
@ kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1034
@ kCLOCK_LPUART4_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1243
@ kCLOCK_LPUART5_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1255
@ kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:971
@ kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1091
@ kCLOCK_EMV1_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1453
@ kCLOCK_CAN3_ClockRoot_MuxSysPll3Pfd3
Definition: fsl_clock.h:1205
@ kCLOCK_ASRC_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1543
@ kCLOCK_CKO2_ClockRoot_MuxSysPll3Pfd1
Definition: fsl_clock.h:1727
@ kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd2
Definition: fsl_clock.h:1137
@ kCLOCK_ADC2_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1063
@ kCLOCK_LCDIF_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1635
@ kCLOCK_SAI4_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1613
@ kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1105
@ kCLOCK_GC355_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1621
@ kCLOCK_LCDIFV2_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1643
@ kCLOCK_CSTRACE_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1024
@ kCLOCK_CAN1_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1186
@ kCLOCK_LPI2C1_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1332
@ kCLOCK_GPT3_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1123
@ kCLOCK_FLEXIO2_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1093
@ kCLOCK_ADC1_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1054
@ kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1358
@ kCLOCK_LPUART12_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1328
@ kCLOCK_LPSPI2_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1406
@ kCLOCK_M4_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:976
@ kCLOCK_USDHC1_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1522
@ kCLOCK_SAI3_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1602
@ kCLOCK_SAI3_ClockRoot_MuxSysPll3Pfd2
Definition: fsl_clock.h:1606
@ kCLOCK_LPI2C2_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1346
@ kCLOCK_LPUART7_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1275
@ kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Pfd1
Definition: fsl_clock.h:1027
@ kCLOCK_SAI3_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1608
@ kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1417
@ kCLOCK_LPI2C1_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1334
@ kCLOCK_USDHC1_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1523
@ kCLOCK_ENET_25M_ClockRoot_MuxAudioPllOut
Definition: fsl_clock.h:1496
@ kCLOCK_LPI2C3_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1354
@ kCLOCK_M4_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:977
@ kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd3
Definition: fsl_clock.h:1108
@ kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:1386
@ kCLOCK_LPUART7_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1272
@ kCLOCK_CSI_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1704
@ kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:993
@ kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1368
@ kCLOCK_CSI2_ClockRoot_MuxVideoPllOut
Definition: fsl_clock.h:1678
@ kCLOCK_CSI_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1702
@ kCLOCK_CSTRACE_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1021
@ kCLOCK_LPSPI2_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1402
@ kCLOCK_LPI2C5_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1373
@ kCLOCK_LPUART4_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1242
@ kCLOCK_ENET1_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1477
@ kCLOCK_ACMP_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1076
@ kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1418
@ kCLOCK_LPSPI6_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1448
@ kCLOCK_ENET_TIMER1_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1502
@ kCLOCK_FLEXIO2_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1092
@ kCLOCK_LPSPI5_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1432
@ kCLOCK_GPT2_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1113
@ kCLOCK_LPI2C4_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1366
@ kCLOCK_LPUART11_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:1316
@ kCLOCK_LPI2C6_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1383
@ kCLOCK_LPSPI1_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1394
@ kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1321
@ kCLOCK_GPT5_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1142
@ kCLOCK_LPSPI4_ClockRoot_MuxSysPll3Pfd2
Definition: fsl_clock.h:1425
@ kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1641
@ kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1691
@ kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1711
@ kCLOCK_ADC1_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1058
@ kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd0
Definition: fsl_clock.h:1526
@ kCLOCK_SAI2_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1593
@ kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd2
Definition: fsl_clock.h:1695
@ kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1191
@ kCLOCK_CSI2_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1673
@ kCLOCK_BUS_LPSR_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:992
@ kCLOCK_M7_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:966
@ kCLOCK_MQS_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1558
@ kCLOCK_LPUART2_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1224
@ kCLOCK_MQS_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1555
@ kCLOCK_USDHC2_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1537
@ kCLOCK_CSI2_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1672
@ kCLOCK_CSSYS_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1014
@ kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd0
Definition: fsl_clock.h:1697
@ kCLOCK_ACMP_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1073
@ kCLOCK_SAI4_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1618
@ kCLOCK_ADC2_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1067
@ kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1681
@ kCLOCK_ACMP_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1072
@ kCLOCK_LPUART1_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1211
@ kCLOCK_GC355_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1623
@ kCLOCK_LPUART7_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1278
@ kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1231
@ kCLOCK_FLEXIO1_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1083
@ kCLOCK_ENET2_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1482
@ kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll3Pfd0
Definition: fsl_clock.h:1667
@ kCLOCK_LPSPI4_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1424
@ kCLOCK_SPDIF_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1578
@ kCLOCK_LCDIF_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1634
@ kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:963
@ kCLOCK_CAN3_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1202
@ kCLOCK_SAI2_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1598
@ kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1347
@ kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1684
@ kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1081
@ kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll2Pfd0
Definition: fsl_clock.h:1037
@ kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Pfd2
Definition: fsl_clock.h:1646
@ kCLOCK_LPSPI3_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1413
@ kCLOCK_LPUART7_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1277
@ kCLOCK_LPSPI6_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1442
@ kCLOCK_LPSPI1_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1396
@ kCLOCK_CAN2_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1194
@ kCLOCK_GPT2_ClockRoot_MuxVideoPllOut
Definition: fsl_clock.h:1118
@ kCLOCK_ENET_25M_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1493
@ kCLOCK_CSTRACE_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1023
@ kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1051
@ kCLOCK_MIC_ClockRoot_MuxAudioPllOut
Definition: fsl_clock.h:1567
@ kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:1036
@ kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1348
@ kCLOCK_CSSYS_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1015
@ kCLOCK_SEMC_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1001
@ kCLOCK_LPSPI2_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1403
@ kCLOCK_SEMC_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1003
@ kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1367
@ kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1411
@ kCLOCK_LPUART11_ClockRoot_MuxSysPll3Pfd3
Definition: fsl_clock.h:1315
@ kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1161
@ kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:1436
@ kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1088
@ kCLOCK_LPUART9_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1298
@ kCLOCK_CSI2_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:1676
@ kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1401
@ kCLOCK_ASRC_ClockRoot_MuxAudioPllOut
Definition: fsl_clock.h:1547
@ kCLOCK_CKO1_ClockRoot_MuxSysPll2Pfd2
Definition: fsl_clock.h:1715
@ kCLOCK_SAI3_ClockRoot_MuxAudioPllOut
Definition: fsl_clock.h:1605
@ kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1391
@ kCLOCK_ADC1_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1053
@ kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1371
@ kCLOCK_LPUART5_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1256
@ kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:991
@ kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1163
@ kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1451
@ kCLOCK_ADC1_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1052
@ kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:997
@ kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1517
@ kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1397
@ kCLOCK_CAN3_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1204
@ kCLOCK_LPUART1_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1214
@ kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1408
@ kCLOCK_LCDIFV2_ClockRoot_MuxSysPll3Pfd0
Definition: fsl_clock.h:1647
@ kCLOCK_LPUART6_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1267
@ kCLOCK_ENET1_ClockRoot_MuxSysPll2Pfd1
Definition: fsl_clock.h:1478
@ kCLOCK_LPUART3_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1236
@ kCLOCK_CKO2_ClockRoot_MuxSysPll2Pfd3
Definition: fsl_clock.h:1725
@ kCLOCK_CAN1_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1185
@ kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1201
@ kCLOCK_GC355_ClockRoot_MuxSysPll2Pfd1
Definition: fsl_clock.h:1626
@ kCLOCK_ASRC_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1544
@ kCLOCK_EMV2_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1465
@ kCLOCK_M4_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:972
@ kCLOCK_LPUART10_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1302
@ kCLOCK_MQS_ClockRoot_MuxAudioPllOut
Definition: fsl_clock.h:1557
@ kCLOCK_CSI2_UI_ClockRoot_MuxVideoPllOut
Definition: fsl_clock.h:1698
@ kCLOCK_BUS_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:985
@ kCLOCK_LPUART11_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1313
@ kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1045
@ kCLOCK_BUS_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:983
@ kCLOCK_GPT2_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1114
@ kCLOCK_SAI3_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1603
@ kCLOCK_LPSPI1_ClockRoot_MuxSysPll3Pfd2
Definition: fsl_clock.h:1395
@ kCLOCK_LPUART3_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1233
@ kCLOCK_LPUART12_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1324
@ kCLOCK_LPUART6_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1264
@ kCLOCK_CSI2_UI_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1693
@ kCLOCK_EMV1_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1452
@ kCLOCK_EMV2_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1462
@ kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1661
@ kCLOCK_ACMP_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1074
@ kCLOCK_EMV1_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1455
@ kCLOCK_GPT6_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1153
@ kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:1376
@ kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:1686
@ kCLOCK_GPT6_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1155
@ kCLOCK_CKO1_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1713
@ kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Out
Definition: fsl_clock.h:1645
@ kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1507
@ kCLOCK_EMV1_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1456
@ kCLOCK_SEMC_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1005
@ kCLOCK_LPI2C3_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1353
@ kCLOCK_SAI3_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1604
@ kCLOCK_LPI2C6_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1384
@ kCLOCK_LPUART6_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1265
@ kCLOCK_EMV2_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1463
@ kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1513
@ kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1521
@ kCLOCK_M4_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:974
@ kCLOCK_SPDIF_ClockRoot_MuxOscRc400M
Definition: fsl_clock.h:1573
@ kCLOCK_LPI2C3_ClockRoot_MuxSysPll3Div2
Definition: fsl_clock.h:1355
@ kCLOCK_SAI4_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1614
@ kCLOCK_CSI_ClockRoot_MuxSysPll3Out
Definition: fsl_clock.h:1706
@ kCLOCK_LPUART10_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1306
@ kCLOCK_LPUART4_ClockRoot_MuxOscRc16M
Definition: fsl_clock.h:1244
@ kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0
Definition: fsl_clock.h:1165
@ kCLOCK_GC355_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1622
@ kCLOCK_LCDIF_ClockRoot_MuxSysPll2Pfd2
Definition: fsl_clock.h:1636
@ kCLOCK_FLEXIO1_ClockRoot_MuxSysPll1Div5
Definition: fsl_clock.h:1086
@ kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd2
Definition: fsl_clock.h:1447
@ kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2
Definition: fsl_clock.h:1721
@ kCLOCK_CKO2_ClockRoot_MuxOsc24MOut
Definition: fsl_clock.h:1722
@ kCLOCK_UsbSrcUnused
Definition: fsl_clock.h:1175
@ kCLOCK_Usb480M
Definition: fsl_clock.h:1174
@ kCLOCK_1MHzOutDisable
Definition: fsl_clock.h:1986
@ kCLOCK_1MHzOutEnableLocked1Mhz
Definition: fsl_clock.h:1987
@ kCLOCK_1MHzOutEnableFreeRunning1Mhz
Definition: fsl_clock.h:1988
@ kCLOCK_PllPostDiv8
Definition: fsl_clock.h:1812
@ kCLOCK_PllPostDiv4
Definition: fsl_clock.h:1813
@ kCLOCK_Level4
Definition: fsl_clock.h:2001
@ kCLOCK_Level3
Definition: fsl_clock.h:2000
@ kCLOCK_Level2
Definition: fsl_clock.h:1999
@ kCLOCK_Level1
Definition: fsl_clock.h:1998
@ kCLOCK_Level0
Definition: fsl_clock.h:1997
@ kCLOCK_ModeWait
Definition: fsl_clock.h:659
@ kCLOCK_ModeStop
Definition: fsl_clock.h:660
@ kCLOCK_ModeRun
Definition: fsl_clock.h:658
@ kCLOCK_PllClkSrc24M
Definition: fsl_clock.h:1188
@ kCLOCK_PllSrcClkPN
Definition: fsl_clock.h:1189
@ kCLOCK_Off
Definition: fsl_clock.h:1774
@ kCLOCK_On
Definition: fsl_clock.h:1775
@ kCLOCK_Gpt6
Definition: fsl_clock.h:568
@ kCLOCK_Snvs
Definition: fsl_clock.h:538
@ kCLOCK_Edma
Definition: fsl_clock.h:520
@ kCLOCK_Video_Mux
Definition: fsl_clock.h:634
@ kCLOCK_Lpuart12
Definition: fsl_clock.h:596
@ kCLOCK_Qtimer3
Definition: fsl_clock.h:571
@ kCLOCK_Flexspi2
Definition: fsl_clock.h:527
@ kCLOCK_Lpuart11
Definition: fsl_clock.h:595
@ kCLOCK_Src
Definition: fsl_clock.h:507
@ kCLOCK_Gpt4
Definition: fsl_clock.h:566
@ kCLOCK_Sim1
Definition: fsl_clock.h:609
@ kCLOCK_Adc_Etc
Definition: fsl_clock.h:547
@ kCLOCK_Usb
Definition: fsl_clock.h:613
@ kCLOCK_Qtimer2
Definition: fsl_clock.h:570
@ kCLOCK_Gpio
Definition: fsl_clock.h:550
@ kCLOCK_Gpc
Definition: fsl_clock.h:509
@ kCLOCK_Sai4
Definition: fsl_clock.h:624
@ kCLOCK_Snvs_Hp
Definition: fsl_clock.h:537
@ kCLOCK_Flexspi1
Definition: fsl_clock.h:526
@ kCLOCK_Dac
Definition: fsl_clock.h:556
@ kCLOCK_Lpadc1
Definition: fsl_clock.h:554
@ kCLOCK_Mu_A
Definition: fsl_clock.h:518
@ kCLOCK_M4_Xrdc
Definition: fsl_clock.h:530
@ kCLOCK_Pit2
Definition: fsl_clock.h:562
@ kCLOCK_Qtimer1
Definition: fsl_clock.h:569
@ kCLOCK_Can3
Definition: fsl_clock.h:584
@ kCLOCK_Xecc
Definition: fsl_clock.h:532
@ kCLOCK_Sim_M7
Definition: fsl_clock.h:500
@ kCLOCK_Gpt3
Definition: fsl_clock.h:565
@ kCLOCK_Iomuxc_Lpsr
Definition: fsl_clock.h:549
@ kCLOCK_M7_Xrdc
Definition: fsl_clock.h:529
@ kCLOCK_Key_Manager
Definition: fsl_clock.h:534
@ kCLOCK_M7
Definition: fsl_clock.h:498
@ kCLOCK_Lpspi6
Definition: fsl_clock.h:608
@ kCLOCK_Mu_B
Definition: fsl_clock.h:519
@ kCLOCK_Sema
Definition: fsl_clock.h:517
@ kCLOCK_Lpi2c5
Definition: fsl_clock.h:601
@ kCLOCK_Ccm
Definition: fsl_clock.h:508
@ kCLOCK_Mipi_Csi
Definition: fsl_clock.h:630
@ kCLOCK_Dcic_Mipi
Definition: fsl_clock.h:632
@ kCLOCK_Asrc
Definition: fsl_clock.h:617
@ kCLOCK_Pdm
Definition: fsl_clock.h:619
@ kCLOCK_Uniq_Edt_I
Definition: fsl_clock.h:635
@ kCLOCK_M4
Definition: fsl_clock.h:499
@ kCLOCK_Enet_1g
Definition: fsl_clock.h:612
@ kCLOCK_Rdc
Definition: fsl_clock.h:528
@ kCLOCK_Sim_M
Definition: fsl_clock.h:501
@ kCLOCK_Cstrace
Definition: fsl_clock.h:541
@ kCLOCK_Lcdif
Definition: fsl_clock.h:627
@ kCLOCK_Lmem
Definition: fsl_clock.h:525
@ kCLOCK_Sim_Lpsr
Definition: fsl_clock.h:504
@ kCLOCK_Gpt5
Definition: fsl_clock.h:567
@ kCLOCK_Qtimer4
Definition: fsl_clock.h:572
@ kCLOCK_Pit1
Definition: fsl_clock.h:561
@ kCLOCK_Lcdifv2
Definition: fsl_clock.h:628
@ kCLOCK_Dcic_Lcd
Definition: fsl_clock.h:633
@ kCLOCK_Sim_Disp
Definition: fsl_clock.h:502
@ kCLOCK_Lpuart10
Definition: fsl_clock.h:594
@ kCLOCK_Edma_Lpsr
Definition: fsl_clock.h:521
@ kCLOCK_Cdog
Definition: fsl_clock.h:614
@ kCLOCK_Gpu2d
Definition: fsl_clock.h:626
@ kCLOCK_Caam
Definition: fsl_clock.h:539
@ kCLOCK_Ssarc
Definition: fsl_clock.h:510
@ kCLOCK_Wdog4
Definition: fsl_clock.h:515
@ kCLOCK_Mipi_Dsi
Definition: fsl_clock.h:629
@ kCLOCK_Lpuart9
Definition: fsl_clock.h:593
@ kCLOCK_Sim_Per
Definition: fsl_clock.h:503
@ kCLOCK_Sim_R
Definition: fsl_clock.h:511
@ kCLOCK_Hrtimer
Definition: fsl_clock.h:577
@ kCLOCK_Romcp
Definition: fsl_clock.h:522
@ kCLOCK_Puf
Definition: fsl_clock.h:535
@ kCLOCK_Flexram
Definition: fsl_clock.h:524
@ kCLOCK_Jtag_Mux
Definition: fsl_clock.h:540
@ kCLOCK_Sim2
Definition: fsl_clock.h:610
@ kCLOCK_Lpadc2
Definition: fsl_clock.h:555
@ kCLOCK_Lpspi5
Definition: fsl_clock.h:607
@ kCLOCK_Lpi2c6
Definition: fsl_clock.h:602
@ kCLOCK_Iee
Definition: fsl_clock.h:533
int32_t status_t
Type used for all status and error return values.
Definition: fsl_common.h:225
PLL configuration for ARM.
Definition: fsl_clock.h:1194
PLL configuration for AUDIO and VIDEO.
Definition: fsl_clock.h:1226
PLL configuration fro AUDIO PLL, SYSTEM PLL1 and VIDEO PLL.
Definition: fsl_clock.h:1884
PLL configuration for ENET.
Definition: fsl_clock.h:1247
The structure used to configure clock group.
Definition: fsl_clock.h:1745
Spread specturm configure Pll.
Definition: fsl_clock.h:1843
Clock root configuration.
Definition: fsl_clock.h:1914
Clock root configuration in SetPoint Mode.
Definition: fsl_clock.h:1922
PLL configure for Sys Pll1.
Definition: fsl_clock.h:1859
PLL configure for Sys Pll2.
Definition: fsl_clock.h:1850
PLL configuration for USB.
Definition: fsl_clock.h:1201
PLL configuration for AUDIO and VIDEO.
Definition: fsl_clock.h:1236
Definition: deflate.c:114