RTEMS 6.1-rc7
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PIXEL_PAYLOAD_SIZE - PEXEL_PAYLOAD_SIZE

#define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK   (0xFFFFU)
 
#define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK)
 

PIXEL_FIFO_SEND_LEVEL - PIXEL_FIFO_SEND_LEVEL

#define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK   (0xFFFFU)
 
#define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK)
 

INTERFACE_COLOR_CODING - INTERFACE_COLOR_CODING

#define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK   (0x7U)
 
#define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT)) & DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK)
 

PIXEL_FORMAT - PIXEL_FORMAT

#define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_MASK   (0x3U)
 
#define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_MASK)
 

VSYNC_POLARITY - VSYNC_POLARITY

#define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_MASK   (0x1U)
 
#define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT)) & DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_MASK)
 

HSYNC_POLARITY - HSYNC_POLARITY

#define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_MASK   (0x1U)
 
#define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT)) & DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_MASK)
 

VIDEO_MODE - VIDEO_MODE

#define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_MASK   (0x3U)
 
#define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_SHIFT)) & DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_MASK)
 

HFP - HFP

#define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_MASK   (0xFFFFU)
 
#define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_MASK)
 

HBP - HBP

#define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_MASK   (0xFFFFU)
 
#define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_MASK)
 

HSA - HSA

#define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_MASK   (0xFFFFU)
 
#define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_MASK)
 

ENABLE_MULT_PKTS - ENABLE_MULT_PKTS

#define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK   (0x1U)
 
#define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT)) & DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK)
 

VBP - VBP

#define DSI_HOST_DPI_INTFC_VBP_NUM_LINES_MASK   (0xFFU)
 
#define DSI_HOST_DPI_INTFC_VBP_NUM_LINES_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_VBP_NUM_LINES(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VBP_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VBP_NUM_LINES_MASK)
 

VFP - VFP

#define DSI_HOST_DPI_INTFC_VFP_NUM_LINES_MASK   (0xFFU)
 
#define DSI_HOST_DPI_INTFC_VFP_NUM_LINES_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_VFP_NUM_LINES(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VFP_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VFP_NUM_LINES_MASK)
 

BLLP_MODE - BLLP_MODE

#define DSI_HOST_DPI_INTFC_BLLP_MODE_LP_MASK   (0x1U)
 
#define DSI_HOST_DPI_INTFC_BLLP_MODE_LP_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_BLLP_MODE_LP(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_BLLP_MODE_LP_SHIFT)) & DSI_HOST_DPI_INTFC_BLLP_MODE_LP_MASK)
 

USE_NULL_PKT_BLLP - USE_NULL_PKT_BLLP

#define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_MASK   (0x1U)
 
#define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_SHIFT)) & DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_MASK)
 

VACTIVE - VACTIVE

#define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_MASK   (0x3FFFU)
 
#define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_MASK)
 

PIXEL_PAYLOAD_SIZE - PEXEL_PAYLOAD_SIZE

#define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK   (0xFFFFU)
 
#define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK)
 

PIXEL_FIFO_SEND_LEVEL - PIXEL_FIFO_SEND_LEVEL

#define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK   (0xFFFFU)
 
#define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK)
 

INTERFACE_COLOR_CODING - INTERFACE_COLOR_CODING

#define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK   (0x7U)
 
#define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT)) & DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK)
 

PIXEL_FORMAT - PIXEL_FORMAT

#define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_MASK   (0x3U)
 
#define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_MASK)
 

VSYNC_POLARITY - VSYNC_POLARITY

#define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_MASK   (0x1U)
 
#define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT)) & DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_MASK)
 

HSYNC_POLARITY - HSYNC_POLARITY

#define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_MASK   (0x1U)
 
#define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT)) & DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_MASK)
 

VIDEO_MODE - VIDEO_MODE

#define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_MASK   (0x3U)
 
#define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_SHIFT)) & DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_MASK)
 

HFP - HFP

#define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_MASK   (0xFFFFU)
 
#define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_MASK)
 

HBP - HBP

#define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_MASK   (0xFFFFU)
 
#define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_MASK)
 

HSA - HSA

#define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_MASK   (0xFFFFU)
 
#define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_MASK)
 

ENABLE_MULT_PKTS - ENABLE_MULT_PKTS

#define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK   (0x1U)
 
#define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT)) & DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK)
 

VBP - VBP

#define DSI_HOST_DPI_INTFC_VBP_NUM_LINES_MASK   (0xFFU)
 
#define DSI_HOST_DPI_INTFC_VBP_NUM_LINES_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_VBP_NUM_LINES(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VBP_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VBP_NUM_LINES_MASK)
 

VFP - VFP

#define DSI_HOST_DPI_INTFC_VFP_NUM_LINES_MASK   (0xFFU)
 
#define DSI_HOST_DPI_INTFC_VFP_NUM_LINES_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_VFP_NUM_LINES(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VFP_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VFP_NUM_LINES_MASK)
 

BLLP_MODE - BLLP_MODE

#define DSI_HOST_DPI_INTFC_BLLP_MODE_LP_MASK   (0x1U)
 
#define DSI_HOST_DPI_INTFC_BLLP_MODE_LP_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_BLLP_MODE_LP(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_BLLP_MODE_LP_SHIFT)) & DSI_HOST_DPI_INTFC_BLLP_MODE_LP_MASK)
 

USE_NULL_PKT_BLLP - USE_NULL_PKT_BLLP

#define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_MASK   (0x1U)
 
#define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_SHIFT)) & DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_MASK)
 

VACTIVE - VACTIVE

#define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_MASK   (0x3FFFU)
 
#define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_SHIFT   (0U)
 
#define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_MASK)
 

Detailed Description

Macro Definition Documentation

◆ DSI_HOST_DPI_INTFC_BLLP_MODE_LP [1/2]

#define DSI_HOST_DPI_INTFC_BLLP_MODE_LP (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_BLLP_MODE_LP_SHIFT)) & DSI_HOST_DPI_INTFC_BLLP_MODE_LP_MASK)

LP - Optimize bllp periods to Low Power mode when possible 0b0..Blanking packets are sent during BLLP periods 0b1..LP mode is used for BLLP periods

◆ DSI_HOST_DPI_INTFC_BLLP_MODE_LP [2/2]

#define DSI_HOST_DPI_INTFC_BLLP_MODE_LP (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_BLLP_MODE_LP_SHIFT)) & DSI_HOST_DPI_INTFC_BLLP_MODE_LP_MASK)

LP - Optimize bllp periods to Low Power mode when possible 0b0..Blanking packets are sent during BLLP periods 0b1..LP mode is used for BLLP periods

◆ DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS [1/2]

#define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT)) & DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK)

ENABLE_MULT_PKTS - Enable Multiple packets per video line. When enabled, PIXEL_PAYLOAD_SIZE[PAYLOAD_SIZE] must be set to exactly half the size of the video line 0b0..Video Line is sent in a single packet 0b1..Video Line is sent in two packets

◆ DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS [2/2]

#define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT)) & DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK)

ENABLE_MULT_PKTS - Enable Multiple packets per video line. When enabled, PIXEL_PAYLOAD_SIZE[PAYLOAD_SIZE] must be set to exactly half the size of the video line 0b0..Video Line is sent in a single packet 0b1..Video Line is sent in two packets

◆ DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE [1/2]

#define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_MASK)

PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal back porch blanking packet.

◆ DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE [2/2]

#define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_MASK)

PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal back porch blanking packet.

◆ DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE [1/2]

#define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_MASK)

PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal front porch blanking packet.

◆ DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE [2/2]

#define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_MASK)

PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal front porch blanking packet.

◆ DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE [1/2]

#define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_MASK)

PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal sync width filler blanking packet.

◆ DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE [2/2]

#define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_MASK)

PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal sync width filler blanking packet.

◆ DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY [1/2]

#define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT)) & DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_MASK)

HSYNC_POLARITY - Sets polarity of dpi_hsync_input 0b0..active low 0b1..active high

◆ DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY [2/2]

#define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT)) & DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_MASK)

HSYNC_POLARITY - Sets polarity of dpi_hsync_input 0b0..active low 0b1..active high

◆ DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG [1/2]

#define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT)) & DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK)

RGB_CONFIG - Sets the distribution of RGB bits within the 24-bit d bus, as specified by the DPI specification. 0b000..16-bit Configuration 1 0b001..16-bit Configuration 2 0b010..16-bit Configuration 3 0b011..18-bit Configuration 1 0b100..18-bit Configuration 2 0b101..24-bit 0b110, 0b111..Reserved

◆ DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG [2/2]

#define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT)) & DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK)

RGB_CONFIG - Sets the distribution of RGB bits within the 24-bit d bus, as specified by the DPI specification. 0b000..16-bit Configuration 1 0b001..16-bit Configuration 2 0b010..16-bit Configuration 3 0b011..18-bit Configuration 1 0b100..18-bit Configuration 2 0b101..24-bit 0b110, 0b111..Reserved

◆ DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL [1/2]

#define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK)

FIFO_SEND_LEVEL - In order to optimize DSI utility, the DPI bridge buffers a certain number of DPI pixels before initiating a DSI packet. This configuration port controls the level at which the DPI Host bridge begins sending pixels.

◆ DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL [2/2]

#define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK)

FIFO_SEND_LEVEL - In order to optimize DSI utility, the DPI bridge buffers a certain number of DPI pixels before initiating a DSI packet. This configuration port controls the level at which the DPI Host bridge begins sending pixels.

◆ DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT [1/2]

#define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_MASK)

PIXEL_FORMAT - Sets the DSI packet type of the pixels 0b00..16 bit 0b01..18 bit 0b10..18 bit loosely packed 0b11..24 bit

◆ DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT [2/2]

#define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_MASK)

PIXEL_FORMAT - Sets the DSI packet type of the pixels 0b00..16 bit 0b01..18 bit 0b10..18 bit loosely packed 0b11..24 bit

◆ DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE [1/2]

#define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK)

PAYLOAD_SIZE - Maximum number of pixels that should be sent as one DSI packet. Recommended to be evenly divisible by the line size (in pixels).

◆ DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE [2/2]

#define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK)

PAYLOAD_SIZE - Maximum number of pixels that should be sent as one DSI packet. Recommended to be evenly divisible by the line size (in pixels).

◆ DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL [1/2]

#define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_SHIFT)) & DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_MASK)

NULL - Selects type of blanking packet to be sent during bllp 0b0..Blanking packet used in bllp region 1 0b1..Null packet used in bllp region

◆ DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL [2/2]

#define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_SHIFT)) & DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_MASK)

NULL - Selects type of blanking packet to be sent during bllp 0b0..Blanking packet used in bllp region 1 0b1..Null packet used in bllp region

◆ DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES [1/2]

#define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_MASK)

NUM_LINES - Sets the number of lines in the vertical active aread.

◆ DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES [2/2]

#define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_MASK)

NUM_LINES - Sets the number of lines in the vertical active aread.

◆ DSI_HOST_DPI_INTFC_VBP_NUM_LINES [1/2]

#define DSI_HOST_DPI_INTFC_VBP_NUM_LINES (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VBP_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VBP_NUM_LINES_MASK)

NUM_LINES - Sets the number of lines in the vertical back porch.

◆ DSI_HOST_DPI_INTFC_VBP_NUM_LINES [2/2]

#define DSI_HOST_DPI_INTFC_VBP_NUM_LINES (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VBP_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VBP_NUM_LINES_MASK)

NUM_LINES - Sets the number of lines in the vertical back porch.

◆ DSI_HOST_DPI_INTFC_VFP_NUM_LINES [1/2]

#define DSI_HOST_DPI_INTFC_VFP_NUM_LINES (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VFP_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VFP_NUM_LINES_MASK)

NUM_LINES - Sets the number of lines in the vertical front porch.

◆ DSI_HOST_DPI_INTFC_VFP_NUM_LINES [2/2]

#define DSI_HOST_DPI_INTFC_VFP_NUM_LINES (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VFP_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VFP_NUM_LINES_MASK)

NUM_LINES - Sets the number of lines in the vertical front porch.

◆ DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE [1/2]

#define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_SHIFT)) & DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_MASK)

VIDEO_MODE - Select DSI video mode that the host DPI module should generate packets for. 0b00..Non-Burst mode with Sync Pulses 0b01..Non-Burst mode with Sync Events 0b10..Burst mode 0b11..Reserved, not valid

◆ DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE [2/2]

#define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_SHIFT)) & DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_MASK)

VIDEO_MODE - Select DSI video mode that the host DPI module should generate packets for. 0b00..Non-Burst mode with Sync Pulses 0b01..Non-Burst mode with Sync Events 0b10..Burst mode 0b11..Reserved, not valid

◆ DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY [1/2]

#define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT)) & DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_MASK)

VSYNC_POLARITY - Sets polarity of dpi_vsync_input 0b0..active low 0b1..active high

◆ DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY [2/2]

#define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY (   x)    (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT)) & DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_MASK)

VSYNC_POLARITY - Sets polarity of dpi_vsync_input 0b0..active low 0b1..active high