RTEMS 6.1-rc7
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Data Fields

Flexible Memory Controller Bank5 and 6. More...

#include <stm32h723xx.h>

Data Fields

__IO uint32_t SDCR [2]
 
__IO uint32_t SDTR [2]
 
__IO uint32_t SDCMR
 
__IO uint32_t SDRTR
 
__IO uint32_t SDSR
 

Detailed Description

Flexible Memory Controller Bank5 and 6.

Field Documentation

◆ SDCMR

__IO uint32_t FMC_Bank5_6_TypeDef::SDCMR

SDRAM Command Mode register, Address offset: 0x150

◆ SDCR

__IO uint32_t FMC_Bank5_6_TypeDef::SDCR

SDRAM Control registers , Address offset: 0x140-0x144

◆ SDRTR

__IO uint32_t FMC_Bank5_6_TypeDef::SDRTR

SDRAM Refresh Timer register, Address offset: 0x154

◆ SDSR

__IO uint32_t FMC_Bank5_6_TypeDef::SDSR

SDRAM Status register, Address offset: 0x158

◆ SDTR

__IO uint32_t FMC_Bank5_6_TypeDef::SDTR

SDRAM Timing registers , Address offset: 0x148-0x14C


The documentation for this struct was generated from the following files: