RTEMS 6.1-rc7
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io.h
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1
7/*
8 * Copyright (c) 2012 Sebastian Huber. All rights reserved.
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#ifndef LIBBSP_ARM_STM32F4_IO_H
16#define LIBBSP_ARM_STM32F4_IO_H
17
18#include <stdbool.h>
19#include <stdint.h>
20#include <bspopts.h>
21
22#ifdef __cplusplus
23extern "C" {
24#endif /* __cplusplus */
25
33#define STM32F4_GPIO_PIN(port, index) ((((port) << 4) | (index)) & 0xff)
34
35#define STM32F4_GPIO_PORT_OF_PIN(pin) (((pin) >> 4) & 0xf)
36
37#define STM32F4_GPIO_INDEX_OF_PIN(pin) ((pin) & 0xf)
38
39#ifdef STM32F4_FAMILY_F4XXXX
40
46typedef enum {
47 STM32F4_GPIO_MODE_INPUT,
48 STM32F4_GPIO_MODE_OUTPUT,
49 STM32F4_GPIO_MODE_AF,
50 STM32F4_GPIO_MODE_ANALOG
51} stm32f4_gpio_mode;
52
53typedef enum {
54 STM32F4_GPIO_OTYPE_PUSH_PULL,
55 STM32F4_GPIO_OTYPE_OPEN_DRAIN
56} stm32f4_gpio_otype;
57
58typedef enum {
59 STM32F4_GPIO_OSPEED_2_MHZ,
60 STM32F4_GPIO_OSPEED_25_MHZ,
61 STM32F4_GPIO_OSPEED_50_MHZ,
62 STM32F4_GPIO_OSPEED_100_MHZ
63} stm32f4_gpio_ospeed;
64
65typedef enum {
66 STM32F4_GPIO_NO_PULL,
67 STM32F4_GPIO_PULL_UP,
68 STM32F4_GPIO_PULL_DOWN
69} stm32f4_gpio_pull;
70
71typedef enum {
72 STM32F4_GPIO_AF_SYSTEM = 0,
73 STM32F4_GPIO_AF_TIM1 = 1,
74 STM32F4_GPIO_AF_TIM2 = 1,
75 STM32F4_GPIO_AF_TIM3 = 2,
76 STM32F4_GPIO_AF_TIM4 = 2,
77 STM32F4_GPIO_AF_TIM5 = 2,
78 STM32F4_GPIO_AF_TIM8 = 3,
79 STM32F4_GPIO_AF_TIM9 = 3,
80 STM32F4_GPIO_AF_TIM10 = 3,
81 STM32F4_GPIO_AF_TIM11 = 3,
82 STM32F4_GPIO_AF_I2C1 = 4,
83 STM32F4_GPIO_AF_I2C2 = 4,
84 STM32F4_GPIO_AF_I2C3 = 4,
85 STM32F4_GPIO_AF_SPI1 = 5,
86 STM32F4_GPIO_AF_SPI2 = 5,
87 STM32F4_GPIO_AF_SPI3 = 6,
88 STM32F4_GPIO_AF_USART1 = 7,
89 STM32F4_GPIO_AF_USART2 = 7,
90 STM32F4_GPIO_AF_USART3 = 7,
91 STM32F4_GPIO_AF_UART4 = 8,
92 STM32F4_GPIO_AF_UART5 = 8,
93 STM32F4_GPIO_AF_USART6 = 8,
94 STM32F4_GPIO_AF_CAN1 = 9,
95 STM32F4_GPIO_AF_CAN2 = 9,
96 STM32F4_GPIO_AF_TIM12 = 9,
97 STM32F4_GPIO_AF_TIM13 = 9,
98 STM32F4_GPIO_AF_TIM14 = 9,
99 STM32F4_GPIO_AF_OTG_FS = 10,
100 STM32F4_GPIO_AF_OTG_HS = 10,
101 STM32F4_GPIO_AF_ETH = 11,
102 STM32F4_GPIO_AF_FSMC = 12,
103 STM32F4_GPIO_AF_OTG_HS_FS = 12,
104 STM32F4_GPIO_AF_SDIO = 12,
105 STM32F4_GPIO_AF_DCMI = 13,
106 STM32F4_GPIO_AF_EVENTOUT = 15
107} stm32f4_gpio_af;
108
109typedef union {
110 struct {
111 uint32_t pin_first : 8;
112 uint32_t pin_last : 8;
113 uint32_t mode : 2;
114 uint32_t otype : 1;
115 uint32_t ospeed : 2;
116 uint32_t pupd : 2;
117 uint32_t output : 1;
118 uint32_t af : 4;
119 uint32_t reserved : 4;
120 } fields;
121
122 uint32_t value;
123} stm32f4_gpio_config;
124
125#define STM32F4_GPIO_CONFIG_TERMINAL \
126 { { 0xff, 0xff, 0x3, 0x1, 0x3, 0x3, 0x1, 0xf, 0xf } }
127
130#endif /* STM32F4_FAMILY_F4XXXX */
131#ifdef STM32F4_FAMILY_F10XXX
132
138typedef enum {
139 STM32F4_GPIO_MODE_INPUT,
140 STM32F4_GPIO_MODE_OUTPUT_10MHz,
141 STM32F4_GPIO_MODE_OUTPUT_2MHz,
142 STM32F4_GPIO_MODE_OUTPUT_50MHz
143} stm32f4_gpio_mode;
144
145typedef enum {
146 STM32F4_GPIO_CNF_IN_ANALOG = 0,
147 STM32F4_GPIO_CNF_IN_FLOATING = 1,
148 STM32F4_GPIO_CNF_IN_PULL_UPDOWN = 2,
149
150 STM32F4_GPIO_CNF_OUT_GPIO_PP = 0,
151 STM32F4_GPIO_CNF_OUT_GPIO_OD = 1,
152 STM32F4_GPIO_CNF_OUT_AF_PP = 2,
153 STM32F4_GPIO_CNF_OUT_AF_OD = 3,
154} stm32f4_gpio_cnf;
155
156typedef enum {
157 STM32F4_GPIO_REMAP_DONT_CHANGE,
158 STM32F4_GPIO_REMAP_SPI1_0,
159 STM32F4_GPIO_REMAP_SPI1_1,
160 STM32F4_GPIO_REMAP_I2C1_0,
161 STM32F4_GPIO_REMAP_I2C1_1,
162 STM32F4_GPIO_REMAP_USART1_0,
163 STM32F4_GPIO_REMAP_USART1_1,
164 STM32F4_GPIO_REMAP_USART2_0,
165 STM32F4_GPIO_REMAP_USART2_1,
166 STM32F4_GPIO_REMAP_USART3_0,
167 STM32F4_GPIO_REMAP_USART3_1,
168 STM32F4_GPIO_REMAP_USART3_3,
169 STM32F4_GPIO_REMAP_TIM1_0,
170 STM32F4_GPIO_REMAP_TIM1_1,
171 STM32F4_GPIO_REMAP_TIM1_3,
172 STM32F4_GPIO_REMAP_TIM2_0,
173 STM32F4_GPIO_REMAP_TIM2_1,
174 STM32F4_GPIO_REMAP_TIM2_2,
175 STM32F4_GPIO_REMAP_TIM2_3,
176 STM32F4_GPIO_REMAP_TIM3_0,
177 STM32F4_GPIO_REMAP_TIM3_2,
178 STM32F4_GPIO_REMAP_TIM3_3,
179 STM32F4_GPIO_REMAP_TIM4_0,
180 STM32F4_GPIO_REMAP_TIM4_1,
181 STM32F4_GPIO_REMAP_CAN1_0,
182 STM32F4_GPIO_REMAP_CAN1_2,
183 STM32F4_GPIO_REMAP_CAN1_3,
184 STM32F4_GPIO_REMAP_PD01_0,
185 STM32F4_GPIO_REMAP_PD01_1,
186 STM32F4_GPIO_REMAP_TIM5CH4_0,
187 STM32F4_GPIO_REMAP_TIM5CH4_1,
188 STM32F4_GPIO_REMAP_ADC1_ETRGINJ_0,
189 STM32F4_GPIO_REMAP_ADC1_ETRGINJ_1,
190 STM32F4_GPIO_REMAP_ADC1_ETRGREG_0,
191 STM32F4_GPIO_REMAP_ADC1_ETRGREG_1,
192 STM32F4_GPIO_REMAP_ADC2_ETRGINJ_0,
193 STM32F4_GPIO_REMAP_ADC2_ETRGINJ_1,
194 STM32F4_GPIO_REMAP_ADC2_ETRGREG_0,
195 STM32F4_GPIO_REMAP_ADC2_ETRGREG_1,
196 STM32F4_GPIO_REMAP_ETH_0,
197 STM32F4_GPIO_REMAP_ETH_1,
198 STM32F4_GPIO_REMAP_CAN2_0,
199 STM32F4_GPIO_REMAP_CAN2_1,
200 STM32F4_GPIO_REMAP_MII_RMII_0,
201 STM32F4_GPIO_REMAP_MII_RMII_1,
202 STM32F4_GPIO_REMAP_SWJ_0,
203 STM32F4_GPIO_REMAP_SWJ_1,
204 STM32F4_GPIO_REMAP_SWJ_2,
205 STM32F4_GPIO_REMAP_SWJ_4,
206 STM32F4_GPIO_REMAP_SPI3_0,
207 STM32F4_GPIO_REMAP_SPI3_1,
208 STM32F4_GPIO_REMAP_TIM2ITR1_0,
209 STM32F4_GPIO_REMAP_TIM2ITR1_1,
210 STM32F4_GPIO_REMAP_PTP_PPS_0,
211 STM32F4_GPIO_REMAP_PTP_PPS_1,
212 STM32F4_GPIO_REMAP_TIM15_0,
213 STM32F4_GPIO_REMAP_TIM15_1,
214 STM32F4_GPIO_REMAP_TIM16_0,
215 STM32F4_GPIO_REMAP_TIM16_1,
216 STM32F4_GPIO_REMAP_TIM17_0,
217 STM32F4_GPIO_REMAP_TIM17_1,
218 STM32F4_GPIO_REMAP_CEC_0,
219 STM32F4_GPIO_REMAP_CEC_1,
220 STM32F4_GPIO_REMAP_TIM1_DMA_0,
221 STM32F4_GPIO_REMAP_TIM1_DMA_1,
222 STM32F4_GPIO_REMAP_TIM9_0,
223 STM32F4_GPIO_REMAP_TIM9_1,
224 STM32F4_GPIO_REMAP_TIM10_0,
225 STM32F4_GPIO_REMAP_TIM10_1,
226 STM32F4_GPIO_REMAP_TIM11_0,
227 STM32F4_GPIO_REMAP_TIM11_1,
228 STM32F4_GPIO_REMAP_TIM13_0,
229 STM32F4_GPIO_REMAP_TIM13_1,
230 STM32F4_GPIO_REMAP_TIM14_0,
231 STM32F4_GPIO_REMAP_TIM14_1,
232 STM32F4_GPIO_REMAP_FSMC_0,
233 STM32F4_GPIO_REMAP_FSMC_1,
234 STM32F4_GPIO_REMAP_TIM67_DAC_DMA_0,
235 STM32F4_GPIO_REMAP_TIM67_DAC_DMA_1,
236 STM32F4_GPIO_REMAP_TIM12_0,
237 STM32F4_GPIO_REMAP_TIM12_1,
238 STM32F4_GPIO_REMAP_MISC_0,
239 STM32F4_GPIO_REMAP_MISC_1,
240} stm32f4_gpio_remap;
241
242typedef union {
243 struct {
244 uint32_t pin_first : 8;
245 uint32_t pin_last : 8;
246 uint32_t mode : 2;
247 uint32_t cnf : 2;
248 uint32_t output : 1;
249 uint32_t remap : 8;
250 uint32_t reserved : 3;
251 } fields;
252
253 uint32_t value;
254} stm32f4_gpio_config;
255
256#define STM32F4_GPIO_CONFIG_TERMINAL \
257 { { 0xff, 0xff, 0x3, 0x3, 0x1, 0xff, 0x7 } }
258
261#endif /* STM32F4_FAMILY_F10XXX */
262
263extern const stm32f4_gpio_config stm32f4_start_config_gpio [];
264
265void stm32f4_gpio_set_clock(int pin, bool set);
266
267void stm32f4_gpio_set_config(const stm32f4_gpio_config *config);
268
273void stm32f4_gpio_set_config_array(const stm32f4_gpio_config *configs);
274
275void stm32f4_gpio_set_output(int pin, bool set);
276
277bool stm32f4_gpio_get_input(int pin);
278
279#ifdef STM32F4_FAMILY_F4XXXX
280
286#define STM32F4_PIN_USART(port, idx, altfunc) \
287 { \
288 { \
289 .pin_first = STM32F4_GPIO_PIN(port, idx), \
290 .pin_last = STM32F4_GPIO_PIN(port, idx), \
291 .mode = STM32F4_GPIO_MODE_AF, \
292 .otype = STM32F4_GPIO_OTYPE_PUSH_PULL, \
293 .ospeed = STM32F4_GPIO_OSPEED_2_MHZ, \
294 .pupd = STM32F4_GPIO_PULL_UP, \
295 .af = altfunc \
296 } \
297 }
298
299#define STM32F4_PIN_USART1_TX_PA9 STM32F4_PIN_USART(0, 9, STM32F4_GPIO_AF_USART1)
300#define STM32F4_PIN_USART1_TX_PB6 STM32F4_PIN_USART(1, 6, STM32F4_GPIO_AF_USART1)
301#define STM32F4_PIN_USART1_RX_PA10 STM32F4_PIN_USART(0, 10, STM32F4_GPIO_AF_USART1)
302#define STM32F4_PIN_USART1_RX_PB7 STM32F4_PIN_USART(1, 7, STM32F4_GPIO_AF_USART1)
303
304#define STM32F4_PIN_USART2_TX_PA2 STM32F4_PIN_USART(0, 2, STM32F4_GPIO_AF_USART2)
305#define STM32F4_PIN_USART2_TX_PD5 STM32F4_PIN_USART(3, 5, STM32F4_GPIO_AF_USART2)
306#define STM32F4_PIN_USART2_RX_PA3 STM32F4_PIN_USART(0, 3, STM32F4_GPIO_AF_USART2)
307#define STM32F4_PIN_USART2_RX_PD6 STM32F4_PIN_USART(3, 6, STM32F4_GPIO_AF_USART2)
308
309#define STM32F4_PIN_USART3_TX_PC10 STM32F4_PIN_USART(2, 10, STM32F4_GPIO_AF_USART3)
310#define STM32F4_PIN_USART3_TX_PD8 STM32F4_PIN_USART(3, 8, STM32F4_GPIO_AF_USART3)
311#define STM32F4_PIN_USART3_RX_PC11 STM32F4_PIN_USART(2, 11, STM32F4_GPIO_AF_USART3)
312#define STM32F4_PIN_USART3_RX_PD9 STM32F4_PIN_USART(3, 9, STM32F4_GPIO_AF_USART3)
313
314#define STM32F4_PIN_UART4_TX_PA0 STM32F4_PIN_USART(0, 0, STM32F4_GPIO_AF_UART4)
315#define STM32F4_PIN_UART4_TX_PC10 STM32F4_PIN_USART(2, 10, STM32F4_GPIO_AF_UART4)
316#define STM32F4_PIN_UART4_RX_PA1 STM32F4_PIN_USART(0, 1, STM32F4_GPIO_AF_UART4)
317#define STM32F4_PIN_UART4_RX_PC11 STM32F4_PIN_USART(2, 11, STM32F4_GPIO_AF_UART4)
318
319#define STM32F4_PIN_UART5_TX_PC12 STM32F4_PIN_USART(2, 12, STM32F4_GPIO_AF_UART5)
320#define STM32F4_PIN_UART5_RX_PD2 STM32F4_PIN_USART(3, 2, STM32F4_GPIO_AF_UART5)
321
322#define STM32F4_PIN_USART6_TX_PC6 STM32F4_PIN_USART(2, 6, STM32F4_GPIO_AF_USART6)
323#define STM32F4_PIN_USART6_RX_PC7 STM32F4_PIN_USART(2, 7, STM32F4_GPIO_AF_USART6)
324
327#endif /* STM32F4_FAMILY_F4XXXX */
328#ifdef STM32F4_FAMILY_F10XXX
329
335#define STM32F4_PIN_USART_TX(port, idx, remapvalue) \
336 { \
337 { \
338 .pin_first = STM32F4_GPIO_PIN(port, idx), \
339 .pin_last = STM32F4_GPIO_PIN(port, idx), \
340 .mode = STM32F4_GPIO_MODE_OUTPUT_2MHz, \
341 .cnf = STM32F4_GPIO_CNF_OUT_AF_PP, \
342 .output = 0, \
343 .remap = remapvalue \
344 } \
345 }
346
347#define STM32F4_PIN_USART_RX(port, idx, remapvalue) \
348 { \
349 { \
350 .pin_first = STM32F4_GPIO_PIN(port, idx), \
351 .pin_last = STM32F4_GPIO_PIN(port, idx), \
352 .mode = STM32F4_GPIO_MODE_INPUT, \
353 .cnf = STM32F4_GPIO_CNF_IN_FLOATING, \
354 .output = 0, \
355 .remap = remapvalue \
356 } \
357 }
358
359#define STM32F4_PIN_USART1_TX_MAP_0 STM32F4_PIN_USART_TX(0, 9, STM32F4_GPIO_REMAP_USART1_0)
360#define STM32F4_PIN_USART1_RX_MAP_0 STM32F4_PIN_USART_RX(0, 10, STM32F4_GPIO_REMAP_USART1_0)
361#define STM32F4_PIN_USART1_TX_MAP_1 STM32F4_PIN_USART_TX(1, 6, STM32F4_GPIO_REMAP_USART1_1)
362#define STM32F4_PIN_USART1_RX_MAP_1 STM32F4_PIN_USART_RX(1, 7, STM32F4_GPIO_REMAP_USART1_1)
363
364#define STM32F4_PIN_USART2_TX_MAP_0 STM32F4_PIN_USART_TX(0, 2, STM32F4_GPIO_REMAP_USART2_0)
365#define STM32F4_PIN_USART2_RX_MAP_0 STM32F4_PIN_USART_RX(0, 3, STM32F4_GPIO_REMAP_USART2_0)
366#define STM32F4_PIN_USART2_TX_MAP_1 STM32F4_PIN_USART_TX(3, 5, STM32F4_GPIO_REMAP_USART2_1)
367#define STM32F4_PIN_USART2_RX_MAP_1 STM32F4_PIN_USART_RX(3, 6, STM32F4_GPIO_REMAP_USART2_1)
368
369#define STM32F4_PIN_USART3_TX_MAP_0 STM32F4_PIN_USART_TX(1, 10, STM32F4_GPIO_REMAP_USART3_0)
370#define STM32F4_PIN_USART3_RX_MAP_0 STM32F4_PIN_USART_RX(1, 11, STM32F4_GPIO_REMAP_USART3_0)
371#define STM32F4_PIN_USART3_TX_MAP_1 STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_USART3_1)
372#define STM32F4_PIN_USART3_RX_MAP_1 STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_USART3_1)
373#define STM32F4_PIN_USART3_TX_MAP_3 STM32F4_PIN_USART_TX(3, 8, STM32F4_GPIO_REMAP_USART3_3)
374#define STM32F4_PIN_USART3_RX_MAP_3 STM32F4_PIN_USART_RX(3, 9, STM32F4_GPIO_REMAP_USART3_3)
375
376#define STM32F4_PIN_UART4_TX STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_DONT_CHANGE)
377#define STM32F4_PIN_UART4_RX STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_DONT_CHANGE)
378
379#define STM32F4_PIN_UART5_TX STM32F4_PIN_USART_TX(2, 12, STM32F4_GPIO_REMAP_DONT_CHANGE)
380#define STM32F4_PIN_UART5_RX STM32F4_PIN_USART_RX(3, 2, STM32F4_GPIO_REMAP_DONT_CHANGE)
381
382#define STM32F4_PIN_I2C(port, idx, remapvalue) \
383 { \
384 { \
385 .pin_first = STM32F4_GPIO_PIN(port, idx), \
386 .pin_last = STM32F4_GPIO_PIN(port, idx), \
387 .mode = STM32F4_GPIO_MODE_OUTPUT_2MHz, \
388 .cnf = STM32F4_GPIO_CNF_OUT_AF_OD, \
389 .output = 0, \
390 .remap = remapvalue \
391 } \
392 }
393
394#define STM32F4_PIN_I2C1_SCL_MAP0 STM32F4_PIN_I2C(1, 6, STM32F4_GPIO_REMAP_I2C1_0)
395#define STM32F4_PIN_I2C1_SDA_MAP0 STM32F4_PIN_I2C(1, 7, STM32F4_GPIO_REMAP_I2C1_0)
396#define STM32F4_PIN_I2C1_SCL_MAP1 STM32F4_PIN_I2C(1, 8, STM32F4_GPIO_REMAP_I2C1_1)
397#define STM32F4_PIN_I2C1_SDA_MAP1 STM32F4_PIN_I2C(1, 9, STM32F4_GPIO_REMAP_I2C1_1)
398
399#define STM32F4_PIN_I2C2_SCL STM32F4_PIN_I2C(1, 10, STM32F4_GPIO_REMAP_DONT_CHANGE)
400#define STM32F4_PIN_I2C2_SDA STM32F4_PIN_I2C(1, 11, STM32F4_GPIO_REMAP_DONT_CHANGE)
401
404#endif /* STM32F4_FAMILY_F10XXX */
405
406#ifdef __cplusplus
407}
408#endif /* __cplusplus */
409
410#endif /* LIBBSP_ARM_STM32F4_IO_H */
void stm32f4_gpio_set_config_array(const stm32f4_gpio_config *configs)
Sets the GPIO configuration of an array terminated by STM32F4_GPIO_CONFIG_TERMINAL.
Definition: io.c:216
Definition: deflate.c:114