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RTEMS 6.1-rc7
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Crypto Processor. More...
#include <stm32h730xx.h>
Data Fields | |
__IO uint32_t | CR |
__IO uint32_t | SR |
__IO uint32_t | DIN |
__IO uint32_t | DOUT |
__IO uint32_t | DMACR |
__IO uint32_t | IMSCR |
__IO uint32_t | RISR |
__IO uint32_t | MISR |
__IO uint32_t | K0LR |
__IO uint32_t | K0RR |
__IO uint32_t | K1LR |
__IO uint32_t | K1RR |
__IO uint32_t | K2LR |
__IO uint32_t | K2RR |
__IO uint32_t | K3LR |
__IO uint32_t | K3RR |
__IO uint32_t | IV0LR |
__IO uint32_t | IV0RR |
__IO uint32_t | IV1LR |
__IO uint32_t | IV1RR |
__IO uint32_t | CSGCMCCM0R |
__IO uint32_t | CSGCMCCM1R |
__IO uint32_t | CSGCMCCM2R |
__IO uint32_t | CSGCMCCM3R |
__IO uint32_t | CSGCMCCM4R |
__IO uint32_t | CSGCMCCM5R |
__IO uint32_t | CSGCMCCM6R |
__IO uint32_t | CSGCMCCM7R |
__IO uint32_t | CSGCM0R |
__IO uint32_t | CSGCM1R |
__IO uint32_t | CSGCM2R |
__IO uint32_t | CSGCM3R |
__IO uint32_t | CSGCM4R |
__IO uint32_t | CSGCM5R |
__IO uint32_t | CSGCM6R |
__IO uint32_t | CSGCM7R |
Crypto Processor.
__IO uint32_t CRYP_TypeDef::CR |
CRYP control register, Address offset: 0x00
__IO uint32_t CRYP_TypeDef::CSGCM0R |
CRYP GCM/GMAC context swap register 0, Address offset: 0x70
__IO uint32_t CRYP_TypeDef::CSGCM1R |
CRYP GCM/GMAC context swap register 1, Address offset: 0x74
__IO uint32_t CRYP_TypeDef::CSGCM2R |
CRYP GCM/GMAC context swap register 2, Address offset: 0x78
__IO uint32_t CRYP_TypeDef::CSGCM3R |
CRYP GCM/GMAC context swap register 3, Address offset: 0x7C
__IO uint32_t CRYP_TypeDef::CSGCM4R |
CRYP GCM/GMAC context swap register 4, Address offset: 0x80
__IO uint32_t CRYP_TypeDef::CSGCM5R |
CRYP GCM/GMAC context swap register 5, Address offset: 0x84
__IO uint32_t CRYP_TypeDef::CSGCM6R |
CRYP GCM/GMAC context swap register 6, Address offset: 0x88
__IO uint32_t CRYP_TypeDef::CSGCM7R |
CRYP GCM/GMAC context swap register 7, Address offset: 0x8C
__IO uint32_t CRYP_TypeDef::CSGCMCCM0R |
CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50
__IO uint32_t CRYP_TypeDef::CSGCMCCM1R |
CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54
__IO uint32_t CRYP_TypeDef::CSGCMCCM2R |
CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58
__IO uint32_t CRYP_TypeDef::CSGCMCCM3R |
CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C
__IO uint32_t CRYP_TypeDef::CSGCMCCM4R |
CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60
__IO uint32_t CRYP_TypeDef::CSGCMCCM5R |
CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64
__IO uint32_t CRYP_TypeDef::CSGCMCCM6R |
CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68
__IO uint32_t CRYP_TypeDef::CSGCMCCM7R |
CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C
__IO uint32_t CRYP_TypeDef::DIN |
CRYP data input register, Address offset: 0x08
__IO uint32_t CRYP_TypeDef::DMACR |
CRYP DMA control register, Address offset: 0x10
__IO uint32_t CRYP_TypeDef::DOUT |
CRYP data output register, Address offset: 0x0C
__IO uint32_t CRYP_TypeDef::IMSCR |
CRYP interrupt mask set/clear register, Address offset: 0x14
__IO uint32_t CRYP_TypeDef::IV0LR |
CRYP initialization vector left-word register 0, Address offset: 0x40
__IO uint32_t CRYP_TypeDef::IV0RR |
CRYP initialization vector right-word register 0, Address offset: 0x44
__IO uint32_t CRYP_TypeDef::IV1LR |
CRYP initialization vector left-word register 1, Address offset: 0x48
__IO uint32_t CRYP_TypeDef::IV1RR |
CRYP initialization vector right-word register 1, Address offset: 0x4C
__IO uint32_t CRYP_TypeDef::K0LR |
CRYP key left register 0, Address offset: 0x20
__IO uint32_t CRYP_TypeDef::K0RR |
CRYP key right register 0, Address offset: 0x24
__IO uint32_t CRYP_TypeDef::K1LR |
CRYP key left register 1, Address offset: 0x28
__IO uint32_t CRYP_TypeDef::K1RR |
CRYP key right register 1, Address offset: 0x2C
__IO uint32_t CRYP_TypeDef::K2LR |
CRYP key left register 2, Address offset: 0x30
__IO uint32_t CRYP_TypeDef::K2RR |
CRYP key right register 2, Address offset: 0x34
__IO uint32_t CRYP_TypeDef::K3LR |
CRYP key left register 3, Address offset: 0x38
__IO uint32_t CRYP_TypeDef::K3RR |
CRYP key right register 3, Address offset: 0x3C
__IO uint32_t CRYP_TypeDef::MISR |
CRYP masked interrupt status register, Address offset: 0x1C
__IO uint32_t CRYP_TypeDef::RISR |
CRYP raw interrupt status register, Address offset: 0x18
__IO uint32_t CRYP_TypeDef::SR |
CRYP status register, Address offset: 0x04