36#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H
37#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H
53#define A9MPCORE_SCU_CTRL_SCU_EN BSP_BIT32(0)
54#define A9MPCORE_SCU_CTRL_ADDR_FLT_EN BSP_BIT32(1)
55#define A9MPCORE_SCU_CTRL_RAM_PAR_EN BSP_BIT32(2)
56#define A9MPCORE_SCU_CTRL_SCU_SPEC_LINE_FILL_EN BSP_BIT32(3)
57#define A9MPCORE_SCU_CTRL_FORCE_PORT_0_EN BSP_BIT32(4)
58#define A9MPCORE_SCU_CTRL_SCU_STANDBY_EN BSP_BIT32(5)
59#define A9MPCORE_SCU_CTRL_IC_STANDBY_EN BSP_BIT32(6)
61#define A9MPCORE_SCU_CFG_CPU_COUNT(val) BSP_FLD32(val, 0, 1)
62#define A9MPCORE_SCU_CFG_CPU_COUNT_GET(reg) BSP_FLD32GET(reg, 0, 1)
63#define A9MPCORE_SCU_CFG_CPU_COUNT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1)
64#define A9MPCORE_SCU_CFG_SMP_MODE(val) BSP_FLD32(val, 4, 7)
65#define A9MPCORE_SCU_CFG_SMP_MODE_GET(reg) BSP_FLD32GET(reg, 4, 7)
66#define A9MPCORE_SCU_CFG_SMP_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
67#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE(val) BSP_FLD32(val, 8, 15)
68#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_GET(reg) BSP_FLD32GET(reg, 8, 15)
69#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
72#define A9MPCORE_SCU_INVSS_CPU0(ways) BSP_FLD32(val, 0, 3)
73#define A9MPCORE_SCU_INVSS_CPU0_GET(reg)
74#define A9MPCORE_SCU_INVSS_CPU0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
75#define A9MPCORE_SCU_INVSS_CPU1(ways) BSP_FLD32(val, 4, 7)
76#define A9MPCORE_SCU_INVSS_CPU1_GET(reg)
77#define A9MPCORE_SCU_INVSS_CPU1_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
78#define A9MPCORE_SCU_INVSS_CPU2(ways) BSP_FLD32(val, 8, 11)
79#define A9MPCORE_SCU_INVSS_CPU2_GET(reg)
80#define A9MPCORE_SCU_INVSS_CPU2_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
81#define A9MPCORE_SCU_INVSS_CPU3(ways) BSP_FLD32(val, 12, 15)
82#define A9MPCORE_SCU_INVSS_CPU3_GET(reg)
83#define A9MPCORE_SCU_INVSS_CPU3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
84 uint32_t reserved_09[8];
86#define A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE BSP_BIT32(0)
87 uint32_t reserved_10[3];
90 uint32_t reserved_48[2];
101#define A9MPCORE_GT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15)
102#define A9MPCORE_GT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15)
103#define A9MPCORE_GT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
104#define A9MPCORE_GT_CTRL_AUTOINC_EN BSP_BIT32(3)
105#define A9MPCORE_GT_CTRL_IRQ_EN BSP_BIT32(2)
106#define A9MPCORE_GT_CTRL_COMP_EN BSP_BIT32(1)
107#define A9MPCORE_GT_CTRL_TMR_EN BSP_BIT32(0)
109#define A9MPCORE_GT_IRQST_EFLG BSP_BIT32(0)
111 uint32_t cmpvallower;
112 uint32_t cmpvalupper;
120#define A9MPCORE_PT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15)
121#define A9MPCORE_PT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15)
122#define A9MPCORE_PT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
123#define A9MPCORE_PT_CTRL_IRQ_EN BSP_BIT32(2)
124#define A9MPCORE_PT_CTRL_AUTO_RLD BSP_BIT32(1)
125#define A9MPCORE_PT_CTRL_TMR_EN BSP_BIT32(0)
127#define A9MPCORE_PT_IRQST_EFLG BSP_BIT32(0)
144 uint32_t reserved_58[42];
146 uint32_t reserved_100[64];
148 uint32_t reserved_21c[249];
150 uint32_t reserved_610[4];
152 uint32_t reserved_638[626];
This header file provides utility macros for BSPs.
Definition: arm-a9mpcore-regs.h:95
Definition: arm-a9mpcore-regs.h:98
Definition: arm-a9mpcore-regs.h:139
Definition: arm-a9mpcore-regs.h:116
Definition: arm-a9mpcore-regs.h:130
Definition: arm-a9mpcore-regs.h:51
Definition: arm-a9mpcore-regs.h:142