RTEMS 6.1-rc7
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stm32h7xx_hal_rcc_ex.h
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1
18/* Define to prevent recursive inclusion -------------------------------------*/
19#ifndef STM32H7xx_HAL_RCC_EX_H
20#define STM32H7xx_HAL_RCC_EX_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26/* Includes ------------------------------------------------------------------*/
27#include "stm32h7xx_hal_def.h"
28
37/* Exported types ------------------------------------------------------------*/
46typedef struct
47{
48
49 uint32_t PLL2M;
52 uint32_t PLL2N;
57 uint32_t PLL2P;
61 uint32_t PLL2Q;
64 uint32_t PLL2R;
66 uint32_t PLL2RGE;
68 uint32_t PLL2VCOSEL;
71 uint32_t PLL2FRACN;
74
78typedef struct
79{
80
81 uint32_t PLL3M;
84 uint32_t PLL3N;
89 uint32_t PLL3P;
93 uint32_t PLL3Q;
96 uint32_t PLL3R;
98 uint32_t PLL3RGE;
100 uint32_t PLL3VCOSEL;
103 uint32_t PLL3FRACN;
106
110typedef struct
111{
112 uint32_t PLL1_P_Frequency;
113 uint32_t PLL1_Q_Frequency;
114 uint32_t PLL1_R_Frequency;
116
120typedef struct
121{
122 uint32_t PLL2_P_Frequency;
123 uint32_t PLL2_Q_Frequency;
124 uint32_t PLL2_R_Frequency;
126
130typedef struct
131{
132 uint32_t PLL3_P_Frequency;
133 uint32_t PLL3_Q_Frequency;
134 uint32_t PLL3_R_Frequency;
136
137
141typedef struct
142{
155#if defined(QUADSPI)
156 uint32_t QspiClockSelection;
158#endif /* QUADSPI */
159
160#if defined(OCTOSPI1) || defined(OCTOSPI2)
161 uint32_t OspiClockSelection;
163#endif /*(OCTOSPI1) || (OCTOSPI2)*/
164
165
166#if defined(DSI)
167 uint32_t DsiClockSelection;
169#endif /* DSI */
170
180#if defined(SAI3)
181 uint32_t Sai23ClockSelection;
183#endif /* SAI3 */
184
185#if defined(RCC_CDCCIP1R_SAI2ASEL)
186 uint32_t Sai2AClockSelection;
188#endif /* RCC_CDCCIP1R_SAI2ASEL */
189
190#if defined(RCC_CDCCIP1R_SAI2BSEL)
191 uint32_t Sai2BClockSelection;
193#endif /* RCC_CDCCIP1R_SAI2BSEL */
194
207#if defined(DFSDM2_BASE)
208 uint32_t Dfsdm2ClockSelection;
210#endif /* DFSDM2_BASE */
211
212#if defined(FDCAN1) || defined(FDCAN2)
213 uint32_t FdcanClockSelection;
215#endif /*FDCAN1 || FDCAN2*/
216
229#if defined(I2C5)
230 uint32_t I2c1235ClockSelection;
232#else
235#endif /*I2C5*/
236
260#if defined(SAI4)
261 uint32_t Sai4AClockSelection;
264 uint32_t Sai4BClockSelection;
266#endif /* SAI4 */
267
274#if defined(HRTIM1)
275 uint32_t Hrtim1ClockSelection;
277#endif /* HRTIM1 */
278
282
284#if defined(I2C5)
285#define I2c123ClockSelection I2c1235ClockSelection
286#else
287#define I2c1235ClockSelection I2c123ClockSelection
288#endif /*I2C5*/
289
290
294typedef struct
295{
296 uint32_t Prescaler;
299 uint32_t Source;
302 uint32_t Polarity;
305 uint32_t ReloadValue;
316
320typedef struct
321{
322 uint32_t ReloadValue;
338
344/* Exported constants --------------------------------------------------------*/
355#if defined(UART9) && defined(USART10)
356#define RCC_PERIPHCLK_USART16910 ((uint64_t)(0x00000001U))
357#define RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16910
358#define RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16910
359#define RCC_PERIPHCLK_UART9 RCC_PERIPHCLK_USART16910
360#define RCC_PERIPHCLK_USART10 RCC_PERIPHCLK_USART16910
361/*alias*/
362#define RCC_PERIPHCLK_USART16 RCC_PERIPHCLK_USART16910
363#else
364#define RCC_PERIPHCLK_USART16 ((uint64_t)(0x00000001U))
365#define RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16
366#define RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16
367/* alias */
368#define RCC_PERIPHCLK_USART16910 RCC_PERIPHCLK_USART16
369#endif /* UART9 && USART10*/
370#define RCC_PERIPHCLK_USART234578 ((uint64_t)(0x00000002U))
371#define RCC_PERIPHCLK_USART2 RCC_PERIPHCLK_USART234578
372#define RCC_PERIPHCLK_USART3 RCC_PERIPHCLK_USART234578
373#define RCC_PERIPHCLK_UART4 RCC_PERIPHCLK_USART234578
374#define RCC_PERIPHCLK_UART5 RCC_PERIPHCLK_USART234578
375#define RCC_PERIPHCLK_UART7 RCC_PERIPHCLK_USART234578
376#define RCC_PERIPHCLK_UART8 RCC_PERIPHCLK_USART234578
377#define RCC_PERIPHCLK_LPUART1 ((uint64_t)(0x00000004U))
378#if defined(I2C5)
379#define RCC_PERIPHCLK_I2C1235 ((uint64_t)(0x00000008U))
380#define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C1235
381#define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C1235
382#define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C1235
383/* alias */
384#define RCC_PERIPHCLK_I2C123 RCC_PERIPHCLK_I2C1235
385#else
386#define RCC_PERIPHCLK_I2C123 ((uint64_t)(0x00000008U))
387#define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C123
388#define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C123
389#define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C123
390#endif /*I2C5*/
391#define RCC_PERIPHCLK_I2C4 ((uint64_t)(0x00000010U))
392#if defined(I2C5)
393#define RCC_PERIPHCLK_I2C5 RCC_PERIPHCLK_I2C1235
394#endif /*I2C5*/
395#define RCC_PERIPHCLK_LPTIM1 ((uint64_t)(0x00000020U))
396#define RCC_PERIPHCLK_LPTIM2 ((uint64_t)(0x00000040U))
397#define RCC_PERIPHCLK_LPTIM345 ((uint64_t)(0x00000080U))
398#define RCC_PERIPHCLK_LPTIM3 RCC_PERIPHCLK_LPTIM345
399#if defined(LPTIM4)
400#define RCC_PERIPHCLK_LPTIM4 RCC_PERIPHCLK_LPTIM345
401#endif /*LPTIM4*/
402#if defined(LPTIM5)
403#define RCC_PERIPHCLK_LPTIM5 RCC_PERIPHCLK_LPTIM345
404#endif /*LPTIM5*/
405#define RCC_PERIPHCLK_SAI1 ((uint64_t)(0x00000100U))
406#if defined(SAI3)
407#define RCC_PERIPHCLK_SAI23 ((uint64_t)(0x00000200U))
408#define RCC_PERIPHCLK_SAI2 RCC_PERIPHCLK_SAI23
409#define RCC_PERIPHCLK_SAI3 RCC_PERIPHCLK_SAI23
410#endif /* SAI3 */
411#if defined(RCC_CDCCIP1R_SAI2ASEL_0)
412#define RCC_PERIPHCLK_SAI2A ((uint64_t)(0x00000200U))
413#endif /* RCC_CDCCIP1R_SAI2ASEL_0 */
414#if defined(RCC_CDCCIP1R_SAI2BSEL_0)
415#define RCC_PERIPHCLK_SAI2B ((uint64_t)(0x00000400U))
416#endif /* RCC_CDCCIP1R_SAI2BSEL_0 */
417#if defined(SAI4)
418#define RCC_PERIPHCLK_SAI4A ((uint64_t)(0x00000400U))
419#define RCC_PERIPHCLK_SAI4B ((uint64_t)(0x00000800U))
420#endif /* SAI4 */
421#define RCC_PERIPHCLK_SPI123 ((uint64_t)(0x00001000U))
422#define RCC_PERIPHCLK_SPI1 RCC_PERIPHCLK_SPI123
423#define RCC_PERIPHCLK_SPI2 RCC_PERIPHCLK_SPI123
424#define RCC_PERIPHCLK_SPI3 RCC_PERIPHCLK_SPI123
425#define RCC_PERIPHCLK_SPI45 ((uint64_t)(0x00002000U))
426#define RCC_PERIPHCLK_SPI4 RCC_PERIPHCLK_SPI45
427#define RCC_PERIPHCLK_SPI5 RCC_PERIPHCLK_SPI45
428#define RCC_PERIPHCLK_SPI6 ((uint64_t)(0x00004000U))
429#define RCC_PERIPHCLK_FDCAN ((uint64_t)(0x00008000U))
430#define RCC_PERIPHCLK_SDMMC ((uint64_t)(0x00010000U))
431#define RCC_PERIPHCLK_RNG ((uint64_t)(0x00020000U))
432#define RCC_PERIPHCLK_USB ((uint64_t)(0x00040000U))
433#define RCC_PERIPHCLK_ADC ((uint64_t)(0x00080000U))
434#define RCC_PERIPHCLK_SWPMI1 ((uint64_t)(0x00100000U))
435#define RCC_PERIPHCLK_DFSDM1 ((uint64_t)(0x00200000U))
436#if defined(DFSDM2_BASE)
437#define RCC_PERIPHCLK_DFSDM2 ((uint64_t)(0x00000800U))
438#endif /* DFSDM2 */
439#define RCC_PERIPHCLK_RTC ((uint64_t)(0x00400000U))
440#define RCC_PERIPHCLK_CEC ((uint64_t)(0x00800000U))
441#define RCC_PERIPHCLK_FMC ((uint64_t)(0x01000000U))
442#if defined(QUADSPI)
443#define RCC_PERIPHCLK_QSPI ((uint64_t)(0x02000000U))
444#endif /* QUADSPI */
445#if defined(OCTOSPI1) || defined(OCTOSPI2)
446#define RCC_PERIPHCLK_OSPI ((uint64_t)(0x02000000U))
447#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
448#define RCC_PERIPHCLK_DSI ((uint64_t)(0x04000000U))
449#define RCC_PERIPHCLK_SPDIFRX ((uint64_t)(0x08000000U))
450#if defined(HRTIM1)
451#define RCC_PERIPHCLK_HRTIM1 ((uint64_t)(0x10000000U))
452#endif /* HRTIM1 */
453#if defined(LTDC)
454#define RCC_PERIPHCLK_LTDC ((uint64_t)(0x20000000U))
455#endif /* LTDC */
456#define RCC_PERIPHCLK_TIM ((uint64_t)(0x40000000U))
457#define RCC_PERIPHCLK_CKPER ((uint64_t)(0x80000000U))
458
459#define RCC_PERIPHCLK_PLL2_DIVP ((uint64_t)(0x0000000100000000U))
460#define RCC_PERIPHCLK_PLL2_DIVQ ((uint64_t)(0x0000000200000000U))
461#define RCC_PERIPHCLK_PLL2_DIVR ((uint64_t)(0x0000000400000000U))
462#define RCC_PERIPHCLK_PLL3_DIVP ((uint64_t)(0x0000000800000000U))
463#define RCC_PERIPHCLK_PLL3_DIVQ ((uint64_t)(0x0000001000000000U))
464#define RCC_PERIPHCLK_PLL3_DIVR ((uint64_t)(0x0000002000000000U))
465
475#define RCC_PLL2_DIVP RCC_PLLCFGR_DIVP2EN
476#define RCC_PLL2_DIVQ RCC_PLLCFGR_DIVQ2EN
477#define RCC_PLL2_DIVR RCC_PLLCFGR_DIVR2EN
478
487#define RCC_PLL3_DIVP RCC_PLLCFGR_DIVP3EN
488#define RCC_PLL3_DIVQ RCC_PLLCFGR_DIVQ3EN
489#define RCC_PLL3_DIVR RCC_PLLCFGR_DIVR3EN
490
499#define RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0
500#define RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1
501#define RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2
502#define RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3
513#define RCC_PLL2VCOWIDE (0x00000000U)
514#define RCC_PLL2VCOMEDIUM RCC_PLLCFGR_PLL2VCOSEL
515
524#define RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0
525#define RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1
526#define RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2
527#define RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3
538#define RCC_PLL3VCOWIDE (0x00000000U)
539#define RCC_PLL3VCOMEDIUM RCC_PLLCFGR_PLL3VCOSEL
540
549#if defined(RCC_D2CCIP2R_USART16SEL)
550#define RCC_USART16CLKSOURCE_D2PCLK2 (0x00000000U)
551/* alias */
552#define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
553#define RCC_USART16CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16SEL_0
554#define RCC_USART16CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16SEL_1
555#define RCC_USART16CLKSOURCE_HSI (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
556#define RCC_USART16CLKSOURCE_CSI RCC_D2CCIP2R_USART16SEL_2
557#define RCC_USART16CLKSOURCE_LSE (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
558
559#elif defined(RCC_CDCCIP2R_USART16910SEL)
560#define RCC_USART16910CLKSOURCE_CDPCLK2 (0x00000000U)
561/* alias */
562#define RCC_USART16910CLKSOURCE_D2PCLK2 RCC_USART16910CLKSOURCE_CDPCLK2
563#define RCC_USART16910CLKSOURCE_PLL2 RCC_CDCCIP2R_USART16910SEL_0
564#define RCC_USART16910CLKSOURCE_PLL3 RCC_CDCCIP2R_USART16910SEL_1
565#define RCC_USART16910CLKSOURCE_HSI (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)
566#define RCC_USART16910CLKSOURCE_CSI RCC_CDCCIP2R_USART16910SEL_2
567#define RCC_USART16910CLKSOURCE_LSE (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)
568
569/* Aliases */
570#define RCC_USART16CLKSOURCE_CDPCLK2 RCC_USART16910CLKSOURCE_CDPCLK2
571#define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16CLKSOURCE_CDPCLK2
572#define RCC_USART16CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_CDPCLK2
573#define RCC_USART16CLKSOURCE_PLL2 RCC_USART16910CLKSOURCE_PLL2
574#define RCC_USART16CLKSOURCE_PLL3 RCC_USART16910CLKSOURCE_PLL3
575#define RCC_USART16CLKSOURCE_HSI RCC_USART16910CLKSOURCE_HSI
576#define RCC_USART16CLKSOURCE_CSI RCC_USART16910CLKSOURCE_CSI
577#define RCC_USART16CLKSOURCE_LSE RCC_USART16910CLKSOURCE_LSE
578
579#else /* RCC_D2CCIP2R_USART16910SEL */
580#define RCC_USART16910CLKSOURCE_D2PCLK2 (0x00000000U)
581#define RCC_USART16910CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16910SEL_0
582#define RCC_USART16910CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16910SEL_1
583#define RCC_USART16910CLKSOURCE_HSI (RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_1)
584#define RCC_USART16910CLKSOURCE_CSI RCC_D2CCIP2R_USART16910SEL_2
585#define RCC_USART16910CLKSOURCE_LSE (RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_2)
586
587/* Aliases */
588#define RCC_USART16CLKSOURCE_D2PCLK2 RCC_USART16910CLKSOURCE_D2PCLK2
589#define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16910CLKSOURCE_D2PCLK2
590#define RCC_USART16CLKSOURCE_PLL2 RCC_USART16910CLKSOURCE_PLL2
591#define RCC_USART16CLKSOURCE_PLL3 RCC_USART16910CLKSOURCE_PLL3
592#define RCC_USART16CLKSOURCE_HSI RCC_USART16910CLKSOURCE_HSI
593#define RCC_USART16CLKSOURCE_CSI RCC_USART16910CLKSOURCE_CSI
594#define RCC_USART16CLKSOURCE_LSE RCC_USART16910CLKSOURCE_LSE
595#endif /* RCC_D2CCIP2R_USART16SEL */
604#define RCC_USART1CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
605#define RCC_USART1CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
606#define RCC_USART1CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
607#define RCC_USART1CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
608#define RCC_USART1CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
609#define RCC_USART1CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE
618#define RCC_USART6CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
619#define RCC_USART6CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
620#define RCC_USART6CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
621#define RCC_USART6CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
622#define RCC_USART6CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
623#define RCC_USART6CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE
624
629#if defined(UART9)
634#define RCC_UART9CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
635#define RCC_UART9CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
636#define RCC_UART9CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
637#define RCC_UART9CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
638#define RCC_UART9CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
639#define RCC_UART9CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE
643#endif /* UART9 */
644
645#if defined(USART10)
650#define RCC_USART10CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
651#define RCC_USART10CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
652#define RCC_USART10CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
653#define RCC_USART10CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
654#define RCC_USART10CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
655#define RCC_USART10CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE
659#endif /* USART10 */
660
665#if defined(RCC_D2CCIP2R_USART28SEL)
666#define RCC_USART234578CLKSOURCE_D2PCLK1 (0x00000000U)
667/* alias */
668#define RCC_USART234578CLKSOURCE_PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
669#define RCC_USART234578CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0
670#define RCC_USART234578CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1
671#define RCC_USART234578CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
672#define RCC_USART234578CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2
673#define RCC_USART234578CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
674#else
675#define RCC_USART234578CLKSOURCE_CDPCLK1 (0x00000000U)
676/* alias */
677#define RCC_USART234578CLKSOURCE_PCLK1 RCC_USART234578CLKSOURCE_CDPCLK1
678#define RCC_USART234578CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_CDPCLK1
679#define RCC_USART234578CLKSOURCE_PLL2 RCC_CDCCIP2R_USART234578SEL_0
680#define RCC_USART234578CLKSOURCE_PLL3 RCC_CDCCIP2R_USART234578SEL_1
681#define RCC_USART234578CLKSOURCE_HSI (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)
682#define RCC_USART234578CLKSOURCE_CSI RCC_CDCCIP2R_USART234578SEL_2
683#define RCC_USART234578CLKSOURCE_LSE (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)
684#endif /* RCC_D2CCIP2R_USART28SEL */
693#define RCC_USART2CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
694#define RCC_USART2CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
695#define RCC_USART2CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
696#define RCC_USART2CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
697#define RCC_USART2CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
698#define RCC_USART2CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
699
708#define RCC_USART3CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
709#define RCC_USART3CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
710#define RCC_USART3CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
711#define RCC_USART3CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
712#define RCC_USART3CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
713#define RCC_USART3CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
714
723#define RCC_UART4CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
724#define RCC_UART4CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
725#define RCC_UART4CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
726#define RCC_UART4CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
727#define RCC_UART4CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
728#define RCC_UART4CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
729
738#define RCC_UART5CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
739#define RCC_UART5CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
740#define RCC_UART5CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
741#define RCC_UART5CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
742#define RCC_UART5CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
743#define RCC_UART5CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
744
753#define RCC_UART7CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
754#define RCC_UART7CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
755#define RCC_UART7CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
756#define RCC_UART7CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
757#define RCC_UART7CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
758#define RCC_UART7CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
759
768#define RCC_UART8CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
769#define RCC_UART8CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
770#define RCC_UART8CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
771#define RCC_UART8CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
772#define RCC_UART8CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
773#define RCC_UART8CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
774
783#if defined(RCC_D3CCIPR_LPUART1SEL)
784#define RCC_LPUART1CLKSOURCE_D3PCLK1 (0x00000000U)
785/* alias */
786#define RCC_LPUART1CLKSOURCE_PCLK4 RCC_LPUART1CLKSOURCE_D3PCLK1
787#define RCC_LPUART1CLKSOURCE_PLL2 RCC_D3CCIPR_LPUART1SEL_0
788#define RCC_LPUART1CLKSOURCE_PLL3 RCC_D3CCIPR_LPUART1SEL_1
789#define RCC_LPUART1CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)
790#define RCC_LPUART1CLKSOURCE_CSI RCC_D3CCIPR_LPUART1SEL_2
791#define RCC_LPUART1CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_2 | RCC_D3CCIPR_LPUART1SEL_0)
792#else
793#define RCC_LPUART1CLKSOURCE_SRDPCLK4 (0x00000000U)
794/* alias*/
795#define RCC_LPUART1CLKSOURCE_PCLK4 RCC_LPUART1CLKSOURCE_SRDPCLK4
796#define RCC_LPUART1CLKSOURCE_D3PCLK1 RCC_LPUART1CLKSOURCE_SRDPCLK4
797#define RCC_LPUART1CLKSOURCE_PLL2 RCC_SRDCCIPR_LPUART1SEL_0
798#define RCC_LPUART1CLKSOURCE_PLL3 RCC_SRDCCIPR_LPUART1SEL_1
799#define RCC_LPUART1CLKSOURCE_HSI (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)
800#define RCC_LPUART1CLKSOURCE_CSI RCC_SRDCCIPR_LPUART1SEL_2
801#define RCC_LPUART1CLKSOURCE_LSE (RCC_SRDCCIPR_LPUART1SEL_2 | RCC_SRDCCIPR_LPUART1SEL_0)
802#endif /* RCC_D3CCIPR_LPUART1SEL */
811#if defined (RCC_D2CCIP2R_I2C123SEL)
812#define RCC_I2C123CLKSOURCE_D2PCLK1 (0x00000000U)
813#define RCC_I2C123CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C123SEL_0
814#define RCC_I2C123CLKSOURCE_HSI RCC_D2CCIP2R_I2C123SEL_1
815#define RCC_I2C123CLKSOURCE_CSI (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
816/* aliases */
817#define RCC_I2C1235CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
818#define RCC_I2C1235CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
819#define RCC_I2C1235CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
820#define RCC_I2C1235CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
821#elif defined(RCC_CDCCIP2R_I2C123SEL)
822#define RCC_I2C123CLKSOURCE_CDPCLK1 (0x00000000U)
823/* alias */
824#define RCC_I2C123CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_CDPCLK1
825#define RCC_I2C123CLKSOURCE_PLL3 RCC_CDCCIP2R_I2C123SEL_0
826#define RCC_I2C123CLKSOURCE_HSI RCC_CDCCIP2R_I2C123SEL_1
827#define RCC_I2C123CLKSOURCE_CSI (RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)
828/* aliases */
829#define RCC_I2C1235CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
830#define RCC_I2C1235CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
831#define RCC_I2C1235CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
832#define RCC_I2C1235CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
833#elif defined(I2C5)
834#define RCC_I2C1235CLKSOURCE_D2PCLK1 (0x00000000U)
835#define RCC_I2C1235CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C1235SEL_0
836#define RCC_I2C1235CLKSOURCE_HSI RCC_D2CCIP2R_I2C1235SEL_1
837#define RCC_I2C1235CLKSOURCE_CSI (RCC_D2CCIP2R_I2C1235SEL_0 | RCC_D2CCIP2R_I2C1235SEL_1)
838/* aliases */
839#define RCC_I2C123CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1
840#define RCC_I2C123CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3
841#define RCC_I2C123CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI
842#define RCC_I2C123CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI
843#endif /* RCC_D2CCIP2R_I2C123SEL */
852#if defined(I2C5)
853#define RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1
854#define RCC_I2C1CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3
855#define RCC_I2C1CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI
856#define RCC_I2C1CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI
857#else
858#define RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
859#define RCC_I2C1CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
860#define RCC_I2C1CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
861#define RCC_I2C1CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
862#endif /*I2C5*/
863
872#if defined(I2C5)
873#define RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1
874#define RCC_I2C2CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3
875#define RCC_I2C2CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI
876#define RCC_I2C2CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI
877#else
878#define RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
879#define RCC_I2C2CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
880#define RCC_I2C2CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
881#define RCC_I2C2CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
882#endif /*I2C5*/
883
892#if defined(I2C5)
893#define RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1
894#define RCC_I2C3CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3
895#define RCC_I2C3CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI
896#define RCC_I2C3CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI
897#else
898#define RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
899#define RCC_I2C3CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
900#define RCC_I2C3CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
901#define RCC_I2C3CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
902#endif /*I2C5*/
903
912#if defined(RCC_D3CCIPR_I2C4SEL)
913#define RCC_I2C4CLKSOURCE_D3PCLK1 (0x00000000U)
914#define RCC_I2C4CLKSOURCE_PLL3 RCC_D3CCIPR_I2C4SEL_0
915#define RCC_I2C4CLKSOURCE_HSI RCC_D3CCIPR_I2C4SEL_1
916#define RCC_I2C4CLKSOURCE_CSI (RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)
917#else
918#define RCC_I2C4CLKSOURCE_SRDPCLK4 (0x00000000U)
919/* alias */
920#define RCC_I2C4CLKSOURCE_D3PCLK1 RCC_I2C4CLKSOURCE_SRDPCLK4
921#define RCC_I2C4CLKSOURCE_PLL3 RCC_SRDCCIPR_I2C4SEL_0
922#define RCC_I2C4CLKSOURCE_HSI RCC_SRDCCIPR_I2C4SEL_1
923#define RCC_I2C4CLKSOURCE_CSI (RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)
924#endif /* RCC_D3CCIPR_I2C4SEL */
925
929#if defined(I2C5)
934#define RCC_I2C5CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1
935#define RCC_I2C5CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3
936#define RCC_I2C5CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI
937#define RCC_I2C5CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI
938
942#endif /*I2C5*/
943
948#if defined(RCC_D2CCIP2R_RNGSEL)
949#define RCC_RNGCLKSOURCE_HSI48 (0x00000000U)
950#define RCC_RNGCLKSOURCE_PLL RCC_D2CCIP2R_RNGSEL_0
951#define RCC_RNGCLKSOURCE_LSE RCC_D2CCIP2R_RNGSEL_1
952#define RCC_RNGCLKSOURCE_LSI RCC_D2CCIP2R_RNGSEL
953#else
954#define RCC_RNGCLKSOURCE_HSI48 (0x00000000U)
955#define RCC_RNGCLKSOURCE_PLL RCC_CDCCIP2R_RNGSEL_0
956#define RCC_RNGCLKSOURCE_LSE RCC_CDCCIP2R_RNGSEL_1
957#define RCC_RNGCLKSOURCE_LSI RCC_CDCCIP2R_RNGSEL
958#endif /* RCC_D2CCIP2R_RNGSEL */
959
963#if defined(HRTIM1)
964
969#define RCC_HRTIM1CLK_TIMCLK (0x00000000U)
970#define RCC_HRTIM1CLK_CPUCLK RCC_CFGR_HRTIMSEL
971
975#endif /*HRTIM1*/
976
981#if defined(RCC_D2CCIP2R_USBSEL)
982#define RCC_USBCLKSOURCE_PLL RCC_D2CCIP2R_USBSEL_0
983#define RCC_USBCLKSOURCE_PLL3 RCC_D2CCIP2R_USBSEL_1
984#define RCC_USBCLKSOURCE_HSI48 RCC_D2CCIP2R_USBSEL
985#else
986#define RCC_USBCLKSOURCE_PLL RCC_CDCCIP2R_USBSEL_0
987#define RCC_USBCLKSOURCE_PLL3 RCC_CDCCIP2R_USBSEL_1
988#define RCC_USBCLKSOURCE_HSI48 RCC_CDCCIP2R_USBSEL
989#endif /* RCC_D2CCIP2R_USBSEL */
990
999#if defined(RCC_D2CCIP1R_SAI1SEL)
1000#define RCC_SAI1CLKSOURCE_PLL (0x00000000U)
1001#define RCC_SAI1CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI1SEL_0
1002#define RCC_SAI1CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI1SEL_1
1003#define RCC_SAI1CLKSOURCE_PIN (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)
1004#define RCC_SAI1CLKSOURCE_CLKP RCC_D2CCIP1R_SAI1SEL_2
1005#else
1006#define RCC_SAI1CLKSOURCE_PLL (0x00000000U)
1007#define RCC_SAI1CLKSOURCE_PLL2 RCC_CDCCIP1R_SAI1SEL_0
1008#define RCC_SAI1CLKSOURCE_PLL3 RCC_CDCCIP1R_SAI1SEL_1
1009#define RCC_SAI1CLKSOURCE_PIN (RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)
1010#define RCC_SAI1CLKSOURCE_CLKP RCC_CDCCIP1R_SAI1SEL_2
1011#endif /* RCC_D2CCIP1R_SAI1SEL */
1016#if defined(SAI3)
1021#define RCC_SAI23CLKSOURCE_PLL (0x00000000U)
1022#define RCC_SAI23CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI23SEL_0
1023#define RCC_SAI23CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI23SEL_1
1024#define RCC_SAI23CLKSOURCE_PIN (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
1025#define RCC_SAI23CLKSOURCE_CLKP RCC_D2CCIP1R_SAI23SEL_2
1034#define RCC_SAI2CLKSOURCE_PLL RCC_SAI23CLKSOURCE_PLL
1035#define RCC_SAI2CLKSOURCE_PLL2 RCC_SAI23CLKSOURCE_PLL2
1036#define RCC_SAI2CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3
1037#define RCC_SAI2CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN
1038#define RCC_SAI2CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP
1039
1048#define RCC_SAI3CLKSOURCE_PLL RCC_SAI23CLKSOURCE_PLL
1049#define RCC_SAI3CLKSOURCE_PLL2 RCC_SAI23CLKSOURCE_PLL2
1050#define RCC_SAI3CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3
1051#define RCC_SAI3CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN
1052#define RCC_SAI3CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP
1056#endif /* SAI3 */
1057
1058#if defined(RCC_CDCCIP1R_SAI2ASEL)
1063#define RCC_SAI2ACLKSOURCE_PLL (0x00000000U)
1064#define RCC_SAI2ACLKSOURCE_PLL2 RCC_CDCCIP1R_SAI2ASEL_0
1065#define RCC_SAI2ACLKSOURCE_PLL3 RCC_CDCCIP1R_SAI2ASEL_1
1066#define RCC_SAI2ACLKSOURCE_PIN (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
1067#define RCC_SAI2ACLKSOURCE_CLKP RCC_CDCCIP1R_SAI2ASEL_2
1068#define RCC_SAI2ACLKSOURCE_SPDIF (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)
1072#endif /* RCC_CDCCIP1R_SAI2ASEL */
1073
1074#if defined(RCC_CDCCIP1R_SAI2BSEL)
1079#define RCC_SAI2BCLKSOURCE_PLL (0x00000000U)
1080#define RCC_SAI2BCLKSOURCE_PLL2 RCC_CDCCIP1R_SAI2BSEL_0
1081#define RCC_SAI2BCLKSOURCE_PLL3 RCC_CDCCIP1R_SAI2BSEL_1
1082#define RCC_SAI2BCLKSOURCE_PIN (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)
1083#define RCC_SAI2BCLKSOURCE_CLKP RCC_CDCCIP1R_SAI2BSEL_2
1084#define RCC_SAI2BCLKSOURCE_SPDIF (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)
1088#endif /* RCC_CDCCIP1R_SAI2BSEL */
1089
1090
1095#if defined(RCC_D2CCIP1R_SPI123SEL)
1096#define RCC_SPI123CLKSOURCE_PLL (0x00000000U)
1097#define RCC_SPI123CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI123SEL_0
1098#define RCC_SPI123CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI123SEL_1
1099#define RCC_SPI123CLKSOURCE_PIN (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
1100#define RCC_SPI123CLKSOURCE_CLKP RCC_D2CCIP1R_SPI123SEL_2
1101#else
1102#define RCC_SPI123CLKSOURCE_PLL (0x00000000U)
1103#define RCC_SPI123CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI123SEL_0
1104#define RCC_SPI123CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI123SEL_1
1105#define RCC_SPI123CLKSOURCE_PIN (RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)
1106#define RCC_SPI123CLKSOURCE_CLKP RCC_CDCCIP1R_SPI123SEL_2
1107#endif /* RCC_D2CCIP1R_SPI123SEL */
1116#define RCC_SPI1CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL
1117#define RCC_SPI1CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2
1118#define RCC_SPI1CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3
1119#define RCC_SPI1CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN
1120#define RCC_SPI1CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP
1121
1130#define RCC_SPI2CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL
1131#define RCC_SPI2CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2
1132#define RCC_SPI2CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3
1133#define RCC_SPI2CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN
1134#define RCC_SPI2CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP
1135
1144#define RCC_SPI3CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL
1145#define RCC_SPI3CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2
1146#define RCC_SPI3CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3
1147#define RCC_SPI3CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN
1148#define RCC_SPI3CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP
1149
1158#if defined(RCC_D2CCIP1R_SPI45SEL)
1159#define RCC_SPI45CLKSOURCE_D2PCLK2 (0x00000000U)
1160#define RCC_SPI45CLKSOURCE_PCLK2 RCC_SPI45CLKSOURCE_D2PCLK2
1161#define RCC_SPI45CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI45SEL_0
1162#define RCC_SPI45CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI45SEL_1
1163#define RCC_SPI45CLKSOURCE_HSI (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
1164#define RCC_SPI45CLKSOURCE_CSI RCC_D2CCIP1R_SPI45SEL_2
1165#define RCC_SPI45CLKSOURCE_HSE (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
1166#else
1167#define RCC_SPI45CLKSOURCE_CDPCLK2 (0x00000000U)
1168/* aliases */
1169#define RCC_SPI45CLKSOURCE_D2PCLK2 RCC_SPI45CLKSOURCE_CDPCLK2 /* D2PCLK2 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
1170#define RCC_SPI45CLKSOURCE_PCLK2 RCC_SPI45CLKSOURCE_CDPCLK2
1171#define RCC_SPI45CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI45SEL_0
1172#define RCC_SPI45CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI45SEL_1
1173#define RCC_SPI45CLKSOURCE_HSI (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
1174#define RCC_SPI45CLKSOURCE_CSI RCC_CDCCIP1R_SPI45SEL_2
1175#define RCC_SPI45CLKSOURCE_HSE (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)
1176#endif /* RCC_D2CCIP1R_SPI45SEL */
1185#define RCC_SPI4CLKSOURCE_D2PCLK2 RCC_SPI45CLKSOURCE_D2PCLK2
1186#define RCC_SPI4CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2
1187#define RCC_SPI4CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3
1188#define RCC_SPI4CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI
1189#define RCC_SPI4CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI
1190#define RCC_SPI4CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE
1191
1200#define RCC_SPI5CLKSOURCE_D2PCLK2 RCC_SPI45CLKSOURCE_D2PCLK2
1201#define RCC_SPI5CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2
1202#define RCC_SPI5CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3
1203#define RCC_SPI5CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI
1204#define RCC_SPI5CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI
1205#define RCC_SPI5CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE
1206
1215#if defined(RCC_D3CCIPR_SPI6SEL)
1216#define RCC_SPI6CLKSOURCE_D3PCLK1 (0x00000000U)
1217#define RCC_SPI6CLKSOURCE_PCLK4 RCC_SPI6CLKSOURCE_D3PCLK1
1218#define RCC_SPI6CLKSOURCE_PLL2 RCC_D3CCIPR_SPI6SEL_0
1219#define RCC_SPI6CLKSOURCE_PLL3 RCC_D3CCIPR_SPI6SEL_1
1220#define RCC_SPI6CLKSOURCE_HSI (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)
1221#define RCC_SPI6CLKSOURCE_CSI RCC_D3CCIPR_SPI6SEL_2
1222#define RCC_SPI6CLKSOURCE_HSE (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)
1223#else
1224#define RCC_SPI6CLKSOURCE_SRDPCLK4 (0x00000000U)
1225/* alias */
1226#define RCC_SPI6CLKSOURCE_D3PCLK1 RCC_SPI6CLKSOURCE_SRDPCLK4 /* D3PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
1227#define RCC_SPI6CLKSOURCE_PCLK4 RCC_SPI6CLKSOURCE_SRDPCLK4
1228#define RCC_SPI6CLKSOURCE_PLL2 RCC_SRDCCIPR_SPI6SEL_0
1229#define RCC_SPI6CLKSOURCE_PLL3 RCC_SRDCCIPR_SPI6SEL_1
1230#define RCC_SPI6CLKSOURCE_HSI (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
1231#define RCC_SPI6CLKSOURCE_CSI RCC_SRDCCIPR_SPI6SEL_2
1232#define RCC_SPI6CLKSOURCE_HSE (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
1233#define RCC_SPI6CLKSOURCE_PIN (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)
1234#endif /* RCC_D3CCIPR_SPI6SEL */
1235
1241#if defined(SAI4_Block_A)
1246#define RCC_SAI4ACLKSOURCE_PLL (0x00000000U)
1247#define RCC_SAI4ACLKSOURCE_PLL2 RCC_D3CCIPR_SAI4ASEL_0
1248#define RCC_SAI4ACLKSOURCE_PLL3 RCC_D3CCIPR_SAI4ASEL_1
1249#define RCC_SAI4ACLKSOURCE_PIN (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)
1250#define RCC_SAI4ACLKSOURCE_CLKP RCC_D3CCIPR_SAI4ASEL_2
1251#if defined(RCC_VER_3_0)
1252#define RCC_SAI4ACLKSOURCE_SPDIF (RCC_D3CCIPR_SAI4ASEL_2 | RCC_D3CCIPR_SAI4ASEL_0)
1253#endif /*RCC_VER_3_0*/
1254
1258#endif /* SAI4_Block_A */
1259
1260
1261
1262#if defined(SAI4_Block_B)
1267#define RCC_SAI4BCLKSOURCE_PLL (0x00000000U)
1268#define RCC_SAI4BCLKSOURCE_PLL2 RCC_D3CCIPR_SAI4BSEL_0
1269#define RCC_SAI4BCLKSOURCE_PLL3 RCC_D3CCIPR_SAI4BSEL_1
1270#define RCC_SAI4BCLKSOURCE_PIN (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)
1271#define RCC_SAI4BCLKSOURCE_CLKP RCC_D3CCIPR_SAI4BSEL_2
1272#if defined(RCC_VER_3_0)
1273#define RCC_SAI4BCLKSOURCE_SPDIF (RCC_D3CCIPR_SAI4BSEL_2 | RCC_D3CCIPR_SAI4BSEL_0)
1274#endif /* RCC_VER_3_0 */
1275
1279#endif /* SAI4_Block_B */
1280
1281
1286#if defined(RCC_D2CCIP2R_LPTIM1SEL)
1287#define RCC_LPTIM1CLKSOURCE_D2PCLK1 (0x00000000U)
1288/* alias */
1289#define RCC_LPTIM1CLKSOURCE_PCLK1 RCC_LPTIM1CLKSOURCE_D2PCLK1
1290#define RCC_LPTIM1CLKSOURCE_PLL2 RCC_D2CCIP2R_LPTIM1SEL_0
1291#define RCC_LPTIM1CLKSOURCE_PLL3 RCC_D2CCIP2R_LPTIM1SEL_1
1292#define RCC_LPTIM1CLKSOURCE_LSE (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)
1293#define RCC_LPTIM1CLKSOURCE_LSI RCC_D2CCIP2R_LPTIM1SEL_2
1294#define RCC_LPTIM1CLKSOURCE_CLKP (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)
1295#else
1296#define RCC_LPTIM1CLKSOURCE_CDPCLK1 (0x00000000U)
1297/* alias */
1298#define RCC_LPTIM1CLKSOURCE_PCLK1 RCC_LPTIM1CLKSOURCE_CDPCLK1
1299#define RCC_LPTIM1CLKSOURCE_D2PCLK1 RCC_LPTIM1CLKSOURCE_CDPCLK1
1300#define RCC_LPTIM1CLKSOURCE_PLL2 RCC_CDCCIP2R_LPTIM1SEL_0
1301#define RCC_LPTIM1CLKSOURCE_PLL3 RCC_CDCCIP2R_LPTIM1SEL_1
1302#define RCC_LPTIM1CLKSOURCE_LSE (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)
1303#define RCC_LPTIM1CLKSOURCE_LSI RCC_CDCCIP2R_LPTIM1SEL_2
1304#define RCC_LPTIM1CLKSOURCE_CLKP (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)
1305#endif /* RCC_D2CCIP2R_LPTIM1SEL */
1306
1315#if defined(RCC_D3CCIPR_LPTIM2SEL)
1316#define RCC_LPTIM2CLKSOURCE_D3PCLK1 (0x00000000U)
1317/* alias */
1318#define RCC_LPTIM2CLKSOURCE_PCLK4 RCC_LPTIM2CLKSOURCE_D3PCLK1
1319#define RCC_LPTIM2CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM2SEL_0
1320#define RCC_LPTIM2CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM2SEL_1
1321#define RCC_LPTIM2CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)
1322#define RCC_LPTIM2CLKSOURCE_LSI RCC_D3CCIPR_LPTIM2SEL_2
1323#define RCC_LPTIM2CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)
1324#else
1325#define RCC_LPTIM2CLKSOURCE_SRDPCLK4 (0x00000000U)
1326/*alias*/
1327#define RCC_LPTIM2CLKSOURCE_PCLK4 RCC_LPTIM2CLKSOURCE_SRDPCLK4
1328#define RCC_LPTIM2CLKSOURCE_D3PCLK1 RCC_LPTIM2CLKSOURCE_SRDPCLK4
1329#define RCC_LPTIM2CLKSOURCE_PLL2 RCC_SRDCCIPR_LPTIM2SEL_0
1330#define RCC_LPTIM2CLKSOURCE_PLL3 RCC_SRDCCIPR_LPTIM2SEL_1
1331#define RCC_LPTIM2CLKSOURCE_LSE (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)
1332#define RCC_LPTIM2CLKSOURCE_LSI RCC_SRDCCIPR_LPTIM2SEL_2
1333#define RCC_LPTIM2CLKSOURCE_CLKP (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)
1334#endif /* RCC_D3CCIPR_LPTIM2SEL */
1343#if defined(RCC_D3CCIPR_LPTIM345SEL)
1344#define RCC_LPTIM345CLKSOURCE_D3PCLK1 (0x00000000U)
1345/* alias*/
1346#define RCC_LPTIM345CLKSOURCE_PCLK4 RCC_LPTIM345CLKSOURCE_D3PCLK1
1347#define RCC_LPTIM345CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM345SEL_0
1348#define RCC_LPTIM345CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM345SEL_1
1349#define RCC_LPTIM345CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
1350#define RCC_LPTIM345CLKSOURCE_LSI RCC_D3CCIPR_LPTIM345SEL_2
1351#define RCC_LPTIM345CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
1352#else
1353#define RCC_LPTIM345CLKSOURCE_SRDPCLK4 (0x00000000U)
1354/* alias */
1355#define RCC_LPTIM345CLKSOURCE_PCLK4 RCC_LPTIM345CLKSOURCE_SRDPCLK4
1356#define RCC_LPTIM345CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_SRDPCLK4
1357#define RCC_LPTIM345CLKSOURCE_PLL2 RCC_SRDCCIPR_LPTIM3SEL_0
1358#define RCC_LPTIM345CLKSOURCE_PLL3 RCC_SRDCCIPR_LPTIM3SEL_1
1359#define RCC_LPTIM345CLKSOURCE_LSE (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)
1360#define RCC_LPTIM345CLKSOURCE_LSI RCC_SRDCCIPR_LPTIM3SEL_2
1361#define RCC_LPTIM345CLKSOURCE_CLKP (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)
1362#endif /* RCC_D3CCIPR_LPTIM345SEL */
1371#define RCC_LPTIM3CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1
1372#define RCC_LPTIM3CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2
1373#define RCC_LPTIM3CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3
1374#define RCC_LPTIM3CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE
1375#define RCC_LPTIM3CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI
1376#define RCC_LPTIM3CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP
1377
1381#if defined(LPTIM4)
1386#define RCC_LPTIM4CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1
1387#define RCC_LPTIM4CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2
1388#define RCC_LPTIM4CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3
1389#define RCC_LPTIM4CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE
1390#define RCC_LPTIM4CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI
1391#define RCC_LPTIM4CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP
1395#endif /* LPTIM4 */
1396
1397#if defined(LPTIM5)
1402#define RCC_LPTIM5CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1
1403#define RCC_LPTIM5CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2
1404#define RCC_LPTIM5CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3
1405#define RCC_LPTIM5CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE
1406#define RCC_LPTIM5CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI
1407#define RCC_LPTIM5CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP
1408
1412#endif /* LPTIM5 */
1413
1414#if defined(QUADSPI)
1419#define RCC_QSPICLKSOURCE_D1HCLK (0x00000000U)
1420#define RCC_QSPICLKSOURCE_PLL RCC_D1CCIPR_QSPISEL_0
1421#define RCC_QSPICLKSOURCE_PLL2 RCC_D1CCIPR_QSPISEL_1
1422#define RCC_QSPICLKSOURCE_CLKP RCC_D1CCIPR_QSPISEL
1423
1427#endif /* QUADSPI */
1428
1429
1430#if defined(OCTOSPI1) || defined(OCTOSPI2)
1436#if defined(RCC_CDCCIPR_OCTOSPISEL)
1437#define RCC_OSPICLKSOURCE_CDHCLK (0x00000000U)
1438/*aliases*/
1439#define RCC_OSPICLKSOURCE_D1HCLK RCC_OSPICLKSOURCE_CDHCLK
1440#define RCC_OSPICLKSOURCE_HCLK RCC_OSPICLKSOURCE_CDHCLK
1441#define RCC_OSPICLKSOURCE_PLL RCC_CDCCIPR_OCTOSPISEL_0
1442#define RCC_OSPICLKSOURCE_PLL2 RCC_CDCCIPR_OCTOSPISEL_1
1443#define RCC_OSPICLKSOURCE_CLKP RCC_CDCCIPR_OCTOSPISEL
1444#else
1445#define RCC_OSPICLKSOURCE_D1HCLK (0x00000000U)
1446#define RCC_OSPICLKSOURCE_HCLK RCC_OSPICLKSOURCE_D1HCLK
1447#define RCC_OSPICLKSOURCE_PLL RCC_D1CCIPR_OCTOSPISEL_0
1448#define RCC_OSPICLKSOURCE_PLL2 RCC_D1CCIPR_OCTOSPISEL_1
1449#define RCC_OSPICLKSOURCE_CLKP RCC_D1CCIPR_OCTOSPISEL
1450#endif /* RCC_CDCCIPR_OCTOSPISEL */
1451
1452
1456#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
1457
1458#if defined(DSI)
1463#define RCC_DSICLKSOURCE_PHY (0x00000000U)
1464#define RCC_DSICLKSOURCE_PLL2 RCC_D1CCIPR_DSISEL
1465
1469#endif /* DSI */
1470
1475#if defined(RCC_D1CCIPR_FMCSEL)
1476#define RCC_FMCCLKSOURCE_D1HCLK (0x00000000U)
1477#define RCC_FMCCLKSOURCE_HCLK RCC_FMCCLKSOURCE_D1HCLK
1478#define RCC_FMCCLKSOURCE_PLL RCC_D1CCIPR_FMCSEL_0
1479#define RCC_FMCCLKSOURCE_PLL2 RCC_D1CCIPR_FMCSEL_1
1480#define RCC_FMCCLKSOURCE_CLKP RCC_D1CCIPR_FMCSEL
1481#else
1482#define RCC_FMCCLKSOURCE_CDHCLK (0x00000000U)
1483#define RCC_FMCCLKSOURCE_HCLK RCC_FMCCLKSOURCE_CDHCLK
1484/*alias*/
1485#define RCC_FMCCLKSOURCE_D1HCLK RCC_FMCCLKSOURCE_CDHCLK
1486#define RCC_FMCCLKSOURCE_PLL RCC_CDCCIPR_FMCSEL_0
1487#define RCC_FMCCLKSOURCE_PLL2 RCC_CDCCIPR_FMCSEL_1
1488#define RCC_FMCCLKSOURCE_CLKP RCC_CDCCIPR_FMCSEL
1489#endif /* RCC_D1CCIPR_FMCSEL */
1494#if defined(FDCAN1) || defined(FDCAN2)
1499#if defined(RCC_D2CCIP1R_FDCANSEL)
1500#define RCC_FDCANCLKSOURCE_HSE (0x00000000U)
1501#define RCC_FDCANCLKSOURCE_PLL RCC_D2CCIP1R_FDCANSEL_0
1502#define RCC_FDCANCLKSOURCE_PLL2 RCC_D2CCIP1R_FDCANSEL_1
1503#else
1504#define RCC_FDCANCLKSOURCE_HSE (0x00000000U)
1505#define RCC_FDCANCLKSOURCE_PLL RCC_CDCCIP1R_FDCANSEL_0
1506#define RCC_FDCANCLKSOURCE_PLL2 RCC_CDCCIP1R_FDCANSEL_1
1507#endif /* D3_SRAM_BASE */
1511#endif /*FDCAN1 || FDCAN2*/
1512
1513
1518#if defined(RCC_D1CCIPR_SDMMCSEL)
1519#define RCC_SDMMCCLKSOURCE_PLL (0x00000000U)
1520#define RCC_SDMMCCLKSOURCE_PLL2 RCC_D1CCIPR_SDMMCSEL
1521#else
1522#define RCC_SDMMCCLKSOURCE_PLL (0x00000000U)
1523#define RCC_SDMMCCLKSOURCE_PLL2 RCC_CDCCIPR_SDMMCSEL
1524#endif /* RCC_D1CCIPR_SDMMCSEL */
1534#if defined(RCC_D3CCIPR_ADCSEL_0)
1535#define RCC_ADCCLKSOURCE_PLL2 (0x00000000U)
1536#define RCC_ADCCLKSOURCE_PLL3 RCC_D3CCIPR_ADCSEL_0
1537#define RCC_ADCCLKSOURCE_CLKP RCC_D3CCIPR_ADCSEL_1
1538#else
1539#define RCC_ADCCLKSOURCE_PLL2 (0x00000000U)
1540#define RCC_ADCCLKSOURCE_PLL3 RCC_SRDCCIPR_ADCSEL_0
1541#define RCC_ADCCLKSOURCE_CLKP RCC_SRDCCIPR_ADCSEL_1
1542#endif /* RCC_D3CCIPR_ADCSEL_0 */
1551#if defined(RCC_D2CCIP1R_SWPSEL)
1552#define RCC_SWPMI1CLKSOURCE_D2PCLK1 (0x00000000U)
1553#define RCC_SWPMI1CLKSOURCE_HSI RCC_D2CCIP1R_SWPSEL
1554#else
1555#define RCC_SWPMI1CLKSOURCE_CDPCLK1 (0x00000000U)
1556/* alias */
1557#define RCC_SWPMI1CLKSOURCE_D2PCLK1 RCC_SWPMI1CLKSOURCE_CDPCLK1
1558#define RCC_SWPMI1CLKSOURCE_HSI RCC_CDCCIP1R_SWPSEL
1559#endif /* RCC_D2CCIP1R_SWPSEL */
1568#if defined(RCC_D2CCIP1R_DFSDM1SEL)
1569#define RCC_DFSDM1CLKSOURCE_D2PCLK1 (0x00000000U)
1570#define RCC_DFSDM1CLKSOURCE_SYS RCC_D2CCIP1R_DFSDM1SEL
1571#else
1572#define RCC_DFSDM1CLKSOURCE_CDPCLK1 (0x00000000U)
1573/* alias */
1574#define RCC_DFSDM1CLKSOURCE_D2PCLK1 RCC_DFSDM1CLKSOURCE_CDPCLK1
1575#define RCC_DFSDM1CLKSOURCE_SYS RCC_CDCCIP1R_DFSDM1SEL
1576#endif /* RCC_D2CCIP1R_DFSDM1SEL */
1581#if defined(DFSDM2_BASE)
1586#define RCC_DFSDM2CLKSOURCE_SRDPCLK4 (0x00000000U)
1587/* alias */
1588#define RCC_DFSDM2CLKSOURCE_SRDPCLK1 RCC_DFSDM2CLKSOURCE_SRDPCLK4
1589#define RCC_DFSDM2CLKSOURCE_SYS RCC_SRDCCIPR_DFSDM2SEL
1593#endif /* DFSDM2 */
1594
1599#if defined(RCC_D2CCIP1R_SPDIFSEL_0)
1600#define RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U)
1601#define RCC_SPDIFRXCLKSOURCE_PLL2 RCC_D2CCIP1R_SPDIFSEL_0
1602#define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_D2CCIP1R_SPDIFSEL_1
1603#define RCC_SPDIFRXCLKSOURCE_HSI RCC_D2CCIP1R_SPDIFSEL
1604#else
1605#define RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U)
1606#define RCC_SPDIFRXCLKSOURCE_PLL2 RCC_CDCCIP1R_SPDIFSEL_0
1607#define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_CDCCIP1R_SPDIFSEL_1
1608#define RCC_SPDIFRXCLKSOURCE_HSI RCC_CDCCIP1R_SPDIFSEL
1609#endif /* RCC_D2CCIP1R_SPDIFSEL_0 */
1618#if defined(RCC_D2CCIP2R_CECSEL_0)
1619#define RCC_CECCLKSOURCE_LSE (0x00000000U)
1620#define RCC_CECCLKSOURCE_LSI RCC_D2CCIP2R_CECSEL_0
1621#define RCC_CECCLKSOURCE_CSI RCC_D2CCIP2R_CECSEL_1
1622#else
1623#define RCC_CECCLKSOURCE_LSE (0x00000000U)
1624#define RCC_CECCLKSOURCE_LSI RCC_CDCCIP2R_CECSEL_0
1625#define RCC_CECCLKSOURCE_CSI RCC_CDCCIP2R_CECSEL_1
1626#endif /* RCC_D2CCIP2R_CECSEL_0 */
1636#if defined(RCC_D1CCIPR_CKPERSEL_0)
1637#define RCC_CLKPSOURCE_HSI (0x00000000U)
1638#define RCC_CLKPSOURCE_CSI RCC_D1CCIPR_CKPERSEL_0
1639#define RCC_CLKPSOURCE_HSE RCC_D1CCIPR_CKPERSEL_1
1640#else
1641#define RCC_CLKPSOURCE_HSI (0x00000000U)
1642#define RCC_CLKPSOURCE_CSI RCC_CDCCIPR_CKPERSEL_0
1643#define RCC_CLKPSOURCE_HSE RCC_CDCCIPR_CKPERSEL_1
1644#endif /* RCC_D1CCIPR_CKPERSEL_0 */
1653#define RCC_TIMPRES_DESACTIVATED (0x00000000U)
1654#define RCC_TIMPRES_ACTIVATED RCC_CFGR_TIMPRE
1655
1660#if defined(DUAL_CORE)
1661
1666#define RCC_BOOT_C1 RCC_GCR_BOOT_C1
1667#define RCC_BOOT_C2 RCC_GCR_BOOT_C2
1668
1672#endif /*DUAL_CORE*/
1673
1674#if defined(DUAL_CORE)
1679#define RCC_WWDG1 RCC_GCR_WW1RSC
1680#define RCC_WWDG2 RCC_GCR_WW2RSC
1681
1686#else
1687
1692#define RCC_WWDG1 RCC_GCR_WW1RSC
1693
1698#endif /*DUAL_CORE*/
1699
1704#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM18
1713#define RCC_CRS_NONE (0x00000000U)
1714#define RCC_CRS_TIMEOUT (0x00000001U)
1715#define RCC_CRS_SYNCOK (0x00000002U)
1716#define RCC_CRS_SYNCWARN (0x00000004U)
1717#define RCC_CRS_SYNCERR (0x00000008U)
1718#define RCC_CRS_SYNCMISS (0x00000010U)
1719#define RCC_CRS_TRIMOVF (0x00000020U)
1728#define RCC_CRS_SYNC_SOURCE_PIN (0x00000000U)
1729#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0
1730#define RCC_CRS_SYNC_SOURCE_USB1 CRS_CFGR_SYNCSRC_1
1731#define RCC_CRS_SYNC_SOURCE_USB2 (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0)
1742#define RCC_CRS_SYNC_DIV1 (0x00000000U)
1743#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0
1744#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1
1745#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)
1746#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2
1747#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)
1748#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)
1749#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV
1758#define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U)
1759#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL
1768#define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU)
1778#define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U)
1787#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U)
1798#define RCC_CRS_FREQERRORDIR_UP (0x00000000U)
1799#define RCC_CRS_FREQERRORDIR_DOWN (CRS_ISR_FEDIR)
1808#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE
1809#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE
1810#define RCC_CRS_IT_ERR CRS_CR_ERRIE
1811#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE
1812#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE
1813#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE
1814#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE
1824#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF
1825#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF
1826#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF
1827#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF
1828#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR
1829#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS
1830#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF
1842/* Exported macro ------------------------------------------------------------*/
1854#define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON)
1855#define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)
1856
1873#define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
1874
1875#define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
1876
1882#define __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
1883
1884#define __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
1885
1918#define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \
1919 do{ \
1920 MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U)); \
1921 WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \
1922 ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \
1923 } while(0)
1924
1941#define __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) \
1942 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos))
1943
1953#define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \
1954 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))
1955
1956
1967#define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \
1968 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))
1969
1976#define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON)
1977#define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)
1978
1984#define __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
1985
1986#define __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
1987
2004#define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
2005
2006#define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
2007
2040#define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \
2041 do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U)); \
2042 WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \
2043 ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \
2044 } while(0)
2045
2046
2047
2064#define __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)
2065
2075#define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \
2076 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))
2077
2078
2089#define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \
2090 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))
2103#if defined(RCC_D2CCIP1R_SAI1SEL)
2104#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\
2105 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
2106#else
2107#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\
2108 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
2109#endif /* RCC_D2CCIP1R_SAI1SEL */
2110
2119#if defined(RCC_D2CCIP1R_SAI1SEL)
2120#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL)))
2121#else
2122#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL)))
2123#endif /* RCC_D2CCIP1R_SAI1SEL */
2124
2136#if defined(RCC_D2CCIP1R_SPDIFSEL)
2137#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\
2138 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
2139#else
2140#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\
2141 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
2142#endif /* RCC_D2CCIP1R_SPDIFSEL */
2143
2148#if defined(RCC_D2CCIP1R_SPDIFSEL)
2149#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)))
2150#else
2151#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL)))
2152#endif /* RCC_D2CCIP1R_SPDIFSEL */
2153
2154#if defined(SAI3)
2167#define __HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__ )\
2168 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__))
2169
2178#define __HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
2179
2192#define __HAL_RCC_SAI2_CONFIG __HAL_RCC_SAI23_CONFIG
2193
2202#define __HAL_RCC_GET_SAI2_SOURCE __HAL_RCC_GET_SAI23_SOURCE
2203
2216#define __HAL_RCC_SAI3_CONFIG __HAL_RCC_SAI23_CONFIG
2217
2226#define __HAL_RCC_GET_SAI3_SOURCE __HAL_RCC_GET_SAI23_SOURCE
2227#endif /* SAI3 */
2228
2229#if defined(RCC_CDCCIP1R_SAI2ASEL)
2243#define __HAL_RCC_SAI2A_CONFIG(__RCC_SAI2ACLKSource__ )\
2244 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL, (__RCC_SAI2ACLKSource__))
2245
2255#define __HAL_RCC_GET_SAI2A_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL)))
2256#endif /* defined(RCC_CDCCIP1R_SAI2ASEL) */
2257
2258#if defined(RCC_CDCCIP1R_SAI2BSEL)
2272#define __HAL_RCC_SAI2B_CONFIG(__RCC_SAI2BCLKSource__ )\
2273 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL, (__RCC_SAI2BCLKSource__))
2274
2284#define __HAL_RCC_GET_SAI2B_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL)))
2285#endif /* defined(RCC_CDCCIP1R_SAI2BSEL) */
2286
2287
2288#if defined(SAI4_Block_A)
2301#define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\
2302 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__))
2303
2312#define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL)))
2313#endif /* SAI4_Block_A */
2314
2315#if defined(SAI4_Block_B)
2328#define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\
2329 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__))
2330
2339#define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL)))
2340#endif /* SAI4_Block_B */
2341
2353#if defined(RCC_D2CCIP2R_I2C123SEL)
2354#define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \
2355 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__))
2356#elif defined(RCC_CDCCIP2R_I2C123SEL)
2357#define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \
2358 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__))
2359#else /* RCC_D2CCIP2R_I2C1235SEL */
2360#define __HAL_RCC_I2C1235_CONFIG(__I2C1235CLKSource__) \
2361 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL, (uint32_t)(__I2C1235CLKSource__))
2362/* alias */
2363#define __HAL_RCC_I2C123_CONFIG __HAL_RCC_I2C1235_CONFIG
2364#endif /* RCC_D2CCIP2R_I2C123SEL */
2365
2375#if defined(RCC_D2CCIP2R_I2C123SEL)
2376#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
2377#elif defined(RCC_CDCCIP2R_I2C123SEL)
2378#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL)))
2379#else /* RCC_D2CCIP2R_I2C1235SEL */
2380#define __HAL_RCC_GET_I2C1235_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL)))
2381/* alias */
2382#define __HAL_RCC_GET_I2C123_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
2383#endif /* RCC_D2CCIP2R_I2C123SEL */
2384
2394#if defined(I2C5)
2395#define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C1235_CONFIG
2396#else
2397#define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C123_CONFIG
2398#endif /*I2C5*/
2399
2407#if defined(I2C5)
2408#define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
2409#else
2410#define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE
2411#endif /*I2C5*/
2412
2422#if defined(I2C5)
2423#define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C1235_CONFIG
2424#else
2425#define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG
2426#endif /*I2C5*/
2427
2435#if defined(I2C5)
2436#define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
2437#else
2438#define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE
2439#endif /*I2C5*/
2440
2450#if defined(I2C5)
2451#define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C1235_CONFIG
2452#else
2453#define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG
2454#endif /*I2C5*/
2455
2463#if defined(I2C5)
2464#define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
2465#else
2466#define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE
2467#endif /*I2C5*/
2468
2478#if defined(RCC_D3CCIPR_I2C4SEL)
2479#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \
2480 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
2481#else
2482#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \
2483 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
2484#endif /* RCC_D3CCIPR_I2C4SEL */
2485
2493#if defined(RCC_D3CCIPR_I2C4SEL)
2494#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))
2495#else
2496#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL)))
2497#endif /* RCC_D3CCIPR_I2C4SEL */
2498
2499#if defined(I2C5)
2509#define __HAL_RCC_I2C5_CONFIG __HAL_RCC_I2C1235_CONFIG
2510#endif /* I2C5 */
2511
2512#if defined(I2C5)
2520#define __HAL_RCC_GET_I2C5_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
2521#endif /* I2C5 */
2522
2536#if defined(RCC_D2CCIP2R_USART16SEL)
2537#define __HAL_RCC_USART16_CONFIG(__USART16910CLKSource__) \
2538 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16910CLKSource__))
2539#elif defined(RCC_CDCCIP2R_USART16910SEL)
2540#define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \
2541 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))
2542/* alias */
2543#define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG
2544#else /* RCC_D2CCIP2R_USART16910SEL */
2545#define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \
2546 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))
2547/* alias */
2548#define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG
2549#endif /* RCC_D2CCIP2R_USART16SEL */
2550
2562#if defined(RCC_D2CCIP2R_USART16SEL)
2563#define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
2564#elif defined(RCC_CDCCIP2R_USART16910SEL)
2565#define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL)))
2566/* alias*/
2567#define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE
2568#else /* RCC_D2CCIP2R_USART16910SEL */
2569#define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL)))
2570/* alias */
2571#define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE
2572#endif /* RCC_D2CCIP2R_USART16SEL */
2573
2585#if defined(RCC_D2CCIP2R_USART28SEL)
2586#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \
2587 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__))
2588#else
2589#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \
2590 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__))
2591#endif /* RCC_D2CCIP2R_USART28SEL */
2592
2602#if defined(RCC_D2CCIP2R_USART28SEL)
2603#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
2604#else
2605#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL)))
2606#endif /* RCC_D2CCIP2R_USART28SEL */
2607
2619#define __HAL_RCC_USART1_CONFIG __HAL_RCC_USART16_CONFIG
2620
2630#define __HAL_RCC_GET_USART1_SOURCE __HAL_RCC_GET_USART16_SOURCE
2631
2643#define __HAL_RCC_USART2_CONFIG __HAL_RCC_USART234578_CONFIG
2644
2654#define __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE
2655
2667#define __HAL_RCC_USART3_CONFIG __HAL_RCC_USART234578_CONFIG
2668
2678#define __HAL_RCC_GET_USART3_SOURCE __HAL_RCC_GET_USART234578_SOURCE
2679
2691#define __HAL_RCC_UART4_CONFIG __HAL_RCC_USART234578_CONFIG
2692
2702#define __HAL_RCC_GET_UART4_SOURCE __HAL_RCC_GET_USART234578_SOURCE
2703
2715#define __HAL_RCC_UART5_CONFIG __HAL_RCC_USART234578_CONFIG
2716
2726#define __HAL_RCC_GET_UART5_SOURCE __HAL_RCC_GET_USART234578_SOURCE
2727
2739#define __HAL_RCC_USART6_CONFIG __HAL_RCC_USART16_CONFIG
2740
2750#define __HAL_RCC_GET_USART6_SOURCE __HAL_RCC_GET_USART16_SOURCE
2751
2763#define __HAL_RCC_UART7_CONFIG __HAL_RCC_USART234578_CONFIG
2764
2774#define __HAL_RCC_GET_UART7_SOURCE __HAL_RCC_GET_USART234578_SOURCE
2775
2787#define __HAL_RCC_UART8_CONFIG __HAL_RCC_USART234578_CONFIG
2788
2798#define __HAL_RCC_GET_UART8_SOURCE __HAL_RCC_GET_USART234578_SOURCE
2799
2800#if defined(UART9)
2812#define __HAL_RCC_UART9_CONFIG __HAL_RCC_USART16_CONFIG
2813
2823#define __HAL_RCC_GET_UART9_SOURCE __HAL_RCC_GET_USART16_SOURCE
2824#endif /* UART9 */
2825
2826#if defined(USART10)
2838#define __HAL_RCC_USART10_CONFIG __HAL_RCC_USART16_CONFIG
2839
2849#define __HAL_RCC_GET_USART10_SOURCE __HAL_RCC_GET_USART16_SOURCE
2850#endif /* USART10 */
2851
2863#if defined (RCC_D3CCIPR_LPUART1SEL)
2864#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
2865 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
2866#else
2867#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
2868 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
2869#endif /* RCC_D3CCIPR_LPUART1SEL */
2870
2880#if defined (RCC_D3CCIPR_LPUART1SEL)
2881#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)))
2882#else
2883#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL)))
2884#endif /* RCC_D3CCIPR_LPUART1SEL */
2885
2897#if defined(RCC_D2CCIP2R_LPTIM1SEL)
2898#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
2899 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
2900#else
2901#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
2902 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
2903#endif /* RCC_D2CCIP2R_LPTIM1SEL */
2904
2914#if defined(RCC_D2CCIP2R_LPTIM1SEL)
2915#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL)))
2916#else
2917#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL)))
2918#endif /* RCC_D2CCIP2R_LPTIM1SEL */
2919
2931#if defined(RCC_D3CCIPR_LPTIM2SEL)
2932#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \
2933 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
2934#else
2935#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \
2936 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
2937#endif /* RCC_D3CCIPR_LPTIM2SEL */
2938
2948#if defined(RCC_D3CCIPR_LPTIM2SEL)
2949#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL)))
2950#else
2951#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL)))
2952#endif /* RCC_D3CCIPR_LPTIM2SEL */
2953
2964#if defined(RCC_D3CCIPR_LPTIM345SEL)
2965#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \
2966 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__))
2967#else
2968#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \
2969 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM345CLKSource__))
2970#endif /* RCC_D3CCIPR_LPTIM345SEL */
2971
2981#if defined(RCC_D3CCIPR_LPTIM345SEL)
2982#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
2983#else
2984#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL)))
2985#endif /* RCC_D3CCIPR_LPTIM345SEL */
2986
2997#define __HAL_RCC_LPTIM3_CONFIG __HAL_RCC_LPTIM345_CONFIG
2998
3008#define __HAL_RCC_GET_LPTIM3_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE
3009
3010#if defined(LPTIM4)
3021#define __HAL_RCC_LPTIM4_CONFIG __HAL_RCC_LPTIM345_CONFIG
3022
3023
3033#define __HAL_RCC_GET_LPTIM4_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE
3034#endif /* LPTIM4 */
3035
3036#if defined(LPTIM5)
3047#define __HAL_RCC_LPTIM5_CONFIG __HAL_RCC_LPTIM345_CONFIG
3048
3049
3059#define __HAL_RCC_GET_LPTIM5_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE
3060#endif /* LPTIM5 */
3061
3062#if defined(QUADSPI)
3071#define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \
3072 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__))
3073
3074
3082#define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)))
3083#endif /* QUADSPI */
3084
3085#if defined(OCTOSPI1) || defined(OCTOSPI2)
3094#if defined(RCC_CDCCIPR_OCTOSPISEL)
3095#define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \
3096 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__))
3097#else
3098#define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \
3099 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__))
3100#endif /* RCC_CDCCIPR_OCTOSPISEL */
3101
3109#if defined(RCC_CDCCIPR_OCTOSPISEL)
3110#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL)))
3111#else
3112#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL)))
3113#endif /* RCC_CDCCIPR_OCTOSPISEL */
3114#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
3115
3116
3117#if defined(DSI)
3124#define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \
3125 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, (uint32_t)(__DSICLKSource__))
3126
3127
3133#define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL)))
3134#endif /*DSI*/
3135
3144#if defined(RCC_D1CCIPR_FMCSEL)
3145#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \
3146 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
3147#else
3148#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \
3149 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
3150#endif /* RCC_D1CCIPR_FMCSEL */
3151
3159#if defined(RCC_D1CCIPR_FMCSEL)
3160#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)))
3161#else
3162#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL)))
3163#endif /* RCC_D1CCIPR_FMCSEL */
3164
3172#if defined(RCC_D2CCIP2R_USBSEL)
3173#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
3174 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
3175#else
3176#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
3177 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
3178#endif /* RCC_D2CCIP2R_USBSEL */
3179
3186#if defined(RCC_D2CCIP2R_USBSEL)
3187#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)))
3188#else
3189#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL)))
3190#endif /* RCC_D2CCIP2R_USBSEL */
3191
3199#if defined(RCC_D3CCIPR_ADCSEL)
3200#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \
3201 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
3202#else
3203#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \
3204 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
3205#endif /* RCC_D3CCIPR_ADCSEL */
3206
3213#if defined(RCC_D3CCIPR_ADCSEL)
3214#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)))
3215#else
3216#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL)))
3217#endif /* RCC_D3CCIPR_ADCSEL */
3218
3225#if defined(RCC_D2CCIP1R_SWPSEL)
3226#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \
3227 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
3228#else
3229#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \
3230 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
3231#endif /* RCC_D2CCIP1R_SWPSEL */
3232
3238#if defined(RCC_D2CCIP1R_SWPSEL)
3239#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)))
3240#else
3241#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL)))
3242#endif /* RCC_D2CCIP1R_SWPSEL */
3243
3250#if defined(RCC_D2CCIP1R_DFSDM1SEL)
3251#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \
3252 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
3253#else
3254#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \
3255 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
3256#endif /* RCC_D2CCIP1R_DFSDM1SEL */
3257
3263#if defined (RCC_D2CCIP1R_DFSDM1SEL)
3264#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)))
3265#else
3266#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL)))
3267#endif /* RCC_D2CCIP1R_DFSDM1SEL */
3268
3269#if defined(DFSDM2_BASE)
3276#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) \
3277 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__))
3278
3284#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL)))
3285#endif /* DFSDM2 */
3286
3295#if defined(RCC_D2CCIP2R_CECSEL)
3296#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
3297 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
3298#else
3299#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
3300 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
3301#endif /* RCC_D2CCIP2R_CECSEL */
3302
3309#if defined(RCC_D2CCIP2R_CECSEL)
3310#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)))
3311#else
3312#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL)))
3313#endif /* RCC_D2CCIP2R_CECSEL */
3314
3322#if defined(RCC_D1CCIPR_CKPERSEL)
3323#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \
3324 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
3325#else
3326#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \
3327 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
3328#endif /* RCC_D1CCIPR_CKPERSEL */
3329
3336#if defined(RCC_D1CCIPR_CKPERSEL)
3337#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)))
3338#else
3339#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL)))
3340#endif /* RCC_D1CCIPR_CKPERSEL */
3341
3342#if defined(FDCAN1) || defined(FDCAN2)
3350#if defined(RCC_D2CCIP1R_FDCANSEL)
3351#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \
3352 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
3353#else
3354#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \
3355 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
3356#endif /* RCC_D2CCIP1R_FDCANSEL */
3357
3364#if defined(RCC_D2CCIP1R_FDCANSEL)
3365#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)))
3366#else
3367#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL)))
3368#endif /* RCC_D2CCIP1R_FDCANSEL */
3369
3370#endif /*FDCAN1 || FDCAN2*/
3371
3384#if defined(RCC_D2CCIP1R_SPI123SEL)
3385#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\
3386 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
3387#else
3388#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\
3389 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
3390#endif /* RCC_D2CCIP1R_SPI123SEL */
3391
3400#if defined(RCC_D2CCIP1R_SPI123SEL)
3401#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
3402#else
3403#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL)))
3404#endif /* RCC_D2CCIP1R_SPI123SEL */
3405
3418#define __HAL_RCC_SPI1_CONFIG __HAL_RCC_SPI123_CONFIG
3419
3428#define __HAL_RCC_GET_SPI1_SOURCE __HAL_RCC_GET_SPI123_SOURCE
3429
3442#define __HAL_RCC_SPI2_CONFIG __HAL_RCC_SPI123_CONFIG
3443
3452#define __HAL_RCC_GET_SPI2_SOURCE __HAL_RCC_GET_SPI123_SOURCE
3453
3466#define __HAL_RCC_SPI3_CONFIG __HAL_RCC_SPI123_CONFIG
3467
3476#define __HAL_RCC_GET_SPI3_SOURCE __HAL_RCC_GET_SPI123_SOURCE
3477
3491#if defined(RCC_D2CCIP1R_SPI45SEL)
3492#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\
3493 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
3494#else
3495#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\
3496 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
3497#endif /* RCC_D2CCIP1R_SPI45SEL */
3498
3508#if defined(RCC_D2CCIP1R_SPI45SEL)
3509#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
3510#else
3511#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL)))
3512#endif /* RCC_D2CCIP1R_SPI45SEL */
3513
3527#define __HAL_RCC_SPI4_CONFIG __HAL_RCC_SPI45_CONFIG
3528
3538#define __HAL_RCC_GET_SPI4_SOURCE __HAL_RCC_GET_SPI45_SOURCE
3539
3553#define __HAL_RCC_SPI5_CONFIG __HAL_RCC_SPI45_CONFIG
3554
3564#define __HAL_RCC_GET_SPI5_SOURCE __HAL_RCC_GET_SPI45_SOURCE
3565
3584#if defined(RCC_D3CCIPR_SPI6SEL)
3585#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\
3586 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
3587#else
3588#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\
3589 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
3590#endif /* RCC_D3CCIPR_SPI6SEL */
3591
3602#if defined(RCC_D3CCIPR_SPI6SEL)
3603#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL)))
3604#else
3605#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL)))
3606#endif /* RCC_D3CCIPR_SPI6SEL */
3607
3614#if defined(RCC_D1CCIPR_SDMMCSEL)
3615#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \
3616 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
3617#else
3618#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \
3619 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
3620#endif /* RCC_D1CCIPR_SDMMCSEL */
3621
3624#if defined(RCC_D1CCIPR_SDMMCSEL)
3625#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)))
3626#else
3627#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL)))
3628#endif /* RCC_D1CCIPR_SDMMCSEL */
3629
3639#if defined(RCC_D2CCIP2R_RNGSEL)
3640#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
3641 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
3642#else
3643#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
3644 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
3645#endif /* RCC_D2CCIP2R_RNGSEL */
3646
3654#if defined(RCC_D2CCIP2R_RNGSEL)
3655#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)))
3656#else
3657#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL)))
3658#endif /* RCC_D2CCIP2R_RNGSEL */
3659
3660#if defined(HRTIM1)
3667#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
3668 MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__))
3669
3675#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)))
3676#endif /* HRTIM1 */
3677
3688#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\
3689 RCC->CFGR |= (__PRESC__); \
3690 }while(0)
3691
3696#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
3697
3702#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
3703
3708#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
3709
3714#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
3715
3716#if defined(DUAL_CORE)
3721#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)
3722
3727#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)
3728
3733#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS)
3734
3739#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS)
3740#endif /* DUAL_CORE */
3741
3746#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
3747
3748
3753#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
3754
3755
3760#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
3761
3766#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
3767
3772#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
3773 do { \
3774 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
3775 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
3776 } while(0)
3777
3782#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
3783 do { \
3784 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
3785 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
3786 } while(0)
3787
3792#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
3793
3798#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
3799
3800#if defined(DUAL_CORE)
3805#define __HAL_RCC_C2_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
3806
3811#define __HAL_RCC_C2_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS)
3812#endif /* DUAL_CORE */
3817#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
3818
3829#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
3830
3841#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
3842
3852#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
3853
3865/* CRS IT Error Mask */
3866#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
3867
3868#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
3869 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
3870 { \
3871 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
3872 } \
3873 else \
3874 { \
3875 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
3876 } \
3877 } while(0)
3878
3892#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
3893
3909/* CRS Flag Error Mask */
3910#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
3911
3912#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
3913 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
3914 { \
3915 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
3916 } \
3917 else \
3918 { \
3919 WRITE_REG(CRS->ICR, (__FLAG__)); \
3920 } \
3921 } while(0)
3922
3932#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
3933
3938#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
3939
3945#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
3946
3951#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
3952
3963#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
3964
3965
3976/* Exported functions --------------------------------------------------------*/
3984HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
3985void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
3986uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk);
3987uint32_t HAL_RCCEx_GetD1PCLK1Freq(void);
3988uint32_t HAL_RCCEx_GetD3PCLK1Freq(void);
3989uint32_t HAL_RCCEx_GetD1SysClockFreq(void);
3990void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks);
3991void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks);
3992void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks);
4000void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
4001void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk);
4002void HAL_RCCEx_EnableLSECSS(void);
4003void HAL_RCCEx_DisableLSECSS(void);
4004void HAL_RCCEx_EnableLSECSS_IT(void);
4005void HAL_RCCEx_LSECSS_IRQHandler(void);
4006void HAL_RCCEx_LSECSS_Callback(void);
4007#if defined(DUAL_CORE)
4008void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx);
4009#endif /*DUAL_CORE*/
4010#if defined(RCC_GCR_WW1RSC)
4011void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx);
4012#endif /*RCC_GCR_WW1RSC*/
4022void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
4023void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
4024void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
4025uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
4026void HAL_RCCEx_CRS_IRQHandler(void);
4027void HAL_RCCEx_CRS_SyncOkCallback(void);
4028void HAL_RCCEx_CRS_SyncWarnCallback(void);
4029void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
4030void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
4031
4040/* Private macros ------------------------------------------------------------*/
4049#define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || \
4050 ((VALUE) == RCC_PLL2_DIVQ) || \
4051 ((VALUE) == RCC_PLL2_DIVR))
4052
4053#define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \
4054 ((VALUE) == RCC_PLL3_DIVQ) || \
4055 ((VALUE) == RCC_PLL3_DIVR))
4056
4057#if defined(RCC_D2CCIP2R_USART16SEL)
4058#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \
4059 ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \
4060 ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \
4061 ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \
4062 ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \
4063 ((SOURCE) == RCC_USART16CLKSOURCE_HSI))
4064#else
4065#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \
4066 ((SOURCE) == RCC_USART16CLKSOURCE_CDPCLK2)|| \
4067 ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \
4068 ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \
4069 ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \
4070 ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \
4071 ((SOURCE) == RCC_USART16CLKSOURCE_HSI))
4072/* alias*/
4073#define IS_RCC_USART16910CLKSOURCE IS_RCC_USART16CLKSOURCE
4074#endif /* RCC_D2CCIP2R_USART16SEL */
4075
4076#if defined(RCC_D2CCIP2R_USART28SEL)
4077#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \
4078 ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \
4079 ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \
4080 ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \
4081 ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \
4082 ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))
4083#else
4084#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \
4085 ((SOURCE) == RCC_USART234578CLKSOURCE_CDPCLK1)|| \
4086 ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \
4087 ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \
4088 ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \
4089 ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \
4090 ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))
4091#endif /* RCC_D2CCIP2R_USART28SEL */
4092
4093#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \
4094 ((SOURCE) == RCC_USART1CLKSOURCE_PLL2) || \
4095 ((SOURCE) == RCC_USART1CLKSOURCE_PLL3) || \
4096 ((SOURCE) == RCC_USART1CLKSOURCE_CSI) || \
4097 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
4098 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
4099
4100#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \
4101 ((SOURCE) == RCC_USART2CLKSOURCE_PLL2) || \
4102 ((SOURCE) == RCC_USART2CLKSOURCE_PLL3) || \
4103 ((SOURCE) == RCC_USART2CLKSOURCE_CSI) || \
4104 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
4105 ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
4106
4107#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \
4108 ((SOURCE) == RCC_USART3CLKSOURCE_PLL2) || \
4109 ((SOURCE) == RCC_USART3CLKSOURCE_PLL3) || \
4110 ((SOURCE) == RCC_USART3CLKSOURCE_CSI) || \
4111 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
4112 ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
4113
4114#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \
4115 ((SOURCE) == RCC_UART4CLKSOURCE_PLL2) || \
4116 ((SOURCE) == RCC_UART4CLKSOURCE_PLL3) || \
4117 ((SOURCE) == RCC_UART4CLKSOURCE_CSI) || \
4118 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
4119 ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
4120
4121#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \
4122 ((SOURCE) == RCC_UART5CLKSOURCE_PLL2) || \
4123 ((SOURCE) == RCC_UART5CLKSOURCE_PLL3) || \
4124 ((SOURCE) == RCC_UART5CLKSOURCE_CSI) || \
4125 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
4126 ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
4127
4128#define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \
4129 ((SOURCE) == RCC_USART6CLKSOURCE_PLL2) || \
4130 ((SOURCE) == RCC_USART6CLKSOURCE_PLL3) || \
4131 ((SOURCE) == RCC_USART6CLKSOURCE_CSI) || \
4132 ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \
4133 ((SOURCE) == RCC_USART6CLKSOURCE_HSI))
4134
4135#define IS_RCC_UART7CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1) || \
4136 ((SOURCE) == RCC_UART7CLKSOURCE_PLL2) || \
4137 ((SOURCE) == RCC_UART7CLKSOURCE_PLL3) || \
4138 ((SOURCE) == RCC_UART7CLKSOURCE_CSI) || \
4139 ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \
4140 ((SOURCE) == RCC_UART7CLKSOURCE_HSI))
4141
4142#define IS_RCC_UART8CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1) || \
4143 ((SOURCE) == RCC_UART8CLKSOURCE_PLL2) || \
4144 ((SOURCE) == RCC_UART8CLKSOURCE_PLL3) || \
4145 ((SOURCE) == RCC_UART8CLKSOURCE_CSI) || \
4146 ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \
4147 ((SOURCE) == RCC_UART8CLKSOURCE_HSI))
4148
4149#if defined(UART9)
4150#define IS_RCC_UART9CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART9CLKSOURCE_D2PCLK2)|| \
4151 ((SOURCE) == RCC_UART9CLKSOURCE_PLL2) || \
4152 ((SOURCE) == RCC_UART9CLKSOURCE_PLL3) || \
4153 ((SOURCE) == RCC_UART9CLKSOURCE_CSI) || \
4154 ((SOURCE) == RCC_UART9CLKSOURCE_LSE) || \
4155 ((SOURCE) == RCC_UART9CLKSOURCE_HSI))
4156#endif
4157
4158#if defined(USART10)
4159#define IS_RCC_USART10CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART10CLKSOURCE_D2PCLK2)|| \
4160 ((SOURCE) == RCC_USART10CLKSOURCE_PLL2) || \
4161 ((SOURCE) == RCC_USART10CLKSOURCE_PLL3) || \
4162 ((SOURCE) == RCC_USART10CLKSOURCE_CSI) || \
4163 ((SOURCE) == RCC_USART10CLKSOURCE_LSE) || \
4164 ((SOURCE) == RCC_USART10CLKSOURCE_HSI))
4165#endif
4166
4167#define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \
4168 ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2) || \
4169 ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3) || \
4170 ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI) || \
4171 ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) || \
4172 ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI))
4173
4174#if defined(I2C5)
4175#define IS_RCC_I2C1235CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1235CLKSOURCE_PLL3) || \
4176 ((SOURCE) == RCC_I2C1235CLKSOURCE_HSI) || \
4177 ((SOURCE) == RCC_I2C1235CLKSOURCE_D2PCLK1) || \
4178 ((SOURCE) == RCC_I2C1235CLKSOURCE_CSI))
4179
4180#define IS_RCC_I2C123CLKSOURCE IS_RCC_I2C1235CLKSOURCE /* For API Backward compatibility */
4181#else
4182#define IS_RCC_I2C123CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3) || \
4183 ((SOURCE) == RCC_I2C123CLKSOURCE_HSI) || \
4184 ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \
4185 ((SOURCE) == RCC_I2C123CLKSOURCE_CSI))
4186#endif /*I2C5*/
4187
4188#define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3) || \
4189 ((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \
4190 ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \
4191 ((SOURCE) == RCC_I2C1CLKSOURCE_CSI))
4192
4193#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3) || \
4194 ((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
4195 ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \
4196 ((SOURCE) == RCC_I2C2CLKSOURCE_CSI))
4197
4198#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3) || \
4199 ((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
4200 ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \
4201 ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
4202
4203#define IS_RCC_I2C4CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3) || \
4204 ((SOURCE) == RCC_I2C4CLKSOURCE_HSI) || \
4205 ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \
4206 ((SOURCE) == RCC_I2C4CLKSOURCE_CSI))
4207
4208#if defined(I2C5)
4209#define IS_RCC_I2C5CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C5CLKSOURCE_PLL3) || \
4210 ((SOURCE) == RCC_I2C5CLKSOURCE_HSI) || \
4211 ((SOURCE) == RCC_I2C5CLKSOURCE_D2PCLK1)|| \
4212 ((SOURCE) == RCC_I2C5CLKSOURCE_CSI))
4213#endif /*I2C5*/
4214
4215#define IS_RCC_RNGCLKSOURCE(SOURCE) (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \
4216 ((SOURCE) == RCC_RNGCLKSOURCE_PLL) || \
4217 ((SOURCE) == RCC_RNGCLKSOURCE_LSE) || \
4218 ((SOURCE) == RCC_RNGCLKSOURCE_LSI))
4219
4220#if defined(HRTIM1)
4221#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \
4222 ((SOURCE) == RCC_HRTIM1CLK_CPUCLK))
4223#endif
4224
4225#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \
4226 ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \
4227 ((SOURCE) == RCC_USBCLKSOURCE_HSI48))
4228
4229#define IS_RCC_SAI1CLK(__SOURCE__) \
4230 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
4231 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \
4232 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \
4233 ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \
4234 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
4235
4236#if defined(SAI3)
4237#define IS_RCC_SAI23CLK(__SOURCE__) \
4238 (((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL) || \
4239 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) || \
4240 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) || \
4241 ((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) || \
4242 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN))
4243
4244#define IS_RCC_SAI2CLK(__SOURCE__) \
4245 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \
4246 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \
4247 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \
4248 ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \
4249 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
4250
4251
4252#define IS_RCC_SAI3CLK(__SOURCE__) \
4253 (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL) || \
4254 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \
4255 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \
4256 ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \
4257 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN))
4258#endif
4259
4260#if defined(RCC_CDCCIP1R_SAI2ASEL)
4261#define IS_RCC_SAI2ACLK(__SOURCE__) \
4262 (((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL) || \
4263 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL2) || \
4264 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL3) || \
4265 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_CLKP) || \
4266 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PIN) || \
4267 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_SPDIF))
4268#endif
4269
4270#if defined(RCC_CDCCIP1R_SAI2BSEL)
4271#define IS_RCC_SAI2BCLK(__SOURCE__) \
4272 (((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL) || \
4273 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL2) || \
4274 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL3) || \
4275 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_CLKP) || \
4276 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PIN) || \
4277 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_SPDIF))
4278#endif
4279
4280#define IS_RCC_SPI123CLK(__SOURCE__) \
4281 (((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL) || \
4282 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || \
4283 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || \
4284 ((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || \
4285 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN))
4286
4287#define IS_RCC_SPI1CLK(__SOURCE__) \
4288 (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL) || \
4289 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \
4290 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \
4291 ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \
4292 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN))
4293
4294#define IS_RCC_SPI2CLK(__SOURCE__) \
4295 (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL) || \
4296 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \
4297 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \
4298 ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \
4299 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN))
4300
4301#define IS_RCC_SPI3CLK(__SOURCE__) \
4302 (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL) || \
4303 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \
4304 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \
4305 ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \
4306 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN))
4307
4308#define IS_RCC_SPI45CLK(__SOURCE__) \
4309 (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK2) || \
4310 ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2) || \
4311 ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3) || \
4312 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) || \
4313 ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI) || \
4314 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE))
4315
4316#define IS_RCC_SPI4CLK(__SOURCE__) \
4317 (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK2) || \
4318 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2) || \
4319 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3) || \
4320 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || \
4321 ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI) || \
4322 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE))
4323
4324#define IS_RCC_SPI5CLK(__SOURCE__) \
4325 (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK2)|| \
4326 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2) || \
4327 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3) || \
4328 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) || \
4329 ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI) || \
4330 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE))
4331
4332#if defined(RCC_D3CCIPR_SPI6SEL)
4333#define IS_RCC_SPI6CLK(__SOURCE__) \
4334 (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \
4335 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \
4336 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \
4337 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \
4338 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \
4339 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE))
4340#else
4341#define IS_RCC_SPI6CLK(__SOURCE__) \
4342 (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \
4343 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \
4344 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \
4345 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \
4346 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \
4347 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE) || \
4348 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN))
4349#endif /* RCC_D3CCIPR_SPI6SEL */
4350
4351#if defined(SAI4)
4352#define IS_RCC_SAI4ACLK(__SOURCE__) \
4353 (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL) || \
4354 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \
4355 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || \
4356 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || \
4357 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN))
4358
4359#define IS_RCC_SAI4BCLK(__SOURCE__) \
4360 (((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL) || \
4361 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || \
4362 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \
4363 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \
4364 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN))
4365#endif /*SAI4*/
4366
4367#define IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
4368#define IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
4369#define IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
4370#define IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
4371#define IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
4372
4373#define IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
4374#define IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
4375#define IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
4376#define IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
4377#define IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
4378
4379#define IS_RCC_PLL2RGE_VALUE(VALUE) (((VALUE) == RCC_PLL2VCIRANGE_0) || \
4380 ((VALUE) == RCC_PLL2VCIRANGE_1) || \
4381 ((VALUE) == RCC_PLL2VCIRANGE_2) || \
4382 ((VALUE) == RCC_PLL2VCIRANGE_3))
4383
4384#define IS_RCC_PLL3RGE_VALUE(VALUE) (((VALUE) == RCC_PLL3VCIRANGE_0) || \
4385 ((VALUE) == RCC_PLL3VCIRANGE_1) || \
4386 ((VALUE) == RCC_PLL3VCIRANGE_2) || \
4387 ((VALUE) == RCC_PLL3VCIRANGE_3))
4388
4389#define IS_RCC_PLL2VCO_VALUE(VALUE) (((VALUE) == RCC_PLL2VCOWIDE) || \
4390 ((VALUE) == RCC_PLL2VCOMEDIUM))
4391
4392#define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE) || \
4393 ((VALUE) == RCC_PLL3VCOMEDIUM))
4394
4395#define IS_RCC_LPTIM1CLK(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \
4396 ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2) || \
4397 ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3) || \
4398 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE) || \
4399 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \
4400 ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP))
4401
4402#define IS_RCC_LPTIM2CLK(SOURCE) (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \
4403 ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2) || \
4404 ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3) || \
4405 ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE) || \
4406 ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI) || \
4407 ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP))
4408
4409#define IS_RCC_LPTIM345CLK(SOURCE) (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| \
4410 ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2) || \
4411 ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3) || \
4412 ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE) || \
4413 ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI) || \
4414 ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP))
4415
4416#define IS_RCC_LPTIM3CLK(SOURCE) (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1) || \
4417 ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2) || \
4418 ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3) || \
4419 ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE) || \
4420 ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI) || \
4421 ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP))
4422
4423#if defined(LPTIM4)
4424#define IS_RCC_LPTIM4CLK(SOURCE) (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \
4425 ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2) || \
4426 ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3) || \
4427 ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE) || \
4428 ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI) || \
4429 ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP))
4430#endif /* LPTIM4*/
4431
4432#if defined(LPTIM5)
4433#define IS_RCC_LPTIM5CLK(SOURCE) (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \
4434 ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2) || \
4435 ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3) || \
4436 ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE) || \
4437 ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI) || \
4438 ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP))
4439#endif /*LPTIM5*/
4440
4441#if defined(QUADSPI)
4442#define IS_RCC_QSPICLK(__SOURCE__) \
4443 (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK) || \
4444 ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL) || \
4445 ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2) || \
4446 ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP))
4447#endif /*QUADSPI*/
4448
4449#if defined(OCTOSPI1) || defined(OCTOSPI1)
4450#define IS_RCC_OSPICLK(__SOURCE__) \
4451 (((__SOURCE__) == RCC_OSPICLKSOURCE_D1HCLK) || \
4452 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL) || \
4453 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2) || \
4454 ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP))
4455#endif /*OCTOSPI1 || OCTOSPI1*/
4456
4457#if defined(DSI)
4458#define IS_RCC_DSICLK(__SOURCE__) \
4459 (((__SOURCE__) == RCC_DSICLKSOURCE_PHY) || \
4460 ((__SOURCE__) == RCC_DSICLKSOURCE_PLL2))
4461#endif /*DSI*/
4462
4463#define IS_RCC_FMCCLK(__SOURCE__) \
4464 (((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK) || \
4465 ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL) || \
4466 ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2) || \
4467 ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP))
4468
4469#if defined(FDCAN1) || defined(FDCAN2)
4470#define IS_RCC_FDCANCLK(__SOURCE__) \
4471 (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \
4472 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \
4473 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2))
4474#endif /*FDCAN1 || FDCAN2*/
4475
4476#define IS_RCC_SDMMC(__SOURCE__) \
4477 (((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL) || \
4478 ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2))
4479
4480#define IS_RCC_ADCCLKSOURCE(SOURCE) (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \
4481 ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \
4482 ((SOURCE) == RCC_ADCCLKSOURCE_CLKP))
4483
4484#define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \
4485 ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI))
4486
4487#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \
4488 ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS))
4489
4490#if defined(DFSDM2_BASE)
4491#define IS_RCC_DFSDM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM2CLKSOURCE_SRDPCLK1) || \
4492 ((SOURCE) == RCC_DFSDM2CLKSOURCE_SYS))
4493#endif /*DFSDM2*/
4494
4495#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL) || \
4496 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \
4497 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \
4498 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI))
4499
4500#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \
4501 ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \
4502 ((SOURCE) == RCC_CECCLKSOURCE_CSI))
4503
4504#define IS_RCC_CLKPSOURCE(SOURCE) (((SOURCE) == RCC_CLKPSOURCE_HSI) || \
4505 ((SOURCE) == RCC_CLKPSOURCE_CSI) || \
4506 ((SOURCE) == RCC_CLKPSOURCE_HSE))
4507#define IS_RCC_TIMPRES(VALUE) \
4508 (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
4509 ((VALUE) == RCC_TIMPRES_ACTIVATED))
4510
4511#if defined(DUAL_CORE)
4512#define IS_RCC_BOOT_CORE(CORE) (((CORE) == RCC_BOOT_C1) || \
4513 ((CORE) == RCC_BOOT_C2))
4514#endif /*DUAL_CORE*/
4515
4516#if defined(DUAL_CORE)
4517#define IS_RCC_SCOPE_WWDG(WWDG) (((WWDG) == RCC_WWDG1) || \
4518 ((WWDG) == RCC_WWDG2))
4519#else
4520#define IS_RCC_SCOPE_WWDG(WWDG) ((WWDG) == RCC_WWDG1)
4521
4522#endif /*DUAL_CORE*/
4523
4524#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \
4525 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
4526 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || \
4527 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN))
4528
4529#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \
4530 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
4531 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
4532 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
4533
4534#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
4535 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
4536
4537#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
4538
4539#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
4540
4541#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
4542
4543#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
4544 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
4561#ifdef __cplusplus
4562}
4563#endif
4564
4565#endif /* STM32H7xx_HAL_RCC_EX_H */
4566
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
RCC PLL1 Clocks structure definition.
Definition: stm32h7xx_hal_rcc_ex.h:111
RCC PLL2 Clocks structure definition.
Definition: stm32h7xx_hal_rcc_ex.h:121
RCC PLL3 Clocks structure definition.
Definition: stm32h7xx_hal_rcc_ex.h:131
RCC_CRS Init structure definition.
Definition: stm32h7xx_hal_rcc_ex.h:295
uint32_t Polarity
Definition: stm32h7xx_hal_rcc_ex.h:302
uint32_t HSI48CalibrationValue
Definition: stm32h7xx_hal_rcc_ex.h:312
uint32_t Prescaler
Definition: stm32h7xx_hal_rcc_ex.h:296
uint32_t ReloadValue
Definition: stm32h7xx_hal_rcc_ex.h:305
uint32_t Source
Definition: stm32h7xx_hal_rcc_ex.h:299
uint32_t ErrorLimitValue
Definition: stm32h7xx_hal_rcc_ex.h:309
RCC_CRS Synchronization structure definition.
Definition: stm32h7xx_hal_rcc_ex.h:321
uint32_t HSI48CalibrationValue
Definition: stm32h7xx_hal_rcc_ex.h:325
uint32_t ReloadValue
Definition: stm32h7xx_hal_rcc_ex.h:322
uint32_t FreqErrorDirection
Definition: stm32h7xx_hal_rcc_ex.h:332
uint32_t FreqErrorCapture
Definition: stm32h7xx_hal_rcc_ex.h:328
PLL2 Clock structure definition.
Definition: stm32h7xx_hal_rcc_ex.h:47
uint32_t PLL2R
Definition: stm32h7xx_hal_rcc_ex.h:64
uint32_t PLL2M
Definition: stm32h7xx_hal_rcc_ex.h:49
uint32_t PLL2RGE
Definition: stm32h7xx_hal_rcc_ex.h:66
uint32_t PLL2N
Definition: stm32h7xx_hal_rcc_ex.h:52
uint32_t PLL2FRACN
Definition: stm32h7xx_hal_rcc_ex.h:71
uint32_t PLL2VCOSEL
Definition: stm32h7xx_hal_rcc_ex.h:68
uint32_t PLL2P
Definition: stm32h7xx_hal_rcc_ex.h:57
uint32_t PLL2Q
Definition: stm32h7xx_hal_rcc_ex.h:61
PLL3 Clock structure definition.
Definition: stm32h7xx_hal_rcc_ex.h:79
uint32_t PLL3Q
Definition: stm32h7xx_hal_rcc_ex.h:93
uint32_t PLL3FRACN
Definition: stm32h7xx_hal_rcc_ex.h:103
uint32_t PLL3N
Definition: stm32h7xx_hal_rcc_ex.h:84
uint32_t PLL3VCOSEL
Definition: stm32h7xx_hal_rcc_ex.h:100
uint32_t PLL3P
Definition: stm32h7xx_hal_rcc_ex.h:89
uint32_t PLL3R
Definition: stm32h7xx_hal_rcc_ex.h:96
uint32_t PLL3RGE
Definition: stm32h7xx_hal_rcc_ex.h:98
uint32_t PLL3M
Definition: stm32h7xx_hal_rcc_ex.h:81
RCC extended clocks structure definition.
Definition: stm32h7xx_hal_rcc_ex.h:142
uint32_t Spi123ClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:195
uint32_t Spi6ClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:268
uint32_t I2c123ClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:233
uint32_t Usart16ClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:223
uint32_t TIMPresSelection
Definition: stm32h7xx_hal_rcc_ex.h:279
uint32_t Lptim1ClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:243
uint32_t CkperClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:174
uint32_t CecClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:240
uint32_t Swpmi1ClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:217
uint64_t PeriphClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:143
uint32_t I2c4ClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:249
uint32_t Lptim2ClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:252
uint32_t SpdifrxClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:201
uint32_t SdmmcClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:171
RCC_PLL2InitTypeDef PLL2
Definition: stm32h7xx_hal_rcc_ex.h:146
uint32_t Dfsdm1ClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:204
RCC_PLL3InitTypeDef PLL3
Definition: stm32h7xx_hal_rcc_ex.h:149
uint32_t Lptim345ClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:255
uint32_t AdcClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:258
uint32_t Usart234578ClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:220
uint32_t FmcClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:152
uint32_t RTCClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:271
uint32_t Sai1ClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:177
uint32_t UsbClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:237
uint32_t Lpuart1ClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:246
uint32_t Spi45ClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:198
uint32_t RngClockSelection
Definition: stm32h7xx_hal_rcc_ex.h:226