36#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H
37#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H
60BSP_START_TEXT_SECTION
static inline void arm_a9mpcore_start_scu_invalidate(
66 scu->invss = (ways & 0xf) << ((cpu_id & 0x3) * 4);
69BSP_START_TEXT_SECTION
static inline void
70arm_a9mpcore_start_errata_764369_handler(
volatile a9mpcore_scu *scu)
72 if (arm_errata_is_applicable_processor_errata_764369()) {
73 scu->diagn_ctrl |= A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE;
77BSP_START_TEXT_SECTION
static inline void
80 scu->ctrl |= A9MPCORE_SCU_CTRL_SCU_EN;
81 arm_a9mpcore_start_errata_764369_handler(scu);
85BSP_START_TEXT_SECTION
static inline void
86arm_a9mpcore_start_on_secondary_processor(
void)
90 arm_gic_irq_initialize_secondary_cpu();
93 arm_cp15_set_vector_base_address(bsp_vector_table_begin);
95 ctrl = arm_cp15_start_setup_mmu_and_cache(
97 ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
100 arm_cp15_set_domain_access_control(
101 ARM_CP15_DAC_DOMAIN(ARM_MMU_DEFAULT_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT)
105 arm_cp15_set_translation_table_base(
106 (uint32_t *) bsp_translation_table_base
109 ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M;
110 arm_cp15_set_control(ctrl);
112 _SMP_Start_multitasking_on_secondary_processor(_Per_CPU_Get());
115BSP_START_TEXT_SECTION
static inline void
116arm_a9mpcore_start_enable_smp_in_auxiliary_control(
void)
122 uint32_t actlr = arm_cp15_get_auxiliary_control();
123 actlr |= ARM_CORTEX_A9_ACTL_SMP | ARM_CORTEX_A9_ACTL_FW;
124 arm_cp15_set_auxiliary_control(actlr);
127BSP_START_TEXT_SECTION
static inline void
128arm_a9mpcore_start_errata_794072_handler(
void)
137 diag = arm_cp15_get_diagnostic_control();
139 arm_cp15_set_diagnostic_control(diag);
142BSP_START_TEXT_SECTION
static inline void
143arm_a9mpcore_start_errata_845369_handler(
void)
151 diag = arm_cp15_get_diagnostic_control();
153 arm_cp15_set_diagnostic_control(diag);
157BSP_START_TEXT_SECTION
static inline void arm_a9mpcore_start_hook_0(
void)
161 uint32_t cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id();
164 arm_a9mpcore_start_scu_enable(scu);
168 arm_a9mpcore_start_errata_794072_handler();
169 arm_a9mpcore_start_errata_845369_handler();
170 arm_a9mpcore_start_enable_smp_in_auxiliary_control();
173 arm_a9mpcore_start_scu_invalidate(scu, cpu_id, 0xf);
177 arm_a9mpcore_start_on_secondary_processor();
182BSP_START_TEXT_SECTION
static inline void arm_a9mpcore_start_global_timer(
void)
189 gt->ctrl = A9MPCORE_GT_CTRL_TMR_EN;
192BSP_START_TEXT_SECTION
static inline void arm_a9mpcore_start_hook_1(
void)
194 arm_a9mpcore_start_global_timer();
This header file provides the interfaces of the Cortex-A9 MPCore Support.
ARM co-processor 15 (CP15) API.
Create #defines which state which erratas shall get applied.
This header file provides interfaces of the ARM Generic Interrupt Controller (GIC) support.
This header file provides interfaces of the SMP Support which are only used by the implementation.
Definition: arm-a9mpcore-regs.h:98
Definition: arm-a9mpcore-regs.h:51