RTEMS 6.1-rc7
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asm.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
15/*
16 * Copyright (c) 2015, Hesham Almatary
17 * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
21 * are met:
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
32 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 */
40
41#ifndef _RTEMS_ASM_H
42#define _RTEMS_ASM_H
43
44/*
45 * Indicate we are in an assembly file and get the basic CPU definitions.
46 */
47
48#ifndef ASM
49#define ASM
50#endif
51
52#include <rtems/score/cpuopts.h>
53
54#ifndef __USER_LABEL_PREFIX__
63#define __USER_LABEL_PREFIX__ _
64#endif
65
66#ifndef __REGISTER_PREFIX__
75#define __REGISTER_PREFIX__
76#endif
77
78#include <rtems/concat.h>
79
81#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
82
84#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
85
86/*
87 * define macros for all of the registers on this CPU
88 *
89 * EXAMPLE: #define d0 REG (d0)
90 */
91
92/*
93 * Define macros to handle section beginning and ends.
94 */
95
96
98#define BEGIN_CODE_DCL .text
100#define END_CODE_DCL
102#define BEGIN_DATA_DCL .data
104#define END_DATA_DCL
106#define BEGIN_CODE .text
108#define END_CODE
110#define BEGIN_DATA
112#define END_DATA
116#define BEGIN_BSS
118#define END_BSS
120#define END
121
128#define PUBLIC(sym) .globl SYM (sym)
129
136#define EXTERN(sym) .globl SYM (sym)
137
138#endif