RTEMS
6.1-rc7
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bsps
aarch64
raspberrypi
include
bsp
raspberrypi.h
Go to the documentation of this file.
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/*
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* Copyright (c) 2022 Mohd Noor Aman
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* Copyright (c) 2024 Ning Yang
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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*
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* http://www.rtems.org/license/LICENSE
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*
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*/
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#ifndef LIBBSP_AARCH64_RASPBERRYPI_RASPBERRYPI_4_H
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#define LIBBSP_AARCH64_RASPBERRYPI_RASPBERRYPI_4_H
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#include <bspopts.h>
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#include <stdint.h>
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#include <
bsp/utility.h
>
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#define BCM2711_REG(x) (*(volatile uint64_t *)(x))
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#define BCM2711_BIT(n) (1 << (n))
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#define BCM2835_REG(addr) (*(volatile uint32_t*)(addr))
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#define RPI_PERIPHERAL_BASE 0xFE000000
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#define BASE_OFFSET 0xFE000000
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#define RPI_PERIPHERAL_SIZE 0x01800000
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#define BUS_TO_PHY(x) ((x) - BASE_OFFSET)
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#define BCM2711_CLOCK_FREQ 250000000
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#define BCM2711_TIMER_BASE (RPI_PERIPHERAL_BASE + 0xB400)
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#define BCM2711_TIMER_LOD (BCM2711_TIMER_BASE + 0x00)
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#define BCM2711_TIMER_VAL (BCM2711_TIMER_BASE + 0x04)
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#define BCM2711_TIMER_CTL (BCM2711_TIMER_BASE + 0x08)
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#define BCM2711_TIMER_CLI (BCM2711_TIMER_BASE + 0x0C)
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#define BCM2711_TIMER_RIS (BCM2711_TIMER_BASE + 0x10)
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#define BCM2711_TIMER_MIS (BCM2711_TIMER_BASE + 0x14)
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#define BCM2711_TIMER_RLD (BCM2711_TIMER_BASE + 0x18)
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#define BCM2711_TIMER_DIV (BCM2711_TIMER_BASE + 0x1C)
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#define BCM2711_TIMER_CNT (BCM2711_TIMER_BASE + 0x20)
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#define BCM2711_TIMER_PRESCALE 0xF9
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#define BCM2711_PM_PASSWD_MAGIC 0x5a000000
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#define BCM2711_PM_BASE (RPI_PERIPHERAL_BASE + 0x100000)
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#define BCM2711_PM_GNRIC (BCM2711_PM_BASE + 0x00)
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#define BCM2711_PM_GNRIC_POWUP 0x00000001
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#define BCM2711_PM_GNRIC_POWOK 0x00000002
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#define BCM2711_PM_GNRIC_ISPOW 0x00000004
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#define BCM2711_PM_GNRIC_MEMREP 0x00000008
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#define BCM2711_PM_GNRIC_MRDONE 0x00000010
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#define BCM2711_PM_GNRIC_ISFUNC 0x00000020
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#define BCM2711_PM_GNRIC_RSTN 0x00000fc0
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#define BCM2711_PM_GNRIC_ENAB 0x00001000
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#define BCM2711_PM_GNRIC_CFG 0x007f0000
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#define BCM2711_PM_AUDIO (BCM2711_PM_BASE + 0x04)
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#define BCM2711_PM_AUDIO_APSM 0x000fffff
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#define BCM2711_PM_AUDIO_CTRLEN 0x00100000
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#define BCM2711_PM_AUDIO_RSTN 0x00200000
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#define BCM2711_PM_STATUS (BCM2711_PM_BASE + 0x18)
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#define BCM2711_PM_RSTC (BCM2711_PM_BASE + 0x1c)
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#define BCM2711_PM_RSTC_DRCFG 0x00000003
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#define BCM2711_PM_RSTC_WRCFG 0x00000030
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#define BCM2711_PM_RSTC_WRCFG_FULL 0x00000020
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#define BCM2711_PM_RSTC_WRCFG_CLR 0xffffffcf
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#define BCM2711_PM_RSTC_SRCFG 0x00000300
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#define BCM2711_PM_RSTC_QRCFG 0x00003000
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#define BCM2711_PM_RSTC_FRCFG 0x00030000
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#define BCM2711_PM_RSTC_HRCFG 0x00300000
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#define BCM2711_PM_RSTC_RESET 0x00000102
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#define BCM2711_PM_RSTS (BCM2711_PM_BASE + 0x20)
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#define BCM2711_PM_RSTS_HADDRQ 0x00000001
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#define BCM2711_PM_RSTS_HADDRF 0x00000002
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#define BCM2711_PM_RSTS_HADDRH 0x00000004
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#define BCM2711_PM_RSTS_HADWRQ 0x00000010
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#define BCM2711_PM_RSTS_HADWRF 0x0000002
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#define BCM2711_PM_RSTS_HADWRH 0x00000040
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#define BCM2711_PM_RSTS_HADSRQ 0x00000100
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#define BCM2711_PM_RSTS_HADSRF 0x00000200
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#define BCM2711_PM_RSTS_HADSRH 0x00000400
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#define BCM2711_PM_RSTS_HADPOR 0x00001000
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#define BCM2711_PM_WDOG (BCM2711_PM_BASE + 0x24)
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#define BCM2711_PM_WDOG_MASK 0x000fffff
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#define BCM2711_AUX_BASE (RPI_PERIPHERAL_BASE + 0x215000)
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#define AUX_ENABLES (BCM2711_AUX_BASE + 0x04)
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#define AUX_MU_IO_REG (BCM2711_AUX_BASE + 0x40)
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#define AUX_MU_IER_REG (BCM2711_AUX_BASE + 0x44)
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#define AUX_MU_IIR_REG (BCM2711_AUX_BASE + 0x48)
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#define AUX_MU_LCR_REG (BCM2711_AUX_BASE + 0x4C)
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#define AUX_MU_MCR_REG (BCM2711_AUX_BASE + 0x50)
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#define AUX_MU_LSR_REG (BCM2711_AUX_BASE + 0x54)
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#define AUX_MU_MSR_REG (BCM2711_AUX_BASE + 0x58)
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#define AUX_MU_SCRATCH (BCM2711_AUX_BASE + 0x5C)
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#define AUX_MU_CNTL_REG (BCM2711_AUX_BASE + 0x60)
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#define AUX_MU_STAT_REG (BCM2711_AUX_BASE + 0x64)
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#define AUX_MU_BAUD_REG (BCM2711_AUX_BASE + 0x68)
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#define BCM2711_PL011_BASE (RPI_PERIPHERAL_BASE + 0x201000)
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#define BCM2711_PL011_SIZE 0xc00
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#define BCM2711_PL011_DEVICE_SIZE 0x200
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#define BCM2711_UART0_BASE (BCM2711_PL011_BASE + 0x000)
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#define BCM2711_UART0_SIZE BCM2711_PL011_DEVICE_SIZE
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#define BCM2711_UART2_BASE (BCM2711_PL011_BASE + 0x400)
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#define BCM2711_UART2_SIZE BCM2711_PL011_DEVICE_SIZE
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#define BCM2711_UART3_BASE (BCM2711_PL011_BASE + 0x600)
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#define BCM2711_UART3_SIZE BCM2711_PL011_DEVICE_SIZE
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#define BCM2711_UART4_BASE (BCM2711_PL011_BASE + 0x800)
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#define BCM2711_UART4_SIZE BCM2711_PL011_DEVICE_SIZE
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#define BCM2711_UART5_BASE (BCM2711_PL011_BASE + 0xa00)
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#define BCM2711_UART5_SIZE BCM2711_PL011_DEVICE_SIZE
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#define BCM2711_GPU_TIMER_BASE (RPI_PERIPHERAL_BASE + 0x3000)
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#define BCM2711_GPU_TIMER_CS (BCM2711_GPU_TIMER_BASE + 0x00)
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#define BCM2711_GPU_TIMER_CS_M0 0x00000001
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#define BCM2711_GPU_TIMER_CS_M1 0x00000002
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#define BCM2711_GPU_TIMER_CS_M2 0x00000004
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#define BCM2711_GPU_TIMER_CS_M3 0x00000008
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#define BCM2711_GPU_TIMER_CLO (BCM2711_GPU_TIMER_BASE + 0x04)
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#define BCM2711_GPU_TIMER_CHI (BCM2711_GPU_TIMER_BASE + 0x08)
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#define BCM2711_GPU_TIMER_C0 (BCM2711_GPU_TIMER_BASE + 0x0C)
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#define BCM2711_GPU_TIMER_C1 (BCM2711_GPU_TIMER_BASE + 0x10)
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#define BCM2711_GPU_TIMER_C2 (BCM2711_GPU_TIMER_BASE + 0x14)
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#define BCM2711_GPU_TIMER_C3 (BCM2711_GPU_TIMER_BASE + 0x18)
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#define BCM2835_GPU_TIMER_CS_M3 BCM2711_GPU_TIMER_CS_M3
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#define BCM2835_GPU_TIMER_C3 BCM2711_GPU_TIMER_C3
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#define BCM2835_GPU_TIMER_CLO BCM2711_GPU_TIMER_CLO
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#define BCM2835_GPU_TIMER_CS BCM2711_GPU_TIMER_CS
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#define BCM2711_GPIO_BASE (RPI_PERIPHERAL_BASE + 0x200000)
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#define BCM2711_GPIO_SIZE 0xf4
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#define BCM2711_GPIO_PIN_COUNT 58
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#define BCM2711_EMMC_BASE (RPI_PERIPHERAL_BASE + 0x300000)
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#define BCM2711_SPI0_BASE (RPI_PERIPHERAL_BASE + 0x204000)
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#define BCM2711_SPI3_BASE (RPI_PERIPHERAL_BASE + 0x204600)
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#define BCM2711_SPI4_BASE (RPI_PERIPHERAL_BASE + 0x204800)
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#define BCM2711_SPI5_BASE (RPI_PERIPHERAL_BASE + 0x204A00)
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#define BCM2711_SPI6_BASE (RPI_PERIPHERAL_BASE + 0x204C00)
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#define BCM2711_MBOX_BASE (RPI_PERIPHERAL_BASE+0xB880)
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#define BCM2711_MBOX_READ (BCM2711_MBOX_BASE+0x00)
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#define BCM2711_MBOX_PEEK (BCM2711_MBOX_BASE+0x10)
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#define BCM2711_MBOX_SENDER (BCM2711_MBOX_BASE+0x14)
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#define BCM2711_MBOX_STATUS (BCM2711_MBOX_BASE+0x18)
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#define BCM2711_MBOX_WRITE (BCM2711_MBOX_BASE+0x20)
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#define BCM2711_MBOX_CONFIG (BCM2711_MBOX_BASE+0x1C)
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#define BCM2711_MBOX_RESPONSE 0x80000000
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#define BCM2711_MBOX_FULL 0x80000000
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#define BCM2711_MBOX_EMPTY 0x40000000
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/* Power Manager channel */
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#define BCM2711_MBOX_CHANNEL_PM 0
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/* Framebuffer channel */
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#define BCM2711_MBOX_CHANNEL_FB 1
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/* Virtual UART channel */
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#define BCM2711_MBOX_CHANNEL_VUART 2
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/* VCHIQ channel */
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#define BCM2711_MBOX_CHANNEL_VCHIQ 3
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/* LEDs channel */
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#define BCM2711_MBOX_CHANNEL_LED 4
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/* Button channel */
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#define BCM2711_MBOX_CHANNEL_BUTTON 5
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/* Touch screen channel */
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#define BCM2711_MBOX_CHANNEL_TOUCHS 6
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#define BCM2711_MBOX_CHANNEL_COUNT 7
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/* Property tags (ARM <-> VC) channel */
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#define BCM2711_MBOX_CHANNEL_PROP_AVC 8
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/* Property tags (VC <-> ARM) channel */
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#define BCM2711_MBOX_CHANNEL_PROP_VCA 9
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/* Timers interrupt control registers */
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#define BCM2711_CORE0_TIMER_IRQ_CTRL_BASE 0xFF800040
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#define BCM2711_CORE1_TIMER_IRQ_CTRL_BASE 0xFF800044
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#define BCM2711_CORE2_TIMER_IRQ_CTRL_BASE 0xFF800048
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#define BCM2711_CORE3_TIMER_IRQ_CTRL_BASE 0xFF80004C
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#define BCM2711_CORE_TIMER_IRQ_CTRL(cpuidx) \
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(BCM2711_CORE0_TIMER_IRQ_CTRL_BASE + 0x4 * (cpuidx))
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#define BCM2711_LOCAL_REGS_BASE 0x4C0000000
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#define BCM2711_LOCAL_REGS_SIZE 0x100
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#define BCM2711_LOCAL_ARM_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x00)
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#define BCM2711_LOCAL_CORE_IRQ_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x0c)
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#define BCM2711_LOCAL_PMU_CONTROL_SET (BCM2711_LOCAL_REGS_BASE + 0x10)
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#define BCM2711_LOCAL_PMU_CONTROL_CLR (BCM2711_LOCAL_REGS_BASE + 0x14)
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#define BCM2711_LOCAL_PERI_IRQ_ROUTE0 (BCM2711_LOCAL_REGS_BASE + 0x24)
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#define BCM2711_LOCAL_AXI_QUIET_TIME (BCM2711_LOCAL_REGS_BASE + 0x30)
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#define BCM2711_LOCAL_LOCAL_TIMER_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x34)
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#define BCM2711_LOCAL_LOCAL_TIMER_IRQ (BCM2711_LOCAL_REGS_BASE + 0x38)
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#define BCM2711_LOCAL_TIMER_CNTRL0 (BCM2711_LOCAL_REGS_BASE + 0x40)
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#define BCM2711_LOCAL_TIMER_CNTRL1 (BCM2711_LOCAL_REGS_BASE + 0x44)
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#define BCM2711_LOCAL_TIMER_CNTRL2 (BCM2711_LOCAL_REGS_BASE + 0x48)
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#define BCM2711_LOCAL_TIMER_CNTRL3 (BCM2711_LOCAL_REGS_BASE + 0x4c)
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#define BCM2711_LOCAL_MAILBOX_CNTRL0 (BCM2711_LOCAL_REGS_BASE + 0x50)
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#define BCM2711_LOCAL_MAILBOX_CNTRL1 (BCM2711_LOCAL_REGS_BASE + 0x54)
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#define BCM2711_LOCAL_MAILBOX_CNTRL2 (BCM2711_LOCAL_REGS_BASE + 0x58)
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#define BCM2711_LOCAL_MAILBOX_CNTRL3 (BCM2711_LOCAL_REGS_BASE + 0x5c)
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#define BCM2711_LOCAL_IRQ_SOURCE0 (BCM2711_LOCAL_REGS_BASE + 0x60)
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#define BCM2711_LOCAL_IRQ_SOURCE1 (BCM2711_LOCAL_REGS_BASE + 0x64)
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#define BCM2711_LOCAL_IRQ_SOURCE2 (BCM2711_LOCAL_REGS_BASE + 0x68)
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#define BCM2711_LOCAL_IRQ_SOURCE3 (BCM2711_LOCAL_REGS_BASE + 0x6c)
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#define BCM2711_LOCAL_FIQ_SOURCE0 (BCM2711_LOCAL_REGS_BASE + 0x70)
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#define BCM2711_LOCAL_FIQ_SOURCE1 (BCM2711_LOCAL_REGS_BASE + 0x74)
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#define BCM2711_LOCAL_FIQ_SOURCE2 (BCM2711_LOCAL_REGS_BASE + 0x78)
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#define BCM2711_LOCAL_FIQ_SOURCE3 (BCM2711_LOCAL_REGS_BASE + 0x7c)
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#define BCM2711_MAILBOX_00_WRITE_SET_BASE 0x4C000080
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#define BCM2711_MAILBOX_01_WRITE_SET_BASE 0x4C000084
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#define BCM2711_MAILBOX_02_WRITE_SET_BASE 0x4C000088
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#define BCM2711_MAILBOX_03_WRITE_SET_BASE 0x4C00008C
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#define BCM2711_MAILBOX_04_WRITE_SET_BASE 0x4C000090
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#define BCM2711_MAILBOX_05_WRITE_SET_BASE 0x4C000094
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#define BCM2711_MAILBOX_06_WRITE_SET_BASE 0x4C000098
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#define BCM2711_MAILBOX_07_WRITE_SET_BASE 0x4C00009C
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#define BCM2711_MAILBOX_08_WRITE_SET_BASE 0x4C0000A0
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#define BCM2711_MAILBOX_09_WRITE_SET_BASE 0x4C0000A4
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#define BCM2711_MAILBOX_10_WRITE_SET_BASE 0x4C0000A8
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#define BCM2711_MAILBOX_11_WRITE_SET_BASE 0x4C0000AC
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#define BCM2711_MAILBOX_12_WRITE_SET_BASE 0x4C0000B0
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#define BCM2711_MAILBOX_13_WRITE_SET_BASE 0x4C0000B4
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#define BCM2711_MAILBOX_14_WRITE_SET_BASE 0x4C0000B8
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#define BCM2711_MAILBOX_15_WRITE_SET_BASE 0x4C0000BC
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#define BCM2711_MAILBOX_00_READ_CLEAR_BASE 0x4C0000C0
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#define BCM2711_MAILBOX_01_READ_CLEAR_BASE 0x4C0000C4
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#define BCM2711_MAILBOX_02_READ_CLEAR_BASE 0x4C0000C8
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#define BCM2711_MAILBOX_03_READ_CLEAR_BASE 0x4C0000CC
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#define BCM2711_MAILBOX_04_READ_CLEAR_BASE 0x4C0000D0
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#define BCM2711_MAILBOX_05_READ_CLEAR_BASE 0x4C0000D4
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#define BCM2711_MAILBOX_06_READ_CLEAR_BASE 0x4C0000D8
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#define BCM2711_MAILBOX_07_READ_CLEAR_BASE 0x4C0000DC
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#define BCM2711_MAILBOX_08_READ_CLEAR_BASE 0x4C0000E0
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#define BCM2711_MAILBOX_09_READ_CLEAR_BASE 0x4C0000E4
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#define BCM2711_MAILBOX_10_READ_CLEAR_BASE 0x4C0000E8
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#define BCM2711_MAILBOX_11_READ_CLEAR_BASE 0x4C0000EC
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#define BCM2711_MAILBOX_12_READ_CLEAR_BASE 0x4C0000F0
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#define BCM2711_MAILBOX_13_READ_CLEAR_BASE 0x4C0000F4
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#define BCM2711_MAILBOX_14_READ_CLEAR_BASE 0x4C0000F8
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#define BCM2711_MAILBOX_15_READ_CLEAR_BASE 0x4C0000FC
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#define BCM2711_ARMC_REGS_BASE (RPI_PERIPHERAL_BASE + 0xB200)
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#define BCM2711_ARMC_REGS_SIZE 0x200
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#define BCM2711_ARMC_IRQ0_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x00)
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#define BCM2711_ARMC_IRQ0_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x04)
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#define BCM2711_ARMC_IRQ0_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x08)
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#define BCM2711_ARMC_IRQ0_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x10)
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#define BCM2711_ARMC_IRQ0_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x14)
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#define BCM2711_ARMC_IRQ0_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x18)
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#define BCM2711_ARMC_IRQ0_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x20)
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#define BCM2711_ARMC_IRQ0_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x24)
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#define BCM2711_ARMC_IRQ0_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x28)
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#define BCM2711_ARMC_IRQ_STATUS0 (BCM2711_ARMC_REGS_BASE + 0x30)
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#define BCM2711_ARMC_IRQ_STATUS1 (BCM2711_ARMC_REGS_BASE + 0x34)
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#define BCM2711_ARMC_IRQ_STATUS2 (BCM2711_ARMC_REGS_BASE + 0x38)
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#define BCM2711_ARMC_IRQ1_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x40)
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#define BCM2711_ARMC_IRQ1_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x44)
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#define BCM2711_ARMC_IRQ1_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x48)
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#define BCM2711_ARMC_IRQ1_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x50)
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#define BCM2711_ARMC_IRQ1_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x54)
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#define BCM2711_ARMC_IRQ1_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x58)
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#define BCM2711_ARMC_IRQ1_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x60)
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#define BCM2711_ARMC_IRQ1_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x64)
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#define BCM2711_ARMC_IRQ1_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x68)
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#define BCM2711_ARMC_IRQ2_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x80)
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#define BCM2711_ARMC_IRQ2_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x84)
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#define BCM2711_ARMC_IRQ2_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x88)
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#define BCM2711_ARMC_IRQ2_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x90)
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#define BCM2711_ARMC_IRQ2_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x94)
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#define BCM2711_ARMC_IRQ2_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x98)
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#define BCM2711_ARMC_IRQ2_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0xA0)
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#define BCM2711_ARMC_IRQ2_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0xA4)
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#define BCM2711_ARMC_IRQ2_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0xA8)
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#define BCM2711_ARMC_IRQ3_PENDING0 (BCM2711_ARMC_REGS_BASE + 0xC0)
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#define BCM2711_ARMC_IRQ3_PENDING1 (BCM2711_ARMC_REGS_BASE + 0xC4)
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#define BCM2711_ARMC_IRQ3_PENDING2 (BCM2711_ARMC_REGS_BASE + 0xC8)
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#define BCM2711_ARMC_IRQ3_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0xD0)
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#define BCM2711_ARMC_IRQ3_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0xD4)
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#define BCM2711_ARMC_IRQ3_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0xD8)
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#define BCM2711_ARMC_IRQ3_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0xE0)
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#define BCM2711_ARMC_IRQ3_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0xE4)
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#define BCM2711_ARMC_IRQ3_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0xE8)
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#define BCM2711_ARMC_FIQ0_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x100)
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#define BCM2711_ARMC_FIQ0_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x104)
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#define BCM2711_ARMC_FIQ0_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x108)
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#define BCM2711_ARMC_FIQ0_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x110)
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#define BCM2711_ARMC_FIQ0_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x114)
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#define BCM2711_ARMC_FIQ0_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x118)
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#define BCM2711_ARMC_FIQ0_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x120)
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#define BCM2711_ARMC_FIQ0_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x124)
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#define BCM2711_ARMC_FIQ0_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x128)
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#define BCM2711_ARMC_FIQ1_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x140)
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#define BCM2711_ARMC_FIQ1_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x144)
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#define BCM2711_ARMC_FIQ1_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x148)
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#define BCM2711_ARMC_FIQ1_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x150)
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#define BCM2711_ARMC_FIQ1_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x154)
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#define BCM2711_ARMC_FIQ1_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x158)
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#define BCM2711_ARMC_FIQ1_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x160)
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#define BCM2711_ARMC_FIQ1_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x164)
496
#define BCM2711_ARMC_FIQ1_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x168)
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#define BCM2711_ARMC_FIQ2_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x180)
499
#define BCM2711_ARMC_FIQ2_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x184)
500
#define BCM2711_ARMC_FIQ2_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x188)
501
#define BCM2711_ARMC_FIQ2_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x190)
502
#define BCM2711_ARMC_FIQ2_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x194)
503
#define BCM2711_ARMC_FIQ2_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x198)
504
#define BCM2711_ARMC_FIQ2_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1A0)
505
#define BCM2711_ARMC_FIQ2_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1A4)
506
#define BCM2711_ARMC_FIQ2_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1A8)
507
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#define BCM2711_ARMC_FIQ3_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x1C0)
509
#define BCM2711_ARMC_FIQ3_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x1C4)
510
#define BCM2711_ARMC_FIQ3_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x1C8)
511
#define BCM2711_ARMC_FIQ3_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1D0)
512
#define BCM2711_ARMC_FIQ3_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1D4)
513
#define BCM2711_ARMC_FIQ3_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1D8)
514
#define BCM2711_ARMC_FIQ3_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1E0)
515
#define BCM2711_ARMC_FIQ3_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1E4)
516
#define BCM2711_ARMC_FIQ3_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1E8)
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518
#define BCM2711_ARMC_SWIRQ_SET (BCM2711_ARMC_REGS_BASE + 0x1F0)
519
#define BCM2711_ARMC_SWIRQ_CLEAR (BCM2711_ARMC_REGS_BASE + 0x1F4)
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#endif
/* LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H */
utility.h
This header file provides utility macros for BSPs.
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