RTEMS 6.1-rc7
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Data Fields

HW Semaphore HSEM. More...

#include <stm32h723xx.h>

Data Fields

__IO uint32_t R [32]
 
__IO uint32_t RLR [32]
 
__IO uint32_t C1IER
 
__IO uint32_t C1ICR
 
__IO uint32_t C1ISR
 
__IO uint32_t C1MISR
 
uint32_t Reserved [12]
 
__IO uint32_t CR
 
__IO uint32_t KEYR
 
__IO uint32_t C2IER
 
__IO uint32_t C2ICR
 
__IO uint32_t C2ISR
 
__IO uint32_t C2MISR
 

Detailed Description

HW Semaphore HSEM.

Field Documentation

◆ C1ICR

__IO uint32_t HSEM_TypeDef::C1ICR

HSEM Interrupt clear register , Address offset: 104h

HSEM Interrupt 0 clear register , Address offset: 104h

◆ C1IER

__IO uint32_t HSEM_TypeDef::C1IER

HSEM Interrupt enable register , Address offset: 100h

HSEM Interrupt 0 enable register , Address offset: 100h

◆ C1ISR

__IO uint32_t HSEM_TypeDef::C1ISR

HSEM Interrupt Status register , Address offset: 108h

HSEM Interrupt 0 Status register , Address offset: 108h

◆ C1MISR

__IO uint32_t HSEM_TypeDef::C1MISR

HSEM Interrupt Masked Status register , Address offset: 10Ch

HSEM Interrupt 0 Masked Status register , Address offset: 10Ch

◆ C2ICR

__IO uint32_t HSEM_TypeDef::C2ICR

HSEM Interrupt 1 clear register , Address offset: 114h

◆ C2IER

__IO uint32_t HSEM_TypeDef::C2IER

HSEM Interrupt 1 enable register , Address offset: 110h

◆ C2ISR

__IO uint32_t HSEM_TypeDef::C2ISR

HSEM Interrupt 1 Status register , Address offset: 118h

◆ C2MISR

__IO uint32_t HSEM_TypeDef::C2MISR

HSEM Interrupt 1 Masked Status register , Address offset: 11Ch

◆ CR

__IO uint32_t HSEM_TypeDef::CR

HSEM Semaphore clear register , Address offset: 140h

◆ KEYR

__IO uint32_t HSEM_TypeDef::KEYR

HSEM Semaphore clear key register , Address offset: 144h

◆ R

__IO uint32_t HSEM_TypeDef::R

2-step write lock and read back registers, Address offset: 00h-7Ch

◆ RLR

__IO uint32_t HSEM_TypeDef::RLR

1-step read lock registers, Address offset: 80h-FCh


The documentation for this struct was generated from the following files: