RTEMS 6.1-rc7
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cpu.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
9/*
10 * Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
11 * Joel Sherrill <joel@OARcorp.com>.
12 *
13 * These changes made the code conditional on standard cpp predefines,
14 * merged the mips1 and mips3 code sequences as much as possible,
15 * and moved some of the assembly code to C. Alan did much of the
16 * initial analysis and rework. Joel took over from there and
17 * wrote the JMR3904 BSP so this could be tested. Joel also
18 * added the new interrupt vectoring support in libcpu and
19 * tried to better support the various interrupt controllers.
20 *
21 */
22
23/*
24 * Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
25 * COPYRIGHT (c) 1996 by Transition Networks Inc.
26 *
27 * To anyone who acknowledges that this file is provided "AS IS"
28 * without any express or implied warranty:
29 * permission to use, copy, modify, and distribute this file
30 * for any purpose is hereby granted without fee, provided that
31 * the above copyright notice and this notice appears in all
32 * copies, and that the name of Transition Networks not be used in
33 * advertising or publicity pertaining to distribution of the
34 * software without specific, written prior permission.
35 * Transition Networks makes no representations about the suitability
36 * of this software for any purpose.
37 *
38 * COPYRIGHT (c) 1989-2012.
39 * On-Line Applications Research Corporation (OAR).
40 *
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
43 * are met:
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
51 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
53 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
54 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
60 * POSSIBILITY OF SUCH DAMAGE.
61 */
62
63#ifndef _RTEMS_SCORE_CPU_H
64#define _RTEMS_SCORE_CPU_H
65
71#ifdef __cplusplus
72extern "C" {
73#endif
74
76#include <rtems/score/mips.h>
77
78/* conditional compilation parameters */
79
80/*
81 * Does the CPU follow the simple vectored interrupt model?
82 *
83 * If TRUE, then RTEMS allocates the vector table it internally manages.
84 * If FALSE, then the BSP is assumed to allocate and manage the vector
85 * table
86 *
87 * MIPS Specific Information:
88 *
89 * Up to and including RTEMS 4.10, the MIPS port used simple vectored
90 * interrupts. But this was changed to the PIC model after 4.10.
91 */
92#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
93
94/*
95 * Does the RTEMS invoke the user's ISR with the vector number and
96 * a pointer to the saved interrupt frame (1) or just the vector
97 * number (0)?
98 *
99 */
100
101#define CPU_ISR_PASSES_FRAME_POINTER TRUE
102
103
104
105/*
106 * Does the CPU have hardware floating point?
107 *
108 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
109 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
110 *
111 * If there is a FP coprocessor such as the i387 or mc68881, then
112 * the answer is TRUE.
113 *
114 * The macro name "MIPS_HAS_FPU" should be made CPU specific.
115 * It indicates whether or not this CPU model has FP support. For
116 * example, it would be possible to have an i386_nofp CPU model
117 * which set this to false to indicate that you have an i386 without
118 * an i387 and wish to leave floating point support out of RTEMS.
119 */
120
121#if ( MIPS_HAS_FPU == 1 )
122#define CPU_HARDWARE_FP TRUE
123#else
124#define CPU_HARDWARE_FP FALSE
125#endif
126
127/*
128 * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
129 *
130 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
131 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
132 *
133 * So far, the only CPU in which this option has been used is the
134 * HP PA-RISC. The HP C compiler and gcc both implicitly use the
135 * floating point registers to perform integer multiplies. If
136 * a function which you would not think utilize the FP unit DOES,
137 * then one can not easily predict which tasks will use the FP hardware.
138 * In this case, this option should be TRUE.
139 *
140 * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
141 *
142 * Mips Note: It appears the GCC can implicitly generate FPU
143 * and Altivec instructions when you least expect them. So make
144 * all tasks floating point.
145 */
146
147#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP
148
149/*
150 * Should the IDLE task have a floating point context?
151 *
152 * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
153 * and it has a floating point context which is switched in and out.
154 * If FALSE, then the IDLE task does not have a floating point context.
155 *
156 * Setting this to TRUE negatively impacts the time required to preempt
157 * the IDLE task from an interrupt because the floating point context
158 * must be saved as part of the preemption.
159 */
160
161#define CPU_IDLE_TASK_IS_FP FALSE
162
163/*
164 * Should the saving of the floating point registers be deferred
165 * until a context switch is made to another different floating point
166 * task?
167 *
168 * If TRUE, then the floating point context will not be stored until
169 * necessary. It will remain in the floating point registers and not
170 * disturned until another floating point task is switched to.
171 *
172 * If FALSE, then the floating point context is saved when a floating
173 * point task is switched out and restored when the next floating point
174 * task is restored. The state of the floating point registers between
175 * those two operations is not specified.
176 *
177 * If the floating point context does NOT have to be saved as part of
178 * interrupt dispatching, then it should be safe to set this to TRUE.
179 *
180 * Setting this flag to TRUE results in using a different algorithm
181 * for deciding when to save and restore the floating point context.
182 * The deferred FP switch algorithm minimizes the number of times
183 * the FP context is saved and restored. The FP context is not saved
184 * until a context switch is made to another, different FP task.
185 * Thus in a system with only one FP task, the FP context will never
186 * be saved or restored.
187 */
188
189#define CPU_USE_DEFERRED_FP_SWITCH TRUE
190
191#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
192
193/*
194 * Does the stack grow up (toward higher addresses) or down
195 * (toward lower addresses)?
196 *
197 * If TRUE, then the grows upward.
198 * If FALSE, then the grows toward smaller addresses.
199 */
200
201/* our stack grows down */
202#define CPU_STACK_GROWS_UP FALSE
203
204/* FIXME: Is this the right value? */
205#define CPU_CACHE_LINE_BYTES 16
206
207#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
208
209/*
210 * The following defines the number of bits actually used in the
211 * interrupt field of the task mode. How those bits map to the
212 * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
213 */
214
215#define CPU_MODES_INTERRUPT_MASK 0x000000ff
216
217#define CPU_SIZEOF_POINTER 4
218
219#define CPU_MAXIMUM_PROCESSORS 32
220
221/*
222 * Processor defined structures
223 *
224 * Examples structures include the descriptor tables from the i386
225 * and the processor control structure on the i960ca.
226 */
227
228/* may need to put some structures here. */
229
230/*
231 * Contexts
232 *
233 * Generally there are 2 types of context to save.
234 * 1. Interrupt registers to save
235 * 2. Task level registers to save
236 *
237 * This means we have the following 3 context items:
238 * 1. task level context stuff:: Context_Control
239 * 2. floating point task stuff:: Context_Control_fp
240 * 3. special interrupt level context :: Context_Control_interrupt
241 *
242 * On some processors, it is cost-effective to save only the callee
243 * preserved registers during a task context switch. This means
244 * that the ISR code needs to save those registers which do not
245 * persist across function calls. It is not mandatory to make this
246 * distinctions between the caller/callee saves registers for the
247 * purpose of minimizing context saved during task switch and on interrupts.
248 * If the cost of saving extra registers is minimal, simplicity is the
249 * choice. Save the same context on interrupt entry as for tasks in
250 * this case.
251 *
252 * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
253 * care should be used in designing the context area.
254 *
255 * On some CPUs with hardware floating point support, the Context_Control_fp
256 * structure will not be used or it simply consist of an array of a
257 * fixed number of bytes. This is done when the floating point context
258 * is dumped by a "FP save context" type instruction and the format
259 * is not really defined by the CPU. In this case, there is no need
260 * to figure out the exact format -- only the size. Of course, although
261 * this is enough information for RTEMS, it is probably not enough for
262 * a debugger such as gdb. But that is another problem.
263 */
264
265#ifndef ASM
266
267/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
268#if (__mips == 1) || (__mips == 32)
269#define __MIPS_REGISTER_TYPE uint32_t
270#define __MIPS_FPU_REGISTER_TYPE uint32_t
271#elif __mips == 3
272#define __MIPS_REGISTER_TYPE uint64_t
273#define __MIPS_FPU_REGISTER_TYPE uint64_t
274#else
275#error "mips register size: unknown architecture level!!"
276#endif
277typedef struct {
278 __MIPS_REGISTER_TYPE s0;
279 __MIPS_REGISTER_TYPE s1;
280 __MIPS_REGISTER_TYPE s2;
281 __MIPS_REGISTER_TYPE s3;
282 __MIPS_REGISTER_TYPE s4;
283 __MIPS_REGISTER_TYPE s5;
284 __MIPS_REGISTER_TYPE s6;
285 __MIPS_REGISTER_TYPE s7;
286 __MIPS_REGISTER_TYPE sp;
287 __MIPS_REGISTER_TYPE fp;
288 __MIPS_REGISTER_TYPE ra;
289 __MIPS_REGISTER_TYPE c0_sr;
290 __MIPS_REGISTER_TYPE c0_epc;
292
293#define _CPU_Context_Get_SP( _context ) \
294 (uintptr_t) (_context)->sp
295
296/* WARNING: If this structure is modified, the constants in cpu.h
297 * must also be updated.
298 */
299
300typedef struct {
301#if ( CPU_HARDWARE_FP == TRUE )
302 __MIPS_FPU_REGISTER_TYPE fp0;
303 __MIPS_FPU_REGISTER_TYPE fp1;
304 __MIPS_FPU_REGISTER_TYPE fp2;
305 __MIPS_FPU_REGISTER_TYPE fp3;
306 __MIPS_FPU_REGISTER_TYPE fp4;
307 __MIPS_FPU_REGISTER_TYPE fp5;
308 __MIPS_FPU_REGISTER_TYPE fp6;
309 __MIPS_FPU_REGISTER_TYPE fp7;
310 __MIPS_FPU_REGISTER_TYPE fp8;
311 __MIPS_FPU_REGISTER_TYPE fp9;
312 __MIPS_FPU_REGISTER_TYPE fp10;
313 __MIPS_FPU_REGISTER_TYPE fp11;
314 __MIPS_FPU_REGISTER_TYPE fp12;
315 __MIPS_FPU_REGISTER_TYPE fp13;
316 __MIPS_FPU_REGISTER_TYPE fp14;
317 __MIPS_FPU_REGISTER_TYPE fp15;
318 __MIPS_FPU_REGISTER_TYPE fp16;
319 __MIPS_FPU_REGISTER_TYPE fp17;
320 __MIPS_FPU_REGISTER_TYPE fp18;
321 __MIPS_FPU_REGISTER_TYPE fp19;
322 __MIPS_FPU_REGISTER_TYPE fp20;
323 __MIPS_FPU_REGISTER_TYPE fp21;
324 __MIPS_FPU_REGISTER_TYPE fp22;
325 __MIPS_FPU_REGISTER_TYPE fp23;
326 __MIPS_FPU_REGISTER_TYPE fp24;
327 __MIPS_FPU_REGISTER_TYPE fp25;
328 __MIPS_FPU_REGISTER_TYPE fp26;
329 __MIPS_FPU_REGISTER_TYPE fp27;
330 __MIPS_FPU_REGISTER_TYPE fp28;
331 __MIPS_FPU_REGISTER_TYPE fp29;
332 __MIPS_FPU_REGISTER_TYPE fp30;
333 __MIPS_FPU_REGISTER_TYPE fp31;
334 uint32_t fpcs;
335#endif
337
338/*
339 * This struct reflects the stack frame employed in ISR_Handler. Note
340 * that the ISR routine save some of the registers to this frame for
341 * all interrupts and exceptions. Other registers are saved only on
342 * exceptions, while others are not touched at all. The untouched
343 * registers are not normally disturbed by high-level language
344 * programs so they can be accessed when required.
345 *
346 * The registers and their ordering in this struct must directly
347 * correspond to the layout and ordering of * shown in iregdef.h,
348 * as cpu_asm.S uses those definitions to fill the stack frame.
349 * This struct provides access to the stack frame for C code.
350 *
351 * Similarly, this structure is used by debugger stubs and exception
352 * processing routines so be careful when changing the format.
353 *
354 * NOTE: The comments with this structure and cpu_asm.S should be kept
355 * in sync. When in doubt, look in the code to see if the
356 * registers you're interested in are actually treated as expected.
357 * The order of the first portion of this structure follows the
358 * order of registers expected by gdb.
359 */
360
361typedef struct
362{
363 __MIPS_REGISTER_TYPE r0; /* 0 -- NOT FILLED IN */
364 __MIPS_REGISTER_TYPE at; /* 1 -- saved always */
365 __MIPS_REGISTER_TYPE v0; /* 2 -- saved always */
366 __MIPS_REGISTER_TYPE v1; /* 3 -- saved always */
367 __MIPS_REGISTER_TYPE a0; /* 4 -- saved always */
368 __MIPS_REGISTER_TYPE a1; /* 5 -- saved always */
369 __MIPS_REGISTER_TYPE a2; /* 6 -- saved always */
370 __MIPS_REGISTER_TYPE a3; /* 7 -- saved always */
371 __MIPS_REGISTER_TYPE t0; /* 8 -- saved always */
372 __MIPS_REGISTER_TYPE t1; /* 9 -- saved always */
373 __MIPS_REGISTER_TYPE t2; /* 10 -- saved always */
374 __MIPS_REGISTER_TYPE t3; /* 11 -- saved always */
375 __MIPS_REGISTER_TYPE t4; /* 12 -- saved always */
376 __MIPS_REGISTER_TYPE t5; /* 13 -- saved always */
377 __MIPS_REGISTER_TYPE t6; /* 14 -- saved always */
378 __MIPS_REGISTER_TYPE t7; /* 15 -- saved always */
379 __MIPS_REGISTER_TYPE s0; /* 16 -- saved on exceptions */
380 __MIPS_REGISTER_TYPE s1; /* 17 -- saved on exceptions */
381 __MIPS_REGISTER_TYPE s2; /* 18 -- saved on exceptions */
382 __MIPS_REGISTER_TYPE s3; /* 19 -- saved on exceptions */
383 __MIPS_REGISTER_TYPE s4; /* 20 -- saved on exceptions */
384 __MIPS_REGISTER_TYPE s5; /* 21 -- saved on exceptions */
385 __MIPS_REGISTER_TYPE s6; /* 22 -- saved on exceptions */
386 __MIPS_REGISTER_TYPE s7; /* 23 -- saved on exceptions */
387 __MIPS_REGISTER_TYPE t8; /* 24 -- saved always */
388 __MIPS_REGISTER_TYPE t9; /* 25 -- saved always */
389 __MIPS_REGISTER_TYPE k0; /* 26 -- NOT FILLED IN, kernel tmp reg */
390 __MIPS_REGISTER_TYPE k1; /* 27 -- NOT FILLED IN, kernel tmp reg */
391 __MIPS_REGISTER_TYPE gp; /* 28 -- saved always */
392 __MIPS_REGISTER_TYPE sp; /* 29 -- saved on exceptions NOT RESTORED */
393 __MIPS_REGISTER_TYPE fp; /* 30 -- saved always */
394 __MIPS_REGISTER_TYPE ra; /* 31 -- saved always */
395 __MIPS_REGISTER_TYPE c0_sr; /* 32 -- saved always, some bits are */
396 /* manipulated per-thread */
397 __MIPS_REGISTER_TYPE mdlo; /* 33 -- saved always */
398 __MIPS_REGISTER_TYPE mdhi; /* 34 -- saved always */
399 __MIPS_REGISTER_TYPE badvaddr; /* 35 -- saved on exceptions, read-only */
400 __MIPS_REGISTER_TYPE cause; /* 36 -- saved on exceptions NOT restored */
401 __MIPS_REGISTER_TYPE epc; /* 37 -- saved always, read-only register */
402 /* but logically restored */
403 __MIPS_FPU_REGISTER_TYPE f0; /* 38 -- saved if FP enabled */
404 __MIPS_FPU_REGISTER_TYPE f1; /* 39 -- saved if FP enabled */
405 __MIPS_FPU_REGISTER_TYPE f2; /* 40 -- saved if FP enabled */
406 __MIPS_FPU_REGISTER_TYPE f3; /* 41 -- saved if FP enabled */
407 __MIPS_FPU_REGISTER_TYPE f4; /* 42 -- saved if FP enabled */
408 __MIPS_FPU_REGISTER_TYPE f5; /* 43 -- saved if FP enabled */
409 __MIPS_FPU_REGISTER_TYPE f6; /* 44 -- saved if FP enabled */
410 __MIPS_FPU_REGISTER_TYPE f7; /* 45 -- saved if FP enabled */
411 __MIPS_FPU_REGISTER_TYPE f8; /* 46 -- saved if FP enabled */
412 __MIPS_FPU_REGISTER_TYPE f9; /* 47 -- saved if FP enabled */
413 __MIPS_FPU_REGISTER_TYPE f10; /* 48 -- saved if FP enabled */
414 __MIPS_FPU_REGISTER_TYPE f11; /* 49 -- saved if FP enabled */
415 __MIPS_FPU_REGISTER_TYPE f12; /* 50 -- saved if FP enabled */
416 __MIPS_FPU_REGISTER_TYPE f13; /* 51 -- saved if FP enabled */
417 __MIPS_FPU_REGISTER_TYPE f14; /* 52 -- saved if FP enabled */
418 __MIPS_FPU_REGISTER_TYPE f15; /* 53 -- saved if FP enabled */
419 __MIPS_FPU_REGISTER_TYPE f16; /* 54 -- saved if FP enabled */
420 __MIPS_FPU_REGISTER_TYPE f17; /* 55 -- saved if FP enabled */
421 __MIPS_FPU_REGISTER_TYPE f18; /* 56 -- saved if FP enabled */
422 __MIPS_FPU_REGISTER_TYPE f19; /* 57 -- saved if FP enabled */
423 __MIPS_FPU_REGISTER_TYPE f20; /* 58 -- saved if FP enabled */
424 __MIPS_FPU_REGISTER_TYPE f21; /* 59 -- saved if FP enabled */
425 __MIPS_FPU_REGISTER_TYPE f22; /* 60 -- saved if FP enabled */
426 __MIPS_FPU_REGISTER_TYPE f23; /* 61 -- saved if FP enabled */
427 __MIPS_FPU_REGISTER_TYPE f24; /* 62 -- saved if FP enabled */
428 __MIPS_FPU_REGISTER_TYPE f25; /* 63 -- saved if FP enabled */
429 __MIPS_FPU_REGISTER_TYPE f26; /* 64 -- saved if FP enabled */
430 __MIPS_FPU_REGISTER_TYPE f27; /* 65 -- saved if FP enabled */
431 __MIPS_FPU_REGISTER_TYPE f28; /* 66 -- saved if FP enabled */
432 __MIPS_FPU_REGISTER_TYPE f29; /* 67 -- saved if FP enabled */
433 __MIPS_FPU_REGISTER_TYPE f30; /* 68 -- saved if FP enabled */
434 __MIPS_FPU_REGISTER_TYPE f31; /* 69 -- saved if FP enabled */
435 __MIPS_REGISTER_TYPE fcsr; /* 70 -- saved on exceptions */
436 /* (oddly not documented on MGV) */
437 __MIPS_REGISTER_TYPE feir; /* 71 -- saved on exceptions */
438 /* (oddly not documented on MGV) */
439
440 /* GDB does not seem to care about anything past this point */
441
442 __MIPS_REGISTER_TYPE tlbhi; /* 72 - NOT FILLED IN, doesn't exist on */
443 /* all MIPS CPUs (at least MGV) */
444#if __mips == 1
445 __MIPS_REGISTER_TYPE tlblo; /* 73 - NOT FILLED IN, doesn't exist on */
446 /* all MIPS CPUs (at least MGV) */
447#endif
448#if (__mips == 3) || (__mips == 32)
449 __MIPS_REGISTER_TYPE tlblo0; /* 73 - NOT FILLED IN, doesn't exist on */
450 /* all MIPS CPUs (at least MGV) */
451#endif
452
453 __MIPS_REGISTER_TYPE inx; /* 74 -- NOT FILLED IN, doesn't exist on */
454 /* all MIPS CPUs (at least MGV) */
455 __MIPS_REGISTER_TYPE rand; /* 75 -- NOT FILLED IN, doesn't exist on */
456 /* all MIPS CPUs (at least MGV) */
457 __MIPS_REGISTER_TYPE ctxt; /* 76 -- NOT FILLED IN, doesn't exist on */
458 /* all MIPS CPUs (at least MGV) */
459 __MIPS_REGISTER_TYPE exctype; /* 77 -- NOT FILLED IN (not enough info) */
460 __MIPS_REGISTER_TYPE mode; /* 78 -- NOT FILLED IN (not enough info) */
461 __MIPS_REGISTER_TYPE prid; /* 79 -- NOT FILLED IN (not need to do so) */
462 __MIPS_REGISTER_TYPE tar ; /* 80 -- target address register, filled on exceptions */
463 /* end of __mips == 1 so NREGS == 81 */
464#if (__mips == 3) || (__mips == 32)
465 __MIPS_REGISTER_TYPE tlblo1; /* 81 -- NOT FILLED IN */
466 __MIPS_REGISTER_TYPE pagemask; /* 82 -- NOT FILLED IN */
467 __MIPS_REGISTER_TYPE wired; /* 83 -- NOT FILLED IN */
468 __MIPS_REGISTER_TYPE count; /* 84 -- NOT FILLED IN */
469 __MIPS_REGISTER_TYPE compare; /* 85 -- NOT FILLED IN */
470 __MIPS_REGISTER_TYPE config; /* 86 -- NOT FILLED IN */
471 __MIPS_REGISTER_TYPE lladdr; /* 87 -- NOT FILLED IN */
472 __MIPS_REGISTER_TYPE watchlo; /* 88 -- NOT FILLED IN */
473 __MIPS_REGISTER_TYPE watchhi; /* 89 -- NOT FILLED IN */
474 __MIPS_REGISTER_TYPE ecc; /* 90 -- NOT FILLED IN */
475 __MIPS_REGISTER_TYPE cacheerr; /* 91 -- NOT FILLED IN */
476 __MIPS_REGISTER_TYPE taglo; /* 92 -- NOT FILLED IN */
477 __MIPS_REGISTER_TYPE taghi; /* 93 -- NOT FILLED IN */
478 __MIPS_REGISTER_TYPE errpc; /* 94 -- NOT FILLED IN */
479 __MIPS_REGISTER_TYPE xctxt; /* 95 -- NOT FILLED IN */
480 /* end of __mips == 3 so NREGS == 96 */
481#endif
482
484
486
487/*
488 * This variable is optional. It is used on CPUs on which it is difficult
489 * to generate an "uninitialized" FP context. It is filled in by
490 * _CPU_Initialize and copied into the task's FP context area during
491 * _CPU_Context_Initialize.
492 */
493
494extern Context_Control_fp _CPU_Null_fp_context;
495
496/*
497 * Nothing prevents the porter from declaring more CPU specific variables.
498 */
499
500/* XXX: if needed, put more variables here */
501
502/*
503 * The size of the floating point context area. On some CPUs this
504 * will not be a "sizeof" because the format of the floating point
505 * area is not defined -- only the size is. This is usually on
506 * CPUs with a "floating point save context" instruction.
507 */
508
509#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
510
511/*
512 * Amount of extra stack (above minimum stack size) required by
513 * system initialization thread. Remember that in a multiprocessor
514 * system the system intialization thread becomes the MP server thread.
515 */
516
517#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
518
519/*
520 * Should be large enough to run all RTEMS tests. This ensures
521 * that a "reasonable" small application should not have any problems.
522 */
523
524#define CPU_STACK_MINIMUM_SIZE (8 * 1024)
525
526/*
527 * CPU's worst alignment requirement for data types on a byte boundary. This
528 * alignment does not take into account the requirements for the stack.
529 */
530
531#define CPU_ALIGNMENT 8
532
533/*
534 * This number corresponds to the byte alignment requirement for the
535 * heap handler. This alignment requirement may be stricter than that
536 * for the data types alignment specified by CPU_ALIGNMENT. It is
537 * common for the heap to follow the same alignment requirement as
538 * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap,
539 * then this should be set to CPU_ALIGNMENT.
540 *
541 * NOTE: This does not have to be a power of 2. It does have to
542 * be greater or equal to than CPU_ALIGNMENT.
543 */
544
545#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
546
547#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
548
549#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
550
551void mips_vector_exceptions( CPU_Interrupt_frame *frame );
552
553/*
554 * ISR handler macros
555 */
556
557/*
558 * Declare the function that is present in the shared libcpu directory,
559 * that returns the processor dependent interrupt mask.
560 */
561
562uint32_t mips_interrupt_mask( void );
563
564/*
565 * Disable all interrupts for an RTEMS critical section. The previous
566 * level is returned in _level.
567 */
568
569#define _CPU_ISR_Disable( _level ) \
570 do { \
571 unsigned int _scratch; \
572 mips_get_sr( _scratch ); \
573 mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \
574 _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \
575 } while(0)
576
577/*
578 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
579 * This indicates the end of an RTEMS critical section. The parameter
580 * _level is not modified.
581 */
582
583#define _CPU_ISR_Enable( _level ) \
584 do { \
585 unsigned int _scratch; \
586 mips_get_sr( _scratch ); \
587 mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \
588 } while(0)
589
590/*
591 * This temporarily restores the interrupt to _level before immediately
592 * disabling them again. This is used to divide long RTEMS critical
593 * sections into two or more parts. The parameter _level is not
594 * modified.
595 */
596
597#define _CPU_ISR_Flash( _xlevel ) \
598 do { \
599 unsigned int _scratch2 = _xlevel; \
600 _CPU_ISR_Enable( _scratch2 ); \
601 _CPU_ISR_Disable( _scratch2 ); \
602 _xlevel = _scratch2; \
603 } while(0)
604
605static inline bool _CPU_ISR_Is_enabled( uint32_t level )
606{
607 return ( level & SR_INTERRUPT_ENABLE_BITS ) != 0;
608}
609
610/*
611 * Map interrupt level in task mode onto the hardware that the CPU
612 * actually provides. Currently, interrupt levels which do not
613 * map onto the CPU in a generic fashion are undefined. Someday,
614 * it would be nice if these were "mapped" by the application
615 * via a callout. For example, m68k has 8 levels 0 - 7, levels
616 * 8 - 255 would be available for bsp/application specific meaning.
617 * This could be used to manage a programmable interrupt controller
618 * via the rtems_task_mode directive.
619 *
620 * On the MIPS, 0 is all on. Non-zero is all off. This only
621 * manipulates the IEC.
622 */
623
624uint32_t _CPU_ISR_Get_level( void ); /* in cpu.c */
625
626void _CPU_ISR_Set_level( uint32_t ); /* in cpu.c */
627
628/* end of ISR handler macros */
629
630/* Context handler macros */
631
632/*
633 * Initialize the context to a state suitable for starting a
634 * task after a context restore operation. Generally, this
635 * involves:
636 *
637 * - setting a starting address
638 * - preparing the stack
639 * - preparing the stack and frame pointers
640 * - setting the proper interrupt level in the context
641 * - initializing the floating point context
642 *
643 * This routine generally does not set any unnecessary register
644 * in the context. The state of the "general data" registers is
645 * undefined at task start time.
646 *
647 * NOTE: This is_fp parameter is TRUE if the thread is to be a floating
648 * point thread. This is typically only used on CPUs where the
649 * FPU may be easily disabled by software such as on the SPARC
650 * where the PSR contains an enable FPU bit.
651 *
652 * The per-thread status register holds the interrupt enable, FP enable
653 * and global interrupt enable for that thread. It means each thread can
654 * enable its own set of interrupts. If interrupts are disabled, RTEMS
655 * can still dispatch via blocking calls. This is the function of the
656 * "Interrupt Level", and on the MIPS, it controls the IEC bit and all
657 * the hardware interrupts as defined in the SR. Software ints
658 * are automatically enabled for all threads, as they will only occur under
659 * program control anyhow. Besides, the interrupt level parm is only 8 bits,
660 * and controlling the software ints plus the others would require 9.
661 *
662 * If the Interrupt Level is 0, all ints are on. Otherwise, the
663 * Interrupt Level should supply a bit pattern to impose on the SR
664 * interrupt bits; bit 0 applies to the mips1 IEC bit/mips3 EXL&IE, bits 1 thru 6
665 * apply to the SR register Intr bits from bit 10 thru bit 15. Bit 7 of
666 * the Interrupt Level parameter is unused at this time.
667 *
668 * These are the only per-thread SR bits, the others are maintained
669 * globally & explicitly preserved by the Context Switch code in cpu_asm.s
670 */
671
672
673#if (__mips == 3) || (__mips == 32)
674#define _INTON SR_IE
675#if __mips_fpr==64
676#define _EXTRABITS SR_FR
677#else
678#define _EXTRABITS 0
679#endif /* __mips_fpr==64 */
680#endif /* __mips == 3 */
681#if __mips == 1
682#define _INTON SR_IEC
683#define _EXTRABITS 0 /* make sure we're in user mode on MIPS1 processors */
684#endif /* __mips == 1 */
685
686
687void _CPU_Context_Initialize(
688 Context_Control *the_context,
689 uintptr_t *stack_base,
690 uint32_t size,
691 uint32_t new_level,
692 void *entry_point,
693 bool is_fp,
694 void *tls_area
695);
696
697
698/*
699 * This routine is responsible for somehow restarting the currently
700 * executing task. If you are lucky, then all that is necessary
701 * is restoring the context. Otherwise, there will need to be
702 * a special assembly routine which does something special in this
703 * case. Context_Restore should work most of the time. It will
704 * not work if restarting self conflicts with the stack frame
705 * assumptions of restoring a context.
706 */
707
708#define _CPU_Context_Restart_self( _the_context ) \
709 _CPU_Context_restore( (_the_context) );
710
711/*
712 * This routine initializes the FP context area passed to it to.
713 * There are a few standard ways in which to initialize the
714 * floating point context. The code included for this macro assumes
715 * that this is a CPU in which a "initial" FP context was saved into
716 * _CPU_Null_fp_context and it simply copies it to the destination
717 * context passed to it.
718 *
719 * Other models include (1) not doing anything, and (2) putting
720 * a "null FP status word" in the correct place in the FP context.
721 */
722
723#if ( CPU_HARDWARE_FP == TRUE )
724#define _CPU_Context_Initialize_fp( _destination ) \
725 { \
726 *(*(_destination)) = _CPU_Null_fp_context; \
727 }
728#endif
729
730/* end of Context handler macros */
731
732extern void mips_break( int error );
733
734#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
735
736#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
737
738/* functions */
739
740/*
741 * _CPU_Initialize
742 *
743 * This routine performs CPU dependent initialization.
744 */
745
746void _CPU_Initialize(void);
747
748RTEMS_NO_RETURN void *_CPU_Thread_Idle_body( uintptr_t ignored );
749
750/*
751 * _CPU_Context_switch
752 *
753 * This routine switches from the run context to the heir context.
754 */
755
757 Context_Control *run,
758 Context_Control *heir
759);
760
761/*
762 * _CPU_Context_restore
763 *
764 * This routine is generally used only to restart self in an
765 * efficient manner. It may simply be a label in _CPU_Context_switch.
766 *
767 * NOTE: May be unnecessary to reload some registers.
768 */
769
770RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context );
771
772/*
773 * _CPU_Context_save_fp
774 *
775 * This routine saves the floating point context passed to it.
776 */
777
779 Context_Control_fp **fp_context_ptr
780);
781
782/*
783 * _CPU_Context_restore_fp
784 *
785 * This routine restores the floating point context passed to it.
786 */
787
789 Context_Control_fp **fp_context_ptr
790);
791
793
794/* The following routine swaps the endian format of an unsigned int.
795 * It must be static because it is referenced indirectly.
796 *
797 * This version will work on any processor, but if there is a better
798 * way for your CPU PLEASE use it. The most common way to do this is to:
799 *
800 * swap least significant two bytes with 16-bit rotate
801 * swap upper and lower 16-bits
802 * swap most significant two bytes with 16-bit rotate
803 *
804 * Some CPUs have special instructions which swap a 32-bit quantity in
805 * a single instruction (e.g. i486). It is probably best to avoid
806 * an "endian swapping control bit" in the CPU. One good reason is
807 * that interrupts would probably have to be disabled to ensure that
808 * an interrupt does not try to access the same "chunk" with the wrong
809 * endian. Another good reason is that on some CPUs, the endian bit
810 * endianness for ALL fetches -- both code and data -- so the code
811 * will be fetched incorrectly.
812 */
813
814static inline uint32_t CPU_swap_u32(
815 uint32_t value
816)
817{
818 uint32_t byte1, byte2, byte3, byte4, swapped;
819
820 byte4 = (value >> 24) & 0xff;
821 byte3 = (value >> 16) & 0xff;
822 byte2 = (value >> 8) & 0xff;
823 byte1 = value & 0xff;
824
825 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
826 return( swapped );
827}
828
829#define CPU_swap_u16( value ) \
830 (((value&0xff) << 8) | ((value >> 8)&0xff))
831
832typedef uint32_t CPU_Counter_ticks;
833
834uint32_t _CPU_Counter_frequency( void );
835
836CPU_Counter_ticks _CPU_Counter_read( void );
837
839typedef uintptr_t CPU_Uint32ptr;
840
841#endif
842
843#ifdef __cplusplus
844}
845#endif
846
848#endif
This header file provides basic definitions used by the API and the implementation.
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
#define _CPU_ISR_Set_level(_new_level)
Definition: cpu.h:378
#define ra
return address *‍/
Definition: regs.h:66
#define sp
stack-pointer *‍/
Definition: regs.h:64
#define k0
kernel private register 0 *‍/
Definition: regs.h:61
#define k1
kernel private register 1 *‍/
Definition: regs.h:62
#define fp
frame-pointer *‍/
Definition: regs.h:65
#define gp
global data pointer *‍/
Definition: regs.h:63
Information to build RTEMS for a "no cpu" while in protected mode.
#define _CPU_Context_restore_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:901
#define _CPU_Context_save_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:895
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
SPARC basic context.
Definition: cpu.h:213
Thread register context.
Definition: cpu.h:173
Definition: bootldr.h:45
Definition: deflate.c:114