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bsps
riscv
niosv
include
altera_avalon_epcq_regs.h
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/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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*
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* Copyright (C) 2024 Kevin Kirspel
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _ALTERA_AVALON_EPCQ_REGS_H
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#define _ALTERA_AVALON_EPCQ_REGS_H
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#include <stdbool.h>
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#include <bsp_system.h>
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/*
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* EPCQ_RD_STATUS register description macros
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*/
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#define ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_MASK (0x00000001)
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#define ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_AVAILABLE (0x00000000)
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#define ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_BUSY (0x00000001)
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/* 0.7 sec time out */
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#define ALTERA_EPCQ_CONTROLLER2_1US_TIMEOUT_VALUE 700000
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/*
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* EPCQ_RD_SID register description macros
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*
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* Specific device values obtained from Table 14 of:
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* "Serial Configuration (EPCS) Devices Datasheet"
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*/
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#define ALTERA_EPCQ_CONTROLLER2_SID_MASK (0x000000FF)
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#define ALTERA_EPCQ_CONTROLLER2_SID_EPCS16 (0x00000014)
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#define ALTERA_EPCQ_CONTROLLER2_SID_EPCS64 (0x00000016)
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#define ALTERA_EPCQ_CONTROLLER2_SID_EPCS128 (0x00000018)
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/*
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* EPCQ_RD_RDID register description macros
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*
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* Specific device values obtained from Table 28 of:
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* "Quad-Serial Configuration
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* (EPCQ (www.altera.com/literature/hb/cfg/cfg_cf52012.pdf))
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* Devices Datasheet"
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*/
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#define ALTERA_EPCQ_CONTROLLER2_RDID_MASK (0x000000FF)
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#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ16 (0x00000015)
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#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ32 (0x00000016)
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#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ64 (0x00000017)
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#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ128 (0x00000018)
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#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ256 (0x00000019)
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#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ512 (0x00000020)
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#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ1024 (0x00000021)
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/*
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* EPCQ_MEM_OP register description macros
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*/
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#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_CMD_MASK (0x00000003)
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#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_BULK_ERASE_CMD (0x00000001)
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#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_ERASE_CMD (0x00000002)
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#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_PROTECT_CMD (0x00000003)
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#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_WRITE_ENABLE_CMD (0x00000004)
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#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_VALUE_MASK (0x00FFFF00)
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/*
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* EPCQ_ISR register description macros
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*/
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#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_MASK (0x00000001)
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#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_ACTIVE (0x00000001)
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#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_MASK (0x00000002)
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#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_ACTIVE (0x00000002)
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/*
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* EPCQ_IMR register description macros
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*/
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#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_ERASE_MASK (0x00000001)
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#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_ERASE_ENABLED (0x00000001)
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#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_WRITE_MASK (0x00000002)
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#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_WRITE_ENABLED (0x00000002)
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/*
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* EPCQ_CHIP_SELECT register description macros
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*/
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#define ALTERA_EPCQ_CHIP1_SELECT (0x00000001)
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#define ALTERA_EPCQ_CHIP2_SELECT (0x00000002)
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#define ALTERA_EPCQ_CHIP3_SELECT (0x00000003)
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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typedef
struct
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{
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volatile
uint32_t rd_status;
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volatile
uint32_t rd_sid;
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volatile
uint32_t rd_rdid;
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volatile
uint32_t mem_op;
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volatile
uint32_t isr;
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volatile
uint32_t imr;
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volatile
uint32_t chip_select;
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volatile
uint32_t flag_status;
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volatile
uint32_t dev_id_0;
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volatile
uint32_t dev_id_1;
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volatile
uint32_t dev_id_2;
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volatile
uint32_t dev_id_3;
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volatile
uint32_t dev_id_4;
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}
altera_avalon_epcq_regs
;
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#define EPCQ_REGS \
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(( volatile altera_avalon_epcq_regs* )EPCQ_CONTROLLER_AVL_CSR_BASE )
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#define EPCQ_MEM \
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(( volatile uint8_t* )EPCQ_CONTROLLER_AVL_MEM_BASE )
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#define EPCQ_MEM_32 \
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(( volatile uint32_t* )EPCQ_CONTROLLER_AVL_MEM_BASE )
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void
epcq_initialize(
void
);
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int
epcq_read_buffer(
int
offset, uint8_t *dest_addr,
int
length );
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int
epcq_write_buffer (
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int
offset,
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const
uint8_t* src_addr,
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int
length,
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bool
erase
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);
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#ifdef __cplusplus
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}
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#endif
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#endif
altera_avalon_epcq_regs
Definition:
altera_avalon_epcq_regs.h:117
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