43#ifndef _RTEMS_POWERPC_REGISTERS_H
44#define _RTEMS_POWERPC_REGISTERS_H
49#define MSR_UCLE (1<<26)
51#define MSR_SPE (1<<25)
53#define MSR_APE (1<<19)
54#define MSR_POW (1<<18)
56#define MSR_TGPR (1<<17)
58#define MSR_ILE (1<<16)
63#define MSR_FE0 (1<<11)
65#define MSR_UBLE (1<<10)
66#define MSR_DWE (1<<10)
70#define MSR_E300_CE (1<<7)
90#define HID0_EMCP (1<<31)
91#define HID0_EBA (1<<29)
92#define HID0_EBD (1<<28)
93#define HID0_SBCLK (1<<27)
94#define HID0_TBEN (1<<26)
99#define HID0_EICE (1<<26)
100#define HID0_ECLK (1<<25)
101#define HID0_PAR (1<<24)
102#define HID0_DOZE (1<<23)
104#define HID0_7455_HIGH_BAT_EN (1<<23)
106#define HID0_NAP (1<<22)
107#define HID0_SLEEP (1<<21)
108#define HID0_DPM (1<<20)
109#define HID0_ICE (1<<15)
110#define HID0_DCE (1<<14)
111#define HID0_ILOCK (1<<13)
112#define HID0_DLOCK (1<<12)
113#define HID0_ICFI (1<<11)
114#define HID0_DCI (1<<10)
116#define HID0_7455_XBSEN (1<<8)
117#define HID0_SIED (1<<7)
118#define HID0_BTIC (1<<5)
120#define HID0_LRSTK (1<<4)
121#define HID0_FOLD (1<<3)
123#define HID0_BHTE (1<<2)
124#define HID0_BTCD (1<<1)
127#define FPSCR_FX (1<<31)
128#define FPSCR_FEX (1<<30)
138#define _PREP_Motorola 0x01
139#define _PREP_Firm 0x02
140#define _PREP_IBM 0x00
141#define _PREP_Bull 0x03
144#define _CHRP_Motorola 0x04
145#define _CHRP_IBM 0x05
236#define L2CR_L2E (1<<31)
237#define L2CR_L2I (1<<21)
245#define L2CR_L2IO_745x 0x100000
246#define L2CR_L2DO_745x 0x10000
247#define L2CR_LOCK_745x (L2CR_L2IO_745x|L2CR_L2DO_745x)
248#define L2CR_L3OH0 0x00080000
251#define L3CR_L3IO_745x 0x400000
252#define L3CR_L3DO_745x 0x40
254#define L3CR_LOCK_745x (L3CR_L3IO_745x|L3CR_L3DO_745x)
256#define L3CR_RESERVED 0x0438003a
257#define L3CR_L3E 0x80000000
258#define L3CR_L3PE 0x40000000
259#define L3CR_L3APE 0x20000000
260#define L3CR_L3SIZ 0x10000000
261#define L3SIZ_1M 0x00000000
262#define L3SIZ_2M 0x10000000
263#define L3CR_L3CLKEN 0x08000000
264#define L3CR_L3CLK 0x03800000
265#define L3CLK_60 0x00000000
266#define L3CLK_20 0x01000000
267#define L3CLK_25 0x01800000
268#define L3CLK_30 0x02000000
269#define L3CLK_35 0x02800000
270#define L3CLK_40 0x03000000
271#define L3CLK_50 0x03800000
272#define L3CR_L3IO 0x00400000
273#define L3CR_L3SPO 0x00040000
274#define L3CR_L3CKSP 0x00030000
275#define L3CKSP_2 0x00000000
276#define L3CKSP_3 0x00010000
277#define L3CKSP_4 0x00020000
278#define L3CKSP_5 0x00030000
279#define L3CR_L3PSP 0x0000e000
280#define L3PSP_0 0x00000000
281#define L3PSP_1 0x00002000
282#define L3PSP_2 0x00004000
283#define L3PSP_3 0x00006000
284#define L3PSP_4 0x00008000
285#define L3PSP_5 0x0000a000
286#define L3CR_L3REP 0x00001000
287#define L3CR_L3HWF 0x00000800
288#define L3CR_L3I 0x00000400
290#define L3CR_L3RT 0x00000300
291#define L3RT_MSUG2_DDR 0x00000000
292#define L3RT_PIPELINE_LATE 0x00000100
293#define L3RT_PB2_SRAM 0x00000300
294#define L3CR_L3NIRCA 0x00000080
295#define L3CR_L3DO 0x00000040
296#define L3CR_PMEN 0x00000004
297#define L3CR_PMSIZ 0x00000004
302#define THRM1_TIN (1<<(31-0))
303#define THRM1_TIV (1<<(31-1))
304#define THRM1_THRES (0x7f<<(31-8))
305#define THRM1_TID (1<<(31-29))
306#define THRM1_TIE (1<<(31-30))
307#define THRM1_V (1<<(31-31))
308#define THRM3_SITV (0x1fff << (31-30))
309#define THRM3_E (1<<(31-31))
329#define BOOKE_DECAR 54
331#define PPC405_MCSR 0x23C
332#define PPC405_ESR 0x3D4
333#define PPC405_DEAR 0x3D5
336#define PPC405_TSR 0x3D8
338#define BOOKE_TSR_ENW (1<<31)
339#define BOOKE_TSR_WIS (1<<30)
340#define BOOKE_TSR_DIS (1<<27)
341#define BOOKE_TSR_FIS (1<<26)
343#define PPC405_TCR 0x3DA
345#define BOOKE_TCR_WP(x) (((x)&3)<<30)
346#define BOOKE_TCR_WP_MASK (3<<30)
347#define BOOKE_TCR_WRC(x) (((x)&3)<<28)
348#define BOOKE_TCR_WRC_MASK (3<<28)
349#define BOOKE_TCR_WIE (1<<27)
350#define BOOKE_TCR_DIE (1<<26)
351#define BOOKE_TCR_FP(x) (((x)&3)<<24)
352#define BOOKE_TCR_FIE (1<<23)
353#define BOOKE_TCR_ARE (1<<22)
354#define BOOKE_TCR_WPEXT(x) (((x)&0xf)<<17)
355#define BOOKE_TCR_WPEXT_MASK (0xf<<17)
356#define BOOKE_TCR_FPEXT(x) (((x)&0xf)<<13)
357#define BOOKE_TCR_FPEXT_MASK (0xf<<13)
360#define BOOKE_CSRR0 58
361#define BOOKE_CSRR1 59
364#define BOOKE_SPRG4_W 260
365#define BOOKE_SPRG5_W 261
366#define BOOKE_SPRG6_W 262
367#define BOOKE_SPRG7_W 263
369#define BOOKE_DBSR 304
371#define BOOKE_EPCR 307
372#define BOOKE_EPCR_EXTGS (1 << 31)
373#define BOOKE_EPCR_DTLBGS (1 << 30)
374#define BOOKE_EPCR_ITLBGS (1 << 29)
375#define BOOKE_EPCR_DSIGS (1 << 28)
376#define BOOKE_EPCR_ISIGS (1 << 27)
377#define BOOKE_EPCR_DUVD (1 << 26)
378#define BOOKE_EPCR_ICM (1 << 25)
379#define BOOKE_EPCR_GICM (1 << 24)
380#define BOOKE_EPCR_DGTMI (1 << 23)
381#define BOOKE_EPCR_DMIUH (1 << 22)
382#define BOOKE_EPCR_PMGS (1 << 21)
384#define BOOKE_DBCR0 308
385#define BOOKE_DBCR1 309
386#define BOOKE_DBCR2 310
387#define BOOKE_IAC1 312
388#define BOOKE_IAC2 313
389#define BOOKE_IAC3 314
390#define BOOKE_IAC4 315
391#define BOOKE_DAC1 316
392#define BOOKE_DAC2 317
393#define BOOKE_DVC1 318
394#define BOOKE_DVC2 319
395#define BOOKE_GSRR0 378
396#define BOOKE_GSRR1 379
397#define BOOKE_GEPR 380
398#define BOOKE_GDEAR 381
399#define BOOKE_GPIR 382
400#define BOOKE_GESR 383
401#define BOOKE_IVOR0 400
402#define BOOKE_IVOR1 401
403#define BOOKE_IVOR2 402
404#define BOOKE_IVOR3 403
405#define BOOKE_IVOR4 404
406#define BOOKE_IVOR5 405
407#define BOOKE_IVOR6 406
408#define BOOKE_IVOR7 407
409#define BOOKE_IVOR8 408
410#define BOOKE_IVOR9 409
411#define BOOKE_IVOR10 410
412#define BOOKE_IVOR11 411
413#define BOOKE_IVOR12 412
414#define BOOKE_IVOR13 413
415#define BOOKE_IVOR14 414
416#define BOOKE_IVOR15 415
417#define BOOKE_IVOR42 436
418#define BOOKE_IVOR32 528
419#define BOOKE_IVOR33 529
420#define BOOKE_IVOR34 530
421#define BOOKE_IVOR35 531
422#define BOOKE_IVOR36 532
423#define BOOKE_IVOR37 533
424#define BOOKE_IVOR38 432
425#define BOOKE_IVOR39 433
426#define BOOKE_IVOR40 434
427#define BOOKE_IVOR41 435
428#define BOOKE_GIVOR2 440
429#define BOOKE_GIVOR3 441
430#define BOOKE_GIVOR4 442
431#define BOOKE_GIVOR8 443
432#define BOOKE_GIVOR13 444
433#define BOOKE_GIVOR14 445
434#define BOOKE_GIVPR 446
435#define BOOKE_MCSRR0 570
436#define BOOKE_MCSRR1 571
437#define BOOKE_MCSR 572
438#define BOOKE_DSRR0 574
439#define BOOKE_DSRR1 575
441#define PPC440_INV0 880
442#define PPC440_INV1 881
443#define PPC440_INV2 882
444#define PPC440_INV3 883
445#define PPC440_ITV0 884
446#define PPC440_ITV1 885
447#define PPC440_ITV2 886
448#define PPC440_ITV3 887
449#define PPC440_CCR1 888
450#define PPC440_DNV0 912
451#define PPC440_DNV1 913
452#define PPC440_DNV2 914
453#define PPC440_DNV3 915
454#define PPC440_DTV0 916
455#define PPC440_DTV1 917
456#define PPC440_DTV2 918
457#define PPC440_DTV3 919
458#define PPC440_DVLIM 920
459#define PPC440_IVLIM 921
460#define PPC440_RSTCFG 923
461#define PPC440_DCDBTRL 924
462#define PPC440_DCDBTRH 925
463#define PPC440_ICDBTRL 926
464#define PPC440_ICDBTRH 927
465#define PPC440_MMUCR 946
466#define PPC440_CCR0 947
467#define PPC440_ICDBDR 979
468#define PPC440_DBDR 1011
470#define PPC440_TLB0_EPN(n) ( (((1<<22)-1)&(n)) << (31-21))
471#define PPC440_TLB0_EPN_GET(n) ( ((n) >> (31-21)) & ((1<<22)-1))
472#define PPC440_TLB0_V ( 1 << (31-22))
473#define PPC440_TLB0_TS ( 1 << (31-23))
474#define PPC440_TLB0_TSIZE(n) ( (0xf & (n)) << (31-27))
475#define PPC440_TLB0_TSIZE_GET(n) ( ((n) >> (31-27)) & 0xf)
476#define PPC440_TLB0_TPAR(n) ( (0xf & (n)) << (31-31))
477#define PPC440_TLB0_TPAR_GET(n) ( ((n) >> (31-31)) & 0xf)
479#define PPC440_PID_TID(n) ( (0xff & (n)) << (31-31))
480#define PPC440_PID_TID_GET(n) ( ((n) >> (31-31)) & 0xff)
482#define PPC440_TLB1_RPN(n) ( (((1<<22)-1)&(n)) << (31-21))
483#define PPC440_TLB1_RPN_GET(n) ( ((n) >> (31-21)) & ((1<<22)-1))
484#define PPC440_TLB1_PAR1(n) ( (0x3 & (n)) << (31-23))
485#define PPC440_TLB1_PAR1_GET(n) ( ((n) >> (31-23)) & 0x3)
486#define PPC440_TLB1_ERPN(n) ( (0xf & (n)) << (31-31))
487#define PPC440_TLB1_ERPN_GET(n) ( ((n) >> (31-31)) & 0xf)
489#define PPC440_TLB2_PAR2(n) ( (0x3 & (n)) << (31- 1))
490#define PPC440_TLB2_PAR2_GET(n) ( ((n) >> (31- 1)) & 0x3)
491#define PPC440_TLB2_U0 ( 1 << (31-16))
492#define PPC440_TLB2_U1 ( 1 << (31-17))
493#define PPC440_TLB2_U2 ( 1 << (31-18))
494#define PPC440_TLB2_U3 ( 1 << (31-19))
495#define PPC440_TLB2_W ( 1 << (31-20))
496#define PPC440_TLB2_I ( 1 << (31-21))
497#define PPC440_TLB2_M ( 1 << (31-22))
498#define PPC440_TLB2_G ( 1 << (31-23))
499#define PPC440_TLB2_E ( 1 << (31-24))
500#define PPC440_TLB2_UX ( 1 << (31-26))
501#define PPC440_TLB2_UW ( 1 << (31-27))
502#define PPC440_TLB2_UR ( 1 << (31-28))
503#define PPC440_TLB2_SX ( 1 << (31-29))
504#define PPC440_TLB2_SW ( 1 << (31-30))
505#define PPC440_TLB2_SR ( 1 << (31-31))
507#define PPC440_TLB2_ATTR(x) ( ((x) & 0x1ff) << 7 )
508#define PPC440_TLB2_ATTR_GET(x) ( ((x) >> 7) & 0x1ff )
510#define PPC440_TLB2_PERM(n) ( (n) & 0x3f )
511#define PPC440_TLB2_PERM_GET(n) ( (n) & 0x3f )
515#define FSL_EIS_BUCSR 1013
516#define FSL_EIS_BUCSR_STAC_EN (1 << (63 - 39))
517#define FSL_EIS_BUCSR_LS_EN (1 << (63 - 41))
518#define FSL_EIS_BUCSR_BBFI (1 << (63 - 54))
519#define FSL_EIS_BUCSR_BALLOC_ALL (0x0 << (63 - 59))
520#define FSL_EIS_BUCSR_BALLOC_FORWARD (0x1 << (63 - 59))
521#define FSL_EIS_BUCSR_BALLOC_BACKWARD (0x2 << (63 - 59))
522#define FSL_EIS_BUCSR_BALLOC_NONE (0x3 << (63 - 59))
523#define FSL_EIS_BUCSR_BPRED_TAKEN (0x0 << (63 - 61))
524#define FSL_EIS_BUCSR_BPRED_TAKEN_ONLY_FORWARD (0x1 << (63 - 62))
525#define FSL_EIS_BUCSR_BPRED_TAKEN_ONLY_BACKWARD (0x2 << (63 - 62))
526#define FSL_EIS_BUCSR_BPRED_NOT_TAKEN (0x3 << (63 - 62))
527#define FSL_EIS_BUCSR_BPEN (1 << (63 - 63))
531#define FSL_EIS_SVR 1023
535#define FSL_EIS_TENSR 437
536#define FSL_EIS_TENS 438
537#define FSL_EIS_TENC 439
538#define FSL_EIS_PPR32 898
542#define FSL_EIS_MAS0 624
543#define FSL_EIS_MAS0_TLBSEL (1 << (63 - 35))
544#define FSL_EIS_MAS0_ESEL(n) ((0xfff & (n)) << (63 - 47))
545#define FSL_EIS_MAS0_ESEL_GET(m) (((m) >> (63 - 47)) & 0xfff)
546#define FSL_EIS_MAS0_NV (1 << (63 - 63))
548#define FSL_EIS_MAS1 625
549#define FSL_EIS_MAS1_V (1 << (63 - 32))
550#define FSL_EIS_MAS1_IPROT (1 << (63 - 33))
551#define FSL_EIS_MAS1_TID(n) ((0xff & (n)) << (63 - 47))
552#define FSL_EIS_MAS1_TID_GET(n) (((n) >> (63 - 47)) & 0xfff)
553#define FSL_EIS_MAS1_TS (1 << (63 - 51))
554#define FSL_EIS_MAS1_TSIZE(n) ((0xf & (n)) << (63 - 55))
555#define FSL_EIS_MAS1_TSIZE_GET(n) (((n)>>(63 - 55)) & 0xf)
557#define FSL_EIS_MAS2 626
558#define FSL_EIS_MAS2_EPN(n) ((((1 << 21) - 1)&(n)) << (63-51))
559#define FSL_EIS_MAS2_EPN_GET(n) (((n) >> (63 - 51)) & 0xfffff)
560#define FSL_EIS_MAS2_EA(n) FSL_EIS_MAS2_EPN((n) >> 12)
561#define FSL_EIS_MAS2_EA_GET(n) (FSL_EIS_MAS2_EPN_GET(n) << 12)
562#define FSL_EIS_MAS2_X0 (1 << (63 - 57))
563#define FSL_EIS_MAS2_X1 (1 << (63 - 58))
564#define FSL_EIS_MAS2_W (1 << (63 - 59))
565#define FSL_EIS_MAS2_I (1 << (63 - 60))
566#define FSL_EIS_MAS2_M (1 << (63 - 61))
567#define FSL_EIS_MAS2_G (1 << (63 - 62))
568#define FSL_EIS_MAS2_E (1 << (63 - 63))
569#define FSL_EIS_MAS2_ATTR(x) ((x) & 0x7f)
570#define FSL_EIS_MAS2_ATTR_GET(x) ((x) & 0x7f)
572#define FSL_EIS_MAS3 627
573#define FSL_EIS_MAS3_RPN(n) ((((1 << 21) - 1) & (n)) << (63-51))
574#define FSL_EIS_MAS3_RPN_GET(n) (((n)>>(63 - 51)) & 0xfffff)
575#define FSL_EIS_MAS3_RA(n) FSL_EIS_MAS3_RPN((n) >> 12)
576#define FSL_EIS_MAS3_RA_GET(n) (FSL_EIS_MAS3_RPN_GET(n) << 12)
577#define FSL_EIS_MAS3_U0 (1 << (63 - 54))
578#define FSL_EIS_MAS3_U1 (1 << (63 - 55))
579#define FSL_EIS_MAS3_U2 (1 << (63 - 56))
580#define FSL_EIS_MAS3_U3 (1 << (63 - 57))
581#define FSL_EIS_MAS3_UX (1 << (63 - 58))
582#define FSL_EIS_MAS3_SX (1 << (63 - 59))
583#define FSL_EIS_MAS3_UW (1 << (63 - 60))
584#define FSL_EIS_MAS3_SW (1 << (63 - 61))
585#define FSL_EIS_MAS3_UR (1 << (63 - 62))
586#define FSL_EIS_MAS3_SR (1 << (63 - 63))
587#define FSL_EIS_MAS3_PERM(n) ((n) & 0x3ff)
588#define FSL_EIS_MAS3_PERM_GET(n) ((n) & 0x3ff)
590#define FSL_EIS_MAS4 628
591#define FSL_EIS_MAS4_TLBSELD (1 << (63 - 35))
592#define FSL_EIS_MAS4_TIDSELD(n) ((0x3 & (n)) << (63 - 47))
593#define FSL_EIS_MAS4_TSIZED(n) ((0xf & (n)) << (63 - 55))
594#define FSL_EIS_MAS4_X0D FSL_EIS_MAS2_X0
595#define FSL_EIS_MAS4_X1D FSL_EIS_MAS2_X1
596#define FSL_EIS_MAS4_WD FSL_EIS_MAS2_W
597#define FSL_EIS_MAS4_ID FSL_EIS_MAS2_I
598#define FSL_EIS_MAS4_MD FSL_EIS_MAS2_M
599#define FSL_EIS_MAS4_GD FSL_EIS_MAS2_G
600#define FSL_EIS_MAS4_ED FSL_EIS_MAS2_E
602#define FSL_EIS_MAS5 629
604#define FSL_EIS_MAS6 630
605#define FSL_EIS_MAS6_SPID0(n) ((0xff & (n)) << (63 - 55))
606#define FSL_EIS_MAS6_SAS (1 << (63 - 63))
608#define FSL_EIS_MAS7 944
610#define FSL_EIS_MAS8 341
612#define FSL_EIS_MMUCFG 1015
613#define FSL_EIS_MMUCSR0 1012
614#define FSL_EIS_PID0 48
615#define FSL_EIS_PID1 633
616#define FSL_EIS_PID2 634
617#define FSL_EIS_TLB0CFG 688
618#define FSL_EIS_TLB1CFG 689
622#define FSL_EIS_L1CFG0 515
623#define FSL_EIS_L1CFG1 516
624#define FSL_EIS_L1CSR0 1010
625#define FSL_EIS_L1CSR0_CFI (1 << (63 - 62))
626#define FSL_EIS_L1CSR1 1011
627#define FSL_EIS_L1CSR1_ICFI (1 << (63 - 62))
631#define FSL_EIS_L2CFG0 519
632#define FSL_EIS_L2CSR0 1017
633#define FSL_EIS_L2CSR0_L2FI (1 << (63 - 42))
634#define FSL_EIS_L2CSR0_L2FL (1 << (63 - 52))
635#define FSL_EIS_L2CSR1 1018
639#define FSL_EIS_ATBL 526
640#define FSL_EIS_ATBU 527
644#define FSL_EIS_MCAR 573
645#define FSL_EIS_DSRR0 574
646#define FSL_EIS_DSRR1 575
647#define FSL_EIS_EPR 702
651#define FSL_EIS_SPEFSCR 512
655#define FSL_EIS_SPRG8 604
656#define FSL_EIS_SPRG9 605
660#define FSL_EIS_DBCR3 561
661#define FSL_EIS_DBCR4 563
662#define FSL_EIS_DBCR5 564
663#define FSL_EIS_DBCR6 603
664#define FSL_EIS_DBCNT 562
672#define PPC_INTERRUPT_DISABLE_MASK_DEFAULT MSR_EE
682#define _CPU_MSR_GET( _msr_value ) \
685 __asm__ volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
688#define _CPU_MSR_SET( _msr_value ) \
689{ __asm__ volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
696#if !defined(PPC_DISABLE_INLINE_ISR_DISABLE_ENABLE)
699static inline uint32_t ppc_interrupt_get_disable_mask(
void )
704static inline uint32_t ppc_interrupt_disable(
void )
708#if defined(__PPC_CPU_E6500__)
719 "lis %1, _PPC_INTERRUPT_DISABLE_MASK@h;"
720 "ori %1, %1, _PPC_INTERRUPT_DISABLE_MASK@l;"
723 :
"=r" (level),
"=r" (mask)
730static inline void ppc_interrupt_enable( uint32_t level )
732#if defined(__PPC_CPU_E6500__)
747static inline void ppc_interrupt_flash( uint32_t level )
749 uint32_t current_level;
755 :
"=&r" (current_level)
760uint32_t ppc_interrupt_get_disable_mask(
void );
761uint32_t ppc_interrupt_disable(
void );
762void ppc_interrupt_enable( uint32_t level );
763void ppc_interrupt_flash( uint32_t level );
766#define _CPU_ISR_Disable( _isr_cookie ) \
768 _isr_cookie = ppc_interrupt_disable(); \
777#define _CPU_ISR_Enable( _isr_cookie ) \
778 ppc_interrupt_enable(_isr_cookie)
791#define _CPU_ISR_Flash( _isr_cookie ) \
792 ppc_interrupt_flash(_isr_cookie)
char _PPC_INTERRUPT_DISABLE_MASK[]
A global symbol used to disable interrupts in the MSR.