RTEMS 6.1-rc7
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cpu.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
12/*
13 * This include file contains information pertaining to the ARM
14 * processor.
15 *
16 * Copyright (C) 2009, 2017 embedded brains GmbH & Co. KG
17 *
18 * Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com>
19 *
20 * Copyright (c) 2006 On-Line Applications Research Corporation (OAR)
21 *
22 * Copyright (c) 2002 Advent Networks, Inc.
23 * Jay Monkman <jmonkman@adventnetworks.com>
24 *
25 * COPYRIGHT (c) 2000 Canon Research Centre France SA.
26 * Emmanuel Raguet, mailto:raguet@crf.canon.fr
27 *
28 * Redistribution and use in source and binary forms, with or without
29 * modification, are permitted provided that the following conditions
30 * are met:
31 * 1. Redistributions of source code must retain the above copyright
32 * notice, this list of conditions and the following disclaimer.
33 * 2. Redistributions in binary form must reproduce the above copyright
34 * notice, this list of conditions and the following disclaimer in the
35 * documentation and/or other materials provided with the distribution.
36 *
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
38 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
39 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
40 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
41 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
42 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
43 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
44 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
45 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
46 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
47 * POSSIBILITY OF SUCH DAMAGE.
48 *
49 */
50
51#ifndef _RTEMS_SCORE_CPU_H
52#define _RTEMS_SCORE_CPU_H
53
55#if defined(RTEMS_PARAVIRT)
56#include <rtems/score/paravirt.h>
57#endif
58#include <rtems/score/arm.h>
59
66#if defined(ARM_MULTILIB_ARCH_V4)
67
68#if defined(__thumb__) && !defined(__thumb2__)
69 #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg
70 #define ARM_SWITCH_TO_ARM ".align 2\nbx pc\n.arm\n"
71 #define ARM_SWITCH_BACK "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n"
72 #define ARM_SWITCH_OUTPUT [arm_switch_reg] "=&r" (arm_switch_reg)
73 #define ARM_SWITCH_ADDITIONAL_OUTPUT , ARM_SWITCH_OUTPUT
74#else
75 #define ARM_SWITCH_REGISTERS
76 #define ARM_SWITCH_TO_ARM
77 #define ARM_SWITCH_BACK
78 #define ARM_SWITCH_OUTPUT
79 #define ARM_SWITCH_ADDITIONAL_OUTPUT
80#endif
81
87#define ARM_PSR_N (1 << 31)
88#define ARM_PSR_Z (1 << 30)
89#define ARM_PSR_C (1 << 29)
90#define ARM_PSR_V (1 << 28)
91#define ARM_PSR_Q (1 << 27)
92#define ARM_PSR_J (1 << 24)
93#define ARM_PSR_GE_SHIFT 16
94#define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT)
95#define ARM_PSR_E (1 << 9)
96#define ARM_PSR_A (1 << 8)
97#define ARM_PSR_I (1 << 7)
98#define ARM_PSR_F (1 << 6)
99#define ARM_PSR_T (1 << 5)
100#define ARM_PSR_M_SHIFT 0
101#define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT)
102#define ARM_PSR_M_USR 0x10
103#define ARM_PSR_M_FIQ 0x11
104#define ARM_PSR_M_IRQ 0x12
105#define ARM_PSR_M_SVC 0x13
106#define ARM_PSR_M_ABT 0x17
107#define ARM_PSR_M_HYP 0x1a
108#define ARM_PSR_M_UND 0x1b
109#define ARM_PSR_M_SYS 0x1f
110
113#endif /* defined(ARM_MULTILIB_ARCH_V4) */
114
115/*
116 * The ARM uses the PIC interrupt model.
117 */
118#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
119
120#define CPU_ISR_PASSES_FRAME_POINTER FALSE
121
122#define CPU_HARDWARE_FP FALSE
123
124#define CPU_SOFTWARE_FP FALSE
125
126#define CPU_ALL_TASKS_ARE_FP FALSE
127
128#define CPU_IDLE_TASK_IS_FP FALSE
129
130#define CPU_USE_DEFERRED_FP_SWITCH FALSE
131
132#define CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE
133
134#define CPU_STACK_GROWS_UP FALSE
135
136#if defined(ARM_MULTILIB_CACHE_LINE_MAX_64)
137 #define CPU_CACHE_LINE_BYTES 64
138#else
139 #define CPU_CACHE_LINE_BYTES 32
140#endif
141
142#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
143
144#define CPU_MODES_INTERRUPT_MASK 0x1
145
146#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
147
148#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
149
150#define CPU_STACK_MINIMUM_SIZE (1024 * 4)
151
152/* AAPCS, section 4.1, Fundamental Data Types */
153#define CPU_SIZEOF_POINTER 4
154
155/* AAPCS, section 4.1, Fundamental Data Types */
156#define CPU_ALIGNMENT 8
157
158#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
159
160/* AAPCS, section 5.2.1.2, Stack constraints at a public interface */
161#define CPU_STACK_ALIGNMENT 8
162
163#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
164
165/*
166 * Bitfield handler macros.
167 *
168 * If we had a particularly fast function for finding the first
169 * bit set in a word, it would go here. Since we don't (*), we'll
170 * just use the universal macros.
171 *
172 * (*) On ARM V5 and later, there's a CLZ function which could be
173 * used to implement much quicker than the default macro.
174 */
175
176#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
177
178#define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE
179
180#define CPU_MAXIMUM_PROCESSORS 32
181
182#define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44
183
184#ifdef ARM_MULTILIB_VFP
185 #define ARM_CONTEXT_CONTROL_D8_OFFSET 48
186#endif
187
188#ifdef ARM_MULTILIB_ARCH_V4
189 #define ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 40
190#endif
191
192#ifdef RTEMS_SMP
193 #if defined(ARM_MULTILIB_VFP)
194 #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112
195 #else
196 #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48
197 #endif
198#endif
199
200#define ARM_EXCEPTION_FRAME_SIZE 80
201
202#define ARM_EXCEPTION_FRAME_REGISTER_R8_OFFSET 32
203
204#define ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET 52
205
206#define ARM_EXCEPTION_FRAME_REGISTER_PC_OFFSET 60
207
208#if defined(ARM_MULTILIB_ARCH_V4)
209 #define ARM_EXCEPTION_FRAME_REGISTER_CPSR_OFFSET 64
210#elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M)
211 #define ARM_EXCEPTION_FRAME_REGISTER_XPSR_OFFSET 64
212#endif
213
214#define ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET 72
215
216#define ARM_VFP_CONTEXT_SIZE 264
217
218#ifndef ASM
219
220#ifdef __cplusplus
221extern "C" {
222#endif
223
224typedef struct {
225#if defined(ARM_MULTILIB_ARCH_V4)
226 uint32_t register_r4;
227 uint32_t register_r5;
228 uint32_t register_r6;
229 uint32_t register_r7;
230 uint32_t register_r8;
231 uint32_t register_r9;
232 uint32_t register_r10;
233 uint32_t register_fp;
234 uint32_t register_sp;
235 uint32_t register_lr;
236 uint32_t isr_dispatch_disable;
237#elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M)
238 uint32_t register_r4;
239 uint32_t register_r5;
240 uint32_t register_r6;
241 uint32_t register_r7;
242 uint32_t register_r8;
243 uint32_t register_r9;
244 uint32_t register_r10;
245 uint32_t register_r11;
246 void *register_lr;
247 void *register_sp;
248 uint32_t isr_nest_level;
249#else
250 void *register_sp;
251#endif
252 uint32_t thread_id;
253#ifdef ARM_MULTILIB_VFP
254 uint64_t register_d8;
255 uint64_t register_d9;
256 uint64_t register_d10;
257 uint64_t register_d11;
258 uint64_t register_d12;
259 uint64_t register_d13;
260 uint64_t register_d14;
261 uint64_t register_d15;
262#endif
263#ifdef RTEMS_SMP
264 volatile bool is_executing;
265#endif
267
268static inline void _ARM_Data_memory_barrier( void )
269{
270#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS
271 __asm__ volatile ( "dmb" : : : "memory" );
272#else
274#endif
275}
276
277static inline void _ARM_Data_synchronization_barrier( void )
278{
279#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS
280 __asm__ volatile ( "dsb" : : : "memory" );
281#else
283#endif
284}
285
286static inline void _ARM_Instruction_synchronization_barrier( void )
287{
288#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS
289 __asm__ volatile ( "isb" : : : "memory" );
290#else
292#endif
293}
294
295#if defined(ARM_DISABLE_INLINE_ISR_DISABLE_ENABLE)
296uint32_t arm_interrupt_disable( void );
297void arm_interrupt_enable( uint32_t level );
298void arm_interrupt_flash( uint32_t level );
299#else
300static inline uint32_t arm_interrupt_disable( void )
301{
302 uint32_t level;
303
304#if defined(ARM_MULTILIB_ARCH_V4)
305 /*
306 * Disable only normal interrupts (IRQ).
307 *
308 * In order to support fast interrupts (FIQ) such that they can do something
309 * useful, we have to disable the operating system support for FIQs. Having
310 * operating system support for them would require that FIQs are disabled
311 * during critical sections of the operating system and application. At this
312 * level IRQs and FIQs would be equal. It is true that FIQs could interrupt
313 * the non critical sections of IRQs, so here they would have a small
314 * advantage. Without operating system support, the FIQs can execute at any
315 * time (of course not during the service of another FIQ). If someone needs
316 * operating system support for a FIQ, she can trigger a software interrupt and
317 * service the request in a two-step process.
318 */
319#if __ARM_ARCH >= 7
320 __asm__ volatile (
321 "mrs %0, cpsr\n"
322 "cpsid i\n"
323 "isb"
324 : "=&r" (level)
325 );
326#else
327 uint32_t arm_switch_reg;
328
329 __asm__ volatile (
330 ARM_SWITCH_TO_ARM
331 "mrs %[level], cpsr\n"
332 "orr %[arm_switch_reg], %[level], #0x80\n"
333 "msr cpsr, %[arm_switch_reg]\n"
334 ARM_SWITCH_BACK
335 : [arm_switch_reg] "=&r" (arm_switch_reg), [level] "=&r" (level)
336 );
337#endif
338#elif defined(ARM_MULTILIB_ARCH_V7M)
339 uint32_t basepri = 0x80;
340
341 __asm__ volatile (
342 "mrs %[level], basepri\n"
343 "msr basepri_max, %[basepri]\n"
344 : [level] "=&r" (level)
345 : [basepri] "r" (basepri)
346 );
347#endif
348
349 return level;
350}
351
352static inline void arm_interrupt_enable( uint32_t level )
353{
354#if defined(ARM_MULTILIB_ARCH_V4)
355 ARM_SWITCH_REGISTERS;
356
357 __asm__ volatile (
358 ARM_SWITCH_TO_ARM
359 "msr cpsr, %[level]\n"
360 ARM_SWITCH_BACK
361 : ARM_SWITCH_OUTPUT
362 : [level] "r" (level)
363 );
364#elif defined(ARM_MULTILIB_ARCH_V7M)
365 __asm__ volatile (
366 "msr basepri, %[level]\n"
367 :
368 : [level] "r" (level)
369 );
370#endif
371}
372
373static inline void arm_interrupt_flash( uint32_t level )
374{
375#if defined(ARM_MULTILIB_ARCH_V4)
376 uint32_t arm_switch_reg;
377
378 __asm__ volatile (
379 ARM_SWITCH_TO_ARM
380 "mrs %[arm_switch_reg], cpsr\n"
381 "msr cpsr, %[level]\n"
382 "msr cpsr, %[arm_switch_reg]\n"
383 ARM_SWITCH_BACK
384 : [arm_switch_reg] "=&r" (arm_switch_reg)
385 : [level] "r" (level)
386 );
387#elif defined(ARM_MULTILIB_ARCH_V7M)
388 uint32_t basepri;
389
390 __asm__ volatile (
391 "mrs %[basepri], basepri\n"
392 "msr basepri, %[level]\n"
393 "msr basepri, %[basepri]\n"
394 : [basepri] "=&r" (basepri)
395 : [level] "r" (level)
396 );
397#endif
398}
399#endif /* !ARM_DISABLE_INLINE_ISR_DISABLE_ENABLE */
400
401#define _CPU_ISR_Disable( _isr_cookie ) \
402 do { \
403 _isr_cookie = arm_interrupt_disable(); \
404 } while (0)
405
406#define _CPU_ISR_Enable( _isr_cookie ) \
407 arm_interrupt_enable( _isr_cookie )
408
409#define _CPU_ISR_Flash( _isr_cookie ) \
410 arm_interrupt_flash( _isr_cookie )
411
412static inline bool _CPU_ISR_Is_enabled( uint32_t level )
413{
414#if defined(ARM_MULTILIB_ARCH_V4)
415 return ( level & 0x80 ) == 0;
416#elif defined(ARM_MULTILIB_ARCH_V7M)
417 return level == 0;
418#endif
419}
420
421void _CPU_ISR_Set_level( uint32_t level );
422
423uint32_t _CPU_ISR_Get_level( void );
424
425void _CPU_Context_Initialize(
426 Context_Control *the_context,
427 void *stack_area_begin,
428 size_t stack_area_size,
429 uint32_t new_level,
430 void (*entry_point)( void ),
431 bool is_fp,
432 void *tls_area
433);
434
435#define _CPU_Context_Get_SP( _context ) \
436 (_context)->register_sp
437
438#ifdef RTEMS_SMP
439 static inline bool _CPU_Context_Get_is_executing(
441 )
442 {
443 return context->is_executing;
444 }
445
446 static inline void _CPU_Context_Set_is_executing(
448 bool is_executing
449 )
450 {
451 context->is_executing = is_executing;
452 }
453
454 RTEMS_NO_RETURN void _ARM_Start_multitasking( Context_Control *heir );
455
456 #define _CPU_Start_multitasking( _heir ) _ARM_Start_multitasking( _heir )
457#endif
458
459#define _CPU_Context_Restart_self( _the_context ) \
460 _CPU_Context_restore( (_the_context) );
461
462#define _CPU_Context_Initialize_fp( _destination ) \
463 do { \
464 *(*(_destination)) = _CPU_Null_fp_context; \
465 } while (0)
466
470void _CPU_Initialize( void );
471
472typedef void ( *CPU_ISR_handler )( void );
473
475 uint32_t vector,
476 CPU_ISR_handler new_handler,
477 CPU_ISR_handler *old_handler
478);
479
484
485RTEMS_NO_RETURN void _CPU_Context_switch_no_return(
486 Context_Control *executing,
487 Context_Control *heir
488);
489
490RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context );
491
492#if defined(ARM_MULTILIB_ARCH_V7M)
493 RTEMS_NO_RETURN void _ARMV7M_Start_multitasking( Context_Control *heir );
494 #define _CPU_Start_multitasking _ARMV7M_Start_multitasking
495#endif
496
497#ifdef RTEMS_SMP
498 uint32_t _CPU_SMP_Initialize( void );
499
500 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
501
502 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
503
504 void _CPU_SMP_Prepare_start_multitasking( void );
505
506 static inline uint32_t _CPU_SMP_Get_current_processor( void )
507 {
508 uint32_t mpidr;
509
510 /* Use ARMv7 Multiprocessor Affinity Register (MPIDR) */
511 __asm__ volatile (
512 "mrc p15, 0, %[mpidr], c0, c0, 5\n"
513 : [mpidr] "=&r" (mpidr)
514 );
515
516 return mpidr & 0xffU;
517 }
518
519 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
520
521 static inline void _ARM_Send_event( void )
522 {
523 __asm__ volatile ( "sev" : : : "memory" );
524 }
525
526 static inline void _ARM_Wait_for_event( void )
527 {
528 __asm__ volatile ( "wfe" : : : "memory" );
529 }
530#endif
531
532
533static inline uint32_t CPU_swap_u32( uint32_t value )
534{
535#if defined(__thumb2__)
536 __asm__ volatile (
537 "rev %0, %0"
538 : "=r" (value)
539 : "0" (value)
540 );
541 return value;
542#elif defined(__thumb__)
543 uint32_t byte1, byte2, byte3, byte4, swapped;
544
545 byte4 = (value >> 24) & 0xff;
546 byte3 = (value >> 16) & 0xff;
547 byte2 = (value >> 8) & 0xff;
548 byte1 = value & 0xff;
549
550 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
551 return swapped;
552#else
553 uint32_t tmp = value; /* make compiler warnings go away */
554 __asm__ volatile ("EOR %1, %0, %0, ROR #16\n"
555 "BIC %1, %1, #0xff0000\n"
556 "MOV %0, %0, ROR #8\n"
557 "EOR %0, %0, %1, LSR #8\n"
558 : "=r" (value), "=r" (tmp)
559 : "0" (value), "1" (tmp));
560 return value;
561#endif
562}
563
564static inline uint16_t CPU_swap_u16( uint16_t value )
565{
566#if defined(__thumb2__)
567 __asm__ volatile (
568 "rev16 %0, %0"
569 : "=r" (value)
570 : "0" (value)
571 );
572 return value;
573#else
574 return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU));
575#endif
576}
577
578typedef uint32_t CPU_Counter_ticks;
579
580uint32_t _CPU_Counter_frequency( void );
581
582CPU_Counter_ticks _CPU_Counter_read( void );
583
584RTEMS_NO_RETURN void *_CPU_Thread_Idle_body( uintptr_t ignored );
585
586#if defined(ARM_MULTILIB_ARCH_V4)
587
588typedef enum {
589 ARM_EXCEPTION_RESET = 0,
590 ARM_EXCEPTION_UNDEF = 1,
591 ARM_EXCEPTION_SWI = 2,
592 ARM_EXCEPTION_PREF_ABORT = 3,
593 ARM_EXCEPTION_DATA_ABORT = 4,
594 ARM_EXCEPTION_RESERVED = 5,
595 ARM_EXCEPTION_IRQ = 6,
596 ARM_EXCEPTION_FIQ = 7,
597 MAX_EXCEPTIONS = 8,
598 ARM_EXCEPTION_MAKE_ENUM_32_BIT = 0x7fffffff
599} Arm_symbolic_exception_name;
600
601#endif /* defined(ARM_MULTILIB_ARCH_V4) */
602
603typedef struct {
604 uint32_t register_fpexc;
605 uint32_t register_fpscr;
606 uint64_t register_d0;
607 uint64_t register_d1;
608 uint64_t register_d2;
609 uint64_t register_d3;
610 uint64_t register_d4;
611 uint64_t register_d5;
612 uint64_t register_d6;
613 uint64_t register_d7;
614 uint64_t register_d8;
615 uint64_t register_d9;
616 uint64_t register_d10;
617 uint64_t register_d11;
618 uint64_t register_d12;
619 uint64_t register_d13;
620 uint64_t register_d14;
621 uint64_t register_d15;
622 uint64_t register_d16;
623 uint64_t register_d17;
624 uint64_t register_d18;
625 uint64_t register_d19;
626 uint64_t register_d20;
627 uint64_t register_d21;
628 uint64_t register_d22;
629 uint64_t register_d23;
630 uint64_t register_d24;
631 uint64_t register_d25;
632 uint64_t register_d26;
633 uint64_t register_d27;
634 uint64_t register_d28;
635 uint64_t register_d29;
636 uint64_t register_d30;
637 uint64_t register_d31;
639
640typedef struct {
641 union {
642 struct {
643 uint32_t register_r0;
644 uint32_t register_r1;
645 uint32_t register_r2;
646 uint32_t register_r3;
647 uint32_t register_r4;
648 uint32_t register_r5;
649 uint32_t register_r6;
650 uint32_t register_r7;
651 uint32_t register_r8;
652 uint32_t register_r9;
653 uint32_t register_r10;
654 uint32_t register_r11;
655 uint32_t register_r12;
656 uint32_t register_sp;
657 void *register_lr;
658 void *register_pc;
659 };
660
661 uint32_t registers[ 16 ];
662 };
663#if defined(ARM_MULTILIB_ARCH_V4)
664 uint32_t register_cpsr;
665 Arm_symbolic_exception_name vector;
666#elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M)
667 uint32_t register_xpsr;
668 uint32_t vector;
669#endif
670 const ARM_VFP_context *vfp_context;
671 uint32_t reserved_for_stack_alignment;
673
675
676RTEMS_NO_RETURN void _ARM_Exception_default( CPU_Exception_frame *frame );
677
679typedef uintptr_t CPU_Uint32ptr;
680
681#ifdef __cplusplus
682}
683#endif
684
685#endif /* ASM */
686
689#endif /* _RTEMS_SCORE_CPU_H */
This header file provides defines derived from ARM multilib defines.
This header file provides basic definitions used by the API and the implementation.
#define RTEMS_COMPILER_MEMORY_BARRIER()
This macro forbids the compiler to reorder read and write commands around it.
Definition: basedefs.h:258
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
#define CPU_swap_u16(value)
Definition: cpu.h:597
#define _CPU_ISR_Set_level(_new_level)
Definition: cpu.h:378
rtems_termios_device_context * context
Definition: console-config.c:62
Definition: cpu.h:603
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Thread register context.
Definition: cpu.h:173