RTEMS 6.1-rc7
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cpu.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
9/*
10 * This include file contains information pertaining to the Moxie
11 * processor.
12 *
13 * Copyright (c) 2013 Anthony Green
14 *
15 * Based on code with the following copyright..
16 * COPYRIGHT (c) 1989-2006, 2010.
17 * On-Line Applications Research Corporation (OAR).
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
21 * are met:
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
32 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 */
40
41#ifndef _RTEMS_SCORE_CPU_H
42#define _RTEMS_SCORE_CPU_H
43
44#ifdef __cplusplus
45extern "C" {
46#endif
47
49#include <rtems/score/moxie.h> /* pick up machine definitions */
50
51#include <rtems/bspIo.h> /* printk */
52
53/* conditional compilation parameters */
54
55/*
56 * Should this target use 16 or 32 bit object Ids?
57 *
58 */
59#define RTEMS_USE_32_BIT_OBJECT
60
61/*
62 * Does the CPU follow the simple vectored interrupt model?
63 *
64 * If TRUE, then RTEMS allocates the vector table it internally manages.
65 * If FALSE, then the BSP is assumed to allocate and manage the vector
66 * table
67 *
68 * MOXIE Specific Information:
69 *
70 * XXX document implementation including references if appropriate
71 */
72#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
73
74#define CPU_HARDWARE_FP FALSE
75
76#define CPU_SOFTWARE_FP FALSE
77
78#define CPU_ALL_TASKS_ARE_FP FALSE
79
80#define CPU_IDLE_TASK_IS_FP FALSE
81
82#define CPU_USE_DEFERRED_FP_SWITCH FALSE
83
84#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
85
86/*
87 * Does the stack grow up (toward higher addresses) or down
88 * (toward lower addresses)?
89 *
90 * If TRUE, then the grows upward.
91 * If FALSE, then the grows toward smaller addresses.
92 *
93 * MOXIE Specific Information:
94 *
95 * XXX
96 */
97#define CPU_STACK_GROWS_UP FALSE
98
99/* FIXME: Is this the right value? */
100#define CPU_CACHE_LINE_BYTES 32
101
102#define CPU_STRUCTURE_ALIGNMENT
103
104/*
105 * The following defines the number of bits actually used in the
106 * interrupt field of the task mode. How those bits map to the
107 * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
108 *
109 * MOXIE Specific Information:
110 *
111 * XXX
112 */
113#define CPU_MODES_INTERRUPT_MASK 0x00000001
114
115#define CPU_MAXIMUM_PROCESSORS 32
116
117/*
118 * Processor defined structures required for cpukit/score.
119 *
120 * MOXIE Specific Information:
121 *
122 * XXX
123 */
124
125/* may need to put some structures here. */
126
127/*
128 * Contexts
129 *
130 * Generally there are 2 types of context to save.
131 * 1. Interrupt registers to save
132 * 2. Task level registers to save
133 *
134 * This means we have the following 3 context items:
135 * 1. task level context stuff:: Context_Control
136 * 2. floating point task stuff:: Context_Control_fp
137 * 3. special interrupt level context :: Context_Control_interrupt
138 *
139 * On some processors, it is cost-effective to save only the callee
140 * preserved registers during a task context switch. This means
141 * that the ISR code needs to save those registers which do not
142 * persist across function calls. It is not mandatory to make this
143 * distinctions between the caller/callee saves registers for the
144 * purpose of minimizing context saved during task switch and on interrupts.
145 * If the cost of saving extra registers is minimal, simplicity is the
146 * choice. Save the same context on interrupt entry as for tasks in
147 * this case.
148 *
149 * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
150 * care should be used in designing the context area.
151 *
152 * On some CPUs with hardware floating point support, the Context_Control_fp
153 * structure will not be used or it simply consist of an array of a
154 * fixed number of bytes. This is done when the floating point context
155 * is dumped by a "FP save context" type instruction and the format
156 * is not really defined by the CPU. In this case, there is no need
157 * to figure out the exact format -- only the size. Of course, although
158 * this is enough information for RTEMS, it is probably not enough for
159 * a debugger such as gdb. But that is another problem.
160 *
161 * MOXIE Specific Information:
162 *
163 * XXX
164 */
165
166#define nogap __attribute__ ((packed))
167
168typedef struct {
169 void *fp nogap;
170 void *sp nogap;
171 uint32_t r0 nogap;
172 uint32_t r1 nogap;
173 uint32_t r2 nogap;
174 uint32_t r3 nogap;
175 uint32_t r4 nogap;
176 uint32_t r5 nogap;
177 uint32_t r6 nogap;
178 uint32_t r7 nogap;
179 uint32_t r8 nogap;
180 uint32_t r9 nogap;
181 uint32_t r10 nogap;
182 uint32_t r11 nogap;
183 uint32_t r12 nogap;
184 uint32_t r13 nogap;
186
187#define _CPU_Context_Get_SP( _context ) \
188 (_context)->sp
189
190typedef struct {
193
194/*
195 * Amount of extra stack (above minimum stack size) required by
196 * system initialization thread. Remember that in a multiprocessor
197 * system the system intialization thread becomes the MP server thread.
198 *
199 * MOXIE Specific Information:
200 *
201 * It is highly unlikely the MOXIE will get used in a multiprocessor system.
202 */
203#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
204
205/*
206 * This defines the number of entries in the ISR_Vector_table managed
207 * by RTEMS.
208 *
209 * MOXIE Specific Information:
210 *
211 * XXX
212 */
213#define CPU_INTERRUPT_NUMBER_OF_VECTORS 64
214#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER \
215 (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
216
217/*
218 * This is defined if the port has a special way to report the ISR nesting
219 * level. Most ports maintain the variable _ISR_Nest_level.
220 */
221#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
222
223/*
224 * Should be large enough to run all RTEMS tests. This ensures
225 * that a "reasonable" small application should not have any problems.
226 *
227 * MOXIE Specific Information:
228 *
229 * XXX
230 */
231#define CPU_STACK_MINIMUM_SIZE (2048)
232
240#define CPU_SIZEOF_POINTER 4
241
242/*
243 * CPU's worst alignment requirement for data types on a byte boundary. This
244 * alignment does not take into account the requirements for the stack.
245 *
246 * MOXIE Specific Information:
247 *
248 * XXX
249 */
250#define CPU_ALIGNMENT 8
251
252/*
253 * This number corresponds to the byte alignment requirement for the
254 * heap handler. This alignment requirement may be stricter than that
255 * for the data types alignment specified by CPU_ALIGNMENT. It is
256 * common for the heap to follow the same alignment requirement as
257 * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap,
258 * then this should be set to CPU_ALIGNMENT.
259 *
260 * NOTE: This does not have to be a power of 2. It does have to
261 * be greater or equal to than CPU_ALIGNMENT.
262 *
263 * MOXIE Specific Information:
264 *
265 * XXX
266 */
267#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
268
269#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
270
271#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
272
273/*
274 * ISR handler macros
275 */
276
277/*
278 * Disable all interrupts for an RTEMS critical section. The previous
279 * level is returned in _level.
280 *
281 * MOXIE Specific Information:
282 *
283 * TODO: As of 7 October 2014, this method is not implemented.
284 */
285#define _CPU_ISR_Disable( _isr_cookie ) \
286 do { \
287 (_isr_cookie) = 0; \
288 } while (0)
289
290/*
291 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
292 * This indicates the end of an RTEMS critical section. The parameter
293 * _level is not modified.
294 *
295 * MOXIE Specific Information:
296 *
297 * TODO: As of 7 October 2014, this method is not implemented.
298 */
299#define _CPU_ISR_Enable( _isr_cookie ) \
300 do { \
301 (_isr_cookie) = (_isr_cookie); \
302 } while (0)
303
304/*
305 * This temporarily restores the interrupt to _level before immediately
306 * disabling them again. This is used to divide long RTEMS critical
307 * sections into two or more parts. The parameter _level is not
308 * modified.
309 *
310 * MOXIE Specific Information:
311 *
312 * TODO: As of 7 October 2014, this method is not implemented.
313 */
314#define _CPU_ISR_Flash( _isr_cookie ) \
315 do { \
316 _CPU_ISR_Enable( _isr_cookie ); \
317 _CPU_ISR_Disable( _isr_cookie ); \
318 } while (0)
319
320static inline bool _CPU_ISR_Is_enabled( uint32_t level )
321{
322 return true;
323}
324
325/*
326 * Map interrupt level in task mode onto the hardware that the CPU
327 * actually provides. Currently, interrupt levels which do not
328 * map onto the CPU in a generic fashion are undefined. Someday,
329 * it would be nice if these were "mapped" by the application
330 * via a callout. For example, m68k has 8 levels 0 - 7, levels
331 * 8 - 255 would be available for bsp/application specific meaning.
332 * This could be used to manage a programmable interrupt controller
333 * via the rtems_task_mode directive.
334 *
335 * MOXIE Specific Information:
336 *
337 * TODO: As of 7 October 2014, this method is not implemented.
338 */
339#define _CPU_ISR_Set_level( _new_level ) \
340 { \
341 if (_new_level) asm volatile ( "nop\n" ); \
342 else asm volatile ( "nop\n" ); \
343 }
344
345uint32_t _CPU_ISR_Get_level( void );
346
347/* end of ISR handler macros */
348
349/* Context handler macros */
350
351/*
352 * Initialize the context to a state suitable for starting a
353 * task after a context restore operation. Generally, this
354 * involves:
355 *
356 * - setting a starting address
357 * - preparing the stack
358 * - preparing the stack and frame pointers
359 * - setting the proper interrupt level in the context
360 * - initializing the floating point context
361 *
362 * This routine generally does not set any unnecessary register
363 * in the context. The state of the "general data" registers is
364 * undefined at task start time.
365 *
366 * NOTE: This is_fp parameter is TRUE if the thread is to be a floating
367 * point thread. This is typically only used on CPUs where the
368 * FPU may be easily disabled by software such as on the SPARC
369 * where the PSR contains an enable FPU bit.
370 *
371 * MOXIE Specific Information:
372 *
373 * TODO: As of 7 October 2014, this method does not ensure that the context
374 * is set up with interrupts disabled/enabled as requested.
375 */
376#define CPU_CCR_INTERRUPTS_ON 0x80
377#define CPU_CCR_INTERRUPTS_OFF 0x00
378
379#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
380 _isr, _entry_point, _is_fp, _tls_area ) \
381 /* Locate Me */ \
382 do { \
383 uintptr_t _stack; \
384 \
385 (void) _is_fp; /* avoid warning for being unused */ \
386 (void) _isr; /* avoid warning for being unused */ \
387 _stack = ((uintptr_t)(_stack_base)) + (_size) - 8; \
388 *((void (**)(void))(_stack)) = (_entry_point); \
389 _stack -= 4; \
390 (_the_context)->fp = (void *)_stack; \
391 (_the_context)->sp = (void *)_stack; \
392 } while (0)
393
394
395/*
396 * This routine is responsible for somehow restarting the currently
397 * executing task. If you are lucky, then all that is necessary
398 * is restoring the context. Otherwise, there will need to be
399 * a special assembly routine which does something special in this
400 * case. Context_Restore should work most of the time. It will
401 * not work if restarting self conflicts with the stack frame
402 * assumptions of restoring a context.
403 *
404 * MOXIE Specific Information:
405 *
406 * XXX
407 */
408#define _CPU_Context_Restart_self( _the_context ) \
409 _CPU_Context_restore( (_the_context) );
410
411/* end of Context handler macros */
412
413#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
414
415#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
416
417/* functions */
418
419/*
420 * _CPU_Initialize
421 *
422 * This routine performs CPU dependent initialization.
423 *
424 * MOXIE Specific Information:
425 *
426 * XXX
427 */
428void _CPU_Initialize(void);
429
430typedef void ( *CPU_ISR_handler )( uint32_t );
431
433 uint32_t vector,
434 CPU_ISR_handler new_handler,
435 CPU_ISR_handler *old_handler
436);
437
438RTEMS_NO_RETURN void *_CPU_Thread_Idle_body( uintptr_t );
439
440/*
441 * _CPU_Context_switch
442 *
443 * This routine switches from the run context to the heir context.
444 *
445 * MOXIE Specific Information:
446 *
447 * XXX
448 */
450 Context_Control *run,
451 Context_Control *heir
452);
453
454/*
455 * _CPU_Context_restore
456 *
457 * This routine is generallu used only to restart self in an
458 * efficient manner. It may simply be a label in _CPU_Context_switch.
459 *
460 * NOTE: May be unnecessary to reload some registers.
461 *
462 * MOXIE Specific Information:
463 *
464 * XXX
465 */
466RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context );
467
477typedef struct {
478 uint32_t integer_registers [16];
480
487
488/* The following routine swaps the endian format of an unsigned int.
489 * It must be static because it is referenced indirectly.
490 *
491 * This version will work on any processor, but if there is a better
492 * way for your CPU PLEASE use it. The most common way to do this is to:
493 *
494 * swap least significant two bytes with 16-bit rotate
495 * swap upper and lower 16-bits
496 * swap most significant two bytes with 16-bit rotate
497 *
498 * Some CPUs have special instructions which swap a 32-bit quantity in
499 * a single instruction (e.g. i486). It is probably best to avoid
500 * an "endian swapping control bit" in the CPU. One good reason is
501 * that interrupts would probably have to be disabled to ensure that
502 * an interrupt does not try to access the same "chunk" with the wrong
503 * endian. Another good reason is that on some CPUs, the endian bit
504 * endianness for ALL fetches -- both code and data -- so the code
505 * will be fetched incorrectly.
506 *
507 * MOXIE Specific Information:
508 *
509 * This is the generic implementation.
510 */
511static inline uint32_t CPU_swap_u32(
512 uint32_t value
513)
514{
515 uint32_t byte1, byte2, byte3, byte4, swapped;
516
517 byte4 = (value >> 24) & 0xff;
518 byte3 = (value >> 16) & 0xff;
519 byte2 = (value >> 8) & 0xff;
520 byte1 = value & 0xff;
521
522 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
523 return( swapped );
524}
525
526#define CPU_swap_u16( value ) \
527 (((value&0xff) << 8) | ((value >> 8)&0xff))
528
529typedef uint32_t CPU_Counter_ticks;
530
531uint32_t _CPU_Counter_frequency( void );
532
533CPU_Counter_ticks _CPU_Counter_read( void );
534
536typedef uintptr_t CPU_Uint32ptr;
537
538#ifdef __cplusplus
539}
540#endif
541
542#endif
This header file provides basic definitions used by the API and the implementation.
This header file provides the kernel character input/output support API.
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
#define sp
stack-pointer *‍/
Definition: regs.h:64
#define fp
frame-pointer *‍/
Definition: regs.h:65
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
uint32_t special_interrupt_register
Definition: cpu.h:191
Thread register context.
Definition: cpu.h:173