RTEMS 6.1-rc7
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cpu.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (c) 2011 embedded brains GmbH & Co. KG
13 *
14 * Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
15 *
16 * COPYRIGHT (c) 1989-2004.
17 * On-Line Applications Research Corporation (OAR).
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
21 * are met:
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
32 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 */
40
41#ifndef _RTEMS_SCORE_CPU_H
42#define _RTEMS_SCORE_CPU_H
43
44#ifdef __cplusplus
45extern "C" {
46#endif
47
49#include <rtems/score/nios2.h>
50
51#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
52
53#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
54
55#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
56
57#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE
58
59#define CPU_ISR_PASSES_FRAME_POINTER FALSE
60
61#define CPU_HARDWARE_FP FALSE
62
63#define CPU_SOFTWARE_FP FALSE
64
65#define CPU_ALL_TASKS_ARE_FP FALSE
66
67#define CPU_IDLE_TASK_IS_FP FALSE
68
69#define CPU_USE_DEFERRED_FP_SWITCH FALSE
70
71#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
72
73#define CPU_STACK_GROWS_UP FALSE
74
75/* FIXME: Is this the right value? */
76#define CPU_CACHE_LINE_BYTES 32
77
78#define CPU_STRUCTURE_ALIGNMENT \
79 RTEMS_SECTION( ".sdata" ) RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
80
81#define CPU_STACK_MINIMUM_SIZE (4 * 1024)
82
83#define CPU_SIZEOF_POINTER 4
84
85/*
86 * Alignment value according to "Nios II Processor Reference" chapter 7
87 * "Application Binary Interface" section "Memory Alignment".
88 */
89#define CPU_ALIGNMENT 4
90
91#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
92
93/*
94 * Alignment value according to "Nios II Processor Reference" chapter 7
95 * "Application Binary Interface" section "Stacks".
96 */
97#define CPU_STACK_ALIGNMENT 4
98
99#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
100
101/*
102 * A Nios II configuration with an external interrupt controller (EIC) supports
103 * up to 64 interrupt levels. A Nios II configuration with an internal
104 * interrupt controller (IIC) has only two interrupt levels (enabled and
105 * disabled). The _CPU_ISR_Get_level() and _CPU_ISR_Set_level() functions will
106 * take care about configuration specific mappings.
107 */
108#define CPU_MODES_INTERRUPT_MASK 0x3f
109
110#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
111
112#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
113
114#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
115
116#define CPU_MAXIMUM_PROCESSORS 32
117
118#ifndef ASM
119
129typedef struct {
130 uint32_t r16;
131 uint32_t r17;
132 uint32_t r18;
133 uint32_t r19;
134 uint32_t r20;
135 uint32_t r21;
136 uint32_t r22;
137 uint32_t r23;
138 uint32_t fp;
139 uint32_t status;
140 uint32_t sp;
141 uint32_t ra;
142
148 uint32_t isr_dispatch_disable;
149
150 uint32_t stack_mpubase;
151 uint32_t stack_mpuacc;
153
154#define _CPU_Context_Get_SP( _context ) \
155 (_context)->sp
156
157typedef void CPU_Interrupt_frame;
158
159typedef struct {
160 uint32_t r1;
161 uint32_t r2;
162 uint32_t r3;
163 uint32_t r4;
164 uint32_t r5;
165 uint32_t r6;
166 uint32_t r7;
167 uint32_t r8;
168 uint32_t r9;
169 uint32_t r10;
170 uint32_t r11;
171 uint32_t r12;
172 uint32_t r13;
173 uint32_t r14;
174 uint32_t r15;
175 uint32_t r16;
176 uint32_t r17;
177 uint32_t r18;
178 uint32_t r19;
179 uint32_t r20;
180 uint32_t r21;
181 uint32_t r22;
182 uint32_t r23;
183 uint32_t gp;
184 uint32_t fp;
185 uint32_t sp;
186 uint32_t ra;
187 uint32_t et;
188 uint32_t ea;
189 uint32_t status;
190 uint32_t ienable;
191 uint32_t ipending;
193
214#define _CPU_ISR_Disable( _isr_cookie ) \
215 do { \
216 int _tmp; \
217 __asm__ volatile ( \
218 "rdctl %0, status\n" \
219 "movhi %1, %%hiadj(_Nios2_ISR_Status_mask)\n" \
220 "addi %1, %1, %%lo(_Nios2_ISR_Status_mask)\n" \
221 "and %1, %0, %1\n" \
222 "ori %1, %1, %%lo(_Nios2_ISR_Status_bits)\n" \
223 "wrctl status, %1" \
224 : "=&r" (_isr_cookie), "=&r" (_tmp) \
225 ); \
226 } while ( 0 )
227
234#define _CPU_ISR_Enable( _isr_cookie ) \
235 __builtin_wrctl( 0, (int) _isr_cookie )
236
248#define _CPU_ISR_Flash( _isr_cookie ) \
249 do { \
250 int _status = __builtin_rdctl( 0 ); \
251 __builtin_wrctl( 0, (int) _isr_cookie ); \
252 __builtin_wrctl( 0, _status ); \
253 } while ( 0 )
254
255bool _CPU_ISR_Is_enabled( uint32_t level );
256
265void _CPU_ISR_Set_level( uint32_t new_level );
266
280uint32_t _CPU_ISR_Get_level( void );
281
299void _CPU_Context_Initialize(
301 void *stack_area_begin,
302 size_t stack_area_size,
303 uint32_t new_level,
304 void (*entry_point)( void ),
305 bool is_fp,
306 void *tls_area
307);
308
309#define _CPU_Context_Restart_self( _the_context ) \
310 _CPU_Context_restore( (_the_context) );
311
315void _CPU_Initialize( void );
316
317typedef void ( *CPU_ISR_handler )( uint32_t );
318
320 uint32_t vector,
321 CPU_ISR_handler new_handler,
322 CPU_ISR_handler *old_handler
323);
324
325RTEMS_NO_RETURN void *_CPU_Thread_Idle_body( uintptr_t ignored );
326
328
329RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context );
330
332
333static inline uint32_t CPU_swap_u32( uint32_t value )
334{
335 uint32_t byte1, byte2, byte3, byte4, swapped;
336
337 byte4 = (value >> 24) & 0xff;
338 byte3 = (value >> 16) & 0xff;
339 byte2 = (value >> 8) & 0xff;
340 byte1 = value & 0xff;
341
342 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
343
344 return swapped;
345}
346
347#define CPU_swap_u16( value ) \
348 (((value&0xff) << 8) | ((value >> 8)&0xff))
349
350typedef uint32_t CPU_Counter_ticks;
351
352uint32_t _CPU_Counter_frequency( void );
353
354CPU_Counter_ticks _CPU_Counter_read( void );
355
357typedef uintptr_t CPU_Uint32ptr;
358
359#endif /* ASM */
360
361#ifdef __cplusplus
362}
363#endif
364
365#endif
This header file provides basic definitions used by the API and the implementation.
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
#define _CPU_ISR_Set_level(_new_level)
Definition: cpu.h:378
#define ra
return address *‍/
Definition: regs.h:66
#define sp
stack-pointer *‍/
Definition: regs.h:64
#define fp
frame-pointer *‍/
Definition: regs.h:65
#define gp
global data pointer *‍/
Definition: regs.h:63
NIOS II Set up Basic CPU Dependency Settings Based on Compiler Settings.
rtems_termios_device_context * context
Definition: console-config.c:62
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
Thread register context.
Definition: cpu.h:173