RTEMS 6.1-rc7
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asm.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
22/*
23 * COPYRIGHT:
24 *
25 * This file is based on similar code found in newlib available
26 * from ftp.cygnus.com. The file which was used had no copyright
27 * notice. This file is freely distributable as long as the source
28 * of the file is noted. This file is:
29 *
30 * COPYRIGHT (c) 2000 Canon Research Centre France SA.
31 * Emmanuel Raguet, mailto:raguet@crf.canon.fr
32 *
33 * Redistribution and use in source and binary forms, with or without
34 * modification, are permitted provided that the following conditions
35 * are met:
36 * 1. Redistributions of source code must retain the above copyright
37 * notice, this list of conditions and the following disclaimer.
38 * 2. Redistributions in binary form must reproduce the above copyright
39 * notice, this list of conditions and the following disclaimer in the
40 * documentation and/or other materials provided with the distribution.
41 *
42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
43 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
45 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
46 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
47 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
48 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
49 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
50 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
51 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
52 * POSSIBILITY OF SUCH DAMAGE.
53 *
54 */
55
56#ifndef _RTEMS_ASM_H
57#define _RTEMS_ASM_H
58
59/*
60 * Indicate we are in an assembly file and get the basic CPU definitions.
61 */
62
63#ifndef ASM
64#define ASM
65#endif
66#include <rtems/score/percpu.h>
67
77/*
78 * Recent versions of GNU cpp define variables which indicate the
79 * need for underscores and percents. If not using GNU cpp or
80 * the version does not support this, then you will obviously
81 * have to define these as appropriate.
82 */
83
84#ifndef __USER_LABEL_PREFIX__
85#define __USER_LABEL_PREFIX__ _
86#endif
87
88#ifndef __REGISTER_PREFIX__
89#define __REGISTER_PREFIX__
90#endif
91
92/* Use the right prefix for global labels. */
93
94#define SYM(x) RTEMS_XCONCAT(__USER_LABEL_PREFIX__, x)
95
96/* Use the right prefix for registers. */
97
98#define REG(x) RTEMS_XCONCAT(__REGISTER_PREFIX__, x)
99
100/*
101 * define macros for all of the registers on this CPU
102 *
103 * EXAMPLE: #define d0 REG (d0)
104 */
105
106#define r0 REG(r0)
107#define r1 REG(r1)
108#define r2 REG(r2)
109#define r3 REG(r3)
110#define r4 REG(r4)
111#define r5 REG(r5)
112#define r6 REG(r6)
113#define r7 REG(r7)
114#define r8 REG(r8)
115#define r9 REG(r9)
116#define r10 REG(r10)
117#define r11 REG(r11)
118#define r12 REG(r12)
119#define r13 REG(r13)
120#define r14 REG(r14)
121#define r15 REG(r15)
122
123#define CPSR REG(CPSR)
124
125#define SPSR REG(SPSR)
126
127#define NUM_IRQ_VECTOR 6 // IRQ number
128#define NUM_FIQ_VECTOR 7 // IRQ number
129 // //
130#define CPSR_IRQ_DISABLE 0x80 // FIQ disabled when =1
131#define CPSR_FIQ_DISABLE 0x40 // FIQ disabled when =1
132#define CPSR_THUMB_ENABLE 0x20 // Thumb mode when =1
133#define CPSR_FIQ_MODE 0x11
134#define CPSR_IRQ_MODE 0x12
135#define CPSR_SUPERVISOR_MODE 0x13
136#define CPSR_UNDEF_MODE 0x1B
137
138#define CPSR_MODE_BITS 0x1F
139
140/*
141 * Define macros to handle section beginning and ends.
142 */
143
144
145#define BEGIN_CODE_DCL .text
146#define END_CODE_DCL
147#define BEGIN_DATA_DCL .data
148#define END_DATA_DCL
149#define BEGIN_CODE .text
150#define END_CODE
151#define BEGIN_DATA
152#define END_DATA
153#define BEGIN_BSS
154#define END_BSS
155#define END
156
157/*
158 * Following must be tailor for a particular flavor of the C compiler.
159 * They may need to put underscores in front of the symbols.
160 */
161
162#define PUBLIC(sym) .globl SYM (sym)
163#define EXTERN(sym) .globl SYM (sym)
164
165#define FUNCTION_THUMB_ENTRY(name) \
166 .thumb; \
167 .thumb_func; \
168 .align 2; \
169 .globl name; \
170 .type name, %function; \
171 name:
172
173#define FUNCTION_ENTRY(name) \
174 .align 2; \
175 .globl name; \
176 .type name, %function; \
177 name:
178
179#define FUNCTION_END(name) \
180 .size name, . - name
181
182#if defined(ARM_MULTILIB_ARCH_V7M)
183 #define DEFINE_FUNCTION_ARM(name) \
184 .thumb_func ; .globl name ; name:
185#elif defined(__thumb__)
186 #define DEFINE_FUNCTION_ARM(name) \
187 .thumb_func ; .globl name ; name: ; bx pc ; \
188 .arm ; .globl name ## _arm ; name ## _arm:
189#else
190 #define DEFINE_FUNCTION_ARM(name) \
191 .globl name ; name: ; .globl name ## _arm ; name ## _arm:
192#endif
193
194.macro SWITCH_FROM_THUMB_TO_ARM
195#ifdef __thumb__
196.align 2
197 bx pc
198.arm
199#endif /* __thumb__ */
200.endm
201
202.macro SWITCH_FROM_ARM_TO_THUMB REG
203#ifdef __thumb__
204 add \REG, pc, #1
205 bx \REG
206.thumb
207#endif /* __thumb__ */
208.endm
209
210.macro SWITCH_FROM_THUMB_2_TO_ARM
211#ifdef __thumb2__
212.align 2
213 bx pc
214.arm
215#endif /* __thumb__ */
216.endm
217
218.macro SWITCH_FROM_ARM_TO_THUMB_2 REG
219#ifdef __thumb2__
220 add \REG, pc, #1
221 bx \REG
222.thumb
223#endif /* __thumb__ */
224.endm
225
226.macro BLX_TO_THUMB_1 TARGET
227#if defined(__thumb__) && !defined(__thumb2__)
228 add lr, pc, #1
229 bx lr
230.thumb
231 bl \TARGET
232.align 2
233 bx pc
234.arm
235#else
236 bl \TARGET
237#endif
238.endm
239
240.macro GET_SELF_CPU_CONTROL REG
241#ifdef RTEMS_SMP
242 /* Use PL1 only Thread ID Register (TPIDRPRW) */
243 mrc p15, 0, \REG, c13, c0, 4
244#else
245 ldr \REG, =_Per_CPU_Information
246#endif
247.endm
248
251#endif /* _RTEMS_ASM_H */
CPU_STRUCTURE_ALIGNMENT Per_CPU_Control_envelope _Per_CPU_Information[]
Set of Per CPU Core Information.
Definition: asm.h:171
#define pc
pc, used on mips16 *‍/
Definition: regs.h:67
This header file provides the interfaces of the Per-CPU Information.