RTEMS 6.1-rc7
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cpuimpl.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#ifndef _RTEMS_SCORE_CPUIMPL_H
37#define _RTEMS_SCORE_CPUIMPL_H
38
39#include <rtems/score/cpu.h>
40
51#define CPU_PER_CPU_CONTROL_SIZE 0
52
53#define CPU_INTERRUPT_FRAME_SIZE 56
54
55#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
56
57#define MICROBLAZE_INTERRUPT_FRAME_R3 0
58#define MICROBLAZE_INTERRUPT_FRAME_R4 4
59#define MICROBLAZE_INTERRUPT_FRAME_R5 8
60#define MICROBLAZE_INTERRUPT_FRAME_R6 12
61#define MICROBLAZE_INTERRUPT_FRAME_R7 16
62#define MICROBLAZE_INTERRUPT_FRAME_R8 20
63#define MICROBLAZE_INTERRUPT_FRAME_R9 24
64#define MICROBLAZE_INTERRUPT_FRAME_R10 28
65#define MICROBLAZE_INTERRUPT_FRAME_R11 32
66#define MICROBLAZE_INTERRUPT_FRAME_R12 36
67#define MICROBLAZE_INTERRUPT_FRAME_R14 40
68#define MICROBLAZE_INTERRUPT_FRAME_R15 44
69#define MICROBLAZE_INTERRUPT_FRAME_R18 48
70#define MICROBLAZE_INTERRUPT_FRAME_MSR 52
71
72#ifndef ASM
73
74#ifdef __cplusplus
75extern "C" {
76#endif
77
78void _CPU_Context_volatile_clobber( uintptr_t pattern );
79
80void _CPU_Context_validate( uintptr_t pattern );
81
82static inline void _CPU_Instruction_illegal( void )
83{
84 __asm__ volatile ( ".word 0x0" );
85}
86
87static inline void _CPU_Instruction_no_operation( void )
88{
89 __asm__ volatile ( "nop" );
90}
91
92static inline void _CPU_Use_thread_local_storage(
94)
95{
96 /*
97 * There is nothing to do since the thread-local storage area is obtained by
98 * calling __tls_get_addr().
99 */
100 (void) context;
101}
102
103static inline void *_CPU_Get_TLS_thread_pointer(
105)
106{
107 return (void *) context->thread_pointer;
108}
109
110#ifdef __cplusplus
111}
112#endif
113
114#endif /* ASM */
115
118#endif /* _RTEMS_SCORE_CPUIMPL_H */
rtems_termios_device_context * context
Definition: console-config.c:62
Thread register context.
Definition: cpu.h:173