RTEMS 6.1-rc7
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Data Fields

External Interrupt/Event Controller. More...

#include <stm32h723xx.h>

Data Fields

__IO uint32_t RTSR1
 
__IO uint32_t FTSR1
 
__IO uint32_t SWIER1
 
__IO uint32_t D3PMR1
 
__IO uint32_t D3PCR1L
 
__IO uint32_t D3PCR1H
 
uint32_t RESERVED1 [2]
 
__IO uint32_t RTSR2
 
__IO uint32_t FTSR2
 
__IO uint32_t SWIER2
 
__IO uint32_t D3PMR2
 
__IO uint32_t D3PCR2L
 
__IO uint32_t D3PCR2H
 
uint32_t RESERVED2 [2]
 
__IO uint32_t RTSR3
 
__IO uint32_t FTSR3
 
__IO uint32_t SWIER3
 
__IO uint32_t D3PMR3
 
__IO uint32_t D3PCR3L
 
__IO uint32_t D3PCR3H
 
uint32_t RESERVED3 [10]
 
__IO uint32_t IMR1
 
__IO uint32_t EMR1
 
__IO uint32_t PR1
 
uint32_t RESERVED4
 
__IO uint32_t IMR2
 
__IO uint32_t EMR2
 
__IO uint32_t PR2
 
uint32_t RESERVED5
 
__IO uint32_t IMR3
 
__IO uint32_t EMR3
 
__IO uint32_t PR3
 
uint32_t RESERVED6 [5]
 
__IO uint32_t C2IMR1
 
__IO uint32_t C2EMR1
 
__IO uint32_t C2PR1
 
uint32_t RESERVED7
 
__IO uint32_t C2IMR2
 
__IO uint32_t C2EMR2
 
__IO uint32_t C2PR2
 
uint32_t RESERVED8
 
__IO uint32_t C2IMR3
 
__IO uint32_t C2EMR3
 
__IO uint32_t C2PR3
 

Detailed Description

External Interrupt/Event Controller.

Field Documentation

◆ C2EMR1

__IO uint32_t EXTI_TypeDef::C2EMR1

EXTI Event mask register, Address offset: 0xC4

◆ C2EMR2

__IO uint32_t EXTI_TypeDef::C2EMR2

EXTI Event mask register, Address offset: 0xD4

◆ C2EMR3

__IO uint32_t EXTI_TypeDef::C2EMR3

EXTI Event mask register, Address offset: 0xE4

◆ C2IMR1

__IO uint32_t EXTI_TypeDef::C2IMR1

EXTI Interrupt mask register, Address offset: 0xC0

◆ C2IMR2

__IO uint32_t EXTI_TypeDef::C2IMR2

EXTI Interrupt mask register, Address offset: 0xD0

◆ C2IMR3

__IO uint32_t EXTI_TypeDef::C2IMR3

EXTI Interrupt mask register, Address offset: 0xE0

◆ C2PR1

__IO uint32_t EXTI_TypeDef::C2PR1

EXTI Pending register, Address offset: 0xC8

◆ C2PR2

__IO uint32_t EXTI_TypeDef::C2PR2

EXTI Pending register, Address offset: 0xD8

◆ C2PR3

__IO uint32_t EXTI_TypeDef::C2PR3

EXTI Pending register, Address offset: 0xE8

◆ D3PCR1H

__IO uint32_t EXTI_TypeDef::D3PCR1H

EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14

◆ D3PCR1L

__IO uint32_t EXTI_TypeDef::D3PCR1L

EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10

◆ D3PCR2H

__IO uint32_t EXTI_TypeDef::D3PCR2H

EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34

◆ D3PCR2L

__IO uint32_t EXTI_TypeDef::D3PCR2L

EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30

◆ D3PCR3H

__IO uint32_t EXTI_TypeDef::D3PCR3H

EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54

◆ D3PCR3L

__IO uint32_t EXTI_TypeDef::D3PCR3L

EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50

◆ D3PMR1

__IO uint32_t EXTI_TypeDef::D3PMR1

EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C

◆ D3PMR2

__IO uint32_t EXTI_TypeDef::D3PMR2

EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C

◆ D3PMR3

__IO uint32_t EXTI_TypeDef::D3PMR3

EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C

◆ EMR1

__IO uint32_t EXTI_TypeDef::EMR1

EXTI Event mask register, Address offset: 0x84

◆ EMR2

__IO uint32_t EXTI_TypeDef::EMR2

EXTI Event mask register, Address offset: 0x94

◆ EMR3

__IO uint32_t EXTI_TypeDef::EMR3

EXTI Event mask register, Address offset: 0xA4

◆ FTSR1

__IO uint32_t EXTI_TypeDef::FTSR1

EXTI Falling trigger selection register, Address offset: 0x04

◆ FTSR2

__IO uint32_t EXTI_TypeDef::FTSR2

EXTI Falling trigger selection register, Address offset: 0x24

◆ FTSR3

__IO uint32_t EXTI_TypeDef::FTSR3

EXTI Falling trigger selection register, Address offset: 0x44

◆ IMR1

__IO uint32_t EXTI_TypeDef::IMR1

EXTI Interrupt mask register, Address offset: 0x80

◆ IMR2

__IO uint32_t EXTI_TypeDef::IMR2

EXTI Interrupt mask register, Address offset: 0x90

◆ IMR3

__IO uint32_t EXTI_TypeDef::IMR3

EXTI Interrupt mask register, Address offset: 0xA0

◆ PR1

__IO uint32_t EXTI_TypeDef::PR1

EXTI Pending register, Address offset: 0x88

◆ PR2

__IO uint32_t EXTI_TypeDef::PR2

EXTI Pending register, Address offset: 0x98

◆ PR3

__IO uint32_t EXTI_TypeDef::PR3

EXTI Pending register, Address offset: 0xA8

◆ RESERVED1

uint32_t EXTI_TypeDef::RESERVED1

Reserved, 0x18 to 0x1C

◆ RESERVED2

uint32_t EXTI_TypeDef::RESERVED2

Reserved, 0x38 to 0x3C

◆ RESERVED3

uint32_t EXTI_TypeDef::RESERVED3

Reserved, 0x58 to 0x7C

◆ RESERVED4

uint32_t EXTI_TypeDef::RESERVED4

Reserved, 0x8C

◆ RESERVED5

uint32_t EXTI_TypeDef::RESERVED5

Reserved, 0x9C

◆ RESERVED6

uint32_t EXTI_TypeDef::RESERVED6

Reserved, 0xAC to 0xBC

◆ RESERVED7

uint32_t EXTI_TypeDef::RESERVED7

Reserved, 0xCC

◆ RESERVED8

uint32_t EXTI_TypeDef::RESERVED8

Reserved, 0xDC

◆ RTSR1

__IO uint32_t EXTI_TypeDef::RTSR1

EXTI Rising trigger selection register, Address offset: 0x00

◆ RTSR2

__IO uint32_t EXTI_TypeDef::RTSR2

EXTI Rising trigger selection register, Address offset: 0x20

◆ RTSR3

__IO uint32_t EXTI_TypeDef::RTSR3

EXTI Rising trigger selection register, Address offset: 0x40

◆ SWIER1

__IO uint32_t EXTI_TypeDef::SWIER1

EXTI Software interrupt event register, Address offset: 0x08

◆ SWIER2

__IO uint32_t EXTI_TypeDef::SWIER2

EXTI Software interrupt event register, Address offset: 0x28

◆ SWIER3

__IO uint32_t EXTI_TypeDef::SWIER3

EXTI Software interrupt event register, Address offset: 0x48


The documentation for this struct was generated from the following files: