63#ifndef _RTEMS_SCORE_CPU_H
64#define _RTEMS_SCORE_CPU_H
92#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
101#define CPU_ISR_PASSES_FRAME_POINTER TRUE
121#if ( MIPS_HAS_FPU == 1 )
122#define CPU_HARDWARE_FP TRUE
124#define CPU_HARDWARE_FP FALSE
147#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP
161#define CPU_IDLE_TASK_IS_FP FALSE
189#define CPU_USE_DEFERRED_FP_SWITCH TRUE
191#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
202#define CPU_STACK_GROWS_UP FALSE
205#define CPU_CACHE_LINE_BYTES 16
207#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
215#define CPU_MODES_INTERRUPT_MASK 0x000000ff
217#define CPU_SIZEOF_POINTER 4
219#define CPU_MAXIMUM_PROCESSORS 32
268#if (__mips == 1) || (__mips == 32)
269#define __MIPS_REGISTER_TYPE uint32_t
270#define __MIPS_FPU_REGISTER_TYPE uint32_t
272#define __MIPS_REGISTER_TYPE uint64_t
273#define __MIPS_FPU_REGISTER_TYPE uint64_t
275#error "mips register size: unknown architecture level!!"
278 __MIPS_REGISTER_TYPE s0;
279 __MIPS_REGISTER_TYPE s1;
280 __MIPS_REGISTER_TYPE s2;
281 __MIPS_REGISTER_TYPE s3;
282 __MIPS_REGISTER_TYPE s4;
283 __MIPS_REGISTER_TYPE s5;
284 __MIPS_REGISTER_TYPE s6;
285 __MIPS_REGISTER_TYPE s7;
286 __MIPS_REGISTER_TYPE
sp;
287 __MIPS_REGISTER_TYPE
fp;
288 __MIPS_REGISTER_TYPE
ra;
289 __MIPS_REGISTER_TYPE c0_sr;
290 __MIPS_REGISTER_TYPE c0_epc;
293#define _CPU_Context_Get_SP( _context ) \
294 (uintptr_t) (_context)->sp
301#if ( CPU_HARDWARE_FP == TRUE )
302 __MIPS_FPU_REGISTER_TYPE fp0;
303 __MIPS_FPU_REGISTER_TYPE fp1;
304 __MIPS_FPU_REGISTER_TYPE fp2;
305 __MIPS_FPU_REGISTER_TYPE fp3;
306 __MIPS_FPU_REGISTER_TYPE fp4;
307 __MIPS_FPU_REGISTER_TYPE fp5;
308 __MIPS_FPU_REGISTER_TYPE fp6;
309 __MIPS_FPU_REGISTER_TYPE fp7;
310 __MIPS_FPU_REGISTER_TYPE fp8;
311 __MIPS_FPU_REGISTER_TYPE fp9;
312 __MIPS_FPU_REGISTER_TYPE fp10;
313 __MIPS_FPU_REGISTER_TYPE fp11;
314 __MIPS_FPU_REGISTER_TYPE fp12;
315 __MIPS_FPU_REGISTER_TYPE fp13;
316 __MIPS_FPU_REGISTER_TYPE fp14;
317 __MIPS_FPU_REGISTER_TYPE fp15;
318 __MIPS_FPU_REGISTER_TYPE fp16;
319 __MIPS_FPU_REGISTER_TYPE fp17;
320 __MIPS_FPU_REGISTER_TYPE fp18;
321 __MIPS_FPU_REGISTER_TYPE fp19;
322 __MIPS_FPU_REGISTER_TYPE fp20;
323 __MIPS_FPU_REGISTER_TYPE fp21;
324 __MIPS_FPU_REGISTER_TYPE fp22;
325 __MIPS_FPU_REGISTER_TYPE fp23;
326 __MIPS_FPU_REGISTER_TYPE fp24;
327 __MIPS_FPU_REGISTER_TYPE fp25;
328 __MIPS_FPU_REGISTER_TYPE fp26;
329 __MIPS_FPU_REGISTER_TYPE fp27;
330 __MIPS_FPU_REGISTER_TYPE fp28;
331 __MIPS_FPU_REGISTER_TYPE fp29;
332 __MIPS_FPU_REGISTER_TYPE fp30;
333 __MIPS_FPU_REGISTER_TYPE fp31;
363 __MIPS_REGISTER_TYPE r0;
364 __MIPS_REGISTER_TYPE at;
365 __MIPS_REGISTER_TYPE v0;
366 __MIPS_REGISTER_TYPE v1;
367 __MIPS_REGISTER_TYPE a0;
368 __MIPS_REGISTER_TYPE a1;
369 __MIPS_REGISTER_TYPE a2;
370 __MIPS_REGISTER_TYPE a3;
371 __MIPS_REGISTER_TYPE t0;
372 __MIPS_REGISTER_TYPE t1;
373 __MIPS_REGISTER_TYPE t2;
374 __MIPS_REGISTER_TYPE t3;
375 __MIPS_REGISTER_TYPE t4;
376 __MIPS_REGISTER_TYPE t5;
377 __MIPS_REGISTER_TYPE t6;
378 __MIPS_REGISTER_TYPE t7;
379 __MIPS_REGISTER_TYPE s0;
380 __MIPS_REGISTER_TYPE s1;
381 __MIPS_REGISTER_TYPE s2;
382 __MIPS_REGISTER_TYPE s3;
383 __MIPS_REGISTER_TYPE s4;
384 __MIPS_REGISTER_TYPE s5;
385 __MIPS_REGISTER_TYPE s6;
386 __MIPS_REGISTER_TYPE s7;
387 __MIPS_REGISTER_TYPE t8;
388 __MIPS_REGISTER_TYPE t9;
389 __MIPS_REGISTER_TYPE
k0;
390 __MIPS_REGISTER_TYPE
k1;
391 __MIPS_REGISTER_TYPE
gp;
392 __MIPS_REGISTER_TYPE
sp;
393 __MIPS_REGISTER_TYPE
fp;
394 __MIPS_REGISTER_TYPE
ra;
395 __MIPS_REGISTER_TYPE c0_sr;
397 __MIPS_REGISTER_TYPE mdlo;
398 __MIPS_REGISTER_TYPE mdhi;
399 __MIPS_REGISTER_TYPE badvaddr;
400 __MIPS_REGISTER_TYPE cause;
401 __MIPS_REGISTER_TYPE epc;
403 __MIPS_FPU_REGISTER_TYPE f0;
404 __MIPS_FPU_REGISTER_TYPE f1;
405 __MIPS_FPU_REGISTER_TYPE f2;
406 __MIPS_FPU_REGISTER_TYPE f3;
407 __MIPS_FPU_REGISTER_TYPE f4;
408 __MIPS_FPU_REGISTER_TYPE f5;
409 __MIPS_FPU_REGISTER_TYPE f6;
410 __MIPS_FPU_REGISTER_TYPE f7;
411 __MIPS_FPU_REGISTER_TYPE f8;
412 __MIPS_FPU_REGISTER_TYPE f9;
413 __MIPS_FPU_REGISTER_TYPE f10;
414 __MIPS_FPU_REGISTER_TYPE f11;
415 __MIPS_FPU_REGISTER_TYPE f12;
416 __MIPS_FPU_REGISTER_TYPE f13;
417 __MIPS_FPU_REGISTER_TYPE f14;
418 __MIPS_FPU_REGISTER_TYPE f15;
419 __MIPS_FPU_REGISTER_TYPE f16;
420 __MIPS_FPU_REGISTER_TYPE f17;
421 __MIPS_FPU_REGISTER_TYPE f18;
422 __MIPS_FPU_REGISTER_TYPE f19;
423 __MIPS_FPU_REGISTER_TYPE f20;
424 __MIPS_FPU_REGISTER_TYPE f21;
425 __MIPS_FPU_REGISTER_TYPE f22;
426 __MIPS_FPU_REGISTER_TYPE f23;
427 __MIPS_FPU_REGISTER_TYPE f24;
428 __MIPS_FPU_REGISTER_TYPE f25;
429 __MIPS_FPU_REGISTER_TYPE f26;
430 __MIPS_FPU_REGISTER_TYPE f27;
431 __MIPS_FPU_REGISTER_TYPE f28;
432 __MIPS_FPU_REGISTER_TYPE f29;
433 __MIPS_FPU_REGISTER_TYPE f30;
434 __MIPS_FPU_REGISTER_TYPE f31;
435 __MIPS_REGISTER_TYPE fcsr;
437 __MIPS_REGISTER_TYPE feir;
442 __MIPS_REGISTER_TYPE tlbhi;
445 __MIPS_REGISTER_TYPE tlblo;
448#if (__mips == 3) || (__mips == 32)
449 __MIPS_REGISTER_TYPE tlblo0;
453 __MIPS_REGISTER_TYPE inx;
455 __MIPS_REGISTER_TYPE rand;
457 __MIPS_REGISTER_TYPE
ctxt;
459 __MIPS_REGISTER_TYPE exctype;
460 __MIPS_REGISTER_TYPE mode;
461 __MIPS_REGISTER_TYPE prid;
462 __MIPS_REGISTER_TYPE tar ;
464#if (__mips == 3) || (__mips == 32)
465 __MIPS_REGISTER_TYPE tlblo1;
466 __MIPS_REGISTER_TYPE pagemask;
467 __MIPS_REGISTER_TYPE wired;
468 __MIPS_REGISTER_TYPE count;
469 __MIPS_REGISTER_TYPE compare;
470 __MIPS_REGISTER_TYPE
config;
471 __MIPS_REGISTER_TYPE lladdr;
472 __MIPS_REGISTER_TYPE watchlo;
473 __MIPS_REGISTER_TYPE watchhi;
474 __MIPS_REGISTER_TYPE ecc;
475 __MIPS_REGISTER_TYPE cacheerr;
476 __MIPS_REGISTER_TYPE taglo;
477 __MIPS_REGISTER_TYPE taghi;
478 __MIPS_REGISTER_TYPE errpc;
479 __MIPS_REGISTER_TYPE xctxt;
509#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
517#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
524#define CPU_STACK_MINIMUM_SIZE (8 * 1024)
531#define CPU_ALIGNMENT 8
545#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
547#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
549#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
562uint32_t mips_interrupt_mask(
void );
569#define _CPU_ISR_Disable( _level ) \
571 unsigned int _scratch; \
572 mips_get_sr( _scratch ); \
573 mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \
574 _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \
583#define _CPU_ISR_Enable( _level ) \
585 unsigned int _scratch; \
586 mips_get_sr( _scratch ); \
587 mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \
597#define _CPU_ISR_Flash( _xlevel ) \
599 unsigned int _scratch2 = _xlevel; \
600 _CPU_ISR_Enable( _scratch2 ); \
601 _CPU_ISR_Disable( _scratch2 ); \
602 _xlevel = _scratch2; \
605static inline bool _CPU_ISR_Is_enabled( uint32_t level )
607 return ( level & SR_INTERRUPT_ENABLE_BITS ) != 0;
673#if (__mips == 3) || (__mips == 32)
676#define _EXTRABITS SR_FR
687void _CPU_Context_Initialize(
689 uintptr_t *stack_base,
708#define _CPU_Context_Restart_self( _the_context ) \
709 _CPU_Context_restore( (_the_context) );
723#if ( CPU_HARDWARE_FP == TRUE )
724#define _CPU_Context_Initialize_fp( _destination ) \
726 *(*(_destination)) = _CPU_Null_fp_context; \
732extern void mips_break(
int error );
734#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
736#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
814static inline uint32_t CPU_swap_u32(
818 uint32_t byte1, byte2, byte3, byte4, swapped;
820 byte4 = (value >> 24) & 0xff;
821 byte3 = (value >> 16) & 0xff;
822 byte2 = (value >> 8) & 0xff;
823 byte1 = value & 0xff;
825 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
829#define CPU_swap_u16( value ) \
830 (((value&0xff) << 8) | ((value >> 8)&0xff))
832typedef uint32_t CPU_Counter_ticks;
This header file provides basic definitions used by the API and the implementation.
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
#define _CPU_ISR_Set_level(_new_level)
Definition: cpu.h:378
#define ra
return address */
Definition: regs.h:66
#define sp
stack-pointer */
Definition: regs.h:64
#define k0
kernel private register 0 */
Definition: regs.h:61
#define k1
kernel private register 1 */
Definition: regs.h:62
#define fp
frame-pointer */
Definition: regs.h:65
#define gp
global data pointer */
Definition: regs.h:63
Information to build RTEMS for a "no cpu" while in protected mode.
#define _CPU_Context_restore_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:901
#define _CPU_Context_save_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:895
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
SPARC basic context.
Definition: cpu.h:213
Thread register context.
Definition: cpu.h:173
Definition: deflate.c:114