37#ifndef _RTEMS_SCORE_CPU_H
38#define _RTEMS_SCORE_CPU_H
41#if defined(RTEMS_PARAVIRT)
42#include <rtems/score/paravirt.h>
45#include <libcpu/vectors.h>
63#define AARCH64_PSTATE_N (1LL << 31)
64#define AARCH64_PSTATE_Z (1LL << 30)
65#define AARCH64_PSTATE_C (1LL << 29)
66#define AARCH64_PSTATE_V (1LL << 28)
67#define AARCH64_PSTATE_D (1LL << 9)
68#define AARCH64_PSTATE_A (1LL << 8)
69#define AARCH64_PSTATE_I (1LL << 7)
70#define AARCH64_PSTATE_F (1LL << 6)
77#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
79#define CPU_ISR_PASSES_FRAME_POINTER FALSE
81#define CPU_HARDWARE_FP FALSE
83#define CPU_SOFTWARE_FP FALSE
85#define CPU_ALL_TASKS_ARE_FP FALSE
87#define CPU_IDLE_TASK_IS_FP FALSE
89#define CPU_USE_DEFERRED_FP_SWITCH FALSE
91#define CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE
93#define CPU_STACK_GROWS_UP FALSE
95#if defined(AARCH64_MULTILIB_CACHE_LINE_MAX_64)
96 #define CPU_CACHE_LINE_BYTES 64
98 #define CPU_CACHE_LINE_BYTES 32
101#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
103#define CPU_MODES_INTERRUPT_MASK 0x1
105#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
107#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
109#define CPU_STACK_MINIMUM_SIZE (1024 * 8)
114#define CPU_SIZEOF_POINTER __SIZEOF_POINTER__
117#define CPU_ALIGNMENT 16
119#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
122#define CPU_STACK_ALIGNMENT 16
124#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
126#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
128#define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE
130#define CPU_MAXIMUM_PROCESSORS 32
132#define AARCH64_CONTEXT_CONTROL_THREAD_ID_OFFSET 0x70
134#ifdef AARCH64_MULTILIB_VFP
135 #define AARCH64_CONTEXT_CONTROL_D8_OFFSET 0x78
138#define AARCH64_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 0x68
141 #if defined(AARCH64_MULTILIB_VFP)
142 #define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0xb8
144 #define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x78
148#define AARCH64_EXCEPTION_FRAME_SIZE 0x350
150#define AARCH64_EXCEPTION_FRAME_REGISTER_SP_OFFSET 0xF8
151#define AARCH64_EXCEPTION_FRAME_REGISTER_LR_OFFSET 0xF0
152#define AARCH64_EXCEPTION_FRAME_REGISTER_DAIF_OFFSET 0x108
153#define AARCH64_EXCEPTION_FRAME_REGISTER_SYNDROME_OFFSET 0x118
154#define AARCH64_EXCEPTION_FRAME_REGISTER_VECTOR_OFFSET 0x128
155#define AARCH64_EXCEPTION_FRAME_REGISTER_FPSR_OFFSET 0x138
156#define AARCH64_EXCEPTION_FRAME_REGISTER_Q0_OFFSET 0x150
168#pragma GCC diagnostic push
169#pragma GCC diagnostic ignored "-Wpedantic"
170typedef unsigned __int128 uint128_t;
171#pragma GCC diagnostic pop
174 uint64_t register_x19;
175 uint64_t register_x20;
176 uint64_t register_x21;
177 uint64_t register_x22;
178 uint64_t register_x23;
179 uint64_t register_x24;
180 uint64_t register_x25;
181 uint64_t register_x26;
182 uint64_t register_x27;
183 uint64_t register_x28;
184 uint64_t register_fp;
185 uint64_t register_lr;
186 uint64_t register_sp;
189#ifdef AARCH64_MULTILIB_VFP
190 uint64_t register_d8;
191 uint64_t register_d9;
192 uint64_t register_d10;
193 uint64_t register_d11;
194 uint64_t register_d12;
195 uint64_t register_d13;
196 uint64_t register_d14;
197 uint64_t register_d15;
200 volatile bool is_executing;
204static inline void _AARCH64_Data_memory_barrier(
void )
206 __asm__
volatile (
"dmb SY" : : :
"memory" );
209static inline void _AARCH64_Data_synchronization_barrier(
void )
211 __asm__
volatile (
"dsb SY" : : :
"memory" );
214static inline void _AARCH64_Instruction_synchronization_barrier(
void )
216 __asm__
volatile (
"isb" : : :
"memory" );
223#if defined(AARCH64_DISABLE_INLINE_ISR_DISABLE_ENABLE)
224uint64_t AArch64_interrupt_disable(
void );
225void AArch64_interrupt_enable( uint64_t isr_cookie );
226void AArch64_interrupt_flash( uint64_t isr_cookie );
228static inline uint64_t AArch64_interrupt_disable(
void )
233 "mrs %[isr_cookie], DAIF\n"
234 "msr DAIFSet, #0x2\n"
235 : [isr_cookie]
"=&r" (isr_cookie)
241static inline void AArch64_interrupt_enable( uint64_t isr_cookie )
244 "msr DAIF, %[isr_cookie]\n"
245 : : [isr_cookie]
"r" (isr_cookie)
249static inline void AArch64_interrupt_flash( uint64_t isr_cookie )
251 AArch64_interrupt_enable(isr_cookie);
252 AArch64_interrupt_disable();
256#define _CPU_ISR_Disable( _isr_cookie ) \
258 _isr_cookie = AArch64_interrupt_disable(); \
261#define _CPU_ISR_Enable( _isr_cookie ) \
262 AArch64_interrupt_enable( _isr_cookie )
264#define _CPU_ISR_Flash( _isr_cookie ) \
265 AArch64_interrupt_flash( _isr_cookie )
267static inline bool _CPU_ISR_Is_enabled( uint64_t isr_cookie )
269 return ( isr_cookie & AARCH64_PSTATE_I ) == 0;
272void _CPU_Context_Initialize(
274 void *stack_area_begin,
275 size_t stack_area_size,
277 void (*entry_point)(
void ),
282#define _CPU_Context_Get_SP( _context ) \
283 (_context)->register_sp
286 static inline bool _CPU_Context_Get_is_executing(
293 static inline void _CPU_Context_Set_is_executing(
298 context->is_executing = is_executing;
303 #define _CPU_Start_multitasking( _heir ) _AArch64_Start_multitasking( _heir )
306#define _CPU_Context_Restart_self( _the_context ) \
307 _CPU_Context_restore( (_the_context) );
309#define _CPU_Context_Initialize_fp( _destination ) \
311 *(*(_destination)) = _CPU_Null_fp_context; \
319typedef void ( *CPU_ISR_handler )( void );
334 uint32_t _CPU_SMP_Initialize(
void );
336 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
338 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
340 void _CPU_SMP_Prepare_start_multitasking(
void );
348 uint32_t _CPU_SMP_Get_current_processor(
void );
350 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
352 static inline void _AARCH64_Send_event(
void )
354 __asm__
volatile (
"sev" : : :
"memory" );
357 static inline void _AARCH64_Wait_for_event(
void )
359 __asm__
volatile (
"wfe" : : :
"memory" );
364static inline uint32_t CPU_swap_u32( uint32_t value )
366 uint32_t tmp = value;
367 __asm__
volatile (
"EOR %1, %0, %0, ROR #16\n"
368 "BIC %1, %1, #0xff0000\n"
369 "MOV %0, %0, ROR #8\n"
370 "EOR %0, %0, %1, LSR #8\n"
371 :
"=r" (value),
"=r" (tmp)
372 :
"0" (value),
"1" (tmp));
378 return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU));
381typedef uint32_t CPU_Counter_ticks;
390 AARCH64_EXCEPTION_SP0_SYNCHRONOUS = 0,
391 AARCH64_EXCEPTION_SP0_IRQ = 1,
392 AARCH64_EXCEPTION_SP0_FIQ = 2,
393 AARCH64_EXCEPTION_SP0_SERROR = 3,
394 AARCH64_EXCEPTION_SPx_SYNCHRONOUS = 4,
395 AARCH64_EXCEPTION_SPx_IRQ = 5,
396 AARCH64_EXCEPTION_SPx_FIQ = 6,
397 AARCH64_EXCEPTION_SPx_SERROR = 7,
398 AARCH64_EXCEPTION_LEL64_SYNCHRONOUS = 8,
399 AARCH64_EXCEPTION_LEL64_IRQ = 9,
400 AARCH64_EXCEPTION_LEL64_FIQ = 10,
401 AARCH64_EXCEPTION_LEL64_SERROR = 11,
402 AARCH64_EXCEPTION_LEL32_SYNCHRONOUS = 12,
403 AARCH64_EXCEPTION_LEL32_IRQ = 13,
404 AARCH64_EXCEPTION_LEL32_FIQ = 14,
405 AARCH64_EXCEPTION_LEL32_SERROR = 15,
407 AARCH64_EXCEPTION_MAKE_ENUM_64_BIT = INT_MAX
408} AArch64_symbolic_exception_name;
410#define VECTOR_POINTER_OFFSET 0x78
411#define VECTOR_ENTRY_SIZE 0x80
412void _AArch64_Exception_interrupt_no_nest(
void );
413void _AArch64_Exception_interrupt_nest(
void );
414static inline void* AArch64_set_exception_handler(
415 AArch64_symbolic_exception_name exception,
416 void (*handler)(
void)
420 char *vbar = (
char*)AArch64_get_vector_base_address();
423 char *cvector_address = vbar + VECTOR_ENTRY_SIZE * exception
424 + VECTOR_POINTER_OFFSET;
427 void (**vector_address)(void) = (
void(**)(void))cvector_address;
428 void (*current_vector_pointer)(void);
429 current_vector_pointer = *vector_address;
432 *vector_address = handler;
440#pragma GCC diagnostic push
441#pragma GCC diagnostic ignored "-Wpedantic"
442 return (
void*)current_vector_pointer;
443#pragma GCC diagnostic pop
447 uint64_t register_x0;
448 uint64_t register_x1;
449 uint64_t register_x2;
450 uint64_t register_x3;
451 uint64_t register_x4;
452 uint64_t register_x5;
453 uint64_t register_x6;
454 uint64_t register_x7;
455 uint64_t register_x8;
456 uint64_t register_x9;
457 uint64_t register_x10;
458 uint64_t register_x11;
459 uint64_t register_x12;
460 uint64_t register_x13;
461 uint64_t register_x14;
462 uint64_t register_x15;
463 uint64_t register_x16;
464 uint64_t register_x17;
465 uint64_t register_x18;
466 uint64_t register_x19;
467 uint64_t register_x20;
468 uint64_t register_x21;
469 uint64_t register_x22;
470 uint64_t register_x23;
471 uint64_t register_x24;
472 uint64_t register_x25;
473 uint64_t register_x26;
474 uint64_t register_x27;
475 uint64_t register_x28;
476 uint64_t register_fp;
478#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
479 uint32_t _register_lr_top;
481 uintptr_t register_sp;
482#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
483 uint32_t _register_sp_top;
486#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
487 uint32_t _register_pc_top;
489 uint64_t register_daif;
490 uint64_t register_cpsr;
491 uint64_t register_syndrome;
492 uint64_t register_fault_address;
493 AArch64_symbolic_exception_name vector;
494 uint64_t reserved_for_stack_alignment;
495 uint64_t register_fpsr;
496 uint64_t register_fpcr;
497 uint128_t register_q0;
498 uint128_t register_q1;
499 uint128_t register_q2;
500 uint128_t register_q3;
501 uint128_t register_q4;
502 uint128_t register_q5;
503 uint128_t register_q6;
504 uint128_t register_q7;
505 uint128_t register_q8;
506 uint128_t register_q9;
507 uint128_t register_q10;
508 uint128_t register_q11;
509 uint128_t register_q12;
510 uint128_t register_q13;
511 uint128_t register_q14;
512 uint128_t register_q15;
513 uint128_t register_q16;
514 uint128_t register_q17;
515 uint128_t register_q18;
516 uint128_t register_q19;
517 uint128_t register_q20;
518 uint128_t register_q21;
519 uint128_t register_q22;
520 uint128_t register_q23;
521 uint128_t register_q24;
522 uint128_t register_q25;
523 uint128_t register_q26;
524 uint128_t register_q27;
525 uint128_t register_q28;
526 uint128_t register_q29;
527 uint128_t register_q30;
528 uint128_t register_q31;
538void _CPU_Exception_disable_thread_dispatch(
void );
545void _CPU_Exception_frame_make_resume_next_instruction(
549void _AArch64_Exception_frame_copy(
ARM AArch64 Assembler Support API.
This header file provides basic definitions used by the API and the implementation.
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
#define CPU_swap_u16(value)
Definition: cpu.h:597
#define _CPU_ISR_Set_level(_new_level)
Definition: cpu.h:378
rtems_termios_device_context * context
Definition: console-config.c:62
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Thread register context.
Definition: cpu.h:173
uint64_t isr_dispatch_disable
This member is used for the external interrupt controller (EIC) support.
Definition: cpu.h:187