RTEMS 6.1-rc7
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cpu.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (c) 2015, Hesham Almatary
13 * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _RTEMS_SCORE_CPU_H
38#define _RTEMS_SCORE_CPU_H
39
42
43#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
44
45#define CPU_ISR_PASSES_FRAME_POINTER FALSE
46
47#define CPU_HARDWARE_FP FALSE
48
49#define CPU_SOFTWARE_FP FALSE
50
51#define CPU_ALL_TASKS_ARE_FP FALSE
52
53#define CPU_IDLE_TASK_IS_FP FALSE
54
55#define CPU_USE_DEFERRED_FP_SWITCH FALSE
56
57#define CPU_STACK_GROWS_UP FALSE
58
62#define CPU_CACHE_LINE_BYTES 64
63
64#define CPU_STRUCTURE_ALIGNMENT
65
66#define CPU_MODES_INTERRUPT_MASK 0x00000001
67
68#define MICROBLAZE_EXCEPTION_FRAME_R1 0
69#define MICROBLAZE_EXCEPTION_FRAME_R2 4
70#define MICROBLAZE_EXCEPTION_FRAME_R3 8
71#define MICROBLAZE_EXCEPTION_FRAME_R4 12
72#define MICROBLAZE_EXCEPTION_FRAME_R5 16
73#define MICROBLAZE_EXCEPTION_FRAME_R6 20
74#define MICROBLAZE_EXCEPTION_FRAME_R7 24
75#define MICROBLAZE_EXCEPTION_FRAME_R8 28
76#define MICROBLAZE_EXCEPTION_FRAME_R9 32
77#define MICROBLAZE_EXCEPTION_FRAME_R10 36
78#define MICROBLAZE_EXCEPTION_FRAME_R11 40
79#define MICROBLAZE_EXCEPTION_FRAME_R12 44
80#define MICROBLAZE_EXCEPTION_FRAME_R13 48
81#define MICROBLAZE_EXCEPTION_FRAME_R14 52
82#define MICROBLAZE_EXCEPTION_FRAME_R15 56
83#define MICROBLAZE_EXCEPTION_FRAME_R16 60
84#define MICROBLAZE_EXCEPTION_FRAME_R17 64
85#define MICROBLAZE_EXCEPTION_FRAME_R18 68
86#define MICROBLAZE_EXCEPTION_FRAME_R19 72
87#define MICROBLAZE_EXCEPTION_FRAME_R20 76
88#define MICROBLAZE_EXCEPTION_FRAME_R21 80
89#define MICROBLAZE_EXCEPTION_FRAME_R22 84
90#define MICROBLAZE_EXCEPTION_FRAME_R23 88
91#define MICROBLAZE_EXCEPTION_FRAME_R24 92
92#define MICROBLAZE_EXCEPTION_FRAME_R25 96
93#define MICROBLAZE_EXCEPTION_FRAME_R26 100
94#define MICROBLAZE_EXCEPTION_FRAME_R27 104
95#define MICROBLAZE_EXCEPTION_FRAME_R28 108
96#define MICROBLAZE_EXCEPTION_FRAME_R29 112
97#define MICROBLAZE_EXCEPTION_FRAME_R30 116
98#define MICROBLAZE_EXCEPTION_FRAME_R31 120
99#define MICROBLAZE_EXCEPTION_FRAME_MSR 124
100#define MICROBLAZE_EXCEPTION_FRAME_EAR 128
101#define MICROBLAZE_EXCEPTION_FRAME_ESR 132
102#define MICROBLAZE_EXCEPTION_FRAME_BTR 136
103
104#define CPU_EXCEPTION_FRAME_SIZE 140
105
106#ifndef ASM
107
108#ifdef __cplusplus
109extern "C" {
110#endif
111
118typedef struct {
119 uint32_t r1;
120 uint32_t r13;
121 uint32_t r14;
122 uint32_t r15;
123 uint32_t r16;
124 uint32_t r17;
125 uint32_t r18;
126 uint32_t r19;
127 uint32_t r20;
128 uint32_t r21;
129 uint32_t r22;
130 uint32_t r23;
131 uint32_t r24;
132 uint32_t r25;
133 uint32_t r26;
134 uint32_t r27;
135 uint32_t r28;
136 uint32_t r29;
137 uint32_t r30;
138 uint32_t r31;
139 uint32_t rmsr;
140 void *thread_pointer;
142
152#define _CPU_Context_Get_SP( _context ) \
153 (_context)->r1
154
155#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
156
157#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
158
159#define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE
160
161#define CPU_MAXIMUM_PROCESSORS 32
162
167#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
168
169#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
170
171#define CPU_STACK_MINIMUM_SIZE (1024*4)
172
173#define CPU_ALIGNMENT 4
174
175#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
176
177#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
178
179#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
180
181/*
182 * bit definitions in the documentation are reversed for all special registers
183 * such that bit 0 is the most significant bit
184 */
185#define MICROBLAZE_MSR_VM ( 1 << 13 )
186#define MICROBLAZE_MSR_UM ( 1 << 11 )
187#define MICROBLAZE_MSR_PVR ( 1 << 10 )
188#define MICROBLAZE_MSR_EIP ( 1 << 9 )
189#define MICROBLAZE_MSR_EE ( 1 << 8 )
190#define MICROBLAZE_MSR_DCE ( 1 << 7 )
191#define MICROBLAZE_MSR_DZO ( 1 << 6 )
192#define MICROBLAZE_MSR_ICE ( 1 << 5 )
193#define MICROBLAZE_MSR_FSL ( 1 << 4 )
194#define MICROBLAZE_MSR_BIP ( 1 << 3 )
195#define MICROBLAZE_MSR_C ( 1 << 2 )
196#define MICROBLAZE_MSR_IE ( 1 << 1 )
197
198#define MICROBLAZE_ESR_DS ( 1 << 12 )
199#define MICROBLAZE_ESR_EC_MASK 0x1f
200#define MICROBLAZE_ESR_ESS_MASK 0x7f
201#define MICROBLAZE_ESR_ESS_SHIFT 5
202
203#define _CPU_MSR_GET( _msr_value ) \
204 do { \
205 (_msr_value) = 0; \
206 __asm__ volatile ("mfs %0, rmsr" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
207 } while (0)
208
209#define _CPU_MSR_SET( _msr_value ) \
210{ __asm__ volatile ("mts rmsr, %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
211
212#define MICROBLAZE_PVR0_VERSION_GET( _pvr0_value ) \
213 ( ( _pvr0_value >> 8 ) & 0xff )
214
215#define _CPU_PVR0_GET( _pvr0_value ) \
216 do { \
217 ( _pvr0_value ) = 0; \
218 __asm__ volatile ( "mfs %0, rpvr0" : "=&r" ( ( _pvr0_value ) ) ); \
219 } while ( 0 )
220
221#define MICROBLAZE_PVR3_BP_GET( _pvr3_value ) \
222 ( ( _pvr3_value >> 25 ) & 0xf )
223
224#define MICROBLAZE_PVR3_RWP_GET( _pvr3_value ) \
225 ( ( _pvr3_value >> 19 ) & 0x7 )
226
227#define MICROBLAZE_PVR3_WWP_GET( _pvr3_value ) \
228 ( ( _pvr3_value >> 13 ) & 0x7 )
229
230#define _CPU_PVR3_GET( _pvr3_value ) \
231 do { \
232 ( _pvr3_value ) = 0; \
233 __asm__ volatile ( "mfs %0, rpvr3" : "=&r" ( ( _pvr3_value ) ) ); \
234 } while ( 0 )
235
236#define _CPU_ISR_Disable( _isr_cookie ) \
237 { \
238 unsigned int _new_msr; \
239 _CPU_MSR_GET(_isr_cookie); \
240 _new_msr = (_isr_cookie) & ~(MICROBLAZE_MSR_IE); \
241 _CPU_MSR_SET(_new_msr); \
242 }
243
244#define _CPU_ISR_Enable( _isr_cookie ) \
245 { \
246 uint32_t _microblaze_interrupt_enable; \
247 uint32_t _microblaze_switch_reg; \
248 \
249 _microblaze_interrupt_enable = (_isr_cookie) & (MICROBLAZE_MSR_IE); \
250 _CPU_MSR_GET(_microblaze_switch_reg); \
251 _microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE); \
252 _microblaze_switch_reg |= _microblaze_interrupt_enable; \
253 _CPU_MSR_SET(_microblaze_switch_reg); \
254 }
255
256#define _CPU_ISR_Flash( _isr_cookie ) \
257 { \
258 unsigned int _new_msr; \
259 _CPU_MSR_SET(_isr_cookie); \
260 _new_msr = (_isr_cookie) & ~(MICROBLAZE_MSR_IE); \
261 _CPU_MSR_SET(_new_msr); \
262 }
263
264void _CPU_ISR_Set_level( uint32_t level );
265
266uint32_t _CPU_ISR_Get_level( void );
267
268static inline bool _CPU_ISR_Is_enabled( uint32_t level )
269{
270 return ( level & MICROBLAZE_MSR_IE ) != 0;
271}
272
273void _CPU_Context_Initialize(
275 void *stack_area_begin,
276 size_t stack_area_size,
277 uint32_t new_level,
278 void (*entry_point)( void ),
279 bool is_fp,
280 void *tls_area
281);
282
283#define _CPU_Context_Restart_self( _the_context ) \
284 _CPU_Context_restore( (_the_context) );
285
286#define _CPU_Context_Initialize_fp( _destination ) \
287 { \
288 *(*(_destination)) = _CPU_Null_fp_context; \
289 }
290
291/* end of Context handler macros */
292
293/* Bitfield handler macros */
294
295#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
296
297#define CPU_SIZEOF_POINTER 4
298
299#define CPU_PER_CPU_CONTROL_SIZE 0
300
301typedef struct {
302 /* r0 is unnecessary since it is always 0 */
303 uint32_t r1;
304 uint32_t r2;
305 uint32_t r3; /* return 1/scratch */
306 uint32_t r4; /* return 2/scratch */
307 uint32_t r5; /* param 1/scratch */
308 uint32_t r6; /* param 2/scratch */
309 uint32_t r7; /* param 3/scratch */
310 uint32_t r8; /* param 4/scratch */
311 uint32_t r9; /* param 5/scratch */
312 uint32_t r10; /* param 6/scratch */
313 uint32_t r11; /* scratch */
314 uint32_t r12; /* scratch */
315 uint32_t r13;
316 uint32_t *r14; /* Interrupt Link Register */
317 uint32_t *r15; /* Link Register */
318 uint32_t *r16; /* Trap/Debug Link Register */
319 uint32_t *r17; /* Exception Link Register */
320 uint32_t r18;
321 uint32_t r19;
322 uint32_t r20;
323 uint32_t r21;
324 uint32_t r22;
325 uint32_t r23;
326 uint32_t r24;
327 uint32_t r25;
328 uint32_t r26;
329 uint32_t r27;
330 uint32_t r28;
331 uint32_t r29;
332 uint32_t r30;
333 uint32_t r31;
334 uint32_t msr; /* Machine Status Register */
335 uint32_t *ear; /* Exception Address Register */
336 uint32_t esr; /* Exception Status Register */
337 uint32_t *btr; /* Branch Target Register */
339
340/* end of Priority handler macros */
341
342/* functions */
343
344void _CPU_Initialize( void );
345
346typedef void ( *CPU_ISR_handler )( uint32_t );
347
349 uint32_t vector,
350 CPU_ISR_handler new_handler,
351 CPU_ISR_handler *old_handler
352);
353
354typedef void ( *MicroBlaze_Exception_handler )( CPU_Exception_frame *ef );
355
356void _MicroBlaze_Exception_install_handler(
357 MicroBlaze_Exception_handler new_handler,
358 MicroBlaze_Exception_handler *old_handler
359);
360
361void _MicroBlaze_Exception_handle(
363);
364
365void _MicroBlaze_Debug_install_handler(
366 MicroBlaze_Exception_handler new_handler,
367 MicroBlaze_Exception_handler *old_handler
368);
369
370void _MicroBlaze_Debug_handle(
372);
373
375 Context_Control *run,
376 Context_Control *heir
377);
378
379/* Selects the appropriate resume function based on CEF state */
380RTEMS_NO_RETURN void _CPU_Exception_resume( CPU_Exception_frame *frame );
381
382RTEMS_NO_RETURN void _MicroBlaze_Exception_resume_from_exception(
384);
385
386RTEMS_NO_RETURN void _MicroBlaze_Exception_resume_from_break(
388);
389
390/*
391 * Only functions for exception cases since debug exception frames will never
392 * need dispatch
393 */
394RTEMS_NO_RETURN void _CPU_Exception_dispatch_and_resume(
396);
397
398void _CPU_Exception_disable_thread_dispatch( void );
399
400int _CPU_Exception_frame_get_signal( CPU_Exception_frame *frame );
401
402void _CPU_Exception_frame_set_resume(
403 CPU_Exception_frame *frame,
404 void *address
405);
406
407void _CPU_Exception_frame_make_resume_next_instruction(
409);
410
411uint32_t *_MicroBlaze_Get_return_address( CPU_Exception_frame *ef );
412
413RTEMS_NO_RETURN void _CPU_Context_restore(
414 Context_Control *new_context
415);
416
417static inline uint32_t CPU_swap_u32(
418 uint32_t value
419)
420{
421 uint32_t byte1, byte2, byte3, byte4, swapped;
422
423 byte4 = (value >> 24) & 0xff;
424 byte3 = (value >> 16) & 0xff;
425 byte2 = (value >> 8) & 0xff;
426 byte1 = value & 0xff;
427
428 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
429 return swapped;
430}
431
432#define CPU_swap_u16( value ) \
433 (((value&0xff) << 8) | ((value >> 8)&0xff))
434
436
437typedef uint32_t CPU_Counter_ticks;
438
439uint32_t _CPU_Counter_frequency( void );
440
441CPU_Counter_ticks _CPU_Counter_read( void );
442
443RTEMS_NO_RETURN void *_CPU_Thread_Idle_body( uintptr_t ignored );
444
445void bsp_interrupt_dispatch( uint32_t source );
446
448typedef uintptr_t CPU_Uint32ptr;
449
450#ifdef __cplusplus
451}
452#endif
453
454#endif /* ASM */
455
456#endif /* _RTEMS_SCORE_CPU_H */
This header file provides basic definitions used by the API and the implementation.
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
#define _CPU_ISR_Set_level(_new_level)
Definition: cpu.h:378
MicroBlaze architecture support.
rtems_termios_device_context * context
Definition: console-config.c:62
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Thread register context.
Definition: cpu.h:173