37#ifndef LIBBSP_MIPS_TX4925_IRQ_H
38#define LIBBSP_MIPS_TX4925_IRQ_H
57#define TX4925_IRQ_RSV1 MIPS_INTERRUPT_BASE+0
58#define TX4925_IRQ_WTE MIPS_INTERRUPT_BASE+1
59#define TX4925_IRQ_INT0 MIPS_INTERRUPT_BASE+2
60#define TX4925_IRQ_INT1 MIPS_INTERRUPT_BASE+3
61#define TX4925_IRQ_INT2 MIPS_INTERRUPT_BASE+4
62#define TX4925_IRQ_INT3 MIPS_INTERRUPT_BASE+5
63#define TX4925_IRQ_INT4 MIPS_INTERRUPT_BASE+6
64#define TX4925_IRQ_INT5 MIPS_INTERRUPT_BASE+7
65#define TX4925_IRQ_INT6 MIPS_INTERRUPT_BASE+8
66#define TX4925_IRQ_INT7 MIPS_INTERRUPT_BASE+9
67#define TX4925_IRQ_RSV2 MIPS_INTERRUPT_BASE+10
68#define TX4925_IRQ_NAND MIPS_INTERRUPT_BASE+11
69#define TX4925_IRQ_SIO0 MIPS_INTERRUPT_BASE+12
70#define TX4925_IRQ_SIO1 MIPS_INTERRUPT_BASE+13
71#define TX4925_IRQ_DMAC0 MIPS_INTERRUPT_BASE+14
72#define TX4925_IRQ_DMAC1 MIPS_INTERRUPT_BASE+15
73#define TX4925_IRQ_DMAC2 MIPS_INTERRUPT_BASE+16
74#define TX4925_IRQ_DMAC3 MIPS_INTERRUPT_BASE+17
75#define TX4925_IRQ_IRC MIPS_INTERRUPT_BASE+18
76#define TX4925_IRQ_PDMAC MIPS_INTERRUPT_BASE+19
77#define TX4925_IRQ_PCIC MIPS_INTERRUPT_BASE+20
78#define TX4925_IRQ_TMR0 MIPS_INTERRUPT_BASE+21
79#define TX4925_IRQ_TMR1 MIPS_INTERRUPT_BASE+22
80#define TX4925_IRQ_TMR2 MIPS_INTERRUPT_BASE+23
81#define TX4925_IRQ_SPI MIPS_INTERRUPT_BASE+24
82#define TX4925_IRQ_RTC MIPS_INTERRUPT_BASE+25
83#define TX4925_IRQ_ACLC MIPS_INTERRUPT_BASE+26
84#define TX4925_IRQ_ACLCPME MIPS_INTERRUPT_BASE+27
85#define TX4925_IRQ_CHI MIPS_INTERRUPT_BASE+28
86#define TX4925_IRQ_PCIERR MIPS_INTERRUPT_BASE+29
87#define TX4925_IRQ_PCIPME MIPS_INTERRUPT_BASE+30
88#define TX4925_IRQ_RSV3 MIPS_INTERRUPT_BASE+31
90#define TX4925_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+32
91#define TX4925_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+33
92#define TX4925_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34
94#define BSP_INTERRUPT_VECTOR_COUNT (TX4925_MAXIMUM_VECTORS + 1)
This header file is provided for backward compatiblility.
Information to build RTEMS for a "no cpu" while in protected mode.
This header file defines the RTEMS Classic API.