RTEMS 6.1-rc7
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irq.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * COPYRIGHT (c) 1989-2012.
13 * On-Line Applications Research Corporation (OAR).
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef LIBBSP_MIPS_TX4938_IRQ_H
38#define LIBBSP_MIPS_TX4938_IRQ_H
39
40#ifndef ASM
41 #include <rtems.h>
42 #include <rtems/irq.h>
43 #include <rtems/irq-extension.h>
44 #include <rtems/score/mips.h>
45#endif
46
53/*
54 * Interrupt Vector Numbers
55 *
56 */
57#define TX4938_IRQ_ECC MIPS_INTERRUPT_BASE+0
58#define TX4938_IRQ_WTE MIPS_INTERRUPT_BASE+1
59#define TX4938_IRQ_INT0 MIPS_INTERRUPT_BASE+2
60#define TX4938_IRQ_INT1 MIPS_INTERRUPT_BASE+3
61#define TX4938_IRQ_INT2 MIPS_INTERRUPT_BASE+4
62#define TX4938_IRQ_INT3 MIPS_INTERRUPT_BASE+5
63#define TX4938_IRQ_INT4 MIPS_INTERRUPT_BASE+6
64#define TX4938_IRQ_INT5 MIPS_INTERRUPT_BASE+7
65#define TX4938_IRQ_SIO0 MIPS_INTERRUPT_BASE+8
66#define TX4938_IRQ_SIO1 MIPS_INTERRUPT_BASE+9
67#define TX4938_IRQ_DMAC00 MIPS_INTERRUPT_BASE+10
68#define TX4938_IRQ_DMAC01 MIPS_INTERRUPT_BASE+11
69#define TX4938_IRQ_DMAC02 MIPS_INTERRUPT_BASE+12
70#define TX4938_IRQ_DMAC03 MIPS_INTERRUPT_BASE+13
71#define TX4938_IRQ_IRC MIPS_INTERRUPT_BASE+14
72#define TX4938_IRQ_PDMAC MIPS_INTERRUPT_BASE+15
73#define TX4938_IRQ_PCIC MIPS_INTERRUPT_BASE+16
74#define TX4938_IRQ_TMR0 MIPS_INTERRUPT_BASE+17
75#define TX4938_IRQ_TMR1 MIPS_INTERRUPT_BASE+18
76#define TX4938_IRQ_TMR2 MIPS_INTERRUPT_BASE+19
77#define TX4938_IRQ_RSV1 MIPS_INTERRUPT_BASE+20
78#define TX4938_IRQ_NDFMC MIPS_INTERRUPT_BASE+21
79#define TX4938_IRQ_PCIERR MIPS_INTERRUPT_BASE+22
80#define TX4938_IRQ_PCIPMC MIPS_INTERRUPT_BASE+23
81#define TX4938_IRQ_ACLC MIPS_INTERRUPT_BASE+24
82#define TX4938_IRQ_ACLCPME MIPS_INTERRUPT_BASE+25
83#define TX4938_IRQ_PCIC1NT MIPS_INTERRUPT_BASE+26
84#define TX4938_IRQ_ACLCPME MIPS_INTERRUPT_BASE+27
85#define TX4938_IRQ_DMAC10 MIPS_INTERRUPT_BASE+28
86#define TX4938_IRQ_DMAC11 MIPS_INTERRUPT_BASE+29
87#define TX4938_IRQ_DMAC12 MIPS_INTERRUPT_BASE+30
88#define TX4938_IRQ_DMAC13 MIPS_INTERRUPT_BASE+31
89
90#define TX4938_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+32
91#define TX4938_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+33
92#define TX4938_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34
93
94#define BSP_INTERRUPT_VECTOR_COUNT (TX4938_MAXIMUM_VECTORS + 1)
95
98#endif /* LIBBSP_MIPS_JMR3904_IRQ_H */
This header file is provided for backward compatiblility.
Information to build RTEMS for a "no cpu" while in protected mode.
This header file defines the RTEMS Classic API.