◆ AHB1ENR
__IO uint32_t RCC_Core_TypeDef::AHB1ENR |
RCC AHB1 peripheral clock register, Address offset: 0x08
◆ AHB1LPENR
__IO uint32_t RCC_Core_TypeDef::AHB1LPENR |
RCC AHB1 peripheral sleep clock register, Address offset: 0x40
◆ AHB2ENR
__IO uint32_t RCC_Core_TypeDef::AHB2ENR |
RCC AHB2 peripheral clock register, Address offset: 0x0C
◆ AHB2LPENR
__IO uint32_t RCC_Core_TypeDef::AHB2LPENR |
RCC AHB2 peripheral sleep clock register, Address offset: 0x44
◆ AHB3ENR
__IO uint32_t RCC_Core_TypeDef::AHB3ENR |
RCC AHB3 peripheral clock register, Address offset: 0x04
◆ AHB3LPENR
__IO uint32_t RCC_Core_TypeDef::AHB3LPENR |
RCC AHB3 peripheral sleep clock register, Address offset: 0x3C
◆ AHB4ENR
__IO uint32_t RCC_Core_TypeDef::AHB4ENR |
RCC AHB4 peripheral clock register, Address offset: 0x10
◆ AHB4LPENR
__IO uint32_t RCC_Core_TypeDef::AHB4LPENR |
RCC AHB4 peripheral sleep clock register, Address offset: 0x48
◆ APB1HENR
__IO uint32_t RCC_Core_TypeDef::APB1HENR |
RCC APB1 peripheral clock High Word register, Address offset: 0x1C
◆ APB1HLPENR
__IO uint32_t RCC_Core_TypeDef::APB1HLPENR |
RCC APB1 peripheral sleep clock High Word register, Address offset: 0x54
◆ APB1LENR
__IO uint32_t RCC_Core_TypeDef::APB1LENR |
RCC APB1 peripheral clock Low Word register, Address offset: 0x18
◆ APB1LLPENR
__IO uint32_t RCC_Core_TypeDef::APB1LLPENR |
RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x50
◆ APB2ENR
__IO uint32_t RCC_Core_TypeDef::APB2ENR |
RCC APB2 peripheral clock register, Address offset: 0x20
◆ APB2LPENR
__IO uint32_t RCC_Core_TypeDef::APB2LPENR |
RCC APB2 peripheral sleep clock register, Address offset: 0x58
◆ APB3ENR
__IO uint32_t RCC_Core_TypeDef::APB3ENR |
RCC APB3 peripheral clock register, Address offset: 0x14
◆ APB3LPENR
__IO uint32_t RCC_Core_TypeDef::APB3LPENR |
RCC APB3 peripheral sleep clock register, Address offset: 0x4C
◆ APB4ENR
__IO uint32_t RCC_Core_TypeDef::APB4ENR |
RCC APB4 peripheral clock register, Address offset: 0x24
◆ APB4LPENR
__IO uint32_t RCC_Core_TypeDef::APB4LPENR |
RCC APB4 peripheral sleep clock register, Address offset: 0x5C
◆ RESERVED10
uint32_t RCC_Core_TypeDef::RESERVED10 |
Reserved, 0x60-0x6C Address offset: 0x60
◆ RESERVED9
uint32_t RCC_Core_TypeDef::RESERVED9 |
Reserved, Address offset: 0x28
◆ RSR
__IO uint32_t RCC_Core_TypeDef::RSR |
RCC Reset status register, Address offset: 0x00
The documentation for this struct was generated from the following files: