RTEMS 6.1-rc7
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irq.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2008, 2011 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#ifndef LIBBSP_POWERPC_IRQ_H
37#define LIBBSP_POWERPC_IRQ_H
38
39#include <rtems/irq-extension.h>
40#include <rtems/irq.h>
41
42#include <bspopts.h>
43
44#ifdef __cplusplus
45extern "C" {
46#endif /* __cplusplus */
47
48/*
49 * Interrupt numbers
50 */
51
52#define MPC55XX_IRQ_INVALID 0x10000U
53#define MPC55XX_IRQ_MIN 0U
54
55/* Software interrupts */
56#define MPC55XX_IRQ_SOFTWARE_MIN 0U
57#define MPC55XX_IRQ_SOFTWARE_MAX 7U
58#define MPC55XX_IRQ_SOFTWARE_GET_INDEX(v) (v)
59#define MPC55XX_IRQ_SOFTWARE_GET_REQUEST(i) (i)
60#define MPC55XX_IRQ_SOFTWARE_NUMBER (MPC55XX_IRQ_SOFTWARE_MAX + 1U)
61
62#if MPC55XX_CHIP_FAMILY == 551
63 #define MPC55XX_IRQ_MAX 293U
64
65 /* eDMA */
66 #define MPC55XX_IRQ_EDMA_ERROR(group) \
67 ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID)
68 #define MPC55XX_IRQ_EDMA(ch) \
69 ((unsigned) (ch) < 16U ? 11U + (ch) : MPC55XX_IRQ_INVALID)
70
71 /* I2C */
72 #define MPC55XX_IRQ_I2C(mod) \
73 ((mod) == 0 ? 48U : MPC55XX_IRQ_INVALID)
74
75 /* SIU external interrupts */
76 #define MPC55XX_IRQ_SIU_EXTERNAL_0 53U
77 #define MPC55XX_IRQ_SIU_EXTERNAL_1 54U
78 #define MPC55XX_IRQ_SIU_EXTERNAL_2 55U
79 #define MPC55XX_IRQ_SIU_EXTERNAL_3 56U
80 #define MPC55XX_IRQ_SIU_EXTERNAL_4_15 57U
81
82 /* PIT */
83 #define MPC55XX_IRQ_RTI 148U
84 #define MPC55XX_IRQ_PIT(timer) (148U + (timer))
85
86 /* eTPU */
87 #define MPC55XX_IRQ_ETPU_BASE(mod) MPC55XX_IRQ_INVALID
88
89 /* DSPI */
90 #define MPC55XX_IRQ_DSPI_BASE(mod) \
91 ((mod) == 0 ? 117U : \
92 ((mod) == 1 ? 122U : \
93 ((mod) == 2 ? 274U : \
94 ((mod) == 3 ? 279U : MPC55XX_IRQ_INVALID))))
95
96 /* eMIOS */
97 #define MPC55XX_IRQ_EMIOS(ch) \
98 ((unsigned) (ch) < 24U ? 58U + (ch) : MPC55XX_IRQ_INVALID)
99
100 /* eQADC */
101 #define MPC55XX_IRQ_EQADC_BASE(mod) \
102 ((mod) == 0 ? 82U : MPC55XX_IRQ_INVALID)
103
104 /* eSCI */
105 #define MPC55XX_IRQ_ESCI(mod) \
106 ((mod) == 0 ? 113U : \
107 ((mod) == 1 ? 114U : \
108 ((mod) == 2 ? 115U : \
109 ((mod) == 3 ? 116U : \
110 ((mod) == 4 ? 270U : \
111 ((mod) == 5 ? 271U : \
112 ((mod) == 6 ? 272U : \
113 ((mod) == 7 ? 273U : MPC55XX_IRQ_INVALID))))))))
114
115 /* FlexCAN */
116 #define MPC55XX_IRQ_CAN_BASE(mod) \
117 ((mod) == 0 ? 127U : \
118 ((mod) == 1 ? 157U : \
119 ((mod) == 2 ? 178U : \
120 ((mod) == 3 ? 199U : \
121 ((mod) == 4 ? 220U : \
122 ((mod) == 5 ? 241U : MPC55XX_IRQ_INVALID))))))
123
124 /* FlexRay */
125 #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
126 ((mod) == 0 ? 284U : MPC55XX_IRQ_INVALID)
127#elif MPC55XX_CHIP_FAMILY == 564
128 #define MPC55XX_IRQ_MAX 255U
129
130 /* eDMA */
131 #define MPC55XX_IRQ_EDMA_ERROR(group) \
132 ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID)
133 #define MPC55XX_IRQ_EDMA(ch) \
134 ((unsigned) (ch) < 16U ? 11U + (ch) : MPC55XX_IRQ_INVALID)
135
136 /* SWT */
137 #define MPC55XX_IRQ_SWT_0 28U
138 #define MPC55XX_IRQ_SWT_1 29U
139
140 /* STM */
141 #define MPC55XX_IRQ_STM_CHANNEL(ch) ((ch) + 30U)
142
143 /* ECSM */
144 #define MPC55XX_IRQ_ECSM_FAS 9U
145 #define MPC55XX_IRQ_ECSM_NCE 35U
146 #define MPC55XX_IRQ_ECSM_COR 36U
147
148 /* MC */
149 #define MPC55XX_IRQ_MC_ME_SAFE_MODE 51U
150 #define MPC55XX_IRQ_MC_ME_MODE_TRANSITION 52U
151 #define MPC55XX_IRQ_MC_ME_INVALID_MODE 53U
152 #define MPC55XX_IRQ_MC_ME_INVALID_CONFIG 54U
153 #define MPC55XX_IRQ_MC_RGM_FRAE 56U
154
155 /* XOSC */
156 #define MPC55XX_IRQ_XOSC 57U
157
158 /* PIT */
159 #define MPC55XX_IRQ_PIT_CHANNEL(ch) \
160 ((ch) == 3 ? 127U : ((ch) + 59U))
161
162 /* SIU external interrupts */
163 #define MPC55XX_IRQ_SIU_EXTERNAL_0 41U
164 #define MPC55XX_IRQ_SIU_EXTERNAL_1 42U
165 #define MPC55XX_IRQ_SIU_EXTERNAL_2 43U
166 #define MPC55XX_IRQ_SIU_EXTERNAL_3 44U
167
168 /* ADC */
169 #define MPC55XX_IRQ_ADC_BASE(mod) \
170 ((mod) == 0 ? 62U : \
171 ((mod) == 1 ? 82U : MPC55XX_IRQ_INVALID))
172
173 /* DSPI */
174 #define MPC55XX_IRQ_DSPI_BASE(mod) \
175 ((mod) == 0 ? 74U : \
176 ((mod) == 1 ? 94U : \
177 ((mod) == 2 ? 114U : MPC55XX_IRQ_INVALID)))
178
179 /* FlexCAN */
180 #define MPC55XX_IRQ_CAN_BASE(mod) \
181 ((mod) == 0 ? 65U : \
182 ((mod) == 1 ? 85U : MPC55XX_IRQ_INVALID))
183
184 /* FlexPWM */
185 #define MPC55XX_IRQ_FLEXPWM_BASE(mod) \
186 ((mod) == 0 ? 179U : \
187 ((mod) == 1 ? 233U : MPC55XX_IRQ_INVALID))
188
189 /* FlexRay */
190 #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
191 ((mod) == 0 ? 131U : MPC55XX_IRQ_INVALID)
192
193 /* LINFlexD */
194 #define MPC55XX_IRQ_LINFLEX_BASE(mod) \
195 ((mod) == 0 ? 79U : \
196 ((mod) == 1 ? 99U : MPC55XX_IRQ_INVALID))
197
198 /* eTimer */
199 #define MPC55XX_IRQ_ETIMER_BASE(mod) \
200 ((mod) == 0 ? 157U : \
201 ((mod) == 1 ? 168U : \
202 ((mod) == 2 ? 222U : MPC55XX_IRQ_INVALID)))
203
204 /* CTU */
205 #define MPC55XX_IRQ_CTU_MRS 193U
206 #define MPC55XX_IRQ_CTU_T(idx) ((idx) + 194U)
207 #define MPC55XX_IRQ_CTU_FIFO(idx) ((idx) + 202U)
208 #define MPC55XX_IRQ_CTU_ADC 206U
209 #define MPC55XX_IRQ_CTU_ERR 207U
210
211 /* SEMA */
212 #define MPC55XX_IRQ_SEMA_0 247U
213 #define MPC55XX_IRQ_SEMA_1 248U
214
215 /* FCCU */
216 #define MPC55XX_IRQ_FCCU_ALRM 250U
217 #define MPC55XX_IRQ_FCCU_CFG_TO 251U
218 #define MPC55XX_IRQ_FCCU_SC_RCC0_F 252U
219 #define MPC55XX_IRQ_FCCU_SC_RCC1_F 253U
220
221 /* PMU */
222 #define MPC55XX_IRQ_PMU 254U
223
224 /* SWG */
225 #define MPC55XX_IRQ_SWG 255U
226#elif MPC55XX_CHIP_FAMILY == 566
227 #define MPC55XX_IRQ_MAX 315U
228
229 /* eDMA */
230 #define MPC55XX_IRQ_EDMA_ERROR(group) \
231 ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID)
232 #define MPC55XX_IRQ_EDMA(ch) \
233 ((unsigned) (ch) < 32U ? 11U + (ch) : MPC55XX_IRQ_INVALID)
234
235 /* PIT */
236 #define MPC55XX_IRQ_PIT_CHANNEL(ch) \
237 ((unsigned) (ch) < 9U ? 148U + (ch) : MPC55XX_IRQ_INVALID)
238
239 /* SIU external interrupts */
240 #define MPC55XX_IRQ_SIU_EXTERNAL_0 53U
241 #define MPC55XX_IRQ_SIU_EXTERNAL_1 54U
242 #define MPC55XX_IRQ_SIU_EXTERNAL_2 55U
243 #define MPC55XX_IRQ_SIU_EXTERNAL_3 56U
244
245 /* eMIOS */
246 #define MPC55XX_IRQ_EMIOS(ch) \
247 ((unsigned) (ch) < 24U ? 58U + (ch) : \
248 ((unsigned) (ch) < 32U ? 262U + (ch) : MPC55XX_IRQ_INVALID))
249
250 /* eSCI */
251 #define MPC55XX_IRQ_ESCI(mod) \
252 ((unsigned) (mod) < 4U ? 113U + (mod) : \
253 ((unsigned) (mod) < 8U ? 270U + (mod) : \
254 ((unsigned) (mod) < 12U ? 306U + (mod) : MPC55XX_IRQ_INVALID)))
255#else
256 #if MPC55XX_CHIP_FAMILY == 555
257 #define MPC55XX_IRQ_MAX 307U
258 #elif MPC55XX_CHIP_FAMILY == 556
259 #define MPC55XX_IRQ_MAX 360U
260 #elif MPC55XX_CHIP_FAMILY == 567
261 #define MPC55XX_IRQ_MAX 479U
262 #else
263 #error "unsupported chip type"
264 #endif
265
266 /* eDMA */
267 #define MPC55XX_IRQ_EDMA_ERROR(group) \
268 ((group) == 0 ? 10U : \
269 ((group) == 1 ? 210U : \
270 ((group) == 2 ? 425U : MPC55XX_IRQ_INVALID)))
271 #define MPC55XX_IRQ_EDMA(ch) \
272 ((unsigned) (ch) < 32U ? 11U + (ch) : \
273 ((unsigned) (ch) < 64U ? 179U + (ch) : \
274 ((unsigned) (ch) < 96U ? 362U + (ch) : MPC55XX_IRQ_INVALID)))
275
276 /* I2C */
277 #define MPC55XX_IRQ_I2C(mod) MPC55XX_IRQ_INVALID
278
279 /* SIU external interrupts */
280 #define MPC55XX_IRQ_SIU_EXTERNAL_0 46U
281 #define MPC55XX_IRQ_SIU_EXTERNAL_1 47U
282 #define MPC55XX_IRQ_SIU_EXTERNAL_2 48U
283 #define MPC55XX_IRQ_SIU_EXTERNAL_3 49U
284 #define MPC55XX_IRQ_SIU_EXTERNAL_4_15 50U
285
286 /* PIT */
287 #define MPC55XX_IRQ_RTI 305U
288 #define MPC55XX_IRQ_PIT(ch) (301U + (ch))
289
290 /* eTPU */
291 #define MPC55XX_IRQ_ETPU_BASE(mod) \
292 ((mod) == 0 ? 67U : \
293 ((mod) == 1 ? 243U : MPC55XX_IRQ_INVALID))
294
295 /* DSPI */
296 #define MPC55XX_IRQ_DSPI_BASE(mod) \
297 ((mod) == 0 ? 275U : \
298 ((mod) == 1 ? 131U : \
299 ((mod) == 2 ? 136U : \
300 ((mod) == 3 ? 141U : MPC55XX_IRQ_INVALID))))
301
302 /* eMIOS */
303 #define MPC55XX_IRQ_EMIOS(ch) \
304 ((unsigned) (ch) < 16U ? 51U + (ch) : \
305 ((unsigned) (ch) < 24U ? 186U + (ch) : \
306 ((unsigned) (ch) < 32U ? 435U + (ch) : MPC55XX_IRQ_INVALID)))
307
308 /* eQADC */
309 #define MPC55XX_IRQ_EQADC_BASE(mod) \
310 ((mod) == 0 ? 100U : \
311 ((mod) == 1 ? 394U : MPC55XX_IRQ_INVALID))
312
313 /* eSCI */
314 #define MPC55XX_IRQ_ESCI(mod) \
315 ((mod) == 0 ? 146U : \
316 ((mod) == 1 ? 149U : \
317 ((mod) == 2 ? 473U : MPC55XX_IRQ_INVALID)))
318
319 /* FlexCAN */
320 #define MPC55XX_IRQ_CAN_BASE(mod) \
321 ((mod) == 0 ? 152U : \
322 ((mod) == 1 ? 280U : \
323 ((mod) == 2 ? 173U : \
324 ((mod) == 3 ? 308U : \
325 ((mod) == 4 ? 329U : MPC55XX_IRQ_INVALID)))))
326
327 /* FlexRay */
328 #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
329 ((mod) == 0 ? 350U : MPC55XX_IRQ_INVALID)
330#endif
331
332#define MPC55XX_IRQ_NUMBER (MPC55XX_IRQ_MAX + 1U)
333
334/* ADC */
335#define MPC55XX_IRQ_ADC_EOC(mod) \
336 (MPC55XX_IRQ_ADC_BASE(mod) + 0U)
337#define MPC55XX_IRQ_ADC_ER(mod) \
338 (MPC55XX_IRQ_ADC_BASE(mod) + 1U)
339#define MPC55XX_IRQ_ADC_WD(mod) \
340 (MPC55XX_IRQ_ADC_BASE(mod) + 2U)
341
342/* eTimer */
343#define MPC55XX_IRQ_ETIMER_TC(mod, ch) \
344 (MPC55XX_IRQ_ETIMER_BASE(mod) + (ch))
345#define MPC55XX_IRQ_ETIMER_WTIF(mod) \
346 (MPC55XX_IRQ_ETIMER_BASE(mod) + 8U)
347#define MPC55XX_IRQ_ETIMER_RCF(mod) \
348 (MPC55XX_IRQ_ETIMER_BASE(mod) + 10U)
349
350/* eTPU */
351#define MPC55XX_IRQ_ETPU(mod) \
352 (MPC55XX_IRQ_ETPU_BASE(mod) + 0U)
353#define MPC55XX_IRQ_ETPU_CHANNEL(mod, ch) \
354 (MPC55XX_IRQ_ETPU_BASE(mod) + 1U + (ch))
355
356/* DSPI */
357#define MPC55XX_IRQ_DSPI_TFUF_RFOF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 0U)
358#define MPC55XX_IRQ_DSPI_EOQF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 1U)
359#define MPC55XX_IRQ_DSPI_TFFF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 2U)
360#define MPC55XX_IRQ_DSPI_TCF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 3U)
361#define MPC55XX_IRQ_DSPI_RFDF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 4U)
362
363/* eQADC */
364#define MPC55XX_IRQ_EQADC_TORF_RFOF_CFUF(mod) \
365 (MPC55XX_IRQ_EQADC_BASE(mod) + 0U)
366#define MPC55XX_IRQ_EQADC_NCF(mod, fifo) \
367 (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 0U)
368#define MPC55XX_IRQ_EQADC_PF(mod, fifo) \
369 (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 1U)
370#define MPC55XX_IRQ_EQADC_EOQF(mod, fifo) \
371 (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 2U)
372#define MPC55XX_IRQ_EQADC_CFFF(mod, fifo) \
373 (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 3U)
374#define MPC55XX_IRQ_EQADC_RFDF(mod, fifo) \
375 (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 4U)
376
377/* FlexCAN */
378#if MPC55XX_CHIP_FAMILY == 564
379 #define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U)
380 #define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U)
381 #define MPC55XX_IRQ_CAN_BUF_0_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U)
382 #define MPC55XX_IRQ_CAN_BUF_4_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U)
383 #define MPC55XX_IRQ_CAN_BUF_8_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U)
384 #define MPC55XX_IRQ_CAN_BUF_12_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U)
385 #define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U)
386#else
387 #define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U)
388 #define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U)
389 #define MPC55XX_IRQ_CAN_BUF_0(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U)
390 #define MPC55XX_IRQ_CAN_BUF_1(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U)
391 #define MPC55XX_IRQ_CAN_BUF_2(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U)
392 #define MPC55XX_IRQ_CAN_BUF_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U)
393 #define MPC55XX_IRQ_CAN_BUF_4(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U)
394 #define MPC55XX_IRQ_CAN_BUF_5(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 8U)
395 #define MPC55XX_IRQ_CAN_BUF_6(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 9U)
396 #define MPC55XX_IRQ_CAN_BUF_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 10U)
397 #define MPC55XX_IRQ_CAN_BUF_8(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U)
398 #define MPC55XX_IRQ_CAN_BUF_9(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U)
399 #define MPC55XX_IRQ_CAN_BUF_10(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 13U)
400 #define MPC55XX_IRQ_CAN_BUF_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 14U)
401 #define MPC55XX_IRQ_CAN_BUF_12(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 15U)
402 #define MPC55XX_IRQ_CAN_BUF_13(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 16U)
403 #define MPC55XX_IRQ_CAN_BUF_14(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 17U)
404 #define MPC55XX_IRQ_CAN_BUF_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 18U)
405 #define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 19U)
406 #define MPC55XX_IRQ_CAN_BUF_32_63(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 20U)
407#endif
408
409/* FlexPWM */
410#define MPC55XX_IRQ_FLEXPWM_RF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 0U)
411#define MPC55XX_IRQ_FLEXPWM_COF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 1U)
412#define MPC55XX_IRQ_FLEXPWM_CAF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 2U)
413#define MPC55XX_IRQ_FLEXPWM_FFLAG(mod) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 12U)
414#define MPC55XX_IRQ_FLEXPWM_REF(mod) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 13U)
415
416/* FlexRay */
417#if MPC55XX_CHIP_FAMILY == 564
418 #define MPC55XX_IRQ_FLEXRAY_LRNEIF_DRNEIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U)
419 #define MPC55XX_IRQ_FLEXRAY_LRCEIF_DRCEIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U)
420 #define MPC55XX_IRQ_FLEXRAY_FAFAIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U)
421 #define MPC55XX_IRQ_FLEXRAY_FAFVIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U)
422 #define MPC55XX_IRQ_FLEXRAY_WUPIEF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U)
423 #define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U)
424 #define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U)
425 #define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U)
426 #define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 8U)
427 #define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 9U)
428#else
429 #define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U)
430 #define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U)
431 #define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U)
432 #define MPC55XX_IRQ_FLEXRAY_WUP_IF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U)
433 #define MPC55XX_IRQ_FLEXRAY_FBNE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U)
434 #define MPC55XX_IRQ_FLEXRAY_FANE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U)
435 #define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U)
436 #define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U)
437#endif
438
439/* LINFlexD */
440#define MPC55XX_IRQ_LINFLEX_RXI(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 0U)
441#define MPC55XX_IRQ_LINFLEX_TXI(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 1U)
442#define MPC55XX_IRQ_LINFLEX_ERR(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 2U)
443
444/* Checks */
445#define MPC55XX_IRQ_IS_VALID(v) \
446 ((v) >= MPC55XX_IRQ_MIN && \
447 (v) <= MPC55XX_IRQ_MAX)
448#define MPC55XX_IRQ_IS_SOFTWARE(v) \
449 ((v) >= MPC55XX_IRQ_SOFTWARE_MIN && \
450 (v) <= MPC55XX_IRQ_SOFTWARE_MAX)
451
452/*
453 * Interrupt controller
454 */
455
456/*
457 * These are RTEMS API priority values, not INTC priority values. We have:
458 * 15 - API-priority == INTC-priority
459 *
460 * The API-priority value 15 (which is INTC-priority 0) effectively disables
461 * the interrupt.
462 */
463#define MPC55XX_INTC_MIN_PRIORITY 14U
464#define MPC55XX_INTC_MAX_PRIORITY 0U
465#define MPC55XX_INTC_DISABLED_PRIORITY 15U
466#define MPC55XX_INTC_INVALID_PRIORITY 16U
467#define MPC55XX_INTC_DEFAULT_PRIORITY 13U
468#define MPC55XX_INTC_IS_VALID_PRIORITY(p) \
469 (((uint32_t) (p)) <= MPC55XX_INTC_DISABLED_PRIORITY)
470
472 rtems_vector_number vector,
473 const char *info,
474 rtems_option options,
475 unsigned priority,
477 void *arg
478);
479
481
483
490#define BSP_INTERRUPT_VECTOR_COUNT (MPC55XX_IRQ_MAX + 1)
491
492#ifdef BSP_INTERRUPT_DISPATCH_TABLE_SIZE
493 #define BSP_INTERRUPT_USE_INDEX_TABLE
494#endif
495
498/* Legacy API */
499#define MPC55XX_IRQ_EDMA_GET_REQUEST(ch) MPC55XX_IRQ_EDMA(ch)
500#define MPC55XX_IRQ_EMIOS_GET_REQUEST(ch) MPC55XX_IRQ_EMIOS(ch)
501
502#ifdef __cplusplus
503};
504#endif /* __cplusplus */
505
506#endif /* LIBBSP_POWERPC_IRQ_H */
rtems_status_code mpc55xx_interrupt_handler_install(rtems_vector_number vector, const char *info, rtems_option options, unsigned priority, rtems_interrupt_handler handler, void *arg)
Installs interrupt handler and sets priority.
Definition: irq.c:103
rtems_status_code mpc55xx_intc_raise_software_irq(rtems_vector_number vector)
Raises the software IRQ with number vector.
Definition: irq.c:77
rtems_status_code mpc55xx_intc_clear_software_irq(rtems_vector_number vector)
Clears the software IRQ with number vector.
Definition: irq.c:90
ISR_Vector_number rtems_vector_number
This integer type represents interrupt vector numbers.
Definition: intr.h:102
void(* rtems_interrupt_handler)(void *)
Interrupt handler routines shall have this type.
Definition: intr.h:1030
uint32_t rtems_option
This type represents a Classic API directive option set.
Definition: options.h:126
rtems_status_code
This enumeration provides status codes for directives of the Classic API.
Definition: status.h:85
This header file is provided for backward compatiblility.