19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
42#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
53#define CPU_ISR_PASSES_FRAME_POINTER TRUE
55#define CPU_HARDWARE_FP FALSE
57#define CPU_SOFTWARE_FP FALSE
83#define CPU_ALL_TASKS_ARE_FP FALSE
100#define CPU_IDLE_TASK_IS_FP FALSE
131#define CPU_USE_DEFERRED_FP_SWITCH TRUE
133#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
146#define CPU_STACK_GROWS_UP FALSE
149#define CPU_CACHE_LINE_BYTES 32
151#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
163#define CPU_MODES_INTERRUPT_MASK 0x00000001
165#define CPU_MAXIMUM_PROCESSORS 32
259#define _CPU_Context_Get_SP( _context ) \
327#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
338#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
344#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
351#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
363#define CPU_STACK_MINIMUM_SIZE (1024*4)
365#define CPU_SIZEOF_POINTER 4
377#define CPU_ALIGNMENT 4
402#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
404#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
406#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
427#define _CPU_ISR_Disable( _isr_cookie ) \
428 lm32_disable_interrupts( _isr_cookie );
441#define _CPU_ISR_Enable( _isr_cookie ) \
442 lm32_enable_interrupts( _isr_cookie );
456#define _CPU_ISR_Flash( _isr_cookie ) \
457 lm32_flash_interrupts( _isr_cookie );
459static inline bool _CPU_ISR_Is_enabled( uint32_t level )
461 return ( level & 0x0001 ) != 0;
479#define _CPU_ISR_Set_level( new_level ) \
481 _CPU_ISR_Enable( ( new_level==0 ) ? 1 : 0 ); \
535#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
536 _isr, _entry_point, _is_fp, _tls_area ) \
538 uint32_t _stack = (uint32_t)(_stack_base) + (_size) - 4; \
542 (_the_context)->gp = (uint32_t)_gp; \
543 (_the_context)->fp = (uint32_t)_stack; \
544 (_the_context)->sp = (uint32_t)_stack; \
545 (_the_context)->ra = (uint32_t)(_entry_point); \
563#define _CPU_Context_Restart_self( _the_context ) \
564 _CPU_Context_restore( (_the_context) );
584#define _CPU_Context_Initialize_fp( _destination )
587 *(*(_destination)) = _CPU_Null_fp_context; \
593#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
595#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
613typedef void ( *CPU_ISR_raw_handler )( void );
617 CPU_ISR_raw_handler new_handler,
618 CPU_ISR_raw_handler *old_handler
624typedef void ( *CPU_ISR_handler )( uint32_t );
628 CPU_ISR_handler new_handler,
629 CPU_ISR_handler *old_handler
714static inline uint32_t CPU_swap_u32(
718 uint32_t byte1, byte2, byte3, byte4, swapped;
720 byte4 = (value >> 24) & 0xff;
721 byte3 = (value >> 16) & 0xff;
722 byte2 = (value >> 8) & 0xff;
723 byte1 = value & 0xff;
725 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
737 return v << 8 | v >> 8;
742typedef uint32_t CPU_Counter_ticks;
This header file provides basic definitions used by the API and the implementation.
void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.c:100
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:166
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
#define CPU_swap_u16(value)
Definition: cpu.h:597
#define ra
return address */
Definition: regs.h:66
#define sp
stack-pointer */
Definition: regs.h:64
#define fp
frame-pointer */
Definition: regs.h:65
#define gp
global data pointer */
Definition: regs.h:63
LM32 Set up Basic CPU Dependency Settings Based on Compiler Settings.
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Interrupt stack frame (ISF).
Definition: cpuimpl.h:64
SPARC basic context.
Definition: cpu.h:213
Thread register context.
Definition: cpu.h:173
unsigned ie
Definition: tte.h:3