RTEMS 6.1-rc7
Loading...
Searching...
No Matches
irq.h
Go to the documentation of this file.
1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * COPYRIGHT (c) 1989-2012.
13 * On-Line Applications Research Corporation (OAR).
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef LIBBSP_MIPS_MALTA_IRQ_H
38#define LIBBSP_MIPS_MALTA_IRQ_H
39
40#ifndef ASM
41 #include <rtems.h>
42 #include <rtems/irq.h>
43 #include <rtems/irq-extension.h>
44 #include <rtems/score/mips.h>
45#endif
46
53/*
54 * Interrupt Vector Numbers
55 *
56 * NOTE: Numbers 0-15 directly map to levels on the IRC.
57 * Number 16 is "1xxxx" per p. 164 of the TX3904 manual.
58 */
59#define MALTA_CPU_INT_START MIPS_INTERRUPT_BASE+0
60#define MALTA_CPU_INT_SW0 MALTA_CPU_INT_START+0
61#define MALTA_CPU_INT_SW2 MALTA_CPU_INT_START+1
62#define MALTA_CPU_INT0 MALTA_CPU_INT_START+2
63#define MALTA_CPU_INT1 MALTA_CPU_INT_START+3
64#define MALTA_CPU_INT2 MALTA_CPU_INT_START+4
65#define MALTA_CPU_INT3 MALTA_CPU_INT_START+5
66#define MALTA_CPU_INT4 MALTA_CPU_INT_START+6
67#define MALTA_CPU_INT5 MALTA_CPU_INT_START+7
68#define MALTA_CPU_INT_LAST MALTA_CPU_INT5
69
70#define MALTA_SB_IRQ_START MALTA_CPU_INT_LAST+1
71#define MALTA_SB_IRQ_0 MALTA_SB_IRQ_START+0
72#define MALTA_SB_IRQ_1 MALTA_SB_IRQ_START+1
73#define MALTA_SB_IRQ_2 MALTA_SB_IRQ_START+2
74#define MALTA_SB_IRQ_3 MALTA_SB_IRQ_START+3
75#define MALTA_SB_IRQ_4 MALTA_SB_IRQ_START+4
76#define MALTA_SB_IRQ_5 MALTA_SB_IRQ_START+5
77#define MALTA_SB_IRQ_6 MALTA_SB_IRQ_START+6
78#define MALTA_SB_IRQ_7 MALTA_SB_IRQ_START+7
79#define MALTA_SB_IRQ_8 MALTA_SB_IRQ_START+8
80#define MALTA_SB_IRQ_9 MALTA_SB_IRQ_START+9
81#define MALTA_SB_IRQ_10 MALTA_SB_IRQ_START+10
82#define MALTA_SB_IRQ_11 MALTA_SB_IRQ_START+11
83#define MALTA_SB_IRQ_12 MALTA_SB_IRQ_START+12
84#define MALTA_SB_IRQ_13 MALTA_SB_IRQ_START+13
85#define MALTA_SB_IRQ_14 MALTA_SB_IRQ_START+14
86#define MALTA_SB_IRQ_15 MALTA_SB_IRQ_START+15
87#define MALTA_SB_IRQ_LAST MALTA_SB_IRQ_15
88
89#define MALTA_PCI_ADP_START MALTA_SB_IRQ_LAST+1
90#define MALTA_PCI_ADP20 MALTA_PCI_ADP_START+0
91#define MALTA_PCI_ADP21 MALTA_PCI_ADP_START+1
92#define MALTA_PCI_ADP22 MALTA_PCI_ADP_START+2
93#define MALTA_PCI_ADP27 MALTA_PCI_ADP_START+3
94#define MALTA_PCI_ADP28 MALTA_PCI_ADP_START+4
95#define MALTA_PCI_ADP29 MALTA_PCI_ADP_START+5
96#define MALTA_PCI_ADP30 MALTA_PCI_ADP_START+6
97#define MALTA_PCI_ADP31 MALTA_PCI_ADP_START+7
98#define MALTA_PCI_ADP_LAST MALTA_PCI_ADP31
99#
100
101#define BSP_INTERRUPT_VECTOR_COUNT (MALTA_PCI_ADP_LAST + 1)
102
103/*
104 * Redefine interrupts with more descriptive names.
105 * The Generic ones above match the hardware name,
106 * where these match the device name.
107 */
108#define MALTA_INT_SOUTHBRIDGE_INTR MALTA_CPU_INT0
109#define MALTA_INT_SOUTHBRIDGE_SMI MALTA_CPU_INT1
110#define MALTA_INT_TTY2 MALTA_CPU_INT2
111#define MALTA_INT_COREHI MALTA_CPU_INT3
112#define MALTA_INT_CORELO MALTA_CPU_INT4
113#define MALTA_INT_TICKER MALTA_CPU_INT5
114
115#define MALTA_IRQ_TIMER_SOUTH_BRIDGE MALTA_SB_IRQ_0
116#define MALTA_IRQ_KEYBOARD_SUPERIO MALTA_SB_IRQ_1
117#define MALTA_IRQ_RESERVED1_SOUTH_BRIDGE MALTA_SB_IRQ_2
118#define MALTA_IRQ_TTY1 MALTA_SB_IRQ_3
119#define MALTA_IRQ_TTY0 MALTA_SB_IRQ_4
120#define MALTA_IRQ_NOT_USED MALTA_SB_IRQ_5
121#define MALTA_IRQ_FLOPPY_SUPERIO MALTA_SB_IRQ_6
122#define MALTA_IRQ_PARALLEL_PORT_SUPERIO MALTA_SB_IRQ_7
123#define MALTA_IRQ_REALTIME_CLOCK_SOUTH_BRIDGE MALTA_SB_IRQ_8
124#define MALTA_IRQ_I2C_SOUTH_BRIDGE MALTA_SB_IRQ_9
125/* PCI A, PCI B (including Ethernet) PCI slot 1..4, Ethernet */
126#define MALTA_IRQ_PCI_A_B MALTA_SB_IRQ_10
127/* PCI slot 1..4 (audio, USB) */
128#define MALTA_IRQ_PCI_C_D MALTA_SB_IRQ_11
129#define MALTA_IRQ_MOUSE_SUPERIO MALTA_SB_IRQ_12
130#define MALTA_IRQ_RESERVED2_SOUTH_BRIDGE MALTA_SB_IRQ_13
131#define MALTA_IRQ_PRIMARY_IDE MALTA_SB_IRQ_14
132#define MALTA_IRQ_SECONDARY_IDE MALTA_SB_IRQ_15
133#define MALTA_IRQ_SOUTH_BRIDGE MALTA_PCI_ADP20
134#define MALTA_IRQ_ETHERNET MALTA_IRQ_PCI_A_B
135#define MALTA_IRQ_AUDIO MALTA_PCI_ADP22
136#define MALTA_IRQ_CORE_CARD MALTA_PCI_ADP27
137#define MALTA_IRQ_PCI_CONNECTOR_1 MALTA_PCI_ADP28
138#define MALTA_IRQ_PCI_CONNECTOR_2 MALTA_PCI_ADP29
139#define MALTA_IRQ_PCI_CONNECTOR_3 MALTA_PCI_ADP30
140#define MALTA_IRQ_PCI_CONNECTOR_4 MALTA_PCI_ADP31
141
142#ifndef ASM
143
144#endif /* ASM */
145
148#endif /* LIBBSP_MIPS_MALTA_IRQ_H */
This header file is provided for backward compatiblility.
Information to build RTEMS for a "no cpu" while in protected mode.
This header file defines the RTEMS Classic API.