![]() |
RTEMS 6.1-rc7
|
PSSI. More...
#include <stm32h723xx.h>
Data Fields | |
__IO uint32_t | CR |
__IO uint32_t | SR |
__IO uint32_t | RIS |
__IO uint32_t | IER |
__IO uint32_t | MIS |
__IO uint32_t | ICR |
__IO uint32_t | RESERVED1 [4] |
__IO uint32_t | DR |
__IO uint32_t | RESERVED2 [241] |
__IO uint32_t | HWCFGR |
__IO uint32_t | VERR |
__IO uint32_t | IPIDR |
__IO uint32_t | SIDR |
PSSI.
__IO uint32_t PSSI_TypeDef::CR |
PSSI control register 1, Address offset: 0x000
__IO uint32_t PSSI_TypeDef::DR |
PSSI data register, Address offset: 0x028
__IO uint32_t PSSI_TypeDef::HWCFGR |
PSSI IP HW configuration register, Address offset: 0x3F0
__IO uint32_t PSSI_TypeDef::ICR |
PSSI interrupt clear register, Address offset: 0x014
__IO uint32_t PSSI_TypeDef::IER |
PSSI interrupt enable register, Address offset: 0x00C
__IO uint32_t PSSI_TypeDef::IPIDR |
PSSI IP ID register, Address offset: 0x3F8
__IO uint32_t PSSI_TypeDef::MIS |
PSSI masked interrupt status register, Address offset: 0x010
__IO uint32_t PSSI_TypeDef::RESERVED1 |
Reserved, 0x018 - 0x024
__IO uint32_t PSSI_TypeDef::RESERVED2 |
Reserved, 0x02C - 0x3EC
__IO uint32_t PSSI_TypeDef::RIS |
PSSI raw interrupt status register, Address offset: 0x008
__IO uint32_t PSSI_TypeDef::SIDR |
PSSI SIZE ID register, Address offset: 0x3FC
__IO uint32_t PSSI_TypeDef::SR |
PSSI status register, Address offset: 0x004
__IO uint32_t PSSI_TypeDef::VERR |
PSSI IP version register, Address offset: 0x3F4