RTEMS 6.1-rc7
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arm-a9mpcore-regs.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (c) 2013 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H
37#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H
38
39#include <bsp/utility.h>
40
51typedef struct {
52 uint32_t ctrl;
53#define A9MPCORE_SCU_CTRL_SCU_EN BSP_BIT32(0)
54#define A9MPCORE_SCU_CTRL_ADDR_FLT_EN BSP_BIT32(1)
55#define A9MPCORE_SCU_CTRL_RAM_PAR_EN BSP_BIT32(2)
56#define A9MPCORE_SCU_CTRL_SCU_SPEC_LINE_FILL_EN BSP_BIT32(3)
57#define A9MPCORE_SCU_CTRL_FORCE_PORT_0_EN BSP_BIT32(4)
58#define A9MPCORE_SCU_CTRL_SCU_STANDBY_EN BSP_BIT32(5)
59#define A9MPCORE_SCU_CTRL_IC_STANDBY_EN BSP_BIT32(6)
60 uint32_t cfg;
61#define A9MPCORE_SCU_CFG_CPU_COUNT(val) BSP_FLD32(val, 0, 1)
62#define A9MPCORE_SCU_CFG_CPU_COUNT_GET(reg) BSP_FLD32GET(reg, 0, 1)
63#define A9MPCORE_SCU_CFG_CPU_COUNT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1)
64#define A9MPCORE_SCU_CFG_SMP_MODE(val) BSP_FLD32(val, 4, 7)
65#define A9MPCORE_SCU_CFG_SMP_MODE_GET(reg) BSP_FLD32GET(reg, 4, 7)
66#define A9MPCORE_SCU_CFG_SMP_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
67#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE(val) BSP_FLD32(val, 8, 15)
68#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_GET(reg) BSP_FLD32GET(reg, 8, 15)
69#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
70 uint32_t pwrst;
71 uint32_t invss;
72#define A9MPCORE_SCU_INVSS_CPU0(ways) BSP_FLD32(val, 0, 3)
73#define A9MPCORE_SCU_INVSS_CPU0_GET(reg) /* Write only register */
74#define A9MPCORE_SCU_INVSS_CPU0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
75#define A9MPCORE_SCU_INVSS_CPU1(ways) BSP_FLD32(val, 4, 7)
76#define A9MPCORE_SCU_INVSS_CPU1_GET(reg) /* Write only register */
77#define A9MPCORE_SCU_INVSS_CPU1_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
78#define A9MPCORE_SCU_INVSS_CPU2(ways) BSP_FLD32(val, 8, 11)
79#define A9MPCORE_SCU_INVSS_CPU2_GET(reg) /* Write only register */
80#define A9MPCORE_SCU_INVSS_CPU2_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
81#define A9MPCORE_SCU_INVSS_CPU3(ways) BSP_FLD32(val, 12, 15)
82#define A9MPCORE_SCU_INVSS_CPU3_GET(reg) /* Write only register */
83#define A9MPCORE_SCU_INVSS_CPU3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
84 uint32_t reserved_09[8];
85 uint32_t diagn_ctrl;
86#define A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE BSP_BIT32(0)
87 uint32_t reserved_10[3];
88 uint32_t fltstart;
89 uint32_t fltend;
90 uint32_t reserved_48[2];
91 uint32_t sac;
92 uint32_t snsac;
94
95typedef struct {
97
98typedef struct {
99 uint32_t cntrlower;
100 uint32_t cntrupper;
101#define A9MPCORE_GT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15)
102#define A9MPCORE_GT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15)
103#define A9MPCORE_GT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
104#define A9MPCORE_GT_CTRL_AUTOINC_EN BSP_BIT32(3)
105#define A9MPCORE_GT_CTRL_IRQ_EN BSP_BIT32(2)
106#define A9MPCORE_GT_CTRL_COMP_EN BSP_BIT32(1)
107#define A9MPCORE_GT_CTRL_TMR_EN BSP_BIT32(0)
108 uint32_t ctrl;
109#define A9MPCORE_GT_IRQST_EFLG BSP_BIT32(0)
110 uint32_t irqst;
111 uint32_t cmpvallower;
112 uint32_t cmpvalupper;
113 uint32_t autoinc;
115
116typedef struct {
117 uint32_t load;
118 uint32_t cntr;
119 uint32_t ctrl;
120#define A9MPCORE_PT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15)
121#define A9MPCORE_PT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15)
122#define A9MPCORE_PT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
123#define A9MPCORE_PT_CTRL_IRQ_EN BSP_BIT32(2)
124#define A9MPCORE_PT_CTRL_AUTO_RLD BSP_BIT32(1)
125#define A9MPCORE_PT_CTRL_TMR_EN BSP_BIT32(0)
126 uint32_t irqst;
127#define A9MPCORE_PT_IRQST_EFLG BSP_BIT32(0)
129
130typedef struct {
131 uint32_t load;
132 uint32_t cntr;
133 uint32_t ctrl;
134 uint32_t irqst;
135 uint32_t rstst;
136 uint32_t dis;
138
139typedef struct {
141
142typedef struct {
143 a9mpcore_scu scu;
144 uint32_t reserved_58[42];
145 a9mpcore_gic gic;
146 uint32_t reserved_100[64];
147 a9mpcore_gt gt;
148 uint32_t reserved_21c[249];
149 a9mpcore_pt pt;
150 uint32_t reserved_610[4];
151 a9mpcore_pw pw;
152 uint32_t reserved_638[626];
153 a9mpcore_idist idist;
154} a9mpcore;
155
158#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H */
This header file provides utility macros for BSPs.
Definition: arm-a9mpcore-regs.h:95
Definition: arm-a9mpcore-regs.h:98
Definition: arm-a9mpcore-regs.h:139
Definition: arm-a9mpcore-regs.h:116
Definition: arm-a9mpcore-regs.h:130
Definition: arm-a9mpcore-regs.h:51
Definition: arm-a9mpcore-regs.h:142