RTEMS 6.1-rc7
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fsl_gpc.h
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2019 NXP
4 * All rights reserved.
5 *
6 *
7 * SPDX-License-Identifier: BSD-3-Clause
8 */
9
10#ifndef _FSL_GPC_H_
11#define _FSL_GPC_H_
12
13#include "fsl_common.h"
14
20/*******************************************************************************
21 * Definitions
22 ******************************************************************************/
23
27#define FSL_GPC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
30#if defined(__cplusplus)
31extern "C" {
32#endif
33
34/*******************************************************************************
35 * API
36 ******************************************************************************/
37
38#if (defined(FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM) && FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM)
44static inline void GPC_AllowIRQs(GPC_Type *base)
45{
46 base->CNTR &= ~GPC_CNTR_GPCIRQM_MASK; /* Events would not be masked. */
47}
48
54static inline void GPC_DisallowIRQs(GPC_Type *base)
55{
56 base->CNTR |= GPC_CNTR_GPCIRQM_MASK; /* Mask all the events. */
57}
58#endif /* FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM */
59
66void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId);
67
74void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId);
75
83bool GPC_GetIRQStatusFlag(GPC_Type *base, uint32_t irqId);
84
85#if (defined(FSL_FEATURE_GPC_HAS_CNTR_L2PGE) && FSL_FEATURE_GPC_HAS_CNTR_L2PGE)
99static inline void GPC_RequestL2CachePowerDown(GPC_Type *base, bool enable)
100{
101 if (enable)
102 {
103 base->CNTR |= GPC_CNTR_L2_PGE_MASK; /* OFF. */
104 }
105 else
106 {
107 base->CNTR &= ~GPC_CNTR_L2_PGE_MASK; /* ON. */
108 }
109}
110#endif /* FSL_FEATURE_GPC_HAS_CNTR_L2PGE */
111
112#if (defined(FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE) && FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE)
124static inline void GPC_RequestPdram0PowerDown(GPC_Type *base, bool enable)
125{
126 if (enable)
127 {
128 base->CNTR |= GPC_CNTR_PDRAM0_PGE_MASK; /* OFF. */
129 }
130 else
131 {
132 base->CNTR &= ~GPC_CNTR_PDRAM0_PGE_MASK; /* ON. */
133 }
134}
135#endif /* FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE */
136
137#if (defined(FSL_FEATURE_GPC_HAS_CNTR_VADC) && FSL_FEATURE_GPC_HAS_CNTR_VADC)
146static inline void GPC_RequestVADCPowerDown(GPC_Type *base, bool enable)
147{
148 if (enable)
149 {
150 base->CNTR &= ~GPC_CNTR_VADC_EXT_PWD_N_MASK; /* VADC power down. */
151 }
152 else
153 {
154 base->CNTR |= GPC_CNTR_VADC_EXT_PWD_N_MASK; /* VADC not power down. */
155 }
156}
157
164static inline bool GPC_GetVADCPowerDownFlag(GPC_Type *base)
165{
166 return (GPC_CNTR_VADC_ANALOG_OFF_MASK == (GPC_CNTR_VADC_ANALOG_OFF_MASK & base->CNTR));
167}
168#endif /* FSL_FEATURE_GPC_HAS_CNTR_VADC */
169
170#if (defined(FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR) && FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR)
177static inline bool GPC_HasDVFS0ChangeRequest(GPC_Type *base)
178{
179 return (GPC_CNTR_DVFS0CR_MASK == (GPC_CNTR_DVFS0CR_MASK & base->CNTR));
180}
181#endif /* FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR */
182
183#if (defined(FSL_FEATURE_GPC_HAS_CNTR_DISPLAY) && FSL_FEATURE_GPC_HAS_CNTR_DISPLAY)
190static inline void GPC_RequestDisplayPowerOn(GPC_Type *base, bool enable)
191{
192 if (enable)
193 {
194 base->CNTR |= GPC_CNTR_DISPLAY_PUP_REQ_MASK; /* Power on sequence. */
195 }
196 else
197 {
198 base->CNTR |= GPC_CNTR_DISPLAY_PDN_REQ_MASK; /* Power down sequence. */
199 }
200}
201#endif /* FSL_FEATURE_GPC_HAS_CNTR_DISPLAY */
202
209static inline void GPC_RequestMEGAPowerOn(GPC_Type *base, bool enable)
210{
211 if (enable)
212 {
213 base->CNTR |= GPC_CNTR_MEGA_PUP_REQ_MASK; /* Power on sequence. */
214 }
215 else
216 {
217 base->CNTR |= GPC_CNTR_MEGA_PDN_REQ_MASK; /* Power down sequence. */
218 }
219}
220
225#if defined(__cplusplus)
226}
227#endif
231#endif /* _FSL_GPC_H_ */
bool GPC_GetIRQStatusFlag(GPC_Type *base, uint32_t irqId)
Get the IRQ/Event flag.
Definition: fsl_gpc.c:80
void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId)
Enable the IRQ.
Definition: fsl_gpc.c:23
void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId)
Disable the IRQ.
Definition: fsl_gpc.c:51
Definition: MIMXRT1052.h:22336