20#ifndef STM32H7xx_HAL_ADC_EX_H
21#define STM32H7xx_HAL_ADC_EX_H
50#if defined(ADC_VER_V5_V90)
124#if defined(ADC_VER_V5_V90)
125 uint32_t InjectedOffsetSign;
130 FunctionalState InjectedOffsetSaturation;
238#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE)
239#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)
240#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)
241#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)
242#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)
243#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)
244#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)
245#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)
246#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)
247#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)
248#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)
249#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)
250#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)
251#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)
252#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)
253#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)
254#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)
256#define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2)
257#define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4)
259#define ADC_EXTERNALTRIGINJEC_LPTIM1_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT)
260#define ADC_EXTERNALTRIGINJEC_LPTIM2_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT)
261#define ADC_EXTERNALTRIGINJEC_LPTIM3_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT)
270#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL)
271#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0)
272#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1)
273#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN)
282#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED)
283#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED)
292#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U)
293#define ADC_OFFSET_1 (LL_ADC_OFFSET_1)
294#define ADC_OFFSET_2 (LL_ADC_OFFSET_2)
295#define ADC_OFFSET_3 (LL_ADC_OFFSET_3)
296#define ADC_OFFSET_4 (LL_ADC_OFFSET_4)
301#if defined(ADC_VER_V5_V90)
306#define ADC3_OFFSET_SIGN_NEGATIVE (0x00000000UL)
307#define ADC3_OFFSET_SIGN_POSITIVE (ADC3_OFR1_OFFSETPOS)
317#define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1)
318#define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2)
319#define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3)
320#define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4)
329#define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT)
330#define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT)
331#define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL)
332#define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT)
333#define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN)
334#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)
335#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)
336#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM)
342#define ADC_DUALMODEDATAFORMAT_DISABLED (0x00000000UL)
343#define ADC_DUALMODEDATAFORMAT_32_10_BITS (ADC_CCR_DAMDF_1)
344#define ADC_DUALMODEDATAFORMAT_8_BITS ((ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1))
353#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5)
354#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5)
355#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5)
356#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5)
357#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5)
358#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5)
359#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5)
360#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)
361#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)
374#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR)
375#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED)
376#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED)
385#define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\
386 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\
387 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\
388 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
389 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\
390 ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN )
399#define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
400 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
401 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
413#define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMNGT | ADC_CFGR_AUTDLY))
417#if defined(ADC_VER_V5_V90)
424#define ADC3_CFGR_FIELDS_2 ((ADC3_CFGR_DMACFG | ADC_CFGR_AUTDLY))
430#if defined(DFSDM1_Channel0)
435#define ADC_DFSDM_MODE_DISABLE (0x00000000UL)
436#define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE)
467#define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \
468 LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)
489#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
490 (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
497#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \
498 (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == 0UL \
506#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \
507 (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance))
518#define ADC_IS_INDEPENDENT(__HANDLE__) \
519 ( ( ( ((__HANDLE__)->Instance) == ADC3) \
533#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
540#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
547#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
554#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
561#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
568#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
575#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
582#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__))
584#if defined(ADC_VER_V5_V90)
590#define ADC3_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC3_CFGR_DMACFG_Pos)
597#define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos)
604#define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__))
611#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos)
618#define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos)
625#define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL)
632#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)
647#if defined(ADC_VER_V5_3)
648#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
650 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \
651 ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
653 ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
656#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
657 (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \
658 ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
660 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \
661 ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
663 ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
667#if defined(ADC_VER_V5_V90)
668#define ADC3_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
669 ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC3_CFGR_RES) >> 3UL) * 2UL))
686#if defined(ADC_VER_V5_3)
687#if defined(ADC_VER_V5_V90)
688#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
689 ( ((__HANDLE__)->Instance == ADC3) \
690 ?((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC3_CFGR_RES)>> 3UL)*2UL)) \
692 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \
693 ?((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
695 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
698#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
700 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \
701 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
703 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
708#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
709 (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \
710 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
712 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \
713 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
715 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
732#if defined(ADC_VER_V5_3) || defined(ADC_VER_V5_V90)
733#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
735 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \
736 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
738 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
741#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
742 (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \
743 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
745 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \
746 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
748 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
761#define ADC12_COMMON_REGISTER(__HANDLE__) (ADC12_COMMON)
768#define ADC3_COMMON_REGISTER(__HANDLE__) (ADC3_COMMON)
777#define ADC_MASTER_REGISTER(__HANDLE__) \
778 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \
780 ((__HANDLE__)->Instance) \
785#define ADC_MASTER_REGISTER(__HANDLE__) ( (ADC1))
793#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \
794 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
796 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \
797 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \
798 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \
808#define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
809 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2) \
813 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET) \
821#define ADC3_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
822 ( ( ((__HANDLE__)->Instance == ADC3) \
826 ((ADC3_COMMON->CCR & ADC_CCR_DUAL) == RESET) \
835#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \
836 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
840 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
841 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
842 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
844#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \
845 ( ( ((__HANDLE__)->Instance == ADC1) \
849 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
850 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
851 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
860#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \
861 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
865 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
866 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \
867 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
869#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \
870 ( ( ((__HANDLE__)->Instance == ADC1) \
874 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
875 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \
876 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
879#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \
895#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
896 ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
905#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC3)
907#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2)
916#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC3)
918#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2)
927#define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC3)
929#define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2)
937#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
944#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FFU))
946#if defined(ADC_VER_V5_V90)
952#define IS_ADC_CALFACT_ADC3(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
960#define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \
961 ((__CHANNEL__) == ADC_CHANNEL_1) || \
962 ((__CHANNEL__) == ADC_CHANNEL_2) || \
963 ((__CHANNEL__) == ADC_CHANNEL_3) || \
964 ((__CHANNEL__) == ADC_CHANNEL_4) || \
965 ((__CHANNEL__) == ADC_CHANNEL_5) || \
966 ((__CHANNEL__) == ADC_CHANNEL_6) || \
967 ((__CHANNEL__) == ADC_CHANNEL_7) || \
968 ((__CHANNEL__) == ADC_CHANNEL_8) || \
969 ((__CHANNEL__) == ADC_CHANNEL_9) || \
970 ((__CHANNEL__) == ADC_CHANNEL_10) || \
971 ((__CHANNEL__) == ADC_CHANNEL_11) || \
972 ((__CHANNEL__) == ADC_CHANNEL_12) || \
973 ((__CHANNEL__) == ADC_CHANNEL_13) || \
974 ((__CHANNEL__) == ADC_CHANNEL_14) || \
975 ((__CHANNEL__) == ADC_CHANNEL_15) || \
976 ((__CHANNEL__) == ADC_CHANNEL_16) || \
977 ((__CHANNEL__) == ADC_CHANNEL_17) || \
978 ((__CHANNEL__) == ADC_CHANNEL_18) || \
979 ((__CHANNEL__) == ADC_CHANNEL_19) || \
980 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
981 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
982 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2)|| \
983 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2)|| \
984 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) )
991#define IS_ADC1_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \
992 ((__CHANNEL__) == ADC_CHANNEL_2) ||\
993 ((__CHANNEL__) == ADC_CHANNEL_3) ||\
994 ((__CHANNEL__) == ADC_CHANNEL_4) ||\
995 ((__CHANNEL__) == ADC_CHANNEL_5) ||\
996 ((__CHANNEL__) == ADC_CHANNEL_10) ||\
997 ((__CHANNEL__) == ADC_CHANNEL_11) ||\
998 ((__CHANNEL__) == ADC_CHANNEL_12) ||\
999 ((__CHANNEL__) == ADC_CHANNEL_16) ||\
1000 ((__CHANNEL__) == ADC_CHANNEL_18) )
1007#define IS_ADC2_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \
1008 ((__CHANNEL__) == ADC_CHANNEL_2) || \
1009 ((__CHANNEL__) == ADC_CHANNEL_3) || \
1010 ((__CHANNEL__) == ADC_CHANNEL_4) || \
1011 ((__CHANNEL__) == ADC_CHANNEL_5) || \
1012 ((__CHANNEL__) == ADC_CHANNEL_10) || \
1013 ((__CHANNEL__) == ADC_CHANNEL_11) || \
1014 ((__CHANNEL__) == ADC_CHANNEL_12) || \
1015 ((__CHANNEL__) == ADC_CHANNEL_18) )
1022#define IS_ADC3_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \
1023 ((__CHANNEL__) == ADC_CHANNEL_2) || \
1024 ((__CHANNEL__) == ADC_CHANNEL_3) || \
1025 ((__CHANNEL__) == ADC_CHANNEL_4) || \
1026 ((__CHANNEL__) == ADC_CHANNEL_5) || \
1027 ((__CHANNEL__) == ADC_CHANNEL_10) || \
1028 ((__CHANNEL__) == ADC_CHANNEL_11) || \
1029 ((__CHANNEL__) == ADC_CHANNEL_13) || \
1030 ((__CHANNEL__) == ADC_CHANNEL_14) || \
1031 ((__CHANNEL__) == ADC_CHANNEL_15) )
1038#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \
1039 ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) )
1046#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
1047 ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \
1048 ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \
1049 ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \
1050 ((__OFFSET_NUMBER__) == ADC_OFFSET_4) )
1051#if defined(ADC_VER_V5_V90)
1057#define IS_ADC3_OFFSET_SIGN(__OFFSET_SIGN__) (((__OFFSET_SIGN__) == ADC3_OFFSET_SIGN_NEGATIVE) || \
1058 ((__OFFSET_SIGN__) == ADC3_OFFSET_SIGN_POSITIVE) )
1065#define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
1066 ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
1067 ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
1068 ((__CHANNEL__) == ADC_INJECTED_RANK_4) )
1076#define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
1077 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
1078 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
1079 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
1080 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
1081 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
1082 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \
1083 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
1084 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
1085 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
1086 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
1087 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
1088 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
1089 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
1090 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
1091 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
1092 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2) || \
1093 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4) || \
1094 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_OUT) || \
1095 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_OUT) || \
1096 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_OUT) || \
1098 ((__INJTRIG__) == ADC_SOFTWARE_START) )
1100#define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
1101 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
1102 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
1103 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
1104 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
1105 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
1106 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \
1107 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
1108 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
1109 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
1110 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
1111 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
1112 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
1113 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
1114 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
1115 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
1116 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_OUT) || \
1117 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_OUT) || \
1118 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_OUT) || \
1120 ((__INJTRIG__) == ADC_SOFTWARE_START) )
1127#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
1128 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
1129 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
1130 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
1137#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \
1138 ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
1139 ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
1140 ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
1141 ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \
1142 ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \
1143 ((__MODE__) == ADC_DUALMODE_INTERL) || \
1144 ((__MODE__) == ADC_DUALMODE_ALTERTRIG) )
1151#define IS_ADC_DUAL_DATA_MODE(MODE) (((MODE) == ADC_DUALMODEDATAFORMAT_DISABLED) || \
1152 ((MODE) == ADC_DUALMODEDATAFORMAT_32_10_BITS) || \
1153 ((MODE) == ADC_DUALMODEDATAFORMAT_8_BITS) )
1160#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \
1161 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \
1162 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \
1163 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \
1164 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
1165 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
1166 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
1167 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
1168 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) )
1175#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
1176 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
1177 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) )
1184#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
1185 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
1186 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
1187 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
1188 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
1189 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
1190 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
1192#if defined(ADC_VER_V5_V90)
1198#define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE_ADC3(__FILTERING_MODE__) (((__FILTERING_MODE__) == ADC3_AWD_FILTERING_NONE) || \
1199 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_2SAMPLES) || \
1200 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_3SAMPLES) || \
1201 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_4SAMPLES) || \
1202 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_5SAMPLES) || \
1203 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_6SAMPLES) || \
1204 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_7SAMPLES) || \
1205 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_8SAMPLES) )
1214#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \
1215 ((__CONVERSION__) == ADC_INJECTED_GROUP) || \
1216 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) )
1223#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
1224 ((__EVENT__) == ADC_AWD_EVENT) || \
1225 ((__EVENT__) == ADC_AWD2_EVENT) || \
1226 ((__EVENT__) == ADC_AWD3_EVENT) || \
1227 ((__EVENT__) == ADC_OVR_EVENT) || \
1228 ((__EVENT__) == ADC_JQOVF_EVENT) )
1235#define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) >= 1UL) && ((RATIO) <= 1024UL))
1237#if defined(ADC_VER_V5_V90)
1243#define IS_ADC_OVERSAMPLING_RATIO_ADC3(__RATIO__) (((__RATIO__) == ADC3_OVERSAMPLING_RATIO_2 ) || \
1244 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_4 ) || \
1245 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_8 ) || \
1246 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_16 ) || \
1247 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_32 ) || \
1248 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_64 ) || \
1249 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_128 ) || \
1250 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_256 ))
1258#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
1259 ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \
1260 ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \
1261 ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \
1262 ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \
1263 ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \
1264 ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \
1265 ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \
1266 ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ) || \
1267 ((__SHIFT__) == ADC_RIGHTBITSHIFT_9 ) || \
1268 ((__SHIFT__) == ADC_RIGHTBITSHIFT_10 ) || \
1269 ((__SHIFT__) == ADC_RIGHTBITSHIFT_11 ))
1276#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
1277 ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
1284#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
1285 ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
1295#if defined(DFSDM1_Channel0)
1296#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) || \
1297 ((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) )
1299#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
1310#if defined(DFSDM1_Channel0)
1311#define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig)
1313#define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)
1333uint32_t HAL_ADCEx_Calibration_GetValue(
ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
1355uint32_t HAL_ADCEx_InjectedGetValue(
ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
ADC handle Structure definition.
Definition: stm32h7xx_hal_adc.h:412
ADC Injected Conversion Oversampling structure definition.
Definition: stm32h7xx_hal_adc_ex.h:48
uint32_t Ratio
Definition: stm32h7xx_hal_adc_ex.h:49
uint32_t RightBitShift
Definition: stm32h7xx_hal_adc_ex.h:56
Structure definition of ADC group injected and ADC channel affected to ADC group injected.
Definition: stm32h7xx_hal_adc_ex.h:77
uint32_t InjectedOffsetNumber
Definition: stm32h7xx_hal_adc_ex.h:110
uint32_t InjectedSingleDiff
Definition: stm32h7xx_hal_adc_ex.h:98
FunctionalState AutoInjectedConv
Definition: stm32h7xx_hal_adc_ex.h:158
uint32_t InjectedSamplingTime
Definition: stm32h7xx_hal_adc_ex.h:87
FunctionalState InjectedOffsetSignedSaturation
Definition: stm32h7xx_hal_adc_ex.h:138
uint32_t ExternalTrigInjecConvEdge
Definition: stm32h7xx_hal_adc_ex.h:184
FunctionalState QueueInjectedContext
Definition: stm32h7xx_hal_adc_ex.h:167
ADC_InjOversamplingTypeDef InjecOversampling
Definition: stm32h7xx_hal_adc_ex.h:194
uint32_t InjectedChannel
Definition: stm32h7xx_hal_adc_ex.h:78
FunctionalState InjectedDiscontinuousConvMode
Definition: stm32h7xx_hal_adc_ex.h:148
uint32_t ExternalTrigInjecConv
Definition: stm32h7xx_hal_adc_ex.h:178
uint32_t InjectedOffsetRightShift
Definition: stm32h7xx_hal_adc_ex.h:121
uint32_t InjectedNbrOfConversion
Definition: stm32h7xx_hal_adc_ex.h:142
uint32_t InjectedOffset
Definition: stm32h7xx_hal_adc_ex.h:114
FunctionalState InjecOversamplingMode
Definition: stm32h7xx_hal_adc_ex.h:190
uint32_t InjectedRank
Definition: stm32h7xx_hal_adc_ex.h:82
Structure definition of ADC multimode.
Definition: stm32h7xx_hal_adc_ex.h:205
uint32_t Mode
Definition: stm32h7xx_hal_adc_ex.h:206
uint32_t TwoSamplingDelay
Definition: stm32h7xx_hal_adc_ex.h:212
uint32_t DualModeData
Definition: stm32h7xx_hal_adc_ex.h:209