RTEMS 6.1-rc7
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stm32h7xx_hal_eth_legacy.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_HAL_ETH_LEGACY_H
21#define STM32H7xx_HAL_ETH_LEGACY_H
22
23#ifdef __cplusplus
24 extern "C" {
25#endif
26
27
28/* Includes ------------------------------------------------------------------*/
29#include "stm32h7xx_hal_def.h"
30
31#if defined(ETH)
32
41/* Exported types ------------------------------------------------------------*/
42#ifndef ETH_TX_DESC_CNT
43 #define ETH_TX_DESC_CNT 4U
44#endif
45
46#ifndef ETH_RX_DESC_CNT
47 #define ETH_RX_DESC_CNT 4U
48#endif
49
50/*********************** Descriptors struct def section ************************/
59typedef struct
60{
61 __IO uint32_t DESC0;
62 __IO uint32_t DESC1;
63 __IO uint32_t DESC2;
64 __IO uint32_t DESC3;
65 uint32_t BackupAddr0; /* used to store rx buffer 1 address */
66 uint32_t BackupAddr1; /* used to store rx buffer 2 address */
67}ETH_DMADescTypeDef;
75typedef struct __ETH_BufferTypeDef
76{
77 uint8_t *buffer; /*<! buffer address */
78
79 uint32_t len; /*<! buffer length */
80
81 struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */
82}ETH_BufferTypeDef;
90typedef struct
91{
92 uint32_t TxDesc[ETH_TX_DESC_CNT]; /*<! Tx DMA descriptors addresses */
93
94 uint32_t CurTxDesc; /*<! Current Tx descriptor index for packet transmission */
95
96 uint32_t* PacketAddress[ETH_TX_DESC_CNT]; /*<! Ethernet packet addresses array */
97
98 uint32_t* CurrentPacketAddress; /*<! Current transmit NX_PACKET addresses */
99
100 uint32_t BuffersInUse; /*<! Buffers in Use */
101}ETH_TxDescListTypeDef;
109typedef struct
110{
111 uint32_t Attributes;
114 uint32_t Length;
116 ETH_BufferTypeDef *TxBuffer;
118 uint32_t SrcAddrCtrl;
121 uint32_t CRCPadCtrl;
124 uint32_t ChecksumCtrl;
127 uint32_t MaxSegmentSize;
130 uint32_t PayloadLen;
133 uint32_t TCPHeaderLen;
136 uint32_t VlanTag;
139 uint32_t VlanCtrl;
142 uint32_t InnerVlanTag;
145 uint32_t InnerVlanCtrl;
148}ETH_TxPacketConfig;
156typedef struct
157{
158 uint32_t RxDesc[ETH_RX_DESC_CNT]; /*<! Rx DMA descriptors addresses. */
159
160 uint32_t CurRxDesc; /*<! Current Rx descriptor, ready for next reception. */
161
162 uint32_t FirstAppDesc; /*<! First descriptor of last received packet. */
163
164 uint32_t AppDescNbr; /*<! Number of descriptors of last received packet. */
165
166 uint32_t AppContextDesc; /*<! If 1 a context descriptor is present in last received packet.
167 If 0 no context descriptor is present in last received packet. */
168
169 uint32_t ItMode; /*<! If 1, DMA will generate the Rx complete interrupt.
170 If 0, DMA will not generate the Rx complete interrupt. */
171}ETH_RxDescListTypeDef;
179typedef struct
180{
181 uint32_t SegmentCnt; /*<! Number of Rx Descriptors */
182
183 uint32_t VlanTag; /*<! Vlan Tag value */
184
185 uint32_t InnerVlanTag; /*<! Inner Vlan Tag value */
186
187 uint32_t Checksum; /*<! Rx Checksum status.
188 This parameter can be a value of @ref ETH_Rx_Checksum_Status */
189
190 uint32_t HeaderType; /*<! IP header type.
191 This parameter can be a value of @ref ETH_Rx_IP_Header_Type */
192
193 uint32_t PayloadType; /*<! Payload type.
194 This parameter can be a value of @ref ETH_Rx_Payload_Type */
195
196 uint32_t MacFilterStatus; /*<! MAC filter status.
197 This parameter can be a value of @ref ETH_Rx_MAC_Filter_Status */
198
199 uint32_t L3FilterStatus; /*<! L3 filter status
200 This parameter can be a value of @ref ETH_Rx_L3_Filter_Status */
201
202 uint32_t L4FilterStatus; /*<! L4 filter status
203 This parameter can be a value of @ref ETH_Rx_L4_Filter_Status */
204
205 uint32_t ErrorCode; /*<! Rx error code
206 This parameter can be a combination of @ref ETH_Rx_Error_Code */
207
208} ETH_RxPacketInfo;
216typedef struct
217{
218 uint32_t SourceAddrControl;
221 FunctionalState ChecksumOffload;
223 uint32_t InterPacketGapVal;
226 FunctionalState GiantPacketSizeLimitControl;
228 FunctionalState Support2KPacket;
230 FunctionalState CRCStripTypePacket;
232 FunctionalState AutomaticPadCRCStrip;
234 FunctionalState Watchdog;
238 FunctionalState Jabber;
242 FunctionalState JumboPacket;
246 uint32_t Speed;
249 uint32_t DuplexMode;
252 FunctionalState LoopbackMode;
254 FunctionalState CarrierSenseBeforeTransmit;
256 FunctionalState ReceiveOwn;
258 FunctionalState CarrierSenseDuringTransmit;
260 FunctionalState RetryTransmission;
262 uint32_t BackOffLimit;
265 FunctionalState DeferralCheck;
267 uint32_t PreambleLength;
270 FunctionalState UnicastSlowProtocolPacketDetect;
272 FunctionalState SlowProtocolDetect;
274 FunctionalState CRCCheckingRxPackets;
276 uint32_t GiantPacketSizeLimit;
280 FunctionalState ExtendedInterPacketGap;
282 uint32_t ExtendedInterPacketGapVal;
285 FunctionalState ProgrammableWatchdog;
287 uint32_t WatchdogTimeout;
290 uint32_t PauseTime;
293 FunctionalState ZeroQuantaPause;
295 uint32_t PauseLowThreshold;
298 FunctionalState TransmitFlowControl;
301 FunctionalState UnicastPausePacketDetect;
303 FunctionalState ReceiveFlowControl;
306 uint32_t TransmitQueueMode;
309 uint32_t ReceiveQueueMode;
312 FunctionalState DropTCPIPChecksumErrorPacket;
314 FunctionalState ForwardRxErrorPacket;
316 FunctionalState ForwardRxUndersizedGoodPacket;
317} ETH_MACConfigTypeDef;
325 typedef struct
326 {
327 uint32_t DMAArbitration;
330 FunctionalState AddressAlignedBeats;
333 uint32_t BurstMode;
336 FunctionalState RebuildINCRxBurst;
339 FunctionalState PBLx8Mode;
341 uint32_t TxDMABurstLength;
344 FunctionalState SecondPacketOperate;
347 uint32_t RxDMABurstLength;
350 FunctionalState FlushRxPacket;
352 FunctionalState TCPSegmentation;
354 uint32_t MaximumSegmentSize;
356} ETH_DMAConfigTypeDef;
364typedef enum
365{
366 HAL_ETH_MII_MODE = 0x00U,
367 HAL_ETH_RMII_MODE = 0x01U
368}ETH_MediaInterfaceTypeDef;
376typedef struct
377{
378
379 uint8_t *MACAddr;
381 ETH_MediaInterfaceTypeDef MediaInterface;
383 ETH_DMADescTypeDef *TxDesc;
385 ETH_DMADescTypeDef *RxDesc;
387 uint32_t RxBuffLen;
389}ETH_InitTypeDef;
397typedef uint32_t HAL_ETH_StateTypeDef;
405#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
406typedef struct __ETH_HandleTypeDef
407#else
408typedef struct
409#endif
410{
411 ETH_TypeDef *Instance;
413 ETH_InitTypeDef Init;
415 ETH_TxDescListTypeDef TxDescList;
418 ETH_RxDescListTypeDef RxDescList;
421 HAL_LockTypeDef Lock;
423 __IO HAL_ETH_StateTypeDef gState;
427 __IO HAL_ETH_StateTypeDef RxState;
430 __IO uint32_t ErrorCode;
433 __IO uint32_t DMAErrorCode;
436 __IO uint32_t MACErrorCode;
439 __IO uint32_t MACWakeUpEvent;
442 __IO uint32_t MACLPIEvent;
445#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
446
447 void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth);
448 void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth);
449 void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth);
450 void (* MACErrorCallback) ( struct __ETH_HandleTypeDef * heth);
451 void (* PMTCallback) ( struct __ETH_HandleTypeDef * heth);
452 void (* EEECallback) ( struct __ETH_HandleTypeDef * heth);
453 void (* WakeUpCallback) ( struct __ETH_HandleTypeDef * heth);
455 void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth);
456 void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth);
458#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
459
460} ETH_HandleTypeDef;
465#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
469typedef enum
470{
471 HAL_ETH_MSPINIT_CB_ID = 0x00U,
472 HAL_ETH_MSPDEINIT_CB_ID = 0x01U,
474 HAL_ETH_TX_COMPLETE_CB_ID = 0x02U,
475 HAL_ETH_RX_COMPLETE_CB_ID = 0x03U,
476 HAL_ETH_DMA_ERROR_CB_ID = 0x04U,
477 HAL_ETH_MAC_ERROR_CB_ID = 0x05U,
478 HAL_ETH_PMT_CB_ID = 0x06U,
479 HAL_ETH_EEE_CB_ID = 0x07U,
480 HAL_ETH_WAKEUP_CB_ID = 0x08U
483}HAL_ETH_CallbackIDTypeDef;
484
488typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth);
490#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
491
495typedef struct{
496 FunctionalState PromiscuousMode;
498 FunctionalState ReceiveAllMode;
500 FunctionalState HachOrPerfectFilter;
502 FunctionalState HashUnicast;
504 FunctionalState HashMulticast;
506 FunctionalState PassAllMulticast;
508 FunctionalState SrcAddrFiltering;
510 FunctionalState SrcAddrInverseFiltering;
512 FunctionalState DestAddrInverseFiltering;
514 FunctionalState BroadcastFilter;
516 uint32_t ControlPacketsFilter;
518}ETH_MACFilterConfigTypeDef;
526typedef struct{
527 FunctionalState WakeUpPacket;
529 FunctionalState MagicPacket;
531 FunctionalState GlobalUnicast;
533 FunctionalState WakeUpForward;
535}ETH_PowerDownConfigTypeDef;
544/* Exported constants --------------------------------------------------------*/
555/*
556 DMA Tx Normal Descriptor Read Format
557 -----------------------------------------------------------------------------------------------
558 TDES0 | Buffer1 or Header Address [31:0] |
559 -----------------------------------------------------------------------------------------------
560 TDES1 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
561 -----------------------------------------------------------------------------------------------
562 TDES2 | IOC(31) | TTSE(30) | Buff2 Length[29:16] | VTIR[15:14] | Header or Buff1 Length[13:0] |
563 -----------------------------------------------------------------------------------------------
564 TDES3 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
565 -----------------------------------------------------------------------------------------------
566*/
567
571#define ETH_DMATXNDESCRF_B1AP ((uint32_t)0xFFFFFFFFU)
576#define ETH_DMATXNDESCRF_B2AP ((uint32_t)0xFFFFFFFFU)
581#define ETH_DMATXNDESCRF_IOC ((uint32_t)0x80000000U)
582#define ETH_DMATXNDESCRF_TTSE ((uint32_t)0x40000000U)
583#define ETH_DMATXNDESCRF_B2L ((uint32_t)0x3FFF0000U)
584#define ETH_DMATXNDESCRF_VTIR ((uint32_t)0x0000C000U)
585#define ETH_DMATXNDESCRF_VTIR_DISABLE ((uint32_t)0x00000000U)
586#define ETH_DMATXNDESCRF_VTIR_REMOVE ((uint32_t)0x00004000U)
587#define ETH_DMATXNDESCRF_VTIR_INSERT ((uint32_t)0x00008000U)
588#define ETH_DMATXNDESCRF_VTIR_REPLACE ((uint32_t)0x0000C000U)
589#define ETH_DMATXNDESCRF_B1L ((uint32_t)0x00003FFFU)
590#define ETH_DMATXNDESCRF_HL ((uint32_t)0x000003FFU)
595#define ETH_DMATXNDESCRF_OWN ((uint32_t)0x80000000U)
596#define ETH_DMATXNDESCRF_CTXT ((uint32_t)0x40000000U)
597#define ETH_DMATXNDESCRF_FD ((uint32_t)0x20000000U)
598#define ETH_DMATXNDESCRF_LD ((uint32_t)0x10000000U)
599#define ETH_DMATXNDESCRF_CPC ((uint32_t)0x0C000000U)
600#define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT ((uint32_t)0x00000000U)
601#define ETH_DMATXNDESCRF_CPC_CRC_INSERT ((uint32_t)0x04000000U)
602#define ETH_DMATXNDESCRF_CPC_DISABLE ((uint32_t)0x08000000U)
603#define ETH_DMATXNDESCRF_CPC_CRC_REPLACE ((uint32_t)0x0C000000U)
604#define ETH_DMATXNDESCRF_SAIC ((uint32_t)0x03800000U)
605#define ETH_DMATXNDESCRF_SAIC_DISABLE ((uint32_t)0x00000000U)
606#define ETH_DMATXNDESCRF_SAIC_INSERT ((uint32_t)0x00800000U)
607#define ETH_DMATXNDESCRF_SAIC_REPLACE ((uint32_t)0x01000000U)
608#define ETH_DMATXNDESCRF_THL ((uint32_t)0x00780000U)
609#define ETH_DMATXNDESCRF_TSE ((uint32_t)0x00040000U)
610#define ETH_DMATXNDESCRF_CIC ((uint32_t)0x00030000U)
611#define ETH_DMATXNDESCRF_CIC_DISABLE ((uint32_t)0x00000000U)
612#define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT ((uint32_t)0x00010000U)
613#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT ((uint32_t)0x00020000U)
615#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC ((uint32_t)0x00030000U)
617#define ETH_DMATXNDESCRF_TPL ((uint32_t)0x0003FFFFU)
618#define ETH_DMATXNDESCRF_FL ((uint32_t)0x00007FFFU)
620/*
621 DMA Tx Normal Descriptor Write Back Format
622 -----------------------------------------------------------------------------------------------
623 TDES0 | Timestamp Low |
624 -----------------------------------------------------------------------------------------------
625 TDES1 | Timestamp High |
626 -----------------------------------------------------------------------------------------------
627 TDES2 | Reserved[31:0] |
628 -----------------------------------------------------------------------------------------------
629 TDES3 | OWN(31) | Status[30:0] |
630 -----------------------------------------------------------------------------------------------
631*/
632
636#define ETH_DMATXNDESCWBF_TTSL ((uint32_t)0xFFFFFFFFU)
641#define ETH_DMATXNDESCWBF_TTSH ((uint32_t)0xFFFFFFFFU)
646#define ETH_DMATXNDESCWBF_OWN ((uint32_t)0x80000000U)
647#define ETH_DMATXNDESCWBF_CTXT ((uint32_t)0x40000000U)
648#define ETH_DMATXNDESCWBF_FD ((uint32_t)0x20000000U)
649#define ETH_DMATXNDESCWBF_LD ((uint32_t)0x10000000U)
650#define ETH_DMATXNDESCWBF_TTSS ((uint32_t)0x00020000U)
651#define ETH_DMATXNDESCWBF_DP ((uint32_t)0x04000000U)
652#define ETH_DMATXNDESCWBF_TTSE ((uint32_t)0x02000000U)
653#define ETH_DMATXNDESCWBF_ES ((uint32_t)0x00008000U)
654#define ETH_DMATXNDESCWBF_JT ((uint32_t)0x00004000U)
655#define ETH_DMATXNDESCWBF_FF ((uint32_t)0x00002000U)
656#define ETH_DMATXNDESCWBF_PCE ((uint32_t)0x00001000U)
657#define ETH_DMATXNDESCWBF_LCA ((uint32_t)0x00000800U)
658#define ETH_DMATXNDESCWBF_NC ((uint32_t)0x00000400U)
659#define ETH_DMATXNDESCWBF_LCO ((uint32_t)0x00000200U)
660#define ETH_DMATXNDESCWBF_EC ((uint32_t)0x00000100U)
661#define ETH_DMATXNDESCWBF_CC ((uint32_t)0x000000F0U)
662#define ETH_DMATXNDESCWBF_ED ((uint32_t)0x00000008U)
663#define ETH_DMATXNDESCWBF_UF ((uint32_t)0x00000004U)
664#define ETH_DMATXNDESCWBF_DB ((uint32_t)0x00000002U)
665#define ETH_DMATXNDESCWBF_IHE ((uint32_t)0x00000004U)
668/*
669 DMA Tx Context Descriptor
670 -----------------------------------------------------------------------------------------------
671 TDES0 | Timestamp Low |
672 -----------------------------------------------------------------------------------------------
673 TDES1 | Timestamp High |
674 -----------------------------------------------------------------------------------------------
675 TDES2 | Inner VLAN Tag[31:16] | Reserved(15) | Maximum Segment Size [14:0] |
676 -----------------------------------------------------------------------------------------------
677 TDES3 | OWN(31) | Status[30:0] |
678 -----------------------------------------------------------------------------------------------
679*/
680
684#define ETH_DMATXCDESC_TTSL ((uint32_t)0xFFFFFFFFU)
689#define ETH_DMATXCDESC_TTSH ((uint32_t)0xFFFFFFFFU)
694#define ETH_DMATXCDESC_IVT ((uint32_t)0xFFFF0000U)
695#define ETH_DMATXCDESC_MSS ((uint32_t)0x00003FFFU)
700#define ETH_DMATXCDESC_OWN ((uint32_t)0x80000000U)
701#define ETH_DMATXCDESC_CTXT ((uint32_t)0x40000000U)
702#define ETH_DMATXCDESC_OSTC ((uint32_t)0x08000000U)
703#define ETH_DMATXCDESC_TCMSSV ((uint32_t)0x04000000U)
704#define ETH_DMATXCDESC_CDE ((uint32_t)0x00800000U)
705#define ETH_DMATXCDESC_IVTIR ((uint32_t)0x000C0000U)
706#define ETH_DMATXCDESC_IVTIR_DISABLE ((uint32_t)0x00000000U)
707#define ETH_DMATXCDESC_IVTIR_REMOVE ((uint32_t)0x00040000U)
708#define ETH_DMATXCDESC_IVTIR_INSERT ((uint32_t)0x00080000U)
709#define ETH_DMATXCDESC_IVTIR_REPLACE ((uint32_t)0x000C0000U)
710#define ETH_DMATXCDESC_IVLTV ((uint32_t)0x00020000U)
711#define ETH_DMATXCDESC_VLTV ((uint32_t)0x00010000U)
712#define ETH_DMATXCDESC_VT ((uint32_t)0x0000FFFFU)
724/*
725 DMA Rx Normal Descriptor read format
726 -----------------------------------------------------------------------------------------------------------
727 RDES0 | Buffer1 or Header Address [31:0] |
728 -----------------------------------------------------------------------------------------------------------
729 RDES1 | Reserved |
730 -----------------------------------------------------------------------------------------------------------
731 RDES2 | Payload or Buffer2 Address[31:0] |
732 -----------------------------------------------------------------------------------------------------------
733 RDES3 | OWN(31) | IOC(30) | Reserved [29:26] | BUF2V(25) | BUF1V(24) | Reserved [23:0] |
734 -----------------------------------------------------------------------------------------------------------
735*/
736
740#define ETH_DMARXNDESCRF_BUF1AP ((uint32_t)0xFFFFFFFFU)
745#define ETH_DMARXNDESCRF_BUF2AP ((uint32_t)0xFFFFFFFFU)
750#define ETH_DMARXNDESCRF_OWN ((uint32_t)0x80000000U)
751#define ETH_DMARXNDESCRF_IOC ((uint32_t)0x40000000U)
752#define ETH_DMARXNDESCRF_BUF2V ((uint32_t)0x02000000U)
753#define ETH_DMARXNDESCRF_BUF1V ((uint32_t)0x01000000U)
755/*
756 DMA Rx Normal Descriptor write back format
757 ---------------------------------------------------------------------------------------------------------------------
758 RDES0 | Inner VLAN Tag[31:16] | Outer VLAN Tag[15:0] |
759 ---------------------------------------------------------------------------------------------------------------------
760 RDES1 | OAM code, or MAC Control Opcode [31:16] | Extended Status |
761 ---------------------------------------------------------------------------------------------------------------------
762 RDES2 | MAC Filter Status[31:16] | VF(15) | Reserved [14:12] | ARP Status [11:10] | Header Length [9:0] |
763 ---------------------------------------------------------------------------------------------------------------------
764 RDES3 | OWN(31) | CTXT(30) | FD(29) | LD(28) | Status[27:16] | ES(15) | Packet Length[14:0] |
765 ---------------------------------------------------------------------------------------------------------------------
766*/
767
771#define ETH_DMARXNDESCWBF_IVT ((uint32_t)0xFFFF0000U)
772#define ETH_DMARXNDESCWBF_OVT ((uint32_t)0x0000FFFFU)
777#define ETH_DMARXNDESCWBF_OPC ((uint32_t)0xFFFF0000U)
778#define ETH_DMARXNDESCWBF_TD ((uint32_t)0x00008000U)
779#define ETH_DMARXNDESCWBF_TSA ((uint32_t)0x00004000U)
780#define ETH_DMARXNDESCWBF_PV ((uint32_t)0x00002000U)
781#define ETH_DMARXNDESCWBF_PFT ((uint32_t)0x00001000U)
782#define ETH_DMARXNDESCWBF_PMT_NO ((uint32_t)0x00000000U)
783#define ETH_DMARXNDESCWBF_PMT_SYNC ((uint32_t)0x00000100U)
784#define ETH_DMARXNDESCWBF_PMT_FUP ((uint32_t)0x00000200U)
785#define ETH_DMARXNDESCWBF_PMT_DREQ ((uint32_t)0x00000300U)
786#define ETH_DMARXNDESCWBF_PMT_DRESP ((uint32_t)0x00000400U)
787#define ETH_DMARXNDESCWBF_PMT_PDREQ ((uint32_t)0x00000500U)
788#define ETH_DMARXNDESCWBF_PMT_PDRESP ((uint32_t)0x00000600U)
789#define ETH_DMARXNDESCWBF_PMT_PDRESPFUP ((uint32_t)0x00000700U)
790#define ETH_DMARXNDESCWBF_PMT_ANNOUNCE ((uint32_t)0x00000800U)
791#define ETH_DMARXNDESCWBF_PMT_MANAG ((uint32_t)0x00000900U)
792#define ETH_DMARXNDESCWBF_PMT_SIGN ((uint32_t)0x00000A00U)
793#define ETH_DMARXNDESCWBF_PMT_RESERVED ((uint32_t)0x00000F00U)
794#define ETH_DMARXNDESCWBF_IPCE ((uint32_t)0x00000080U)
795#define ETH_DMARXNDESCWBF_IPCB ((uint32_t)0x00000040U)
796#define ETH_DMARXNDESCWBF_IPV6 ((uint32_t)0x00000020U)
797#define ETH_DMARXNDESCWBF_IPV4 ((uint32_t)0x00000010U)
798#define ETH_DMARXNDESCWBF_IPHE ((uint32_t)0x00000008U)
799#define ETH_DMARXNDESCWBF_PT ((uint32_t)0x00000003U)
800#define ETH_DMARXNDESCWBF_PT_UNKNOWN ((uint32_t)0x00000000U)
801#define ETH_DMARXNDESCWBF_PT_UDP ((uint32_t)0x00000001U)
802#define ETH_DMARXNDESCWBF_PT_TCP ((uint32_t)0x00000002U)
803#define ETH_DMARXNDESCWBF_PT_ICMP ((uint32_t)0x00000003U)
808#define ETH_DMARXNDESCWBF_L3L4FM ((uint32_t)0x20000000U)
809#define ETH_DMARXNDESCWBF_L4FM ((uint32_t)0x10000000U)
810#define ETH_DMARXNDESCWBF_L3FM ((uint32_t)0x08000000U)
811#define ETH_DMARXNDESCWBF_MADRM ((uint32_t)0x07F80000U)
812#define ETH_DMARXNDESCWBF_HF ((uint32_t)0x00040000U)
813#define ETH_DMARXNDESCWBF_DAF ((uint32_t)0x00020000U)
814#define ETH_DMARXNDESCWBF_SAF ((uint32_t)0x00010000U)
815#define ETH_DMARXNDESCWBF_VF ((uint32_t)0x00008000U)
816#define ETH_DMARXNDESCWBF_ARPNR ((uint32_t)0x00000400U)
822#define ETH_DMARXNDESCWBF_OWN ((uint32_t)0x80000000U)
823#define ETH_DMARXNDESCWBF_CTXT ((uint32_t)0x40000000U)
824#define ETH_DMARXNDESCWBF_FD ((uint32_t)0x20000000U)
825#define ETH_DMARXNDESCWBF_LD ((uint32_t)0x10000000U)
826#define ETH_DMARXNDESCWBF_RS2V ((uint32_t)0x08000000U)
827#define ETH_DMARXNDESCWBF_RS1V ((uint32_t)0x04000000U)
828#define ETH_DMARXNDESCWBF_RS0V ((uint32_t)0x02000000U)
829#define ETH_DMARXNDESCWBF_CE ((uint32_t)0x01000000U)
830#define ETH_DMARXNDESCWBF_GP ((uint32_t)0x00800000U)
831#define ETH_DMARXNDESCWBF_RWT ((uint32_t)0x00400000U)
832#define ETH_DMARXNDESCWBF_OE ((uint32_t)0x00200000U)
833#define ETH_DMARXNDESCWBF_RE ((uint32_t)0x00100000U)
834#define ETH_DMARXNDESCWBF_DE ((uint32_t)0x00080000U)
835#define ETH_DMARXNDESCWBF_LT ((uint32_t)0x00070000U)
836#define ETH_DMARXNDESCWBF_LT_LP ((uint32_t)0x00000000U)
837#define ETH_DMARXNDESCWBF_LT_TP ((uint32_t)0x00010000U)
838#define ETH_DMARXNDESCWBF_LT_ARP ((uint32_t)0x00030000U)
839#define ETH_DMARXNDESCWBF_LT_VLAN ((uint32_t)0x00040000U)
840#define ETH_DMARXNDESCWBF_LT_DVLAN ((uint32_t)0x00050000U)
841#define ETH_DMARXNDESCWBF_LT_MAC ((uint32_t)0x00060000U)
842#define ETH_DMARXNDESCWBF_LT_OAM ((uint32_t)0x00070000U)
843#define ETH_DMARXNDESCWBF_ES ((uint32_t)0x00008000U)
844#define ETH_DMARXNDESCWBF_PL ((uint32_t)0x00007FFFU)
846/*
847 DMA Rx context Descriptor
848 ---------------------------------------------------------------------------------------------------------------------
849 RDES0 | Timestamp Low[31:0] |
850 ---------------------------------------------------------------------------------------------------------------------
851 RDES1 | Timestamp High[31:0] |
852 ---------------------------------------------------------------------------------------------------------------------
853 RDES2 | Reserved |
854 ---------------------------------------------------------------------------------------------------------------------
855 RDES3 | OWN(31) | CTXT(30) | Reserved[29:0] |
856 ---------------------------------------------------------------------------------------------------------------------
857*/
858
862#define ETH_DMARXCDESC_RTSL ((uint32_t)0xFFFFFFFFU)
867#define ETH_DMARXCDESC_RTSH ((uint32_t)0xFFFFFFFFU)
872#define ETH_DMARXCDESC_OWN ((uint32_t)0x80000000U)
873#define ETH_DMARXCDESC_CTXT ((uint32_t)0x40000000U)
883#define ETH_MAX_PACKET_SIZE ((uint32_t)1528U)
884#define ETH_HEADER ((uint32_t)14U)
885#define ETH_CRC ((uint32_t)4U)
886#define ETH_VLAN_TAG ((uint32_t)4U)
887#define ETH_MIN_PAYLOAD ((uint32_t)46U)
888#define ETH_MAX_PAYLOAD ((uint32_t)1500U)
889#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U)
898#define HAL_ETH_ERROR_NONE ((uint32_t)0x00000000U)
899#define HAL_ETH_ERROR_PARAM ((uint32_t)0x00000001U)
900#define HAL_ETH_ERROR_BUSY ((uint32_t)0x00000002U)
901#define HAL_ETH_ERROR_TIMEOUT ((uint32_t)0x00000004U)
902#define HAL_ETH_ERROR_DMA ((uint32_t)0x00000008U)
903#define HAL_ETH_ERROR_MAC ((uint32_t)0x00000010U)
904#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
905#define HAL_ETH_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)
906#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
915#define ETH_TX_PACKETS_FEATURES_CSUM ((uint32_t)0x00000001U)
916#define ETH_TX_PACKETS_FEATURES_SAIC ((uint32_t)0x00000002U)
917#define ETH_TX_PACKETS_FEATURES_VLANTAG ((uint32_t)0x00000004U)
918#define ETH_TX_PACKETS_FEATURES_INNERVLANTAG ((uint32_t)0x00000008U)
919#define ETH_TX_PACKETS_FEATURES_TSO ((uint32_t)0x00000010U)
920#define ETH_TX_PACKETS_FEATURES_CRCPAD ((uint32_t)0x00000020U)
929#define ETH_SRC_ADDR_CONTROL_DISABLE ETH_DMATXNDESCRF_SAIC_DISABLE
930#define ETH_SRC_ADDR_INSERT ETH_DMATXNDESCRF_SAIC_INSERT
931#define ETH_SRC_ADDR_REPLACE ETH_DMATXNDESCRF_SAIC_REPLACE
940#define ETH_CRC_PAD_DISABLE ETH_DMATXNDESCRF_CPC_DISABLE
941#define ETH_CRC_PAD_INSERT ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT
942#define ETH_CRC_INSERT ETH_DMATXNDESCRF_CPC_CRC_INSERT
943#define ETH_CRC_REPLACE ETH_DMATXNDESCRF_CPC_CRC_REPLACE
952#define ETH_CHECKSUM_DISABLE ETH_DMATXNDESCRF_CIC_DISABLE
953#define ETH_CHECKSUM_IPHDR_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_INSERT
954#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT
955#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC
964#define ETH_VLAN_DISABLE ETH_DMATXNDESCRF_VTIR_DISABLE
965#define ETH_VLAN_REMOVE ETH_DMATXNDESCRF_VTIR_REMOVE
966#define ETH_VLAN_INSERT ETH_DMATXNDESCRF_VTIR_INSERT
967#define ETH_VLAN_REPLACE ETH_DMATXNDESCRF_VTIR_REPLACE
976#define ETH_INNER_VLAN_DISABLE ETH_DMATXCDESC_IVTIR_DISABLE
977#define ETH_INNER_VLAN_REMOVE ETH_DMATXCDESC_IVTIR_REMOVE
978#define ETH_INNER_VLAN_INSERT ETH_DMATXCDESC_IVTIR_INSERT
979#define ETH_INNER_VLAN_REPLACE ETH_DMATXCDESC_IVTIR_REPLACE
988#define ETH_CHECKSUM_BYPASSED ETH_DMARXNDESCWBF_IPCB
989#define ETH_CHECKSUM_IP_HEADER_ERROR ETH_DMARXNDESCWBF_IPHE
990#define ETH_CHECKSUM_IP_PAYLOAD_ERROR ETH_DMARXNDESCWBF_IPCE
999#define ETH_IP_HEADER_IPV4 ETH_DMARXNDESCWBF_IPV4
1000#define ETH_IP_HEADER_IPV6 ETH_DMARXNDESCWBF_IPV6
1009#define ETH_IP_PAYLOAD_UNKNOWN ETH_DMARXNDESCWBF_PT_UNKNOWN
1010#define ETH_IP_PAYLOAD_UDP ETH_DMARXNDESCWBF_PT_UDP
1011#define ETH_IP_PAYLOAD_TCP ETH_DMARXNDESCWBF_PT_TCP
1012#define ETH_IP_PAYLOAD_ICMPN ETH_DMARXNDESCWBF_PT_ICMP
1021#define ETH_HASH_FILTER_PASS ETH_DMARXNDESCWBF_HF
1022#define ETH_VLAN_FILTER_PASS ETH_DMARXNDESCWBF_VF
1023#define ETH_DEST_ADDRESS_FAIL ETH_DMARXNDESCWBF_DAF
1024#define ETH_SOURCE_ADDRESS_FAIL ETH_DMARXNDESCWBF_SAF
1033#define ETH_L3_FILTER0_MATCH ETH_DMARXNDESCWBF_L3FM
1034#define ETH_L3_FILTER1_MATCH (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM)
1043#define ETH_L4_FILTER0_MATCH ETH_DMARXNDESCWBF_L4FM
1044#define ETH_L4_FILTER1_MATCH (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM)
1053#define ETH_DRIBBLE_BIT_ERROR ETH_DMARXNDESCWBF_DE
1054#define ETH_RECEIVE_ERROR ETH_DMARXNDESCWBF_RE
1055#define ETH_RECEIVE_OVERFLOW ETH_DMARXNDESCWBF_OE
1056#define ETH_WATCHDOG_TIMEOUT ETH_DMARXNDESCWBF_RWT
1057#define ETH_GIANT_PACKET ETH_DMARXNDESCWBF_GP
1058#define ETH_CRC_ERROR ETH_DMARXNDESCWBF_CE
1067#define ETH_DMAARBITRATION_RX ETH_DMAMR_DA
1068#define ETH_DMAARBITRATION_RX1_TX1 ((uint32_t)0x00000000U)
1069#define ETH_DMAARBITRATION_RX2_TX1 ETH_DMAMR_PR_2_1
1070#define ETH_DMAARBITRATION_RX3_TX1 ETH_DMAMR_PR_3_1
1071#define ETH_DMAARBITRATION_RX4_TX1 ETH_DMAMR_PR_4_1
1072#define ETH_DMAARBITRATION_RX5_TX1 ETH_DMAMR_PR_5_1
1073#define ETH_DMAARBITRATION_RX6_TX1 ETH_DMAMR_PR_6_1
1074#define ETH_DMAARBITRATION_RX7_TX1 ETH_DMAMR_PR_7_1
1075#define ETH_DMAARBITRATION_RX8_TX1 ETH_DMAMR_PR_8_1
1076#define ETH_DMAARBITRATION_TX (ETH_DMAMR_TXPR | ETH_DMAMR_DA)
1077#define ETH_DMAARBITRATION_TX1_RX1 ((uint32_t)0x00000000U)
1078#define ETH_DMAARBITRATION_TX2_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1)
1079#define ETH_DMAARBITRATION_TX3_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1)
1080#define ETH_DMAARBITRATION_TX4_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1)
1081#define ETH_DMAARBITRATION_TX5_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1)
1082#define ETH_DMAARBITRATION_TX6_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1)
1083#define ETH_DMAARBITRATION_TX7_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1)
1084#define ETH_DMAARBITRATION_TX8_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1)
1093#define ETH_BURSTLENGTH_FIXED ETH_DMASBMR_FB
1094#define ETH_BURSTLENGTH_MIXED ETH_DMASBMR_MB
1095#define ETH_BURSTLENGTH_UNSPECIFIED ((uint32_t)0x00000000U)
1104#define ETH_TXDMABURSTLENGTH_1BEAT ETH_DMACTCR_TPBL_1PBL
1105#define ETH_TXDMABURSTLENGTH_2BEAT ETH_DMACTCR_TPBL_2PBL
1106#define ETH_TXDMABURSTLENGTH_4BEAT ETH_DMACTCR_TPBL_4PBL
1107#define ETH_TXDMABURSTLENGTH_8BEAT ETH_DMACTCR_TPBL_8PBL
1108#define ETH_TXDMABURSTLENGTH_16BEAT ETH_DMACTCR_TPBL_16PBL
1109#define ETH_TXDMABURSTLENGTH_32BEAT ETH_DMACTCR_TPBL_32PBL
1118#define ETH_RXDMABURSTLENGTH_1BEAT ETH_DMACRCR_RPBL_1PBL
1119#define ETH_RXDMABURSTLENGTH_2BEAT ETH_DMACRCR_RPBL_2PBL
1120#define ETH_RXDMABURSTLENGTH_4BEAT ETH_DMACRCR_RPBL_4PBL
1121#define ETH_RXDMABURSTLENGTH_8BEAT ETH_DMACRCR_RPBL_8PBL
1122#define ETH_RXDMABURSTLENGTH_16BEAT ETH_DMACRCR_RPBL_16PBL
1123#define ETH_RXDMABURSTLENGTH_32BEAT ETH_DMACRCR_RPBL_32PBL
1132#define ETH_DMA_NORMAL_IT ETH_DMACIER_NIE
1133#define ETH_DMA_ABNORMAL_IT ETH_DMACIER_AIE
1134#define ETH_DMA_CONTEXT_DESC_ERROR_IT ETH_DMACIER_CDEE
1135#define ETH_DMA_FATAL_BUS_ERROR_IT ETH_DMACIER_FBEE
1136#define ETH_DMA_EARLY_RX_IT ETH_DMACIER_ERIE
1137#define ETH_DMA_EARLY_TX_IT ETH_DMACIER_ETIE
1138#define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT ETH_DMACIER_RWTE
1139#define ETH_DMA_RX_PROCESS_STOPPED_IT ETH_DMACIER_RSE
1140#define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_RBUE
1141#define ETH_DMA_RX_IT ETH_DMACIER_RIE
1142#define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_TBUE
1143#define ETH_DMA_TX_PROCESS_STOPPED_IT ETH_DMACIER_TXSE
1144#define ETH_DMA_TX_IT ETH_DMACIER_TIE
1153#define ETH_DMA_RX_NO_ERROR_FLAG ((uint32_t)0x00000000U)
1154#define ETH_DMA_RX_DESC_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0)
1155#define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1)
1156#define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0)
1157#define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_REB_BIT_2
1158#define ETH_DMA_TX_NO_ERROR_FLAG ((uint32_t)0x00000000U)
1159#define ETH_DMA_TX_DESC_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0)
1160#define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1)
1161#define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0)
1162#define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_TEB_BIT_2
1163#define ETH_DMA_CONTEXT_DESC_ERROR_FLAG ETH_DMACSR_CDE
1164#define ETH_DMA_FATAL_BUS_ERROR_FLAG ETH_DMACSR_FBE
1165#define ETH_DMA_EARLY_TX_IT_FLAG ETH_DMACSR_ERI
1166#define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG ETH_DMACSR_RWT
1167#define ETH_DMA_RX_PROCESS_STOPPED_FLAG ETH_DMACSR_RPS
1168#define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG ETH_DMACSR_RBU
1169#define ETH_DMA_TX_PROCESS_STOPPED_FLAG ETH_DMACSR_TPS
1178#define ETH_TRANSMITSTOREFORWARD ETH_MTLTQOMR_TSF
1179#define ETH_TRANSMITTHRESHOLD_32 ETH_MTLTQOMR_TTC_32BITS
1180#define ETH_TRANSMITTHRESHOLD_64 ETH_MTLTQOMR_TTC_64BITS
1181#define ETH_TRANSMITTHRESHOLD_96 ETH_MTLTQOMR_TTC_96BITS
1182#define ETH_TRANSMITTHRESHOLD_128 ETH_MTLTQOMR_TTC_128BITS
1183#define ETH_TRANSMITTHRESHOLD_192 ETH_MTLTQOMR_TTC_192BITS
1184#define ETH_TRANSMITTHRESHOLD_256 ETH_MTLTQOMR_TTC_256BITS
1185#define ETH_TRANSMITTHRESHOLD_384 ETH_MTLTQOMR_TTC_384BITS
1186#define ETH_TRANSMITTHRESHOLD_512 ETH_MTLTQOMR_TTC_512BITS
1195#define ETH_RECEIVESTOREFORWARD ETH_MTLRQOMR_RSF
1196#define ETH_RECEIVETHRESHOLD8_64 ETH_MTLRQOMR_RTC_64BITS
1197#define ETH_RECEIVETHRESHOLD8_32 ETH_MTLRQOMR_RTC_32BITS
1198#define ETH_RECEIVETHRESHOLD8_96 ETH_MTLRQOMR_RTC_96BITS
1199#define ETH_RECEIVETHRESHOLD8_128 ETH_MTLRQOMR_RTC_128BITS
1208#define ETH_PAUSELOWTHRESHOLD_MINUS_4 ETH_MACTFCR_PLT_MINUS4
1209#define ETH_PAUSELOWTHRESHOLD_MINUS_28 ETH_MACTFCR_PLT_MINUS28
1210#define ETH_PAUSELOWTHRESHOLD_MINUS_36 ETH_MACTFCR_PLT_MINUS36
1211#define ETH_PAUSELOWTHRESHOLD_MINUS_144 ETH_MACTFCR_PLT_MINUS144
1212#define ETH_PAUSELOWTHRESHOLD_MINUS_256 ETH_MACTFCR_PLT_MINUS256
1213#define ETH_PAUSELOWTHRESHOLD_MINUS_512 ETH_MACTFCR_PLT_MINUS512
1222#define ETH_WATCHDOGTIMEOUT_2KB ETH_MACWTR_WTO_2KB
1223#define ETH_WATCHDOGTIMEOUT_3KB ETH_MACWTR_WTO_3KB
1224#define ETH_WATCHDOGTIMEOUT_4KB ETH_MACWTR_WTO_4KB
1225#define ETH_WATCHDOGTIMEOUT_5KB ETH_MACWTR_WTO_5KB
1226#define ETH_WATCHDOGTIMEOUT_6KB ETH_MACWTR_WTO_6KB
1227#define ETH_WATCHDOGTIMEOUT_7KB ETH_MACWTR_WTO_7KB
1228#define ETH_WATCHDOGTIMEOUT_8KB ETH_MACWTR_WTO_8KB
1229#define ETH_WATCHDOGTIMEOUT_9KB ETH_MACWTR_WTO_9KB
1230#define ETH_WATCHDOGTIMEOUT_10KB ETH_MACWTR_WTO_10KB
1231#define ETH_WATCHDOGTIMEOUT_11KB ETH_MACWTR_WTO_12KB
1232#define ETH_WATCHDOGTIMEOUT_12KB ETH_MACWTR_WTO_12KB
1233#define ETH_WATCHDOGTIMEOUT_13KB ETH_MACWTR_WTO_13KB
1234#define ETH_WATCHDOGTIMEOUT_14KB ETH_MACWTR_WTO_14KB
1235#define ETH_WATCHDOGTIMEOUT_15KB ETH_MACWTR_WTO_15KB
1236#define ETH_WATCHDOGTIMEOUT_16KB ETH_MACWTR_WTO_16KB
1245#define ETH_INTERPACKETGAP_96BIT ETH_MACCR_IPG_96BIT
1246#define ETH_INTERPACKETGAP_88BIT ETH_MACCR_IPG_88BIT
1247#define ETH_INTERPACKETGAP_80BIT ETH_MACCR_IPG_80BIT
1248#define ETH_INTERPACKETGAP_72BIT ETH_MACCR_IPG_72BIT
1249#define ETH_INTERPACKETGAP_64BIT ETH_MACCR_IPG_64BIT
1250#define ETH_INTERPACKETGAP_56BIT ETH_MACCR_IPG_56BIT
1251#define ETH_INTERPACKETGAP_48BIT ETH_MACCR_IPG_48BIT
1252#define ETH_INTERPACKETGAP_40BIT ETH_MACCR_IPG_40BIT
1261#define ETH_SPEED_10M ((uint32_t)0x00000000U)
1262#define ETH_SPEED_100M ETH_MACCR_FES
1271#define ETH_FULLDUPLEX_MODE ETH_MACCR_DM
1272#define ETH_HALFDUPLEX_MODE ((uint32_t)0x00000000U)
1281#define ETH_BACKOFFLIMIT_10 ETH_MACCR_BL_10
1282#define ETH_BACKOFFLIMIT_8 ETH_MACCR_BL_8
1283#define ETH_BACKOFFLIMIT_4 ETH_MACCR_BL_4
1284#define ETH_BACKOFFLIMIT_1 ETH_MACCR_BL_1
1293#define ETH_PREAMBLELENGTH_7 ETH_MACCR_PRELEN_7
1294#define ETH_PREAMBLELENGTH_5 ETH_MACCR_PRELEN_5
1295#define ETH_PREAMBLELENGTH_3 ETH_MACCR_PRELEN_3
1304#define ETH_SOURCEADDRESS_DISABLE ((uint32_t)0x00000000U)
1305#define ETH_SOURCEADDRESS_INSERT_ADDR0 ETH_MACCR_SARC_INSADDR0
1306#define ETH_SOURCEADDRESS_INSERT_ADDR1 ETH_MACCR_SARC_INSADDR1
1307#define ETH_SOURCEADDRESS_REPLACE_ADDR0 ETH_MACCR_SARC_REPADDR0
1308#define ETH_SOURCEADDRESS_REPLACE_ADDR1 ETH_MACCR_SARC_REPADDR1
1317#define ETH_CTRLPACKETS_BLOCK_ALL ETH_MACPFR_PCF_BLOCKALL
1318#define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA
1319#define ETH_CTRLPACKETS_FORWARD_ALL ETH_MACPFR_PCF_FORWARDALL
1320#define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER
1329#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U)
1330#define ETH_VLANTAGCOMPARISON_12BIT ETH_MACVTR_ETV
1339#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U)
1340#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U)
1341#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U)
1342#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U)
1351#define ETH_MAC_RX_STATUS_IT ETH_MACIER_RXSTSIE
1352#define ETH_MAC_TX_STATUS_IT ETH_MACIER_TXSTSIE
1353#define ETH_MAC_TIMESTAMP_IT ETH_MACIER_TSIE
1354#define ETH_MAC_LPI_IT ETH_MACIER_LPIIE
1355#define ETH_MAC_PMT_IT ETH_MACIER_PMTIE
1356#define ETH_MAC_PHY_IT ETH_MACIER_PHYIE
1365#define ETH_WAKEUP_PACKET_RECIEVED ETH_MACPCSR_RWKPRCVD
1366#define ETH_MAGIC_PACKET_RECIEVED ETH_MACPCSR_MGKPRCVD
1375#define ETH_RECEIVE_WATCHDOG_TIMEOUT ETH_MACRXTXSR_RWT
1376#define ETH_EXECESSIVE_COLLISIONS ETH_MACRXTXSR_EXCOL
1377#define ETH_LATE_COLLISIONS ETH_MACRXTXSR_LCOL
1378#define ETH_EXECESSIVE_DEFERRAL ETH_MACRXTXSR_EXDEF
1379#define ETH_LOSS_OF_CARRIER ETH_MACRXTXSR_LCARR
1380#define ETH_NO_CARRIER ETH_MACRXTXSR_NCARR
1381#define ETH_TRANSMIT_JABBR_TIMEOUT ETH_MACRXTXSR_TJT
1390#define HAL_ETH_STATE_RESET ((uint32_t)0x00000000U)
1391#define HAL_ETH_STATE_READY ((uint32_t)0x00000010U)
1392#define HAL_ETH_STATE_BUSY ((uint32_t)0x00000023U)
1393#define HAL_ETH_STATE_BUSY_TX ((uint32_t)0x00000021U)
1394#define HAL_ETH_STATE_BUSY_RX ((uint32_t)0x00000022U)
1395#define HAL_ETH_STATE_ERROR ((uint32_t)0x000000E0U)
1403/* Exported macro ------------------------------------------------------------*/
1413#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1414#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
1415 (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \
1416 (__HANDLE__)->RxState = HAL_ETH_STATE_RESET; \
1417 (__HANDLE__)->MspInitCallback = NULL; \
1418 (__HANDLE__)->MspDeInitCallback = NULL; \
1419 } while(0)
1420#else
1421#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
1422 (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \
1423 (__HANDLE__)->RxState = HAL_ETH_STATE_RESET; \
1424 } while(0)
1425#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
1426
1434#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__))
1435
1443#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__))
1444
1451#define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACIER & (__INTERRUPT__)) == (__INTERRUPT__))
1452
1459#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACSR & (__INTERRUPT__)) == (__INTERRUPT__))
1460
1467#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__))
1468
1475#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__))
1476
1483#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))
1484
1492#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))
1493
1501#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))
1502
1509#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__))
1510
1512#define ETH_WAKEUP_EXTI_LINE ((uint32_t)0x00400000U) /* !< 86 - 64 = 22 */
1513
1520#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI_D1->IMR3 |= (__EXTI_LINE__))
1521
1528#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 & (__EXTI_LINE__))
1529
1536#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__))
1537
1538#if defined(DUAL_CORE)
1545#define __HAL_ETH_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__) (EXTI_D2->IMR3 |= (__EXTI_LINE__))
1546
1553#define __HAL_ETH_WAKEUP_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 & (__EXTI_LINE__))
1554
1561#define __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 = (__EXTI_LINE__))
1562#endif
1563
1570#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \
1571 (EXTI->RTSR3 |= (__EXTI_LINE__))
1572
1579#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\
1580 (EXTI->FTSR3 |= (__EXTI_LINE__))
1581
1588#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 |= (__EXTI_LINE__));\
1589 (EXTI->FTSR3 |= (__EXTI_LINE__))
1590
1597#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__))
1598
1603/* Include ETH HAL Extension module */
1604#include "stm32h7xx_hal_eth_ex.h"
1605
1606/* Exported functions --------------------------------------------------------*/
1607
1615/* Initialization and de initialization functions **********************************/
1616HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
1617HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
1618void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
1619void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
1620HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1,uint8_t *pBuffer2);
1621
1622/* Callbacks Register/UnRegister functions ***********************************/
1623#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1624HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback);
1625HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
1626#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1627
1635/* IO operation functions *******************************************************/
1636HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
1637HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth);
1638HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
1639HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth);
1640
1641uint8_t HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth);
1642HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer);
1643HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length);
1644HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo);
1645HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth);
1646
1647HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout);
1648HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig);
1649
1650HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue);
1651HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue);
1652
1653void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
1654void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
1655void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
1656void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth);
1657void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth);
1658void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth);
1659void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth);
1660void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth);
1668/* Peripheral Control functions **********************************************/
1669/* MAC & DMA Configuration APIs **********************************************/
1670HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
1671HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
1672HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
1673HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
1674void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);
1675
1676/* MAC VLAN Processing APIs ************************************************/
1677void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier);
1678
1679/* MAC L2 Packet Filtering APIs **********************************************/
1680HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
1681HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
1682HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);
1683HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr);
1684
1685/* MAC Power Down APIs *****************************************************/
1686void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig);
1687void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);
1688HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count);
1689
1697/* Peripheral State functions **************************************************/
1698HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
1699uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth);
1700uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth);
1701uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth);
1702uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth);
1719#endif /* ETH */
1720
1721#ifdef __cplusplus
1722}
1723#endif
1724
1725#endif /* STM32H7xx_HAL_ETH_LEGACY_H */
#define __IO
Definition: core_cm4.h:239
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32h7xx_hal_def.h:58
Header file of ETH HAL Extended module.
Ethernet MAC.
Definition: stm32h723xx.h:717