RTEMS 6.1-rc6
Loading...
Searching...
No Matches
tx4925.h
Go to the documentation of this file.
1/* SPDX-License-Identifier: BSD-2-Clause */
2
9/*
10 * COPYRIGHT (c) 1989-2012.
11 * On-Line Applications Research Corporation (OAR).
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __TX4925_h
36#define __TX4925_h
37
38#define TX4925_REG_BASE 0xFF1F0000
39
40
41/*
42 * Configuration Registers
43 */
44#define TX4925_CFG_CCFG 0xE000 /* Chip Configuration Register */
45#define TX4925_CFG_REVID 0xE004 /* Chip Revision ID Register */
46#define TX4925_CFG_PCFG 0xE008 /* Pin Configuration Register */
47#define TX4925_CFG_TOEA 0xE00C /* TimeOut Error Access Address Register */
48#define TX4925_CFG_PDNCTR 0xE010 /* Power Down Control Register */
49#define TX4925_CFG_GARBP 0xE018 /* GBUS Arbiter Priority Register */
50#define TX4925_CFG_TOCNT 0xE020 /* Timeout Count Register */
51#define TX4925_CFG_DRQCTR 0xE024 /* DMA Request Control Register */
52#define TX4925_CFG_CLKCTR 0xE028 /* Clock Control Register */
53#define TX4925_CFG_GARBC 0xE02C /* GBUS Arbiter Control Register */
54#define TX4925_CFG_RAMP 0xE030 /* Register Address Mapping Register */
55
56/* Pin Configuration register bits */
57#define SELCHI 0x00100000
58#define SELTMR0 0x00000200
59
60
61/*
62 * Timer Registers
63 */
64
65#define TX4925_TIMER0_BASE 0xF000
66#define TX4925_TIMER1_BASE 0xF100
67#define TX4925_TIMER2_BASE 0xF200
68
69#define TX4925_TIMER_TCR 0x00 /* Timer Control Register */
70#define TX4925_TIMER_TISR 0x04 /* Timer Interrupt Status Register */
71#define TX4925_TIMER_CPRA 0x08 /* Compare Register A */
72#define TX4925_TIMER_CPRB 0x0C /* Compare Register B */
73#define TX4925_TIMER_ITMR 0x10 /* Interval Timer Mode Register */
74#define TX4925_TIMER_CCDR 0x20 /* Divide Cycle Register */
75#define TX4925_TIMER_PGMR 0x30 /* Pulse Generator Mode Register */
76#define TX4925_TIMER_WTMR 0x40 /* Reserved Register */
77#define TX4925_TIMER_TRR 0xF0 /* Timer Read Register */
78
79/* ITMR register bits */
80#define TIMER_CLEAR_ENABLE_MASK 0x1
81#define TIMER_INT_ENABLE_MASK 0x8000
82
83/* PGMR register bits */
84#define FFI 0x1
85#define TPIAE 0x4000
86#define TPIBE 0x8000
87
88/* TISR register bits */
89#define TIIS 0x1
90#define TPIAS 0x2
91#define TPIBS 0x4
92#define TWIS 0x8
93
94
95/*
96 * Interrupt Controller Registers
97 */
98#define TX4925_IRQCTL_DEN 0xF600 /* Interrupt Detection Enable Register */
99#define TX4925_IRQCTL_DM0 0xF604 /* Interrupt Detection Mode Register 0 */
100#define TX4925_IRQCTL_DM1 0xF608 /* Interrupt Detection Mode Register 1 */
101#define TX4925_IRQCTL_LVL0 0xF610 /* Interrupt Level Register 0 */
102#define TX4925_IRQCTL_LVL1 0xF614 /* Interrupt Level Register 1 */
103#define TX4925_IRQCTL_LVL2 0xF618 /* Interrupt Level Register 2 */
104#define TX4925_IRQCTL_LVL3 0xF61C /* Interrupt Level Register 3 */
105#define TX4925_IRQCTL_LVL4 0xF620 /* Interrupt Level Register 4 */
106#define TX4925_IRQCTL_LVL5 0xF624 /* Interrupt Level Register 5 */
107#define TX4925_IRQCTL_LVL6 0xF628 /* Interrupt Level Register 6 */
108#define TX4925_IRQCTL_LVL7 0xF62C /* Interrupt Level Register 7 */
109#define TX4925_IRQCTL_MSK 0xF640 /* Interrupt Mask Register */
110#define TX4925_IRQCTL_EDC 0xF660 /* Interrupt Edge Detection Clear Register */
111#define TX4925_IRQCTL_PND 0xF680 /* Interrupt Pending Register */
112#define TX4925_IRQCTL_CS 0xF6A0 /* Interrupt Current Status Register */
113#define TX4925_IRQCTL_FLAG0 0xF510 /* Interrupt Request Flag Register 0 */
114#define TX4925_IRQCTL_FLAG1 0xF514 /* Interrupt Request Flag Register 1 */
115#define TX4925_IRQCTL_POL 0xF518 /* Interrupt Request Polarity Control Register */
116#define TX4925_IRQCTL_RCNT 0xF51C /* Interrupt Request Control Register */
117#define TX4925_IRQCTL_MASKINT 0xF520 /* Interrupt Request Internal Interrupt Mask Register */
118#define TX4925_IRQCTL_MASKEXT 0xF524 /* Interrupt Request External Interrupt Mask Register */
119
120#define TX4925_REG_READ( _base, _register ) \
121 *((volatile uint32_t *)((_base) + (_register)))
122
123#define TX4925_REG_WRITE( _base, _register, _value ) \
124 *((volatile uint32_t *)((_base) + (_register))) = (_value)
125
126#endif