56#ifndef LIBBSP_ARM_TMS570_SELFTEST_H
57#define LIBBSP_ARM_TMS570_SELFTEST_H
62#define CCMSELFCHECK_FAIL1 1U
63#define CCMSELFCHECK_FAIL2 2U
64#define CCMSELFCHECK_FAIL3 3U
65#define CCMSELFCHECK_FAIL4 4U
66#define PBISTSELFCHECK_FAIL1 5U
67#define EFCCHECK_FAIL1 6U
68#define EFCCHECK_FAIL2 7U
69#define FMCECCCHECK_FAIL1 8U
70#define CHECKB0RAMECC_FAIL1 9U
71#define CHECKB1RAMECC_FAIL1 10U
72#define CHECKFLASHECC_FAIL1 11U
73#define VIMPARITYCHECK_FAIL1 12U
74#define DMAPARITYCHECK_FAIL1 13U
75#define HET1PARITYCHECK_FAIL1 14U
76#define HTU1PARITYCHECK_FAIL1 15U
77#define HET2PARITYCHECK_FAIL1 16U
78#define HTU2PARITYCHECK_FAIL1 17U
79#define ADC1PARITYCHECK_FAIL1 18U
80#define ADC2PARITYCHECK_FAIL1 19U
81#define CAN1PARITYCHECK_FAIL1 20U
82#define CAN2PARITYCHECK_FAIL1 21U
83#define CAN3PARITYCHECK_FAIL1 22U
84#define MIBSPI1PARITYCHECK_FAIL1 23U
85#define MIBSPI3PARITYCHECK_FAIL1 24U
86#define MIBSPI5PARITYCHECK_FAIL1 25U
87#define CHECKRAMECC_FAIL1 26U
88#define CHECKRAMECC_FAIL2 27U
89#define CHECKCLOCKMONITOR_FAIL1 28U
90#define CHECKFLASHEEPROMECC_FAIL1 29U
91#define CHECKFLASHEEPROMECC_FAIL2 31U
92#define CHECKFLASHEEPROMECC_FAIL3 32U
93#define CHECKFLASHEEPROMECC_FAIL4 33U
94#define CHECKPLL1SLIP_FAIL1 34U
95#define CHECKRAMADDRPARITY_FAIL1 35U
96#define CHECKRAMADDRPARITY_FAIL2 36U
97#define CHECKRAMUERRTEST_FAIL1 37U
98#define CHECKRAMUERRTEST_FAIL2 38U
99#define FMCBUS1PARITYCHECK_FAIL1 39U
100#define FMCBUS1PARITYCHECK_FAIL2 40U
101#define PBISTSELFCHECK_FAIL2 41U
102#define PBISTSELFCHECK_FAIL3 42U
105#define PBIST_ROM_PBIST_RAM_GROUP 1U
106#define STC_ROM_PBIST_RAM_GROUP 2U
108#define VIMRAMLOC (*(volatile uint32_t *)0xFFF82000U)
109#define VIMRAMPARLOC (*(volatile uint32_t *)0xFFF82400U)
111#define NHET1RAMPARLOC (*(volatile uint32_t *)0xFF462000U)
112#define NHET2RAMPARLOC (*(volatile uint32_t *)0xFF442000U)
113#define adcPARRAM1 (*(volatile uint32_t *)(0xFF3E0000U + 0x1000U))
114#define adcPARRAM2 (*(volatile uint32_t *)(0xFF3A0000U + 0x1000U))
115#define canPARRAM1 (*(volatile uint32_t *)(0xFF1E0000U + 0x10U))
116#define canPARRAM2 (*(volatile uint32_t *)(0xFF1C0000U + 0x10U))
117#define canPARRAM3 (*(volatile uint32_t *)(0xFF1A0000U + 0x10U))
118#define HTU1PARLOC (*(volatile uint32_t *)0xFF4E0200U)
119#define HTU2PARLOC (*(volatile uint32_t *)0xFF4C0200U)
121#define NHET1RAMLOC (*(volatile uint32_t *)0xFF460000U)
122#define NHET2RAMLOC (*(volatile uint32_t *)0xFF440000U)
123#define HTU1RAMLOC (*(volatile uint32_t *)0xFF4E0000U)
124#define HTU2RAMLOC (*(volatile uint32_t *)0xFF4C0000U)
126#define adcRAM1 (*(volatile uint32_t *)0xFF3E0000U)
127#define adcRAM2 (*(volatile uint32_t *)0xFF3A0000U)
128#define canRAM1 (*(volatile uint32_t *)0xFF1E0000U)
129#define canRAM2 (*(volatile uint32_t *)0xFF1C0000U)
130#define canRAM3 (*(volatile uint32_t *)0xFF1A0000U)
132#define DMARAMPARLOC (*(volatile uint32_t *)(0xFFF80A00U))
133#define DMARAMLOC (*(volatile uint32_t *)(0xFFF80000U))
135#define MIBSPI1RAMLOC (*(volatile uint32_t *)(0xFF0E0000U))
136#define MIBSPI3RAMLOC (*(volatile uint32_t *)(0xFF0C0000U))
137#define MIBSPI5RAMLOC (*(volatile uint32_t *)(0xFF0A0000U))
139#define mibspiPARRAM1 (*(volatile uint32_t *)(0xFF0E0000U + 0x00000400U))
140#define mibspiPARRAM3 (*(volatile uint32_t *)(0xFF0C0000U + 0x00000400U))
141#define mibspiPARRAM5 (*(volatile uint32_t *)(0xFF0A0000U + 0x00000400U))
167void bsp_selftest_fail_notification( uint32_t flag );
169void tms570_memory_port0_fail_notification(
170 uint32_t groupSelect,
213void tms570_check_tcram_ecc(
void );
int tms570_esm_channel_sr_get(unsigned grp, unsigned chan)
Routine to test is specified error channel is signalling error.
Definition: tms570_selftest.c:592
void tms570_pbist_self_check(void)
PBIST self test Driver (HCG:pbistSelfCheck)
Definition: tms570_selftest.c:261
void tms570_pbist_run(uint32_t raminfoL, uint32_t algomask)
CPU self test Driver (HCG:pbistRun)
Definition: tms570_selftest.c:351
@ PBIST_March13N_DP
Definition: tms570_selftest.h:160
@ PBIST_TripleReadFast
Definition: tms570_selftest.h:159
@ PBIST_TripleReadSlow
Definition: tms570_selftest.h:158
void tms570_pbist_fail(void)
Reaction to PBIST failure (HCG:pbistFail)
Definition: tms570_selftest.c:503
bool tms570_pbist_is_test_passed(void)
Checks to see if the PBIST test is completed successfully (HCG:pbistIsTestPassed)
Definition: tms570_selftest.c:431
bool tms570_pbist_port_test_status(uint32_t port)
Checks to see if the PBIST Port test is completed successfully (HCG:pbistPortTestStatus)
Definition: tms570_selftest.c:481
bool tms570_efc_stuck_zero(void)
Checks to see if the EFUSE Stuck at zero test is completed successfully (HCG:efcStuckZeroTest)....
Definition: tms570_selftest.c:90
void tms570_pbist_run_and_check(uint32_t raminfoL, uint32_t algomask)
Definition: tms570_selftest.c:448
void tms570_efc_self_test(void)
EFUSE module self check Driver (HCG:efcSelfTest)
Definition: tms570_selftest.c:149
void tms570_esm_channel_sr_clear(unsigned grp, unsigned chan)
Routine to clear specified error channel signalling bit.
Definition: tms570_selftest.c:574
void tms570_enable_parity(void)
Enable peripheral RAM parity (HCG:enableParity)
Definition: tms570_selftest.c:614
void tms570_pbist_stop(void)
Routine to stop PBIST test enabled (HCG:pbistStop)
Definition: tms570_selftest.c:400
void tms570_disable_parity(void)
Disable peripheral RAM parity (HCG:disableParity)
Definition: tms570_selftest.c:636
bool tms570_efc_check_self_test(void)
EFUSE module self check Driver (HCG:checkefcSelfTest)
Definition: tms570_selftest.c:173
pbistPort
Alias names for pbist Port number.
Definition: tms570_selftest.h:152
@ PBIST_PORT0
Definition: tms570_selftest.h:153
@ PBIST_PORT1
Definition: tms570_selftest.h:154
bool tms570_pbist_is_test_completed(void)
Checks to see if the PBIST test is completed (HCG:pbistIsTestCompleted)
Definition: tms570_selftest.c:417
uint32_t tms570_efc_check(void)
EFUSE module self check Driver (HCG:efcCheck)
Definition: tms570_selftest.c:216