22#ifndef LIBBSP_ARM_LPC176X_TIMER_DEFS_H
23#define LIBBSP_ARM_LPC176X_TIMER_DEFS_H
32#define LPC176X_TMR0_BASE_ADDR 0x40004000U
34#define LPC176X_T0IR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
36#define LPC176X_T0TCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
38#define LPC176X_T0TC ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
40#define LPC176X_T0PR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
42#define LPC176X_T0PC ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
44#define LPC176X_T0MCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
46#define LPC176X_T0MR0 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
48#define LPC176X_T0MR1 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
50#define LPC176X_T0MR2 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
52#define LPC176X_T0MR3 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
54#define LPC176X_T0CCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
56#define LPC176X_T0CR0 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
58#define LPC176X_T0CR1 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
60#define LPC176X_T0CR2 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
62#define LPC176X_T0CR3 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
64#define LPC176X_T0EMR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
66#define LPC176X_T0CTCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
70#define LPC176X_TMR1_BASE_ADDR 0x40008000U
72#define LPC176X_T1IR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
74#define LPC176X_T1TCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
76#define LPC176X_T1TC ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
78#define LPC176X_T1PR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
80#define LPC176X_T1PC ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
82#define LPC176X_T1MCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
84#define LPC176X_T1MR0 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
86#define LPC176X_T1MR1 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
88#define LPC176X_T1MR2 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
90#define LPC176X_T1MR3 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
92#define LPC176X_T1CCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
94#define LPC176X_T1CR0 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
96#define LPC176X_T1CR1 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
98#define LPC176X_T1CR2 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
100#define LPC176X_T1CR3 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
102#define LPC176X_T1EMR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
104#define LPC176X_T1CTCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
108#define LPC176X_TMR2_BASE_ADDR 0x40090000U
110#define LPC176X_T2IR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
112#define LPC176X_T2TCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
114#define LPC176X_T2TC ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
116#define LPC176X_T2PR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
118#define LPC176X_T2PC ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
120#define LPC176X_T2MCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
122#define LPC176X_T2MR0 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
124#define LPC176X_T2MR1 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
126#define LPC176X_T2MR2 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
128#define LPC176X_T2MR3 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
130#define LPC176X_T2CCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
132#define LPC176X_T2CR0 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
134#define LPC176X_T2CR1 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
136#define LPC176X_T2CR2 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
138#define LPC176X_T2CR3 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
140#define LPC176X_T2EMR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
142#define LPC176X_T2CTCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
146#define LPC176X_TMR3_BASE_ADDR 0x40094000U
148#define LPC176X_T3IR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
150#define LPC176X_T3TCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
152#define LPC176X_T3TC ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
154#define LPC176X_T3PR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
156#define LPC176X_T3PC ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
158#define LPC176X_T3MCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
160#define LPC176X_T3MR0 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
162#define LPC176X_T3MR1 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
164#define LPC176X_T3MR2 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
166#define LPC176X_T3MR3 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
168#define LPC176X_T3CCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
170#define LPC176X_T3CR0 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
172#define LPC176X_T3CR1 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
174#define LPC176X_T3CR2 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
176#define LPC176X_T3CR3 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
178#define LPC176X_T3EMR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
180#define LPC176X_T3CTCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
190 volatile uint32_t
IR;
198 volatile uint32_t
TC;
202 volatile uint32_t
PR;
206 volatile uint32_t
PC;
214 volatile uint32_t MR[ 4 ];
222 volatile uint32_t CR[ 2 ];
223 volatile uint32_t reserved0;
224 volatile uint32_t reserved1;
229 volatile uint32_t reserved2[ 12 ];
236#define LPC176X_PIN_SELECT_TIMER 3U
237#define LPC176X_PINSEL_NO_PORT 999U
239#define LPC176X_TIMER_RESET ( 1U << 1U )
240#define LPC176X_TIMER_START 1U
241#define LPC176X_TIMER_MODE_COUNTER_SOURCE_CAP0 0U
242#define LPC176X_TIMER_MODE_COUNTER_SOURCE_CAP1 ( 1U << 2U )
243#define LPC176X_TIMER0_CAPTURE_PORTS { 58U, 59U }
244#define LPC176X_TIMER1_CAPTURE_PORTS { 50U, 51U }
245#define LPC176X_TIMER2_CAPTURE_PORTS { 4U, 5U }
246#define LPC176X_TIMER3_CAPTURE_PORTS { 23U, 24U }
247#define LPC176X_TIMER0_EMATCH_PORTS { 60U, \
249 LPC176X_PINSEL_NO_PORT, \
250 LPC176X_PINSEL_NO_PORT }
251#define LPC176X_TIMER1_EMATCH_PORTS { 54U, \
253 LPC176X_PINSEL_NO_PORT, \
254 LPC176X_PINSEL_NO_PORT }
255#define LPC176X_TIMER2_EMATCH_PORTS { 6U, 7U, 8U, 9U }
256#define LPC176X_TIMER3_EMATCH_PORTS { 10U, \
258 LPC176X_PINSEL_NO_PORT, \
259 LPC176X_PINSEL_NO_PORT }
260#define LPC176X_TIMER_DEFAULT_RESOLUTION 1U
261#define LPC176X_TIMER_MCR_MASK 7U
262#define LPC176X_TIMER_MCR_MASK_SIZE 3U
263#define LPC176X_TIMER_CCR_MASK 7U
264#define LPC176X_TIMER_CCR_MASK_SIZE 3U
265#define LPC176X_TIMER_EMR_MASK 3U
266#define LPC176X_TIMER_EMR_MASK_SIZE 2U
267#define LPC176X_TIMER_EMR_MASK_OFFSET 4U
268#define LPC176X_TIMER_CLEAR_FUNCTION 0U
269#define LPC176X_TIMER_PRESCALER_DIVISOR 1000000U
270#define LPC176X_TIMER_VECTOR_NUMBER( timernumber ) ( timernumber + 1U )
271#define LPC176X_TIMER_INTERRUPT_SOURCE_BIT( i ) ( 1U << i )
272#define LPC176X_TIMER_MATCH_FUNCTION_COUNT 8U
273#define LPC176X_TIMER_CAPTURE_FUNCTION_COUNT 8U
275#define LPC176X_ISR_NAME_STRING_SIZE 10U
277#define LPC176X_SET_MCR( mcr, match_port, function ) \
280 ( 0x7U << ( 3U * match_port ) ), \
281 ( 3U * match_port ) )
282#define LPC176X_SET_CCR( mcr, capture_port, function ) \
283 SET_FIELD( mcr, function, ( 0x7U << ( 3U * capture_port ) ), \
284 ( 3U * capture_port ) )
285#define LPC176X_SET_EMR( mcr, match_port, function ) \
286 SET_FIELD( mcr, function, ( 0x3U << ( 2U * match_port + 4U ) ), \
287 ( 2U * match_port + 4U ) )
297 LPC176X_CAPTURE_PORTS_COUNT
310 LPC176X_EMATCH_PORTS_COUNT
319 LPC176X_TIMER_MODE_TIMER,
320 LPC176X_TIMER_MODE_COUNTER_RISING_CAP0,
321 LPC176X_TIMER_MODE_COUNTER_FALLING_CAP0,
322 LPC176X_TIMER_MODE_COUNTER_BOTH_CAP0,
323 LPC176X_TIMER_MODE_COUNTER_RISING_CAP1 = ( 1U & ( 1U << 2U ) ),
324 LPC176X_TIMER_MODE_COUNTER_FALLING_CAP1 = ( 2U & ( 1U << 2U ) ),
325 LPC176X_TIMER_MODE_COUNTER_BOTH_CAP1 = ( 3U & ( 1U << 2U ) ),
348 LPC176X_MAT0_ISR_FUNCTION,
349 LPC176X_MAT1_ISR_FUNCTION,
350 LPC176X_MAT2_ISR_FUNCTION,
351 LPC176X_MAT3_ISR_FUNCTION,
352 LPC176X_CAP0_ISR_FUNCTION,
353 LPC176X_CAP1_ISR_FUNCTION,
354 LPC176X_ISR_FUNCTIONS_COUNT
365 LPC176X_TIMER_MATCH_FUNCTION_NONE = 0U,
366 LPC176X_TIMER_MATCH_FUNCTION_INTERRUPT = 1U,
367 LPC176X_TIMER_MATCH_FUNCTION_RESET = ( 1U << 1U ),
368 LPC176X_TIMER_MATCH_FUNCTION_STOP = ( 1U << 2U )
379 LPC176X_TIMER_CAPTURE_FUNCTION_NONE = 0U,
380 LPC176X_TIMER_CAPTURE_FUNCTION_RISING = 1U,
381 LPC176X_TIMER_CAPTURE_FUNCTION_FALLING = ( 1U << 1U ),
382 LPC176X_TIMER_CAPTURE_FUNCTION_INTERRUPT = ( 1U << 2U )
392 LPC176X_TIMER_EXTMATCH_FUNCTION_NONE,
393 LPC176X_TIMER_EXTMATCH_FUNCTION_CLEAR,
394 LPC176X_TIMER_EXTMATCH_FUNCTION_SET,
395 LPC176X_TIMER_EXTMATCH_FUNCTION_TOGGLE
411 LPC176X_ISR_FUNCTIONS_COUNT ];
Definitions types used by some devices in common.
lpc176x_module
lpc176x module representation.
Definition: common-types.h:44
uint32_t lpc176x_pin_number
A pin of the board.
Definition: common-types.h:32
Represents the timer device registers.
Definition: timer-defs.h:186
volatile uint32_t MCR
Match Control Register.
Definition: timer-defs.h:210
volatile uint32_t TC
Timer Counter.
Definition: timer-defs.h:198
volatile uint32_t PR
Prescale Register.
Definition: timer-defs.h:202
volatile uint32_t EMR
External Match Register.
Definition: timer-defs.h:228
volatile uint32_t PC
Prescale Counter.
Definition: timer-defs.h:206
volatile uint32_t TCR
Timer Control Register.
Definition: timer-defs.h:194
volatile uint32_t CCR
Capture Control Register.
Definition: timer-defs.h:218
volatile uint32_t CTCR
Count Control Register.
Definition: timer-defs.h:233
volatile uint32_t IR
Interrupt Register.
Definition: timer-defs.h:190
The Timer functions.
Definition: timer-defs.h:438
const lpc176x_isr_funct_vector * funct_vector
The vector of isr functions for this timer.
Definition: timer-defs.h:442
The Timer device representation.
Definition: timer-defs.h:416
lpc176x_timer_device *const device
The address of the controlling registers for the timer.
Definition: timer-defs.h:420
const lpc176x_module module
The module for the RTEMS module starting (power and clock).
Definition: timer-defs.h:424
void(* lpc176x_isr_funct)(const lpc176x_timer_number tnumber)
A function that attends an interruption for a timer.
Definition: timer-defs.h:404
lpc176x_ext_match_function
The possible functions at match, for the external ports.
Definition: timer-defs.h:391
lpc176x_timer_number
The timer devices in the board.
Definition: timer-defs.h:333
lpc176x_isr_funct const lpc176x_isr_funct_vector[LPC176X_ISR_FUNCTIONS_COUNT]
The vector of functions that attends each possible interrupt source for a timer.
Definition: timer-defs.h:411
lpc176x_match_port
Match ports of a timer.
Definition: timer-defs.h:305
lpc176x_match_function
The possible functions at match. This options could be used together.
Definition: timer-defs.h:364
lpc176x_capture_function
The possible functions at capture. This options could be used together.
Definition: timer-defs.h:378
lpc176x_isr_function
The index for the isr_funct_vector representing the functions that attends each possible interrupt so...
Definition: timer-defs.h:347
lpc176x_timer_mode
Timer modes of a timer.
Definition: timer-defs.h:318
lpc176x_capture_port
Capture ports of a timer.
Definition: timer-defs.h:294