20#ifndef STM32H7xx_LL_RTC_H
21#define STM32H7xx_LL_RTC_H
49#define RTC_LL_INIT_MASK 0xFFFFFFFFU
50#define RTC_LL_RSF_MASK 0xFFFFFF5FU
53#define RTC_WRITE_PROTECTION_DISABLE 0xFFU
54#define RTC_WRITE_PROTECTION_ENABLE_1 0xCAU
55#define RTC_WRITE_PROTECTION_ENABLE_2 0x53U
58#define RTC_OFFSET_WEEKDAY 24U
59#define RTC_OFFSET_DAY 16U
60#define RTC_OFFSET_MONTH 8U
61#define RTC_OFFSET_HOUR 16U
62#define RTC_OFFSET_MINUTE 8U
69#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
80#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
97 uint32_t AsynchPrescaler;
103 uint32_t SynchPrescaler;
168 LL_RTC_TimeTypeDef AlarmTime;
177 uint32_t AlarmDateWeekDaySel;
184 uint8_t AlarmDateWeekDay;
195} LL_RTC_AlarmTypeDef;
208#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
213#define LL_RTC_FORMAT_BIN 0x00000000U
214#define LL_RTC_FORMAT_BCD 0x00000001U
223#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U
224#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
233#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U
234#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL
247#define LL_RTC_SCR_ITSF RTC_SCR_CITSF
248#define LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF
249#define LL_RTC_SCR_TSF RTC_SCR_CTSF
250#define LL_RTC_SCR_WUTF RTC_SCR_CWUTF
251#define LL_RTC_SCR_ALRBF RTC_SCR_CALRBF
252#define LL_RTC_SCR_ALRAF RTC_SCR_CALRAF
254#define LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF
255#define LL_RTC_ICSR_INITF RTC_ICSR_INITF
256#define LL_RTC_ICSR_RSF RTC_ICSR_RSF
257#define LL_RTC_ICSR_INITS RTC_ICSR_INITS
258#define LL_RTC_ICSR_SHPF RTC_ICSR_SHPF
259#define LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF
261#define LL_RTC_ISR_ITSF RTC_ISR_ITSF
262#define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF
263#define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F
264#define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F
265#define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F
266#define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF
267#define LL_RTC_ISR_TSF RTC_ISR_TSF
268#define LL_RTC_ISR_WUTF RTC_ISR_WUTF
269#define LL_RTC_ISR_ALRBF RTC_ISR_ALRBF
270#define LL_RTC_ISR_ALRAF RTC_ISR_ALRAF
271#define LL_RTC_ISR_INITF RTC_ISR_INITF
272#define LL_RTC_ISR_RSF RTC_ISR_RSF
273#define LL_RTC_ISR_INITS RTC_ISR_INITS
274#define LL_RTC_ISR_SHPF RTC_ISR_SHPF
275#define LL_RTC_ISR_WUTWF RTC_ISR_WUTWF
276#define LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF
277#define LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF
288#define LL_RTC_CR_TSIE RTC_CR_TSIE
289#define LL_RTC_CR_WUTIE RTC_CR_WUTIE
290#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
291#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE
293#define LL_RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE
294#define LL_RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE
295#define LL_RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE
296#define LL_RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE
306#define LL_RTC_WEEKDAY_MONDAY (uint8_t)0x01
307#define LL_RTC_WEEKDAY_TUESDAY (uint8_t)0x02
308#define LL_RTC_WEEKDAY_WEDNESDAY (uint8_t)0x03
309#define LL_RTC_WEEKDAY_THURSDAY (uint8_t)0x04
310#define LL_RTC_WEEKDAY_FRIDAY (uint8_t)0x05
311#define LL_RTC_WEEKDAY_SATURDAY (uint8_t)0x06
312#define LL_RTC_WEEKDAY_SUNDAY (uint8_t)0x07
321#define LL_RTC_MONTH_JANUARY (uint8_t)0x01
322#define LL_RTC_MONTH_FEBRUARY (uint8_t)0x02
323#define LL_RTC_MONTH_MARCH (uint8_t)0x03
324#define LL_RTC_MONTH_APRIL (uint8_t)0x04
325#define LL_RTC_MONTH_MAY (uint8_t)0x05
326#define LL_RTC_MONTH_JUNE (uint8_t)0x06
327#define LL_RTC_MONTH_JULY (uint8_t)0x07
328#define LL_RTC_MONTH_AUGUST (uint8_t)0x08
329#define LL_RTC_MONTH_SEPTEMBER (uint8_t)0x09
330#define LL_RTC_MONTH_OCTOBER (uint8_t)0x10
331#define LL_RTC_MONTH_NOVEMBER (uint8_t)0x11
332#define LL_RTC_MONTH_DECEMBER (uint8_t)0x12
341#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U
342#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT
351#define LL_RTC_ALARMOUT_DISABLE 0x00000000U
352#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0
353#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1
354#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL
364#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE
365#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0x00000000U
367#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U
368#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_OR_ALARMOUTTYPE
378#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U
379#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL
388#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U
389#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM
398#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U
399#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S
408#define LL_RTC_ALMA_MASK_NONE 0x00000000U
409#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4
410#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3
411#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2
412#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1
413#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)
422#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U
423#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM
432#define LL_RTC_ALMB_MASK_NONE 0x00000000U
433#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4
434#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3
435#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2
436#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1
437#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)
446#define LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U
447#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM
456#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U
457#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE
466#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U
467#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM
477#define LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E
478#define LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E
479#define LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E
488#define LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MSK
489#define LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MSK
490#define LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MSK
499#define LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1NOERASE
500#define LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2NOERASE
501#define LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3NOERASE
510#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U
511#define LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0
512#define LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1
513#define LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH
522#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U
523#define LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0
524#define LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1
525#define LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT
534#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U
535#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0
536#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1
537#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0)
538#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2
539#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0)
540#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1)
541#define LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ
550#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG
551#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG
552#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG
561#define LL_RTC_TAMPER_1 RTC_TAMPCR_TAMP1E
562#define LL_RTC_TAMPER_2 RTC_TAMPCR_TAMP2E
563#define LL_RTC_TAMPER_3 RTC_TAMPCR_TAMP3E
572#define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAMPCR_TAMP1MF
573#define LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAMPCR_TAMP2MF
574#define LL_RTC_TAMPER_MASK_TAMPER3 RTC_TAMPCR_TAMP3MF
583#define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAMPCR_TAMP1NOERASE
584#define LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAMPCR_TAMP2NOERASE
585#define LL_RTC_TAMPER_NOERASE_TAMPER3 RTC_TAMPCR_TAMP3NOERASE
594#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U
595#define LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0
596#define LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAMPCR_TAMPPRCH_1
597#define LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAMPCR_TAMPPRCH
606#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U
607#define LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0
608#define LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1
609#define LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAMPCR_TAMPFLT
618#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U
619#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAMPCR_TAMPFREQ_0
620#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAMPCR_TAMPFREQ_1
621#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_0)
622#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 RTC_TAMPCR_TAMPFREQ_2
623#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_0)
624#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_1)
625#define LL_RTC_TAMPER_SAMPLFREQDIV_256 RTC_TAMPCR_TAMPFREQ
634#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAMPCR_TAMP1TRG
635#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAMPCR_TAMP2TRG
636#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAMPCR_TAMP3TRG
647#define LL_RTC_TAMPER_ATAMP_TAMP1AM TAMP_ATCR1_TAMP1AM
648#define LL_RTC_TAMPER_ATAMP_TAMP2AM TAMP_ATCR1_TAMP2AM
649#define LL_RTC_TAMPER_ATAMP_TAMP3AM TAMP_ATCR1_TAMP3AM
658#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK 0U
659#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0
660#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1
661#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)
662#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2
663#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0)
664#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1)
665#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)
674#define LL_RTC_TAMPER_ATAMP1IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL1_Pos)
675#define LL_RTC_TAMPER_ATAMP1IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL1_Pos)
676#define LL_RTC_TAMPER_ATAMP1IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL1_Pos)
678#define LL_RTC_TAMPER_ATAMP2IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL2_Pos)
679#define LL_RTC_TAMPER_ATAMP2IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL2_Pos)
680#define LL_RTC_TAMPER_ATAMP2IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL2_Pos)
682#define LL_RTC_TAMPER_ATAMP3IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL3_Pos)
683#define LL_RTC_TAMPER_ATAMP3IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL3_Pos)
684#define LL_RTC_TAMPER_ATAMP3IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL3_Pos)
694#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U
695#define LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0
696#define LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1
697#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0)
698#define LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2
699#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1)
708#define LL_RTC_BKP_DR0 0x00000000U
709#define LL_RTC_BKP_DR1 0x00000001U
710#define LL_RTC_BKP_DR2 0x00000002U
711#define LL_RTC_BKP_DR3 0x00000003U
712#define LL_RTC_BKP_DR4 0x00000004U
713#define LL_RTC_BKP_DR5 0x00000005U
714#define LL_RTC_BKP_DR6 0x00000006U
715#define LL_RTC_BKP_DR7 0x00000007U
716#define LL_RTC_BKP_DR8 0x00000008U
717#define LL_RTC_BKP_DR9 0x00000009U
718#define LL_RTC_BKP_DR10 0x0000000AU
719#define LL_RTC_BKP_DR11 0x0000000BU
720#define LL_RTC_BKP_DR12 0x0000000CU
721#define LL_RTC_BKP_DR13 0x0000000DU
722#define LL_RTC_BKP_DR14 0x0000000EU
723#define LL_RTC_BKP_DR15 0x0000000FU
724#define LL_RTC_BKP_DR16 0x00000010U
725#define LL_RTC_BKP_DR17 0x00000011U
726#define LL_RTC_BKP_DR18 0x00000012U
727#define LL_RTC_BKP_DR19 0x00000013U
728#define LL_RTC_BKP_DR20 0x00000014U
729#define LL_RTC_BKP_DR21 0x00000015U
730#define LL_RTC_BKP_DR22 0x00000016U
731#define LL_RTC_BKP_DR23 0x00000017U
732#define LL_RTC_BKP_DR24 0x00000018U
733#define LL_RTC_BKP_DR25 0x00000019U
734#define LL_RTC_BKP_DR26 0x0000001AU
735#define LL_RTC_BKP_DR27 0x0000001BU
736#define LL_RTC_BKP_DR28 0x0000001CU
737#define LL_RTC_BKP_DR29 0x0000001DU
738#define LL_RTC_BKP_DR30 0x0000001EU
739#define LL_RTC_BKP_DR31 0x0000001FU
748#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U
749#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL)
750#define LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE
759#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U
760#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP
769#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U
770#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16
771#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8
798#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, __VALUE__)
806#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
821#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
828#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) ((uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0) >> (uint8_t)0x4) * 10U) + ((__VALUE__) & (uint8_t)0x0F)))
851#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
858#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
877#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
884#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
900#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
907#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
914#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
946__STATIC_INLINE
void LL_RTC_SetHourFormat(
RTC_TypeDef *RTCx, uint32_t HourFormat)
948 MODIFY_REG(RTCx->
CR, RTC_CR_FMT, HourFormat);
959__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(
RTC_TypeDef *RTCx)
961 return (uint32_t)(READ_BIT(RTCx->
CR, RTC_CR_FMT));
976__STATIC_INLINE
void LL_RTC_SetAlarmOutEvent(
RTC_TypeDef *RTCx, uint32_t AlarmOutput)
978 MODIFY_REG(RTCx->
CR, RTC_CR_OSEL, AlarmOutput);
991__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(
RTC_TypeDef *RTCx)
993 return (uint32_t)(READ_BIT(RTCx->
CR, RTC_CR_OSEL));
1006__STATIC_INLINE
void LL_RTC_SetAlarmOutputType(
RTC_TypeDef *RTCx, uint32_t Output)
1019__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(
RTC_TypeDef *RTCx)
1034__STATIC_INLINE
void LL_RTC_SetAlarmOutputType(
RTC_TypeDef *RTCx, uint32_t Output)
1036 MODIFY_REG(RTCx->
OR, RTC_OR_ALARMOUTTYPE, Output);
1048__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(
RTC_TypeDef *RTCx)
1050 return (uint32_t)(READ_BIT(RTCx->
OR, RTC_OR_ALARMOUTTYPE));
1064__STATIC_INLINE
void LL_RTC_EnableInitMode(
RTC_TypeDef *RTCx)
1067 WRITE_REG(RTCx->
ICSR, RTC_LL_INIT_MASK);
1076__STATIC_INLINE
void LL_RTC_DisableInitMode(
RTC_TypeDef *RTCx)
1079 WRITE_REG(RTCx->
ICSR, (uint32_t)~RTC_ICSR_INIT);
1092__STATIC_INLINE
void LL_RTC_EnableInitMode(
RTC_TypeDef *RTCx)
1095 WRITE_REG(RTCx->
ISR, RTC_LL_INIT_MASK);
1104__STATIC_INLINE
void LL_RTC_DisableInitMode(
RTC_TypeDef *RTCx)
1107 WRITE_REG(RTCx->
ISR, (uint32_t)~RTC_ISR_INIT);
1121__STATIC_INLINE
void LL_RTC_SetOutputPolarity(
RTC_TypeDef *RTCx, uint32_t Polarity)
1123 MODIFY_REG(RTCx->
CR, RTC_CR_POL, Polarity);
1134__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(
RTC_TypeDef *RTCx)
1136 return (uint32_t)(READ_BIT(RTCx->
CR, RTC_CR_POL));
1146__STATIC_INLINE
void LL_RTC_EnableShadowRegBypass(
RTC_TypeDef *RTCx)
1148 SET_BIT(RTCx->
CR, RTC_CR_BYPSHAD);
1157__STATIC_INLINE
void LL_RTC_DisableShadowRegBypass(
RTC_TypeDef *RTCx)
1159 CLEAR_BIT(RTCx->
CR, RTC_CR_BYPSHAD);
1168__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(
RTC_TypeDef *RTCx)
1170 return ((READ_BIT(RTCx->
CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1UL : 0UL);
1181__STATIC_INLINE
void LL_RTC_EnableRefClock(
RTC_TypeDef *RTCx)
1183 SET_BIT(RTCx->
CR, RTC_CR_REFCKON);
1194__STATIC_INLINE
void LL_RTC_DisableRefClock(
RTC_TypeDef *RTCx)
1196 CLEAR_BIT(RTCx->
CR, RTC_CR_REFCKON);
1206__STATIC_INLINE
void LL_RTC_SetAsynchPrescaler(
RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
1208 MODIFY_REG(RTCx->
PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos);
1218__STATIC_INLINE
void LL_RTC_SetSynchPrescaler(
RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
1220 MODIFY_REG(RTCx->
PRER, RTC_PRER_PREDIV_S, SynchPrescaler);
1229__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(
RTC_TypeDef *RTCx)
1231 return (uint32_t)(READ_BIT(RTCx->
PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos);
1240__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(
RTC_TypeDef *RTCx)
1242 return (uint32_t)(READ_BIT(RTCx->
PRER, RTC_PRER_PREDIV_S));
1251__STATIC_INLINE
void LL_RTC_EnableWriteProtection(
RTC_TypeDef *RTCx)
1253 WRITE_REG(RTCx->
WPR, RTC_WRITE_PROTECTION_DISABLE);
1262__STATIC_INLINE
void LL_RTC_DisableWriteProtection(
RTC_TypeDef *RTCx)
1264 WRITE_REG(RTCx->
WPR, RTC_WRITE_PROTECTION_ENABLE_1);
1265 WRITE_REG(RTCx->
WPR, RTC_WRITE_PROTECTION_ENABLE_2);
1277__STATIC_INLINE
void LL_RTC_EnableTamperOutput(
RTC_TypeDef *RTCx)
1288__STATIC_INLINE
void LL_RTC_DisableTamperOutput(
RTC_TypeDef *RTCx)
1299__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(
RTC_TypeDef *RTCx)
1310__STATIC_INLINE
void LL_RTC_EnableAlarmPullUp(
RTC_TypeDef *RTCx)
1321__STATIC_INLINE
void LL_RTC_DisableAlarmPullUp(
RTC_TypeDef *RTCx)
1332__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(
RTC_TypeDef *RTCx)
1346__STATIC_INLINE
void LL_RTC_EnableOutput2(
RTC_TypeDef *RTCx)
1357__STATIC_INLINE
void LL_RTC_DisableOutput2(
RTC_TypeDef *RTCx)
1368__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(
RTC_TypeDef *RTCx)
1379__STATIC_INLINE
void LL_RTC_EnableOutRemap(
RTC_TypeDef *RTCx)
1381 SET_BIT(RTCx->
OR, RTC_OR_OUT_RMP);
1390__STATIC_INLINE
void LL_RTC_DisableOutRemap(
RTC_TypeDef *RTCx)
1392 CLEAR_BIT(RTCx->
OR, RTC_OR_OUT_RMP);
1416__STATIC_INLINE
void LL_RTC_TIME_SetFormat(
RTC_TypeDef *RTCx, uint32_t TimeFormat)
1418 MODIFY_REG(RTCx->
TR, RTC_TR_PM, TimeFormat);
1433__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(
RTC_TypeDef *RTCx)
1435 return (uint32_t)(READ_BIT(RTCx->
TR, RTC_TR_PM));
1449__STATIC_INLINE
void LL_RTC_TIME_SetHour(
RTC_TypeDef *RTCx, uint32_t Hours)
1451 MODIFY_REG(RTCx->
TR, (RTC_TR_HT | RTC_TR_HU),
1452 (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)));
1468__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(
RTC_TypeDef *RTCx)
1470 return (uint32_t)((READ_BIT(RTCx->
TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos);
1484__STATIC_INLINE
void LL_RTC_TIME_SetMinute(
RTC_TypeDef *RTCx, uint32_t Minutes)
1486 MODIFY_REG(RTCx->
TR, (RTC_TR_MNT | RTC_TR_MNU),
1487 (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)));
1503__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(
RTC_TypeDef *RTCx)
1505 return (uint32_t)(READ_BIT(RTCx->
TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);
1519__STATIC_INLINE
void LL_RTC_TIME_SetSecond(
RTC_TypeDef *RTCx, uint32_t Seconds)
1521 MODIFY_REG(RTCx->
TR, (RTC_TR_ST | RTC_TR_SU),
1522 (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)));
1538__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(
RTC_TypeDef *RTCx)
1540 return (uint32_t)(READ_BIT(RTCx->
TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);
1564__STATIC_INLINE
void LL_RTC_TIME_Config(
RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
1568 temp = Format12_24 | \
1569 (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \
1570 (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
1571 (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
1572 MODIFY_REG(RTCx->
TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
1592__STATIC_INLINE uint32_t LL_RTC_TIME_Get(
RTC_TypeDef *RTCx)
1596 temp = READ_BIT(RTCx->
TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
1597 return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \
1598 (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
1599 ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));
1609__STATIC_INLINE
void LL_RTC_TIME_EnableDayLightStore(
RTC_TypeDef *RTCx)
1611 SET_BIT(RTCx->
CR, RTC_CR_BKP);
1621__STATIC_INLINE
void LL_RTC_TIME_DisableDayLightStore(
RTC_TypeDef *RTCx)
1623 CLEAR_BIT(RTCx->
CR, RTC_CR_BKP);
1632__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(
RTC_TypeDef *RTCx)
1634 return ((READ_BIT(RTCx->
CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1UL : 0UL);
1644__STATIC_INLINE
void LL_RTC_TIME_DecHour(
RTC_TypeDef *RTCx)
1646 SET_BIT(RTCx->
CR, RTC_CR_SUB1H);
1656__STATIC_INLINE
void LL_RTC_TIME_IncHour(
RTC_TypeDef *RTCx)
1658 SET_BIT(RTCx->
CR, RTC_CR_ADD1H);
1674__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(
RTC_TypeDef *RTCx)
1676 return (uint32_t)(READ_BIT(RTCx->
SSR, RTC_SSR_SS));
1693__STATIC_INLINE
void LL_RTC_TIME_Synchronize(
RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
1695 WRITE_REG(RTCx->
SHIFTR, ShiftSecond | Fraction);
1716__STATIC_INLINE
void LL_RTC_DATE_SetYear(
RTC_TypeDef *RTCx, uint32_t Year)
1718 MODIFY_REG(RTCx->
DR, (RTC_DR_YT | RTC_DR_YU),
1719 (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)));
1732__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(
RTC_TypeDef *RTCx)
1734 return (uint32_t)((READ_BIT(RTCx->
DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos);
1751__STATIC_INLINE
void LL_RTC_DATE_SetWeekDay(
RTC_TypeDef *RTCx, uint32_t WeekDay)
1753 MODIFY_REG(RTCx->
DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos);
1771__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(
RTC_TypeDef *RTCx)
1773 return (uint32_t)(READ_BIT(RTCx->
DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos);
1797__STATIC_INLINE
void LL_RTC_DATE_SetMonth(
RTC_TypeDef *RTCx, uint32_t Month)
1799 MODIFY_REG(RTCx->
DR, (RTC_DR_MT | RTC_DR_MU),
1800 (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)));
1825__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(
RTC_TypeDef *RTCx)
1827 return (uint32_t)((READ_BIT(RTCx->
DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos);
1839__STATIC_INLINE
void LL_RTC_DATE_SetDay(
RTC_TypeDef *RTCx, uint32_t Day)
1841 MODIFY_REG(RTCx->
DR, (RTC_DR_DT | RTC_DR_DU),
1842 (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)));
1855__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(
RTC_TypeDef *RTCx)
1857 return (uint32_t)((READ_BIT(RTCx->
DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos);
1895__STATIC_INLINE
void LL_RTC_DATE_Config(
RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
1899 temp = (WeekDay << RTC_DR_WDU_Pos) | \
1900 (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \
1901 (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
1902 (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
1904 MODIFY_REG(RTCx->
DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
1923__STATIC_INLINE uint32_t LL_RTC_DATE_Get(
RTC_TypeDef *RTCx)
1927 temp = READ_BIT(RTCx->
DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
1928 return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
1929 (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \
1930 (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \
1931 ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));
1950__STATIC_INLINE
void LL_RTC_ALMA_Enable(
RTC_TypeDef *RTCx)
1952 SET_BIT(RTCx->
CR, RTC_CR_ALRAE);
1962__STATIC_INLINE
void LL_RTC_ALMA_Disable(
RTC_TypeDef *RTCx)
1964 CLEAR_BIT(RTCx->
CR, RTC_CR_ALRAE);
1983__STATIC_INLINE
void LL_RTC_ALMA_SetMask(
RTC_TypeDef *RTCx, uint32_t Mask)
1985 MODIFY_REG(RTCx->
ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask);
2003__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(
RTC_TypeDef *RTCx)
2005 return (uint32_t)(READ_BIT(RTCx->
ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));
2014__STATIC_INLINE
void LL_RTC_ALMA_EnableWeekday(
RTC_TypeDef *RTCx)
2016 SET_BIT(RTCx->
ALRMAR, RTC_ALRMAR_WDSEL);
2025__STATIC_INLINE
void LL_RTC_ALMA_DisableWeekday(
RTC_TypeDef *RTCx)
2027 CLEAR_BIT(RTCx->
ALRMAR, RTC_ALRMAR_WDSEL);
2039__STATIC_INLINE
void LL_RTC_ALMA_SetDay(
RTC_TypeDef *RTCx, uint32_t Day)
2041 MODIFY_REG(RTCx->
ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
2042 (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos)));
2053__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(
RTC_TypeDef *RTCx)
2055 return (uint32_t)((READ_BIT(RTCx->
ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos);
2072__STATIC_INLINE
void LL_RTC_ALMA_SetWeekDay(
RTC_TypeDef *RTCx, uint32_t WeekDay)
2074 MODIFY_REG(RTCx->
ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos);
2090__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(
RTC_TypeDef *RTCx)
2092 return (uint32_t)(READ_BIT(RTCx->
ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos);
2104__STATIC_INLINE
void LL_RTC_ALMA_SetTimeFormat(
RTC_TypeDef *RTCx, uint32_t TimeFormat)
2106 MODIFY_REG(RTCx->
ALRMAR, RTC_ALRMAR_PM, TimeFormat);
2117__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(
RTC_TypeDef *RTCx)
2119 return (uint32_t)(READ_BIT(RTCx->
ALRMAR, RTC_ALRMAR_PM));
2131__STATIC_INLINE
void LL_RTC_ALMA_SetHour(
RTC_TypeDef *RTCx, uint32_t Hours)
2133 MODIFY_REG(RTCx->
ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
2134 (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)));
2145__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(
RTC_TypeDef *RTCx)
2147 return (uint32_t)((READ_BIT(RTCx->
ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos);
2159__STATIC_INLINE
void LL_RTC_ALMA_SetMinute(
RTC_TypeDef *RTCx, uint32_t Minutes)
2161 MODIFY_REG(RTCx->
ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
2162 (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)));
2173__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(
RTC_TypeDef *RTCx)
2175 return (uint32_t)((READ_BIT(RTCx->
ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos);
2187__STATIC_INLINE
void LL_RTC_ALMA_SetSecond(
RTC_TypeDef *RTCx, uint32_t Seconds)
2189 MODIFY_REG(RTCx->
ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
2190 (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)));
2201__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(
RTC_TypeDef *RTCx)
2203 return (uint32_t)((READ_BIT(RTCx->
ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos);
2224__STATIC_INLINE
void LL_RTC_ALMA_ConfigTime(
RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
2228 temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \
2229 (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
2230 (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
2232 MODIFY_REG(RTCx->
ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
2248__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(
RTC_TypeDef *RTCx)
2250 return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
2262__STATIC_INLINE
void LL_RTC_ALMA_SetSubSecondMask(
RTC_TypeDef *RTCx, uint32_t Mask)
2264 MODIFY_REG(RTCx->
ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos);
2273__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(
RTC_TypeDef *RTCx)
2275 return (uint32_t)(READ_BIT(RTCx->
ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos);
2285__STATIC_INLINE
void LL_RTC_ALMA_SetSubSecond(
RTC_TypeDef *RTCx, uint32_t Subsecond)
2287 MODIFY_REG(RTCx->
ALRMASSR, RTC_ALRMASSR_SS, Subsecond);
2296__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(
RTC_TypeDef *RTCx)
2298 return (uint32_t)(READ_BIT(RTCx->
ALRMASSR, RTC_ALRMASSR_SS));
2317__STATIC_INLINE
void LL_RTC_ALMB_Enable(
RTC_TypeDef *RTCx)
2319 SET_BIT(RTCx->
CR, RTC_CR_ALRBE);
2329__STATIC_INLINE
void LL_RTC_ALMB_Disable(
RTC_TypeDef *RTCx)
2331 CLEAR_BIT(RTCx->
CR, RTC_CR_ALRBE);
2350__STATIC_INLINE
void LL_RTC_ALMB_SetMask(
RTC_TypeDef *RTCx, uint32_t Mask)
2352 MODIFY_REG(RTCx->
ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask);
2370__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(
RTC_TypeDef *RTCx)
2372 return (uint32_t)(READ_BIT(RTCx->
ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));
2381__STATIC_INLINE
void LL_RTC_ALMB_EnableWeekday(
RTC_TypeDef *RTCx)
2383 SET_BIT(RTCx->
ALRMBR, RTC_ALRMBR_WDSEL);
2392__STATIC_INLINE
void LL_RTC_ALMB_DisableWeekday(
RTC_TypeDef *RTCx)
2394 CLEAR_BIT(RTCx->
ALRMBR, RTC_ALRMBR_WDSEL);
2406__STATIC_INLINE
void LL_RTC_ALMB_SetDay(
RTC_TypeDef *RTCx, uint32_t Day)
2408 MODIFY_REG(RTCx->
ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
2409 (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));
2420__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(
RTC_TypeDef *RTCx)
2422 return (uint32_t)((READ_BIT(RTCx->
ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos);
2439__STATIC_INLINE
void LL_RTC_ALMB_SetWeekDay(
RTC_TypeDef *RTCx, uint32_t WeekDay)
2441 MODIFY_REG(RTCx->
ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos);
2457__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(
RTC_TypeDef *RTCx)
2459 return (uint32_t)(READ_BIT(RTCx->
ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos);
2471__STATIC_INLINE
void LL_RTC_ALMB_SetTimeFormat(
RTC_TypeDef *RTCx, uint32_t TimeFormat)
2473 MODIFY_REG(RTCx->
ALRMBR, RTC_ALRMBR_PM, TimeFormat);
2484__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(
RTC_TypeDef *RTCx)
2486 return (uint32_t)(READ_BIT(RTCx->
ALRMBR, RTC_ALRMBR_PM));
2498__STATIC_INLINE
void LL_RTC_ALMB_SetHour(
RTC_TypeDef *RTCx, uint32_t Hours)
2500 MODIFY_REG(RTCx->
ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),
2501 (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)));
2512__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(
RTC_TypeDef *RTCx)
2514 return (uint32_t)((READ_BIT(RTCx->
ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos);
2526__STATIC_INLINE
void LL_RTC_ALMB_SetMinute(
RTC_TypeDef *RTCx, uint32_t Minutes)
2528 MODIFY_REG(RTCx->
ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),
2529 (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)));
2540__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(
RTC_TypeDef *RTCx)
2542 return (uint32_t)((READ_BIT(RTCx->
ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos);
2554__STATIC_INLINE
void LL_RTC_ALMB_SetSecond(
RTC_TypeDef *RTCx, uint32_t Seconds)
2556 MODIFY_REG(RTCx->
ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),
2557 (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)));
2568__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(
RTC_TypeDef *RTCx)
2570 return (uint32_t)((READ_BIT(RTCx->
ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos);
2591__STATIC_INLINE
void LL_RTC_ALMB_ConfigTime(
RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
2595 temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \
2596 (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
2597 (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
2599 MODIFY_REG(RTCx->
ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp);
2615__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(
RTC_TypeDef *RTCx)
2617 return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));
2629__STATIC_INLINE
void LL_RTC_ALMB_SetSubSecondMask(
RTC_TypeDef *RTCx, uint32_t Mask)
2631 MODIFY_REG(RTCx->
ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos);
2640__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(
RTC_TypeDef *RTCx)
2642 return (uint32_t)(READ_BIT(RTCx->
ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos);
2652__STATIC_INLINE
void LL_RTC_ALMB_SetSubSecond(
RTC_TypeDef *RTCx, uint32_t Subsecond)
2654 MODIFY_REG(RTCx->
ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond);
2663__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(
RTC_TypeDef *RTCx)
2665 return (uint32_t)(READ_BIT(RTCx->
ALRMBSSR, RTC_ALRMBSSR_SS));
2684__STATIC_INLINE
void LL_RTC_TS_EnableInternalEvent(
RTC_TypeDef *RTCx)
2686 SET_BIT(RTCx->
CR, RTC_CR_ITSE);
2696__STATIC_INLINE
void LL_RTC_TS_DisableInternalEvent(
RTC_TypeDef *RTCx)
2698 CLEAR_BIT(RTCx->
CR, RTC_CR_ITSE);
2708__STATIC_INLINE
void LL_RTC_TS_Enable(
RTC_TypeDef *RTCx)
2710 SET_BIT(RTCx->
CR, RTC_CR_TSE);
2720__STATIC_INLINE
void LL_RTC_TS_Disable(
RTC_TypeDef *RTCx)
2722 CLEAR_BIT(RTCx->
CR, RTC_CR_TSE);
2736__STATIC_INLINE
void LL_RTC_TS_SetActiveEdge(
RTC_TypeDef *RTCx, uint32_t Edge)
2738 MODIFY_REG(RTCx->
CR, RTC_CR_TSEDGE, Edge);
2750__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(
RTC_TypeDef *RTCx)
2752 return (uint32_t)(READ_BIT(RTCx->
CR, RTC_CR_TSEDGE));
2763__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(
RTC_TypeDef *RTCx)
2765 return (uint32_t)(READ_BIT(RTCx->
TSTR, RTC_TSTR_PM));
2776__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(
RTC_TypeDef *RTCx)
2778 return (uint32_t)(READ_BIT(RTCx->
TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos);
2789__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(
RTC_TypeDef *RTCx)
2791 return (uint32_t)(READ_BIT(RTCx->
TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos);
2802__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(
RTC_TypeDef *RTCx)
2804 return (uint32_t)(READ_BIT(RTCx->
TSTR, RTC_TSTR_ST | RTC_TSTR_SU));
2820__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(
RTC_TypeDef *RTCx)
2822 return (uint32_t)(READ_BIT(RTCx->
TSTR,
2823 RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU));
2839__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(
RTC_TypeDef *RTCx)
2841 return (uint32_t)(READ_BIT(RTCx->
TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos);
2864__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(
RTC_TypeDef *RTCx)
2866 return (uint32_t)(READ_BIT(RTCx->
TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos);
2877__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(
RTC_TypeDef *RTCx)
2879 return (uint32_t)(READ_BIT(RTCx->
TSDR, RTC_TSDR_DT | RTC_TSDR_DU));
2894__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(
RTC_TypeDef *RTCx)
2896 return (uint32_t)(READ_BIT(RTCx->
TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));
2905__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(
RTC_TypeDef *RTCx)
2907 return (uint32_t)(READ_BIT(RTCx->
TSSSR, RTC_TSSSR_SS));
2926__STATIC_INLINE
void LL_RTC_TS_EnableOnTamper(
RTC_TypeDef *RTCx)
2928 SET_BIT(RTCx->
TAMPCR, RTC_TAMPCR_TAMPTS);
2937__STATIC_INLINE
void LL_RTC_TS_DisableOnTamper(
RTC_TypeDef *RTCx)
2939 CLEAR_BIT(RTCx->
TAMPCR, RTC_TAMPCR_TAMPTS);
2949__STATIC_INLINE
void LL_RTC_TS_EnableOnTamper(
RTC_TypeDef *RTCx)
2960__STATIC_INLINE
void LL_RTC_TS_DisableOnTamper(
RTC_TypeDef *RTCx)
2989__STATIC_INLINE
void LL_RTC_TAMPER_Enable(
RTC_TypeDef *RTCx, uint32_t Tamper)
2991 SET_BIT(RTCx->
TAMPCR, Tamper);
3007__STATIC_INLINE
void LL_RTC_TAMPER_Disable(
RTC_TypeDef *RTCx, uint32_t Tamper)
3009 CLEAR_BIT(RTCx->
TAMPCR, Tamper);
3026__STATIC_INLINE
void LL_RTC_TAMPER_EnableMask(
RTC_TypeDef *RTCx, uint32_t Mask)
3028 SET_BIT(RTCx->
TAMPCR, Mask);
3044__STATIC_INLINE
void LL_RTC_TAMPER_DisableMask(
RTC_TypeDef *RTCx, uint32_t Mask)
3046 CLEAR_BIT(RTCx->
TAMPCR, Mask);
3062__STATIC_INLINE
void LL_RTC_TAMPER_EnableEraseBKP(
RTC_TypeDef *RTCx, uint32_t Tamper)
3064 CLEAR_BIT(RTCx->
TAMPCR, Tamper);
3080__STATIC_INLINE
void LL_RTC_TAMPER_DisableEraseBKP(
RTC_TypeDef *RTCx, uint32_t Tamper)
3082 SET_BIT(RTCx->
TAMPCR, Tamper);
3091__STATIC_INLINE
void LL_RTC_TAMPER_DisablePullUp(
RTC_TypeDef *RTCx)
3093 SET_BIT(RTCx->
TAMPCR, RTC_TAMPCR_TAMPPUDIS);
3102__STATIC_INLINE
void LL_RTC_TAMPER_EnablePullUp(
RTC_TypeDef *RTCx)
3104 CLEAR_BIT(RTCx->
TAMPCR, RTC_TAMPCR_TAMPPUDIS);
3118__STATIC_INLINE
void LL_RTC_TAMPER_SetPrecharge(
RTC_TypeDef *RTCx, uint32_t Duration)
3120 MODIFY_REG(RTCx->
TAMPCR, RTC_TAMPCR_TAMPPRCH, Duration);
3133__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(
RTC_TypeDef *RTCx)
3135 return (uint32_t)(READ_BIT(RTCx->
TAMPCR, RTC_TAMPCR_TAMPPRCH));
3149__STATIC_INLINE
void LL_RTC_TAMPER_SetFilterCount(
RTC_TypeDef *RTCx, uint32_t FilterCount)
3151 MODIFY_REG(RTCx->
TAMPCR, RTC_TAMPCR_TAMPFLT, FilterCount);
3164__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(
RTC_TypeDef *RTCx)
3166 return (uint32_t)(READ_BIT(RTCx->
TAMPCR, RTC_TAMPCR_TAMPFLT));
3184__STATIC_INLINE
void LL_RTC_TAMPER_SetSamplingFreq(
RTC_TypeDef *RTCx, uint32_t SamplingFreq)
3186 MODIFY_REG(RTCx->
TAMPCR, RTC_TAMPCR_TAMPFREQ, SamplingFreq);
3203__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(
RTC_TypeDef *RTCx)
3205 return (uint32_t)(READ_BIT(RTCx->
TAMPCR, RTC_TAMPCR_TAMPFREQ));
3221__STATIC_INLINE
void LL_RTC_TAMPER_EnableActiveLevel(
RTC_TypeDef *RTCx, uint32_t Tamper)
3223 SET_BIT(RTCx->
TAMPCR, Tamper);
3239__STATIC_INLINE
void LL_RTC_TAMPER_DisableActiveLevel(
RTC_TypeDef *RTCx, uint32_t Tamper)
3241 CLEAR_BIT(RTCx->
TAMPCR, Tamper);
3259__STATIC_INLINE
void LL_RTC_TAMPER_Enable(
TAMP_TypeDef *TAMPx, uint32_t Tamper)
3261 SET_BIT(TAMPx->
CR1, Tamper);
3277__STATIC_INLINE
void LL_RTC_TAMPER_Disable(
TAMP_TypeDef *TAMPx, uint32_t Tamper)
3279 CLEAR_BIT(TAMPx->
CR1, Tamper);
3296__STATIC_INLINE
void LL_RTC_TAMPER_EnableMask(
TAMP_TypeDef *TAMPx, uint32_t Mask)
3298 SET_BIT(TAMPx->
CR2, Mask);
3314__STATIC_INLINE
void LL_RTC_TAMPER_DisableMask(
TAMP_TypeDef *TAMPx, uint32_t Mask)
3316 CLEAR_BIT(TAMPx->
CR2, Mask);
3332__STATIC_INLINE
void LL_RTC_TAMPER_EnableEraseBKP(
TAMP_TypeDef *TAMPx, uint32_t Tamper)
3334 CLEAR_BIT(TAMPx->
CR2, Tamper);
3350__STATIC_INLINE
void LL_RTC_TAMPER_DisableEraseBKP(
TAMP_TypeDef *TAMPx, uint32_t Tamper)
3352 SET_BIT(TAMPx->
CR2, Tamper);
3368__STATIC_INLINE
void LL_RTC_TAMPER_EnableActiveLevel(
TAMP_TypeDef *TAMPx, uint32_t Tamper)
3370 SET_BIT(TAMPx->
CR2, Tamper);
3386__STATIC_INLINE
void LL_RTC_TAMPER_DisableActiveLevel(
TAMP_TypeDef *TAMPx, uint32_t Tamper)
3388 CLEAR_BIT(TAMPx->
CR2, Tamper);
3397__STATIC_INLINE
void LL_RTC_TAMPER_DisablePullUp(
TAMP_TypeDef *TAMPx)
3399 SET_BIT(TAMPx->
FLTCR, TAMP_FLTCR_TAMPPUDIS);
3408__STATIC_INLINE
void LL_RTC_TAMPER_EnablePullUp(
TAMP_TypeDef *TAMPx)
3410 CLEAR_BIT(TAMPx->
FLTCR, TAMP_FLTCR_TAMPPUDIS);
3424__STATIC_INLINE
void LL_RTC_TAMPER_SetPrecharge(
TAMP_TypeDef *TAMPx, uint32_t Duration)
3426 MODIFY_REG(TAMPx->
FLTCR, TAMP_FLTCR_TAMPPRCH, Duration);
3439__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(
TAMP_TypeDef *TAMPx)
3441 return (uint32_t)(READ_BIT(TAMPx->
FLTCR, TAMP_FLTCR_TAMPPRCH));
3455__STATIC_INLINE
void LL_RTC_TAMPER_SetFilterCount(
TAMP_TypeDef *TAMPx, uint32_t FilterCount)
3457 MODIFY_REG(TAMPx->
FLTCR, TAMP_FLTCR_TAMPFLT, FilterCount);
3470__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(
TAMP_TypeDef *TAMPx)
3472 return (uint32_t)(READ_BIT(TAMPx->
FLTCR, TAMP_FLTCR_TAMPFLT));
3490__STATIC_INLINE
void LL_RTC_TAMPER_SetSamplingFreq(
TAMP_TypeDef *TAMPx, uint32_t SamplingFreq)
3492 MODIFY_REG(TAMPx->
FLTCR, TAMP_FLTCR_TAMPFREQ, SamplingFreq);
3509__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(
TAMP_TypeDef *TAMPx)
3511 return (uint32_t)(READ_BIT(TAMPx->
FLTCR, TAMP_FLTCR_TAMPFREQ));
3531__STATIC_INLINE
void LL_RTC_WAKEUP_Enable(
RTC_TypeDef *RTCx)
3533 SET_BIT(RTCx->
CR, RTC_CR_WUTE);
3543__STATIC_INLINE
void LL_RTC_WAKEUP_Disable(
RTC_TypeDef *RTCx)
3545 CLEAR_BIT(RTCx->
CR, RTC_CR_WUTE);
3554__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(
RTC_TypeDef *RTCx)
3556 return ((READ_BIT(RTCx->
CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1UL : 0UL);
3574__STATIC_INLINE
void LL_RTC_WAKEUP_SetClock(
RTC_TypeDef *RTCx, uint32_t WakeupClock)
3576 MODIFY_REG(RTCx->
CR, RTC_CR_WUCKSEL, WakeupClock);
3591__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(
RTC_TypeDef *RTCx)
3593 return (uint32_t)(READ_BIT(RTCx->
CR, RTC_CR_WUCKSEL));
3604__STATIC_INLINE
void LL_RTC_WAKEUP_SetAutoReload(
RTC_TypeDef *RTCx, uint32_t Value)
3606 MODIFY_REG(RTCx->
WUTR, RTC_WUTR_WUT, Value);
3615__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(
RTC_TypeDef *RTCx)
3617 return (uint32_t)(READ_BIT(RTCx->
WUTR, RTC_WUTR_WUT));
3671__STATIC_INLINE
void LL_RTC_BAK_SetRegister(
RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
3675 tmp = (uint32_t)(&(RTCx->
BKP0R));
3676 tmp += (BackupRegister * 4U);
3679 *(
__IO uint32_t *)tmp = (uint32_t)Data;
3721__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(
RTC_TypeDef *RTCx, uint32_t BackupRegister)
3725 tmp = (uint32_t)(&(RTCx->
BKP0R));
3726 tmp += (BackupRegister * 4U);
3729 return (*(
__IO uint32_t *)tmp);
3772__STATIC_INLINE
void LL_RTC_BKP_SetRegister(
TAMP_TypeDef *TAMPx, uint32_t BackupRegister, uint32_t Data)
3776 tmp = (uint32_t)(&(TAMPx->
BKP0R));
3777 tmp += (BackupRegister * 4U);
3780 *(
__IO uint32_t *)tmp = (uint32_t)Data;
3822__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(
TAMP_TypeDef *TAMPx, uint32_t BackupRegister)
3826 tmp = (uint32_t)(&(TAMPx->
BKP0R));
3827 tmp += (BackupRegister * 4U);
3830 return (*(
__IO uint32_t *)tmp);
3856__STATIC_INLINE
void LL_RTC_CAL_SetOutputFreq(
RTC_TypeDef *RTCx, uint32_t Frequency)
3858 MODIFY_REG(RTCx->
CR, RTC_CR_COE | RTC_CR_COSEL, Frequency);
3871__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(
RTC_TypeDef *RTCx)
3873 return (uint32_t)(READ_BIT(RTCx->
CR, RTC_CR_COE | RTC_CR_COSEL));
3887__STATIC_INLINE
void LL_RTC_CAL_SetPulse(
RTC_TypeDef *RTCx, uint32_t Pulse)
3889 MODIFY_REG(RTCx->
CALR, RTC_CALR_CALP, Pulse);
3898__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(
RTC_TypeDef *RTCx)
3900 return ((READ_BIT(RTCx->
CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1UL : 0UL);
3916__STATIC_INLINE
void LL_RTC_CAL_SetPeriod(
RTC_TypeDef *RTCx, uint32_t Period)
3918 MODIFY_REG(RTCx->
CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period);
3931__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(
RTC_TypeDef *RTCx)
3933 return (uint32_t)(READ_BIT(RTCx->
CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16));
3945__STATIC_INLINE
void LL_RTC_CAL_SetMinus(
RTC_TypeDef *RTCx, uint32_t CalibMinus)
3947 MODIFY_REG(RTCx->
CALR, RTC_CALR_CALM, CalibMinus);
3956__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(
RTC_TypeDef *RTCx)
3958 return (uint32_t)(READ_BIT(RTCx->
CALR, RTC_CALR_CALM));
3978__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(
RTC_TypeDef *RTCx)
3980 return ((READ_BIT(RTCx->
ISR, RTC_ISR_ITSF) == (RTC_ISR_ITSF)) ? 1UL : 0UL);
3989__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(
RTC_TypeDef *RTCx)
3991 return ((READ_BIT(RTCx->
ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF)) ? 1UL : 0UL);
4000__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(
RTC_TypeDef *RTCx)
4002 return ((READ_BIT(RTCx->
ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F)) ? 1UL : 0UL);
4011__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(
RTC_TypeDef *RTCx)
4013 return ((READ_BIT(RTCx->
ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F)) ? 1UL : 0UL);
4022__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(
RTC_TypeDef *RTCx)
4024 return ((READ_BIT(RTCx->
ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F)) ? 1UL : 0UL);
4033__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(
RTC_TypeDef *RTCx)
4035 return ((READ_BIT(RTCx->
ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF)) ? 1UL : 0UL);
4044__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(
RTC_TypeDef *RTCx)
4046 return ((READ_BIT(RTCx->
ISR, RTC_ISR_TSF) == (RTC_ISR_TSF)) ? 1UL : 0UL);
4055__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(
RTC_TypeDef *RTCx)
4057 return ((READ_BIT(RTCx->
ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF)) ? 1UL : 0UL);
4066__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(
RTC_TypeDef *RTCx)
4068 return ((READ_BIT(RTCx->
ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF)) ? 1UL : 0UL);
4077__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(
RTC_TypeDef *RTCx)
4079 return ((READ_BIT(RTCx->
ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF)) ? 1UL : 0UL);
4088__STATIC_INLINE
void LL_RTC_ClearFlag_ITS(
RTC_TypeDef *RTCx)
4090 WRITE_REG(RTCx->
ISR, (~((RTC_ISR_ITSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->
ISR & RTC_ISR_INIT)));
4099__STATIC_INLINE
void LL_RTC_ClearFlag_TAMP3(
RTC_TypeDef *RTCx)
4101 WRITE_REG(RTCx->
ISR, (~((RTC_ISR_TAMP3F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->
ISR & RTC_ISR_INIT)));
4110__STATIC_INLINE
void LL_RTC_ClearFlag_TAMP2(
RTC_TypeDef *RTCx)
4112 WRITE_REG(RTCx->
ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->
ISR & RTC_ISR_INIT)));
4121__STATIC_INLINE
void LL_RTC_ClearFlag_TAMP1(
RTC_TypeDef *RTCx)
4123 WRITE_REG(RTCx->
ISR, (~((RTC_ISR_TAMP1F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->
ISR & RTC_ISR_INIT)));
4132__STATIC_INLINE
void LL_RTC_ClearFlag_TSOV(
RTC_TypeDef *RTCx)
4134 WRITE_REG(RTCx->
ISR, (~((RTC_ISR_TSOVF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->
ISR & RTC_ISR_INIT)));
4143__STATIC_INLINE
void LL_RTC_ClearFlag_TS(
RTC_TypeDef *RTCx)
4145 WRITE_REG(RTCx->
ISR, (~((RTC_ISR_TSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->
ISR & RTC_ISR_INIT)));
4154__STATIC_INLINE
void LL_RTC_ClearFlag_WUT(
RTC_TypeDef *RTCx)
4156 WRITE_REG(RTCx->
ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->
ISR & RTC_ISR_INIT)));
4165__STATIC_INLINE
void LL_RTC_ClearFlag_ALRB(
RTC_TypeDef *RTCx)
4167 WRITE_REG(RTCx->
ISR, (~((RTC_ISR_ALRBF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->
ISR & RTC_ISR_INIT)));
4176__STATIC_INLINE
void LL_RTC_ClearFlag_ALRA(
RTC_TypeDef *RTCx)
4178 WRITE_REG(RTCx->
ISR, (~((RTC_ISR_ALRAF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->
ISR & RTC_ISR_INIT)));
4187__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(
RTC_TypeDef *RTCx)
4189 return ((READ_BIT(RTCx->
ISR, RTC_ISR_INITF) == (RTC_ISR_INITF)) ? 1UL : 0UL);
4198__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(
RTC_TypeDef *RTCx)
4200 return ((READ_BIT(RTCx->
ISR, RTC_ISR_RSF) == (RTC_ISR_RSF)) ? 1UL : 0UL);
4209__STATIC_INLINE
void LL_RTC_ClearFlag_RS(
RTC_TypeDef *RTCx)
4211 WRITE_REG(RTCx->
ISR, (~((RTC_ISR_RSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->
ISR & RTC_ISR_INIT)));
4220__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(
RTC_TypeDef *RTCx)
4222 return ((READ_BIT(RTCx->
ISR, RTC_ISR_INITS) == (RTC_ISR_INITS)) ? 1UL : 0UL);
4231__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(
RTC_TypeDef *RTCx)
4233 return ((READ_BIT(RTCx->
ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF)) ? 1UL : 0UL);
4242__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(
RTC_TypeDef *RTCx)
4244 return ((READ_BIT(RTCx->
ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF)) ? 1UL : 0UL);
4253__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(
RTC_TypeDef *RTCx)
4255 return ((READ_BIT(RTCx->
ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF)) ? 1UL : 0UL);
4264__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(
RTC_TypeDef *RTCx)
4266 return ((READ_BIT(RTCx->
ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)) ? 1UL : 0UL);
4277__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(
RTC_TypeDef *RTCx)
4279 return ((READ_BIT(RTCx->
SR, RTC_SR_ITSF) == (RTC_SR_ITSF)) ? 1UL : 0UL);
4288__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(
RTC_TypeDef *RTCx)
4290 return ((READ_BIT(RTCx->
SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)) ? 1UL : 0UL);
4299__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(
RTC_TypeDef *RTCx)
4301 return ((READ_BIT(RTCx->
SR, RTC_SR_TSF) == (RTC_SR_TSF)) ? 1UL : 0UL);
4310__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(
RTC_TypeDef *RTCx)
4312 return ((READ_BIT(RTCx->
SR, RTC_SR_WUTF) == (RTC_SR_WUTF)) ? 1UL : 0UL);
4321__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(
RTC_TypeDef *RTCx)
4323 return ((READ_BIT(RTCx->
SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)) ? 1UL : 0UL);
4332__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(
RTC_TypeDef *RTCx)
4334 return ((READ_BIT(RTCx->
SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1UL : 0UL);
4343__STATIC_INLINE
void LL_RTC_ClearFlag_ITS(
RTC_TypeDef *RTCx)
4345 SET_BIT(RTCx->
SCR, RTC_SCR_CITSF);
4354__STATIC_INLINE
void LL_RTC_ClearFlag_TSOV(
RTC_TypeDef *RTCx)
4356 SET_BIT(RTCx->
SCR, RTC_SCR_CTSOVF);
4365__STATIC_INLINE
void LL_RTC_ClearFlag_TS(
RTC_TypeDef *RTCx)
4367 SET_BIT(RTCx->
SCR, RTC_SCR_CTSF);
4376__STATIC_INLINE
void LL_RTC_ClearFlag_WUT(
RTC_TypeDef *RTCx)
4378 SET_BIT(RTCx->
SCR, RTC_SCR_CWUTF);
4387__STATIC_INLINE
void LL_RTC_ClearFlag_ALRB(
RTC_TypeDef *RTCx)
4389 SET_BIT(RTCx->
SCR, RTC_SCR_CALRBF);
4398__STATIC_INLINE
void LL_RTC_ClearFlag_ALRA(
RTC_TypeDef *RTCx)
4400 SET_BIT(RTCx->
SCR, RTC_SCR_CALRAF);
4409__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(
RTC_TypeDef *RTCx)
4411 return ((READ_BIT(RTCx->
ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)) ? 1UL : 0UL);
4420__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(
RTC_TypeDef *RTCx)
4422 return ((READ_BIT(RTCx->
ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)) ? 1UL : 0UL);
4431__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(
RTC_TypeDef *RTCx)
4433 return ((READ_BIT(RTCx->
ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)) ? 1UL : 0UL);
4442__STATIC_INLINE
void LL_RTC_ClearFlag_RS(
RTC_TypeDef *RTCx)
4444 WRITE_REG(RTCx->
ICSR, (~((RTC_ICSR_RSF | RTC_ICSR_INIT) & 0x000000FFU) | (RTCx->
ICSR & RTC_ICSR_INIT)));
4453__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(
RTC_TypeDef *RTCx)
4455 return ((READ_BIT(RTCx->
ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)) ? 1UL : 0UL);
4464__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(
RTC_TypeDef *RTCx)
4466 return ((READ_BIT(RTCx->
ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)) ? 1UL : 0UL);
4475__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(
RTC_TypeDef *RTCx)
4477 return ((READ_BIT(RTCx->
ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)) ? 1UL : 0UL);
4486__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(
RTC_TypeDef *RTCx)
4488 return ((READ_BIT(RTCx->
ICSR, RTC_ICSR_ALRBWF) == (RTC_ICSR_ALRBWF)) ? 1UL : 0UL);
4497__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(
RTC_TypeDef *RTCx)
4499 return ((READ_BIT(RTCx->
ICSR, RTC_ICSR_ALRAWF) == (RTC_ICSR_ALRAWF)) ? 1UL : 0UL);
4508__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(
RTC_TypeDef *RTCx)
4510 return ((READ_BIT(RTCx->
MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)) ? 1UL : 0UL);
4519__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(
RTC_TypeDef *RTCx)
4521 return ((READ_BIT(RTCx->
MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)) ? 1UL : 0UL);
4530__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(
RTC_TypeDef *RTCx)
4532 return ((READ_BIT(RTCx->
MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)) ? 1UL : 0UL);
4541__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(
RTC_TypeDef *RTCx)
4543 return ((READ_BIT(RTCx->
MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)) ? 1UL : 0UL);
4552__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(
RTC_TypeDef *RTCx)
4554 return ((READ_BIT(RTCx->
MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)) ? 1UL : 0UL);
4563__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(
RTC_TypeDef *RTCx)
4565 return ((READ_BIT(RTCx->
MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)) ? 1UL : 0UL);
4574__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(
TAMP_TypeDef *TAMPx)
4576 return ((READ_BIT(TAMPx->
SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)) ? 1UL : 0UL);
4585__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(
TAMP_TypeDef *TAMPx)
4587 return ((READ_BIT(TAMPx->
SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)) ? 1UL : 0UL);
4596__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(
TAMP_TypeDef *TAMPx)
4598 return ((READ_BIT(TAMPx->
SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1UL : 0UL);
4607__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(
TAMP_TypeDef *TAMPx)
4609 return ((READ_BIT(TAMPx->
MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)) ? 1UL : 0UL);
4618__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(
TAMP_TypeDef *TAMPx)
4620 return ((READ_BIT(TAMPx->
MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)) ? 1UL : 0UL);
4629__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(
TAMP_TypeDef *TAMPx)
4631 return ((READ_BIT(TAMPx->
MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1UL : 0UL);
4640__STATIC_INLINE
void LL_RTC_ClearFlag_TAMP1(
TAMP_TypeDef *TAMPx)
4642 SET_BIT(TAMPx->
SCR, TAMP_SCR_CTAMP1F);
4651__STATIC_INLINE
void LL_RTC_ClearFlag_TAMP2(
TAMP_TypeDef *TAMPx)
4653 SET_BIT(TAMPx->
SCR, TAMP_SCR_CTAMP2F);
4662__STATIC_INLINE
void LL_RTC_ClearFlag_TAMP3(
TAMP_TypeDef *TAMPx)
4664 SET_BIT(TAMPx->
SCR, TAMP_SCR_CTAMP3F);
4684__STATIC_INLINE
void LL_RTC_EnableIT_TS(
RTC_TypeDef *RTCx)
4686 SET_BIT(RTCx->
CR, RTC_CR_TSIE);
4696__STATIC_INLINE
void LL_RTC_DisableIT_TS(
RTC_TypeDef *RTCx)
4698 CLEAR_BIT(RTCx->
CR, RTC_CR_TSIE);
4708__STATIC_INLINE
void LL_RTC_EnableIT_WUT(
RTC_TypeDef *RTCx)
4710 SET_BIT(RTCx->
CR, RTC_CR_WUTIE);
4720__STATIC_INLINE
void LL_RTC_DisableIT_WUT(
RTC_TypeDef *RTCx)
4722 CLEAR_BIT(RTCx->
CR, RTC_CR_WUTIE);
4732__STATIC_INLINE
void LL_RTC_EnableIT_ALRB(
RTC_TypeDef *RTCx)
4734 SET_BIT(RTCx->
CR, RTC_CR_ALRBIE);
4744__STATIC_INLINE
void LL_RTC_DisableIT_ALRB(
RTC_TypeDef *RTCx)
4746 CLEAR_BIT(RTCx->
CR, RTC_CR_ALRBIE);
4756__STATIC_INLINE
void LL_RTC_EnableIT_ALRA(
RTC_TypeDef *RTCx)
4758 SET_BIT(RTCx->
CR, RTC_CR_ALRAIE);
4768__STATIC_INLINE
void LL_RTC_DisableIT_ALRA(
RTC_TypeDef *RTCx)
4770 CLEAR_BIT(RTCx->
CR, RTC_CR_ALRAIE);
4780__STATIC_INLINE
void LL_RTC_EnableIT_TAMP3(
RTC_TypeDef *RTCx)
4782 SET_BIT(RTCx->
TAMPCR, RTC_TAMPCR_TAMP3IE);
4791__STATIC_INLINE
void LL_RTC_DisableIT_TAMP3(
RTC_TypeDef *RTCx)
4793 CLEAR_BIT(RTCx->
TAMPCR, RTC_TAMPCR_TAMP3IE);
4802__STATIC_INLINE
void LL_RTC_EnableIT_TAMP2(
RTC_TypeDef *RTCx)
4804 SET_BIT(RTCx->
TAMPCR, RTC_TAMPCR_TAMP2IE);
4813__STATIC_INLINE
void LL_RTC_DisableIT_TAMP2(
RTC_TypeDef *RTCx)
4815 CLEAR_BIT(RTCx->
TAMPCR, RTC_TAMPCR_TAMP2IE);
4824__STATIC_INLINE
void LL_RTC_EnableIT_TAMP1(
RTC_TypeDef *RTCx)
4826 SET_BIT(RTCx->
TAMPCR, RTC_TAMPCR_TAMP1IE);
4835__STATIC_INLINE
void LL_RTC_DisableIT_TAMP1(
RTC_TypeDef *RTCx)
4837 CLEAR_BIT(RTCx->
TAMPCR, RTC_TAMPCR_TAMP1IE);
4846__STATIC_INLINE
void LL_RTC_EnableIT_TAMP(
RTC_TypeDef *RTCx)
4848 SET_BIT(RTCx->
TAMPCR, RTC_TAMPCR_TAMPIE);
4857__STATIC_INLINE
void LL_RTC_DisableIT_TAMP(
RTC_TypeDef *RTCx)
4859 CLEAR_BIT(RTCx->
TAMPCR, RTC_TAMPCR_TAMPIE);
4869__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(
RTC_TypeDef *RTCx)
4871 return ((READ_BIT(RTCx->
CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1UL : 0UL);
4880__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(
RTC_TypeDef *RTCx)
4882 return ((READ_BIT(RTCx->
CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1UL : 0UL);
4891__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(
RTC_TypeDef *RTCx)
4893 return ((READ_BIT(RTCx->
CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1UL : 0UL);
4902__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(
RTC_TypeDef *RTCx)
4904 return ((READ_BIT(RTCx->
CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL);
4914__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(
RTC_TypeDef *RTCx)
4916 return ((READ_BIT(RTCx->
TAMPCR, RTC_TAMPCR_TAMP3IE) == (RTC_TAMPCR_TAMP3IE)) ? 1UL : 0UL);
4925__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(
RTC_TypeDef *RTCx)
4927 return ((READ_BIT(RTCx->
TAMPCR, RTC_TAMPCR_TAMP2IE) == (RTC_TAMPCR_TAMP2IE)) ? 1UL : 0UL);
4937__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(
RTC_TypeDef *RTCx)
4939 return ((READ_BIT(RTCx->
TAMPCR, RTC_TAMPCR_TAMP1IE) == (RTC_TAMPCR_TAMP1IE)) ? 1UL : 0UL);
4948__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(
RTC_TypeDef *RTCx)
4950 return ((READ_BIT(RTCx->
TAMPCR, RTC_TAMPCR_TAMPIE) == (RTC_TAMPCR_TAMPIE)) ? 1UL : 0UL);
4961__STATIC_INLINE
void LL_RTC_EnableIT_TAMP1(
TAMP_TypeDef *TAMPx)
4963 SET_BIT(TAMPx->
IER, TAMP_IER_TAMP1IE);
4972__STATIC_INLINE
void LL_RTC_DisableIT_TAMP1(
TAMP_TypeDef *TAMPx)
4974 CLEAR_BIT(TAMPx->
IER, TAMP_IER_TAMP1IE);
4983__STATIC_INLINE
void LL_RTC_EnableIT_TAMP2(
TAMP_TypeDef *TAMPx)
4985 SET_BIT(TAMPx->
IER, TAMP_IER_TAMP2IE);
4994__STATIC_INLINE
void LL_RTC_DisableIT_TAMP2(
TAMP_TypeDef *TAMPx)
4996 CLEAR_BIT(TAMPx->
IER, TAMP_IER_TAMP2IE);
5005__STATIC_INLINE
void LL_RTC_EnableIT_TAMP3(
TAMP_TypeDef *TAMPx)
5007 SET_BIT(TAMPx->
IER, TAMP_IER_TAMP3IE);
5016__STATIC_INLINE
void LL_RTC_DisableIT_TAMP3(
TAMP_TypeDef *TAMPx)
5018 CLEAR_BIT(TAMPx->
IER, TAMP_IER_TAMP3IE);
5027__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(
TAMP_TypeDef *TAMPx)
5029 return ((READ_BIT(TAMPx->
IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)) ? 1UL : 0UL);
5038__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(
TAMP_TypeDef *TAMPx)
5040 return ((READ_BIT(TAMPx->
IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)) ? 1UL : 0UL);
5049__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(
TAMP_TypeDef *TAMPx)
5051 return ((READ_BIT(TAMPx->
IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1UL : 0UL);
5072__STATIC_INLINE
void LL_RTC_TAMPER_ATAMP_EnableActiveMode(uint32_t Tamper)
5074 SET_BIT(TAMP->ATCR1, Tamper);
5087__STATIC_INLINE
void LL_RTC_TAMPER_ATAMP_DisableActiveMode(uint32_t Tamper)
5089 CLEAR_BIT(TAMP->ATCR1, Tamper);
5097__STATIC_INLINE
void LL_RTC_TAMPER_ATAMP_EnableFilter(
void)
5099 SET_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN);
5107__STATIC_INLINE
void LL_RTC_TAMPER_ATAMP_DisableFilter(
void)
5109 CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN);
5118__STATIC_INLINE
void LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod(uint32_t ActiveOutputChangePeriod)
5120 MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATPER, (ActiveOutputChangePeriod << TAMP_ATCR1_ATPER_Pos));
5128__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod(
void)
5130 return (READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATPER) >> TAMP_ATCR1_ATPER_Pos);
5141__STATIC_INLINE
void LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler(uint32_t ActiveAsynvPrescaler)
5143 MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL, ActiveAsynvPrescaler);
5151__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler(
void)
5153 return (READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL));
5161__STATIC_INLINE
void LL_RTC_TAMPER_ATAMP_EnableOutputSharing(
void)
5163 SET_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE);
5171__STATIC_INLINE
void LL_RTC_TAMPER_ATAMP_DisableOutputSharing(
void)
5173 CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE);
5184__STATIC_INLINE
void LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection(uint32_t OutputSelection)
5186 MODIFY_REG(TAMP->ATCR1, (TAMP_ATCR1_ATOSEL1 | TAMP_ATCR1_ATOSEL2 | TAMP_ATCR1_ATOSEL3), \
5195__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetSharedOuputSelection(
void)
5197 return (READ_BIT(TAMP->ATCR1, (TAMP_ATCR1_ATOSEL1 | TAMP_ATCR1_ATOSEL2 | TAMP_ATCR1_ATOSEL3)));
5206__STATIC_INLINE
void LL_RTC_TAMPER_ATAMP_WriteSeed(uint32_t Seed)
5208 WRITE_REG(TAMP->ATSEEDR, Seed);
5216__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_INITS(
void)
5218 return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) == (TAMP_ATOR_INITS)) ? 1U : 0U);
5226__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_SEEDF(
void)
5228 return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) == (TAMP_ATOR_SEEDF)) ? 1U : 0U);
5237#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
5244ErrorStatus LL_RTC_Init(
RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
5245void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
5246ErrorStatus LL_RTC_TIME_Init(
RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
5247void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
5248ErrorStatus LL_RTC_DATE_Init(
RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct);
5249void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);
5250ErrorStatus LL_RTC_ALMA_Init(
RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
5251ErrorStatus LL_RTC_ALMB_Init(
RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
5252void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
5253void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
5254ErrorStatus LL_RTC_EnterInitMode(
RTC_TypeDef *RTCx);
5255ErrorStatus LL_RTC_ExitInitMode(
RTC_TypeDef *RTCx);
5256ErrorStatus LL_RTC_WaitForSynchro(
RTC_TypeDef *RTCx);
#define __IO
Definition: core_cm4.h:239
#define RTC_CR_OUT2EN
Definition: stm32h7a3xx.h:14660
#define RTC_CR_TAMPOE
Definition: stm32h7a3xx.h:14669
#define RTC_CR_TAMPALRM_PU
Definition: stm32h7a3xx.h:14666
#define RTC_CR_TAMPALRM_TYPE
Definition: stm32h7a3xx.h:14663
#define RTC_CR_TAMPTS
Definition: stm32h7a3xx.h:14672
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
Real-Time Clock.
Definition: stm32h723xx.h:1307
__IO uint32_t SCR
Definition: stm32h7a3xx.h:1176
__IO uint32_t TSTR
Definition: stm32h723xx.h:1320
__IO uint32_t TSSSR
Definition: stm32h723xx.h:1322
__IO uint32_t ALRMBSSR
Definition: stm32h723xx.h:1326
__IO uint32_t TR
Definition: stm32h723xx.h:1308
__IO uint32_t SR
Definition: stm32h7a3xx.h:1173
__IO uint32_t ISR
Definition: stm32h723xx.h:1311
__IO uint32_t PRER
Definition: stm32h723xx.h:1312
__IO uint32_t SHIFTR
Definition: stm32h723xx.h:1319
__IO uint32_t CR
Definition: stm32h723xx.h:1310
__IO uint32_t DR
Definition: stm32h723xx.h:1309
__IO uint32_t MISR
Definition: stm32h7a3xx.h:1174
__IO uint32_t ALRMBR
Definition: stm32h723xx.h:1316
__IO uint32_t TSDR
Definition: stm32h723xx.h:1321
__IO uint32_t BKP0R
Definition: stm32h723xx.h:1328
__IO uint32_t TAMPCR
Definition: stm32h723xx.h:1324
__IO uint32_t OR
Definition: stm32h723xx.h:1327
__IO uint32_t ALRMASSR
Definition: stm32h723xx.h:1325
__IO uint32_t WPR
Definition: stm32h723xx.h:1317
__IO uint32_t ALRMAR
Definition: stm32h723xx.h:1315
__IO uint32_t WUTR
Definition: stm32h723xx.h:1313
__IO uint32_t CALR
Definition: stm32h723xx.h:1323
__IO uint32_t SSR
Definition: stm32h723xx.h:1318
__IO uint32_t ICSR
Definition: stm32h7a3xx.h:1156
Tamper and backup registers.
Definition: stm32h7a3xx.h:1184
__IO uint32_t MISR
Definition: stm32h7a3xx.h:1195
__IO uint32_t SR
Definition: stm32h7a3xx.h:1194
__IO uint32_t FLTCR
Definition: stm32h7a3xx.h:1188
__IO uint32_t SCR
Definition: stm32h7a3xx.h:1197
__IO uint32_t IER
Definition: stm32h7a3xx.h:1193
__IO uint32_t CR2
Definition: stm32h7a3xx.h:1186
__IO uint32_t CR1
Definition: stm32h7a3xx.h:1185
__IO uint32_t BKP0R
Definition: stm32h7a3xx.h:1202