html/doxygen/stm32h7xx__ll__rcc_8h_source.html

/* Define to prevent recursive inclusion -------------------------------------*/

#ifndef STM32H7xx_LL_RCC_H

#define STM32H7xx_LL_RCC_H


#ifdef __cplusplus

extern "C" {

#endif


/* Includes ------------------------------------------------------------------*/

#include "stm32h7xx.h"

#include <math.h>


#if defined(RCC)


/* Private types -------------------------------------------------------------*/

/* Private variables ---------------------------------------------------------*/

extern const uint8_t LL_RCC_PrescTable[16];


/* Private constants ---------------------------------------------------------*/

/* Private macros ------------------------------------------------------------*/

#if !defined(UNUSED)

#define UNUSED(x) ((void)(x))

#endif


/* 32            24           16            8             0

   --------------------------------------------------------

   | Mask        | ClkSource   |  Bit       | Register    |

   |             |  Config     | Position   | Offset      |

   --------------------------------------------------------*/


#if defined(RCC_VER_2_0)

/* Clock source register offset Vs CDCCIPR register */

#define CDCCIP    0x0UL

#define CDCCIP1   0x4UL

#define CDCCIP2   0x8UL

#define SRDCCIP   0xCUL

#else

/* Clock source register offset Vs D1CCIPR register */

#define D1CCIP    0x0UL

#define D2CCIP1   0x4UL

#define D2CCIP2   0x8UL

#define D3CCIP    0xCUL

#endif /* RCC_VER_2_0 */


#define LL_RCC_REG_SHIFT     0U

#define LL_RCC_POS_SHIFT     8U

#define LL_RCC_CONFIG_SHIFT  16U

#define LL_RCC_MASK_SHIFT    24U


#define LL_CLKSOURCE_SHIFT(__CLKSOURCE__)   (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT   ) & 0x1FUL)


#define LL_CLKSOURCE_MASK(__CLKSOURCE__)   ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT  ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))


#define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))


#define LL_CLKSOURCE_REG(__CLKSOURCE__)     (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT   ) & 0xFFUL)


#define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \

                                                                     (( __POS__              ) << LL_RCC_POS_SHIFT)  | \

                                                                     (( __REG__              ) << LL_RCC_REG_SHIFT)  | \

                                                                     (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT)))

/* Exported types ------------------------------------------------------------*/

#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)

typedef struct

{

  uint32_t SYSCLK_Frequency;

  uint32_t CPUCLK_Frequency;

  uint32_t HCLK_Frequency;

  uint32_t PCLK1_Frequency;

  uint32_t PCLK2_Frequency;

  uint32_t PCLK3_Frequency;

  uint32_t PCLK4_Frequency;

} LL_RCC_ClocksTypeDef;


typedef struct

{

  uint32_t PLL_P_Frequency;

  uint32_t PLL_Q_Frequency;

  uint32_t PLL_R_Frequency;

} LL_PLL_ClocksTypeDef;


#endif /* USE_FULL_LL_DRIVER */


/* Exported constants --------------------------------------------------------*/

#if !defined  (HSE_VALUE)

#if defined(RCC_VER_X) || defined(RCC_VER_3_0)

#define HSE_VALUE    25000000U

#else

#define HSE_VALUE    24000000U

#endif /* RCC_VER_X || RCC_VER_3_0 */

#endif /* HSE_VALUE */


#if !defined  (HSI_VALUE)

#define HSI_VALUE    64000000U

#endif /* HSI_VALUE */


#if !defined  (CSI_VALUE)

#define CSI_VALUE    4000000U

#endif /* CSI_VALUE */


#if !defined  (LSE_VALUE)

#define LSE_VALUE    32768U

#endif /* LSE_VALUE */


#if !defined  (LSI_VALUE)

#define LSI_VALUE    32000U

#endif /* LSI_VALUE */


#if !defined  (EXTERNAL_CLOCK_VALUE)

#define EXTERNAL_CLOCK_VALUE    12288000U

#endif /* EXTERNAL_CLOCK_VALUE */


#if !defined  (HSI48_VALUE)

#define HSI48_VALUE  48000000U

#endif /* HSI48_VALUE */


#define LL_RCC_HSI_DIV1                   RCC_CR_HSIDIV_1

#define LL_RCC_HSI_DIV2                   RCC_CR_HSIDIV_2

#define LL_RCC_HSI_DIV4                   RCC_CR_HSIDIV_4

#define LL_RCC_HSI_DIV8                   RCC_CR_HSIDIV_8

#define LL_RCC_LSEDRIVE_LOW                (uint32_t)(0x00000000U)

#define LL_RCC_LSEDRIVE_MEDIUMLOW          (uint32_t)(RCC_BDCR_LSEDRV_0)

#define LL_RCC_LSEDRIVE_MEDIUMHIGH         (uint32_t)(RCC_BDCR_LSEDRV_1)

#define LL_RCC_LSEDRIVE_HIGH               (uint32_t)(RCC_BDCR_LSEDRV)

#define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI

#define LL_RCC_SYS_CLKSOURCE_CSI           RCC_CFGR_SW_CSI

#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE

#define LL_RCC_SYS_CLKSOURCE_PLL1          RCC_CFGR_SW_PLL1

#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI

#define LL_RCC_SYS_CLKSOURCE_STATUS_CSI    RCC_CFGR_SWS_CSI

#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE

#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1   RCC_CFGR_SWS_PLL1

#define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI     (uint32_t)(0x00000000U)

#define LL_RCC_SYSWAKEUP_CLKSOURCE_CSI     (uint32_t)(RCC_CFGR_STOPWUCK)

#define LL_RCC_KERWAKEUP_CLKSOURCE_HSI     (uint32_t)(0x00000000U)

#define LL_RCC_KERWAKEUP_CLKSOURCE_CSI     (uint32_t)(RCC_CFGR_STOPKERWUCK)

#if defined(RCC_D1CFGR_D1CPRE_DIV1)

#define LL_RCC_SYSCLK_DIV_1                RCC_D1CFGR_D1CPRE_DIV1

#define LL_RCC_SYSCLK_DIV_2                RCC_D1CFGR_D1CPRE_DIV2

#define LL_RCC_SYSCLK_DIV_4                RCC_D1CFGR_D1CPRE_DIV4

#define LL_RCC_SYSCLK_DIV_8                RCC_D1CFGR_D1CPRE_DIV8

#define LL_RCC_SYSCLK_DIV_16               RCC_D1CFGR_D1CPRE_DIV16

#define LL_RCC_SYSCLK_DIV_64               RCC_D1CFGR_D1CPRE_DIV64

#define LL_RCC_SYSCLK_DIV_128              RCC_D1CFGR_D1CPRE_DIV128

#define LL_RCC_SYSCLK_DIV_256              RCC_D1CFGR_D1CPRE_DIV256

#define LL_RCC_SYSCLK_DIV_512              RCC_D1CFGR_D1CPRE_DIV512

#else

#define LL_RCC_SYSCLK_DIV_1                RCC_CDCFGR1_CDCPRE_DIV1

#define LL_RCC_SYSCLK_DIV_2                RCC_CDCFGR1_CDCPRE_DIV2

#define LL_RCC_SYSCLK_DIV_4                RCC_CDCFGR1_CDCPRE_DIV4

#define LL_RCC_SYSCLK_DIV_8                RCC_CDCFGR1_CDCPRE_DIV8

#define LL_RCC_SYSCLK_DIV_16               RCC_CDCFGR1_CDCPRE_DIV16

#define LL_RCC_SYSCLK_DIV_64               RCC_CDCFGR1_CDCPRE_DIV64

#define LL_RCC_SYSCLK_DIV_128              RCC_CDCFGR1_CDCPRE_DIV128

#define LL_RCC_SYSCLK_DIV_256              RCC_CDCFGR1_CDCPRE_DIV256

#define LL_RCC_SYSCLK_DIV_512              RCC_CDCFGR1_CDCPRE_DIV512

#endif /* RCC_D1CFGR_D1CPRE_DIV1 */

#if defined(RCC_D1CFGR_HPRE_DIV1)

#define LL_RCC_AHB_DIV_1                   RCC_D1CFGR_HPRE_DIV1

#define LL_RCC_AHB_DIV_2                   RCC_D1CFGR_HPRE_DIV2

#define LL_RCC_AHB_DIV_4                   RCC_D1CFGR_HPRE_DIV4

#define LL_RCC_AHB_DIV_8                   RCC_D1CFGR_HPRE_DIV8

#define LL_RCC_AHB_DIV_16                  RCC_D1CFGR_HPRE_DIV16

#define LL_RCC_AHB_DIV_64                  RCC_D1CFGR_HPRE_DIV64

#define LL_RCC_AHB_DIV_128                 RCC_D1CFGR_HPRE_DIV128

#define LL_RCC_AHB_DIV_256                 RCC_D1CFGR_HPRE_DIV256

#define LL_RCC_AHB_DIV_512                 RCC_D1CFGR_HPRE_DIV512

#else

#define LL_RCC_AHB_DIV_1                   RCC_CDCFGR1_HPRE_DIV1

#define LL_RCC_AHB_DIV_2                   RCC_CDCFGR1_HPRE_DIV2

#define LL_RCC_AHB_DIV_4                   RCC_CDCFGR1_HPRE_DIV4

#define LL_RCC_AHB_DIV_8                   RCC_CDCFGR1_HPRE_DIV8

#define LL_RCC_AHB_DIV_16                  RCC_CDCFGR1_HPRE_DIV16

#define LL_RCC_AHB_DIV_64                  RCC_CDCFGR1_HPRE_DIV64

#define LL_RCC_AHB_DIV_128                 RCC_CDCFGR1_HPRE_DIV128

#define LL_RCC_AHB_DIV_256                 RCC_CDCFGR1_HPRE_DIV256

#define LL_RCC_AHB_DIV_512                 RCC_CDCFGR1_HPRE_DIV512

#endif /* RCC_D1CFGR_HPRE_DIV1 */

#if defined(RCC_D2CFGR_D2PPRE1_DIV1)

#define LL_RCC_APB1_DIV_1                  RCC_D2CFGR_D2PPRE1_DIV1

#define LL_RCC_APB1_DIV_2                  RCC_D2CFGR_D2PPRE1_DIV2

#define LL_RCC_APB1_DIV_4                  RCC_D2CFGR_D2PPRE1_DIV4

#define LL_RCC_APB1_DIV_8                  RCC_D2CFGR_D2PPRE1_DIV8

#define LL_RCC_APB1_DIV_16                 RCC_D2CFGR_D2PPRE1_DIV16

#else

#define LL_RCC_APB1_DIV_1                  RCC_CDCFGR2_CDPPRE1_DIV1

#define LL_RCC_APB1_DIV_2                  RCC_CDCFGR2_CDPPRE1_DIV2

#define LL_RCC_APB1_DIV_4                  RCC_CDCFGR2_CDPPRE1_DIV4

#define LL_RCC_APB1_DIV_8                  RCC_CDCFGR2_CDPPRE1_DIV8

#define LL_RCC_APB1_DIV_16                 RCC_CDCFGR2_CDPPRE1_DIV16

#endif /* RCC_D2CFGR_D2PPRE1_DIV1 */

#if defined(RCC_D2CFGR_D2PPRE2_DIV1)

#define LL_RCC_APB2_DIV_1                  RCC_D2CFGR_D2PPRE2_DIV1

#define LL_RCC_APB2_DIV_2                  RCC_D2CFGR_D2PPRE2_DIV2

#define LL_RCC_APB2_DIV_4                  RCC_D2CFGR_D2PPRE2_DIV4

#define LL_RCC_APB2_DIV_8                  RCC_D2CFGR_D2PPRE2_DIV8

#define LL_RCC_APB2_DIV_16                 RCC_D2CFGR_D2PPRE2_DIV16

#else

#define LL_RCC_APB2_DIV_1                  RCC_CDCFGR2_CDPPRE2_DIV1

#define LL_RCC_APB2_DIV_2                  RCC_CDCFGR2_CDPPRE2_DIV2

#define LL_RCC_APB2_DIV_4                  RCC_CDCFGR2_CDPPRE2_DIV4

#define LL_RCC_APB2_DIV_8                  RCC_CDCFGR2_CDPPRE2_DIV8

#define LL_RCC_APB2_DIV_16                 RCC_CDCFGR2_CDPPRE2_DIV16

#endif /* RCC_D2CFGR_D2PPRE2_DIV1 */

#if defined(RCC_D1CFGR_D1PPRE_DIV1)

#define LL_RCC_APB3_DIV_1                  RCC_D1CFGR_D1PPRE_DIV1

#define LL_RCC_APB3_DIV_2                  RCC_D1CFGR_D1PPRE_DIV2

#define LL_RCC_APB3_DIV_4                  RCC_D1CFGR_D1PPRE_DIV4

#define LL_RCC_APB3_DIV_8                  RCC_D1CFGR_D1PPRE_DIV8

#define LL_RCC_APB3_DIV_16                 RCC_D1CFGR_D1PPRE_DIV16

#else

#define LL_RCC_APB3_DIV_1                  RCC_CDCFGR1_CDPPRE_DIV1

#define LL_RCC_APB3_DIV_2                  RCC_CDCFGR1_CDPPRE_DIV2

#define LL_RCC_APB3_DIV_4                  RCC_CDCFGR1_CDPPRE_DIV4

#define LL_RCC_APB3_DIV_8                  RCC_CDCFGR1_CDPPRE_DIV8

#define LL_RCC_APB3_DIV_16                 RCC_CDCFGR1_CDPPRE_DIV16

#endif /* RCC_D1CFGR_D1PPRE_DIV1 */

#if defined(RCC_D3CFGR_D3PPRE_DIV1)

#define LL_RCC_APB4_DIV_1                  RCC_D3CFGR_D3PPRE_DIV1

#define LL_RCC_APB4_DIV_2                  RCC_D3CFGR_D3PPRE_DIV2

#define LL_RCC_APB4_DIV_4                  RCC_D3CFGR_D3PPRE_DIV4

#define LL_RCC_APB4_DIV_8                  RCC_D3CFGR_D3PPRE_DIV8

#define LL_RCC_APB4_DIV_16                 RCC_D3CFGR_D3PPRE_DIV16

#else

#define LL_RCC_APB4_DIV_1                  RCC_SRDCFGR_SRDPPRE_DIV1

#define LL_RCC_APB4_DIV_2                  RCC_SRDCFGR_SRDPPRE_DIV2

#define LL_RCC_APB4_DIV_4                  RCC_SRDCFGR_SRDPPRE_DIV4

#define LL_RCC_APB4_DIV_8                  RCC_SRDCFGR_SRDPPRE_DIV8

#define LL_RCC_APB4_DIV_16                 RCC_SRDCFGR_SRDPPRE_DIV16

#endif /* RCC_D3CFGR_D3PPRE_DIV1 */

#define LL_RCC_MCO1SOURCE_HSI              (uint32_t)((RCC_CFGR_MCO1>>16U) | 0x00000000U)

#define LL_RCC_MCO1SOURCE_LSE              (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_0)

#define LL_RCC_MCO1SOURCE_HSE              (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1)

#define LL_RCC_MCO1SOURCE_PLL1QCLK         (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0)

#define LL_RCC_MCO1SOURCE_HSI48            (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_2)

#define LL_RCC_MCO2SOURCE_SYSCLK           (uint32_t)((RCC_CFGR_MCO2>>16U) | 0x00000000U)

#define LL_RCC_MCO2SOURCE_PLL2PCLK         (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_0)

#define LL_RCC_MCO2SOURCE_HSE              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1)

#define LL_RCC_MCO2SOURCE_PLL1PCLK         (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0)

#define LL_RCC_MCO2SOURCE_CSI              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2)

#define LL_RCC_MCO2SOURCE_LSI              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2|RCC_CFGR_MCO2_0)

#define LL_RCC_MCO1_DIV_1                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0)

#define LL_RCC_MCO1_DIV_2                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1)

#define LL_RCC_MCO1_DIV_3                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)

#define LL_RCC_MCO1_DIV_4                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2)

#define LL_RCC_MCO1_DIV_5                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)

#define LL_RCC_MCO1_DIV_6                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)

#define LL_RCC_MCO1_DIV_7                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)

#define LL_RCC_MCO1_DIV_8                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3)

#define LL_RCC_MCO1_DIV_9                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)

#define LL_RCC_MCO1_DIV_10                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)

#define LL_RCC_MCO1_DIV_11                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)

#define LL_RCC_MCO1_DIV_12                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)

#define LL_RCC_MCO1_DIV_13                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)

#define LL_RCC_MCO1_DIV_14                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)

#define LL_RCC_MCO1_DIV_15                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE)

#define LL_RCC_MCO2_DIV_1                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0)

#define LL_RCC_MCO2_DIV_2                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1)

#define LL_RCC_MCO2_DIV_3                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1)

#define LL_RCC_MCO2_DIV_4                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2)

#define LL_RCC_MCO2_DIV_5                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2)

#define LL_RCC_MCO2_DIV_6                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)

#define LL_RCC_MCO2_DIV_7                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)

#define LL_RCC_MCO2_DIV_8                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3)

#define LL_RCC_MCO2_DIV_9                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_3)

#define LL_RCC_MCO2_DIV_10                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)

#define LL_RCC_MCO2_DIV_11                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)

#define LL_RCC_MCO2_DIV_12                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)

#define LL_RCC_MCO2_DIV_13                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)

#define LL_RCC_MCO2_DIV_14                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)

#define LL_RCC_MCO2_DIV_15                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE)


#define LL_RCC_RTC_NOCLOCK                  (uint32_t)(0x00000000U)

#define LL_RCC_RTC_HSE_DIV_2                (uint32_t)(RCC_CFGR_RTCPRE_1)

#define LL_RCC_RTC_HSE_DIV_3                (uint32_t)(RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_4                (uint32_t)(RCC_CFGR_RTCPRE_2)

#define LL_RCC_RTC_HSE_DIV_5                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_6                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

#define LL_RCC_RTC_HSE_DIV_7                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_8                (uint32_t)(RCC_CFGR_RTCPRE_3)

#define LL_RCC_RTC_HSE_DIV_9                (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_10               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)

#define LL_RCC_RTC_HSE_DIV_11               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_12               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)

#define LL_RCC_RTC_HSE_DIV_13               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_14               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

#define LL_RCC_RTC_HSE_DIV_15               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_16               (uint32_t)(RCC_CFGR_RTCPRE_4)

#define LL_RCC_RTC_HSE_DIV_17               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_18               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)

#define LL_RCC_RTC_HSE_DIV_19               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_20               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)

#define LL_RCC_RTC_HSE_DIV_21               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_22               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

#define LL_RCC_RTC_HSE_DIV_23               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_24               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)

#define LL_RCC_RTC_HSE_DIV_25               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_26               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)

#define LL_RCC_RTC_HSE_DIV_27               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_28               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)

#define LL_RCC_RTC_HSE_DIV_29               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_30               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

#define LL_RCC_RTC_HSE_DIV_31               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_32               (uint32_t)(RCC_CFGR_RTCPRE_5)

#define LL_RCC_RTC_HSE_DIV_33               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_34               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1)

#define LL_RCC_RTC_HSE_DIV_35               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_36               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2)

#define LL_RCC_RTC_HSE_DIV_37               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_38               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

#define LL_RCC_RTC_HSE_DIV_39               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_40               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3)

#define LL_RCC_RTC_HSE_DIV_41               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_42               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)

#define LL_RCC_RTC_HSE_DIV_43               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_44               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)

#define LL_RCC_RTC_HSE_DIV_45               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_46               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

#define LL_RCC_RTC_HSE_DIV_47               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_48               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4)

#define LL_RCC_RTC_HSE_DIV_49               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_50               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)

#define LL_RCC_RTC_HSE_DIV_51               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_52               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)

#define LL_RCC_RTC_HSE_DIV_53               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_54               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

#define LL_RCC_RTC_HSE_DIV_55               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_56               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)

#define LL_RCC_RTC_HSE_DIV_57               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_58               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)

#define LL_RCC_RTC_HSE_DIV_59               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_60               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)

#define LL_RCC_RTC_HSE_DIV_61               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

#define LL_RCC_RTC_HSE_DIV_62               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

#define LL_RCC_RTC_HSE_DIV_63               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

#if defined(RCC_D2CCIP2R_USART16SEL)

#define LL_RCC_USART16_CLKSOURCE_PCLK2         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)

#define LL_RCC_USART16_CLKSOURCE_PLL2Q         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0)

#define LL_RCC_USART16_CLKSOURCE_PLL3Q         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_1)

#define LL_RCC_USART16_CLKSOURCE_HSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)

#define LL_RCC_USART16_CLKSOURCE_CSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_2)

#define LL_RCC_USART16_CLKSOURCE_LSE           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)

/*  Aliases */

#define LL_RCC_USART16910_CLKSOURCE_PCLK2      LL_RCC_USART16_CLKSOURCE_PCLK2

#define LL_RCC_USART16910_CLKSOURCE_PLL2Q      LL_RCC_USART16_CLKSOURCE_PLL2Q

#define LL_RCC_USART16910_CLKSOURCE_PLL3Q      LL_RCC_USART16_CLKSOURCE_PLL3Q

#define LL_RCC_USART16910_CLKSOURCE_HSI        LL_RCC_USART16_CLKSOURCE_HSI

#define LL_RCC_USART16910_CLKSOURCE_CSI        LL_RCC_USART16_CLKSOURCE_CSI

#define LL_RCC_USART16910_CLKSOURCE_LSE        LL_RCC_USART16_CLKSOURCE_LSE


#elif defined(RCC_D2CCIP2R_USART16910SEL)

#define LL_RCC_USART16910_CLKSOURCE_PCLK2      LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U)

#define LL_RCC_USART16910_CLKSOURCE_PLL2Q      LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0)

#define LL_RCC_USART16910_CLKSOURCE_PLL3Q      LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_1)

#define LL_RCC_USART16910_CLKSOURCE_HSI        LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_1)

#define LL_RCC_USART16910_CLKSOURCE_CSI        LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_2)

#define LL_RCC_USART16910_CLKSOURCE_LSE        LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_2)

/*  Aliases */

#define LL_RCC_USART16_CLKSOURCE_PCLK2         LL_RCC_USART16910_CLKSOURCE_PCLK2

#define LL_RCC_USART16_CLKSOURCE_PLL2Q         LL_RCC_USART16910_CLKSOURCE_PLL2Q

#define LL_RCC_USART16_CLKSOURCE_PLL3Q         LL_RCC_USART16910_CLKSOURCE_PLL3Q

#define LL_RCC_USART16_CLKSOURCE_HSI           LL_RCC_USART16910_CLKSOURCE_HSI

#define LL_RCC_USART16_CLKSOURCE_CSI           LL_RCC_USART16910_CLKSOURCE_CSI

#define LL_RCC_USART16_CLKSOURCE_LSE           LL_RCC_USART16910_CLKSOURCE_LSE


#else

#define LL_RCC_USART16910_CLKSOURCE_PCLK2      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)

#define LL_RCC_USART16910_CLKSOURCE_PLL2Q      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0)

#define LL_RCC_USART16910_CLKSOURCE_PLL3Q      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_1)

#define LL_RCC_USART16910_CLKSOURCE_HSI        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)

#define LL_RCC_USART16910_CLKSOURCE_CSI        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_2)

#define LL_RCC_USART16910_CLKSOURCE_LSE        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)

/*  Aliases */

#define LL_RCC_USART16_CLKSOURCE_PCLK2         LL_RCC_USART16910_CLKSOURCE_PCLK2

#define LL_RCC_USART16_CLKSOURCE_PLL2Q         LL_RCC_USART16910_CLKSOURCE_PLL2Q

#define LL_RCC_USART16_CLKSOURCE_PLL3Q         LL_RCC_USART16910_CLKSOURCE_PLL3Q

#define LL_RCC_USART16_CLKSOURCE_HSI           LL_RCC_USART16910_CLKSOURCE_HSI

#define LL_RCC_USART16_CLKSOURCE_CSI           LL_RCC_USART16910_CLKSOURCE_CSI

#define LL_RCC_USART16_CLKSOURCE_LSE           LL_RCC_USART16910_CLKSOURCE_LSE

#endif  /* RCC_D2CCIP2R_USART16SEL */

#if defined(RCC_D2CCIP2R_USART28SEL)

#define LL_RCC_USART234578_CLKSOURCE_PCLK1     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)

#define LL_RCC_USART234578_CLKSOURCE_PLL2Q     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0)

#define LL_RCC_USART234578_CLKSOURCE_PLL3Q     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_1)

#define LL_RCC_USART234578_CLKSOURCE_HSI       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)

#define LL_RCC_USART234578_CLKSOURCE_CSI       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_2)

#define LL_RCC_USART234578_CLKSOURCE_LSE       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)

#else

#define LL_RCC_USART234578_CLKSOURCE_PCLK1     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)

#define LL_RCC_USART234578_CLKSOURCE_PLL2Q     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0)

#define LL_RCC_USART234578_CLKSOURCE_PLL3Q     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_1)

#define LL_RCC_USART234578_CLKSOURCE_HSI       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)

#define LL_RCC_USART234578_CLKSOURCE_CSI       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_2)

#define LL_RCC_USART234578_CLKSOURCE_LSE       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)

#endif /* RCC_D2CCIP2R_USART28SEL */

#if defined(RCC_D3CCIPR_LPUART1SEL)

#define LL_RCC_LPUART1_CLKSOURCE_PCLK4         (0x00000000U)

#define LL_RCC_LPUART1_CLKSOURCE_PLL2Q         (RCC_D3CCIPR_LPUART1SEL_0)

#define LL_RCC_LPUART1_CLKSOURCE_PLL3Q         (RCC_D3CCIPR_LPUART1SEL_1)

#define LL_RCC_LPUART1_CLKSOURCE_HSI           (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)

#define LL_RCC_LPUART1_CLKSOURCE_CSI           (RCC_D3CCIPR_LPUART1SEL_2)

#define LL_RCC_LPUART1_CLKSOURCE_LSE           (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_2)

#else

#define LL_RCC_LPUART1_CLKSOURCE_PCLK4         (0x00000000U)

#define LL_RCC_LPUART1_CLKSOURCE_PLL2Q         (RCC_SRDCCIPR_LPUART1SEL_0)

#define LL_RCC_LPUART1_CLKSOURCE_PLL3Q         (RCC_SRDCCIPR_LPUART1SEL_1)

#define LL_RCC_LPUART1_CLKSOURCE_HSI           (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)

#define LL_RCC_LPUART1_CLKSOURCE_CSI           (RCC_SRDCCIPR_LPUART1SEL_2)

#define LL_RCC_LPUART1_CLKSOURCE_LSE           (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_2)

#endif /* RCC_D3CCIPR_LPUART1SEL */

#if defined (RCC_D2CCIP2R_I2C123SEL)

#define LL_RCC_I2C123_CLKSOURCE_PCLK1          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)

#define LL_RCC_I2C123_CLKSOURCE_PLL3R          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0)

#define LL_RCC_I2C123_CLKSOURCE_HSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_1)

#define LL_RCC_I2C123_CLKSOURCE_CSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)

/*  Aliases */

#define LL_RCC_I2C1235_CLKSOURCE_PCLK1         LL_RCC_I2C123_CLKSOURCE_PCLK1

#define LL_RCC_I2C1235_CLKSOURCE_PLL3R         LL_RCC_I2C123_CLKSOURCE_PLL3R

#define LL_RCC_I2C1235_CLKSOURCE_HSI           LL_RCC_I2C123_CLKSOURCE_HSI

#define LL_RCC_I2C1235_CLKSOURCE_CSI           LL_RCC_I2C123_CLKSOURCE_CSI


#elif defined (RCC_D2CCIP2R_I2C1235SEL)

#define LL_RCC_I2C1235_CLKSOURCE_PCLK1         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U)

#define LL_RCC_I2C1235_CLKSOURCE_PLL3R         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0)

#define LL_RCC_I2C1235_CLKSOURCE_HSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_1)

#define LL_RCC_I2C1235_CLKSOURCE_CSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0 | RCC_D2CCIP2R_I2C1235SEL_1)

/*  Aliases */

#define LL_RCC_I2C123_CLKSOURCE_PCLK1          LL_RCC_I2C1235_CLKSOURCE_PCLK1

#define LL_RCC_I2C123_CLKSOURCE_PLL3R          LL_RCC_I2C1235_CLKSOURCE_PLL3R

#define LL_RCC_I2C123_CLKSOURCE_HSI            LL_RCC_I2C1235_CLKSOURCE_HSI

#define LL_RCC_I2C123_CLKSOURCE_CSI            LL_RCC_I2C1235_CLKSOURCE_CSI


#else

#define LL_RCC_I2C123_CLKSOURCE_PCLK1          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)

#define LL_RCC_I2C123_CLKSOURCE_PLL3R          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0)

#define LL_RCC_I2C123_CLKSOURCE_HSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_1)

#define LL_RCC_I2C123_CLKSOURCE_CSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)

#endif /* RCC_D2CCIP2R_I2C123SEL */

#if defined (RCC_D3CCIPR_I2C4SEL)

#define LL_RCC_I2C4_CLKSOURCE_PCLK4            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    0x00000000U)

#define LL_RCC_I2C4_CLKSOURCE_PLL3R            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_0)

#define LL_RCC_I2C4_CLKSOURCE_HSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_1)

#define LL_RCC_I2C4_CLKSOURCE_CSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)

#else

#define LL_RCC_I2C4_CLKSOURCE_PCLK4            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    0x00000000U)

#define LL_RCC_I2C4_CLKSOURCE_PLL3R            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_0)

#define LL_RCC_I2C4_CLKSOURCE_HSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_1)

#define LL_RCC_I2C4_CLKSOURCE_CSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)

#endif /* RCC_D3CCIPR_I2C4SEL */

#if defined(RCC_D2CCIP2R_LPTIM1SEL)

#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  0x00000000U)

#define LL_RCC_LPTIM1_CLKSOURCE_PLL2P          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0)

#define LL_RCC_LPTIM1_CLKSOURCE_PLL3R          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_1)

#define LL_RCC_LPTIM1_CLKSOURCE_LSE            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)

#define LL_RCC_LPTIM1_CLKSOURCE_LSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_2)

#define LL_RCC_LPTIM1_CLKSOURCE_CLKP           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)

#else

#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  0x00000000U)

#define LL_RCC_LPTIM1_CLKSOURCE_PLL2P          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0)

#define LL_RCC_LPTIM1_CLKSOURCE_PLL3R          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_1)

#define LL_RCC_LPTIM1_CLKSOURCE_LSE            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)

#define LL_RCC_LPTIM1_CLKSOURCE_LSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_2)

#define LL_RCC_LPTIM1_CLKSOURCE_CLKP           LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)

#endif /* RCC_D2CCIP2R_LPTIM1SEL */

#if defined(RCC_D3CCIPR_LPTIM2SEL)

#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   0x00000000U)

#define LL_RCC_LPTIM2_CLKSOURCE_PLL2P          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0)

#define LL_RCC_LPTIM2_CLKSOURCE_PLL3R          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_1)

#define LL_RCC_LPTIM2_CLKSOURCE_LSE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)

#define LL_RCC_LPTIM2_CLKSOURCE_LSI            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_2)

#define LL_RCC_LPTIM2_CLKSOURCE_CLKP           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)

#else

#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   0x00000000U)

#define LL_RCC_LPTIM2_CLKSOURCE_PLL2P          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0)

#define LL_RCC_LPTIM2_CLKSOURCE_PLL3R          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_1)

#define LL_RCC_LPTIM2_CLKSOURCE_LSE            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)

#define LL_RCC_LPTIM2_CLKSOURCE_LSI            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_2)

#define LL_RCC_LPTIM2_CLKSOURCE_CLKP           LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)

#endif /* RCC_D3CCIPR_LPTIM2SEL */

#if defined(RCC_D3CCIPR_LPTIM345SEL)

#define LL_RCC_LPTIM345_CLKSOURCE_PCLK4        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U)

#define LL_RCC_LPTIM345_CLKSOURCE_PLL2P        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0)

#define LL_RCC_LPTIM345_CLKSOURCE_PLL3R        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_1)

#define LL_RCC_LPTIM345_CLKSOURCE_LSE          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)

#define LL_RCC_LPTIM345_CLKSOURCE_LSI          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_2)

#define LL_RCC_LPTIM345_CLKSOURCE_CLKP         LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)

#else

#define LL_RCC_LPTIM345_CLKSOURCE_PCLK4        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U)

#define LL_RCC_LPTIM345_CLKSOURCE_PLL2P        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0)

#define LL_RCC_LPTIM345_CLKSOURCE_PLL3R        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_1)

#define LL_RCC_LPTIM345_CLKSOURCE_LSE          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)

#define LL_RCC_LPTIM345_CLKSOURCE_LSI          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_2)

#define LL_RCC_LPTIM345_CLKSOURCE_CLKP         LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)

/* aliases*/

#define LL_RCC_LPTIM3_CLKSOURCE_PCLK4          LL_RCC_LPTIM345_CLKSOURCE_PCLK4

#define LL_RCC_LPTIM3_CLKSOURCE_PLL2P          LL_RCC_LPTIM345_CLKSOURCE_PLL2P

#define LL_RCC_LPTIM3_CLKSOURCE_PLL3R          LL_RCC_LPTIM345_CLKSOURCE_PLL3R

#define LL_RCC_LPTIM3_CLKSOURCE_LSE            LL_RCC_LPTIM345_CLKSOURCE_LSE

#define LL_RCC_LPTIM3_CLKSOURCE_LSI            LL_RCC_LPTIM345_CLKSOURCE_LSI

#define LL_RCC_LPTIM3_CLKSOURCE_CLKP           LL_RCC_LPTIM345_CLKSOURCE_CLKP

#endif /* RCC_D3CCIPR_LPTIM345SEL */

#if defined(RCC_D2CCIP1R_SAI1SEL)

#define LL_RCC_SAI1_CLKSOURCE_PLL1Q            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  0x00000000U)

#define LL_RCC_SAI1_CLKSOURCE_PLL2P            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_0)

#define LL_RCC_SAI1_CLKSOURCE_PLL3P            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_1)

#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)

#define LL_RCC_SAI1_CLKSOURCE_CLKP             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_2)

#else

#define LL_RCC_SAI1_CLKSOURCE_PLL1Q            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  0x00000000U)

#define LL_RCC_SAI1_CLKSOURCE_PLL2P            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_0)

#define LL_RCC_SAI1_CLKSOURCE_PLL3P            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_1)

#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)

#define LL_RCC_SAI1_CLKSOURCE_CLKP             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_2)

#endif

#if defined(SAI3)

#define LL_RCC_SAI23_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)

#define LL_RCC_SAI23_CLKSOURCE_PLL2P           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0)

#define LL_RCC_SAI23_CLKSOURCE_PLL3P           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_1)

#define LL_RCC_SAI23_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)

#define LL_RCC_SAI23_CLKSOURCE_CLKP            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_2)

#endif /* SAI3 */

#if defined(RCC_CDCCIP1R_SAI2ASEL)

#define LL_RCC_SAI2A_CLKSOURCE_PLL1Q           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  0x00000000U)

#define LL_RCC_SAI2A_CLKSOURCE_PLL2P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0)

#define LL_RCC_SAI2A_CLKSOURCE_PLL3P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_1)

#define LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)

#define LL_RCC_SAI2A_CLKSOURCE_CLKP            LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_2)

#define LL_RCC_SAI2A_CLKSOURCE_SPDIF           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)

#endif /* RCC_CDCCIP1R_SAI2ASEL */

#if defined(RCC_CDCCIP1R_SAI2BSEL)

#define LL_RCC_SAI2B_CLKSOURCE_PLL1Q           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  0x00000000U)

#define LL_RCC_SAI2B_CLKSOURCE_PLL2P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0)

#define LL_RCC_SAI2B_CLKSOURCE_PLL3P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_1)

#define LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)

#define LL_RCC_SAI2B_CLKSOURCE_CLKP            LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_2)

#define LL_RCC_SAI2B_CLKSOURCE_SPDIF           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)

#endif /* RCC_CDCCIP1R_SAI2BSEL */

#if defined(SAI4_Block_A)

#define LL_RCC_SAI4A_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  0x00000000U)

#define LL_RCC_SAI4A_CLKSOURCE_PLL2P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_0)

#define LL_RCC_SAI4A_CLKSOURCE_PLL3P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_1)

#define LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)

#define LL_RCC_SAI4A_CLKSOURCE_CLKP            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_2)

#if defined(RCC_VER_3_0)

#define LL_RCC_SAI4A_CLKSOURCE_SPDIF           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_2 | RCC_D3CCIPR_SAI4ASEL_0)

#endif /* RCC_VER_3_0 */

#endif /* SAI4_Block_A */

#if defined(SAI4_Block_B)

#define LL_RCC_SAI4B_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  0x00000000U)

#define LL_RCC_SAI4B_CLKSOURCE_PLL2P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_0)

#define LL_RCC_SAI4B_CLKSOURCE_PLL3P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_1)

#define LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)

#define LL_RCC_SAI4B_CLKSOURCE_CLKP            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_2)

#if defined(RCC_VER_3_0)

#define LL_RCC_SAI4B_CLKSOURCE_SPDIF           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_2 | RCC_D3CCIPR_SAI4BSEL_0)

#endif /* RCC_VER_3_0 */

#endif /* SAI4_Block_B */

#if defined(RCC_D1CCIPR_SDMMCSEL)

#define LL_RCC_SDMMC_CLKSOURCE_PLL1Q           (0x00000000U)

#define LL_RCC_SDMMC_CLKSOURCE_PLL2R           (RCC_D1CCIPR_SDMMCSEL)

#else

#define LL_RCC_SDMMC_CLKSOURCE_PLL1Q           (0x00000000U)

#define LL_RCC_SDMMC_CLKSOURCE_PLL2R           (RCC_CDCCIPR_SDMMCSEL)

#endif /* RCC_D1CCIPR_SDMMCSEL */

#if defined(RCC_D2CCIP2R_RNGSEL)

#define LL_RCC_RNG_CLKSOURCE_HSI48             (0x00000000U)

#define LL_RCC_RNG_CLKSOURCE_PLL1Q             (RCC_D2CCIP2R_RNGSEL_0)

#define LL_RCC_RNG_CLKSOURCE_LSE               (RCC_D2CCIP2R_RNGSEL_1)

#define LL_RCC_RNG_CLKSOURCE_LSI               (RCC_D2CCIP2R_RNGSEL_1 | RCC_D2CCIP2R_RNGSEL_0)

#else

#define LL_RCC_RNG_CLKSOURCE_HSI48             (0x00000000U)

#define LL_RCC_RNG_CLKSOURCE_PLL1Q             (RCC_CDCCIP2R_RNGSEL_0)

#define LL_RCC_RNG_CLKSOURCE_LSE               (RCC_CDCCIP2R_RNGSEL_1)

#define LL_RCC_RNG_CLKSOURCE_LSI               (RCC_CDCCIP2R_RNGSEL_1 | RCC_CDCCIP2R_RNGSEL_0)

#endif /* RCC_D2CCIP2R_RNGSEL */

#if defined(RCC_D2CCIP2R_USBSEL)

#define LL_RCC_USB_CLKSOURCE_DISABLE           (0x00000000U)

#define LL_RCC_USB_CLKSOURCE_PLL1Q             (RCC_D2CCIP2R_USBSEL_0)

#define LL_RCC_USB_CLKSOURCE_PLL3Q             (RCC_D2CCIP2R_USBSEL_1)

#define LL_RCC_USB_CLKSOURCE_HSI48             (RCC_D2CCIP2R_USBSEL_1 | RCC_D2CCIP2R_USBSEL_0)

#else

#define LL_RCC_USB_CLKSOURCE_DISABLE           (0x00000000U)

#define LL_RCC_USB_CLKSOURCE_PLL1Q             (RCC_CDCCIP2R_USBSEL_0)

#define LL_RCC_USB_CLKSOURCE_PLL3Q             (RCC_CDCCIP2R_USBSEL_1)

#define LL_RCC_USB_CLKSOURCE_HSI48             (RCC_CDCCIP2R_USBSEL_1 | RCC_CDCCIP2R_USBSEL_0)

#endif /* RCC_D2CCIP2R_USBSEL */

#if defined(RCC_D2CCIP2R_CECSEL)

#define LL_RCC_CEC_CLKSOURCE_LSE               (0x00000000U)

#define LL_RCC_CEC_CLKSOURCE_LSI               (RCC_D2CCIP2R_CECSEL_0)

#define LL_RCC_CEC_CLKSOURCE_CSI_DIV122        (RCC_D2CCIP2R_CECSEL_1)

#else

#define LL_RCC_CEC_CLKSOURCE_LSE               (0x00000000U)

#define LL_RCC_CEC_CLKSOURCE_LSI               (RCC_CDCCIP2R_CECSEL_0)

#define LL_RCC_CEC_CLKSOURCE_CSI_DIV122        (RCC_CDCCIP2R_CECSEL_1)

#endif

#if defined(DSI)

#define LL_RCC_DSI_CLKSOURCE_PHY               (0x00000000U)

#define LL_RCC_DSI_CLKSOURCE_PLL2Q             (RCC_D1CCIPR_DSISEL)

#endif /* DSI */


#if defined(RCC_D2CCIP1R_DFSDM1SEL)

#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          (0x00000000U)

#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         (RCC_D2CCIP1R_DFSDM1SEL)

#else

#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          (0x00000000U)

#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         (RCC_CDCCIP1R_DFSDM1SEL)

#endif /* RCC_D2CCIP1R_DFSDM1SEL */

#if defined(DFSDM2_BASE)

#define LL_RCC_DFSDM2_CLKSOURCE_PCLK4          (0x00000000U)

#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK         (RCC_SRDCCIPR_DFSDM2SEL)

#endif /* DFSDM2_BASE */


#if defined(RCC_D1CCIPR_FMCSEL)

#define LL_RCC_FMC_CLKSOURCE_HCLK              (0x00000000U)

#define LL_RCC_FMC_CLKSOURCE_PLL1Q             (RCC_D1CCIPR_FMCSEL_0)

#define LL_RCC_FMC_CLKSOURCE_PLL2R             (RCC_D1CCIPR_FMCSEL_1)

#define LL_RCC_FMC_CLKSOURCE_CLKP              (RCC_D1CCIPR_FMCSEL_0 | RCC_D1CCIPR_FMCSEL_1)

#else

#define LL_RCC_FMC_CLKSOURCE_HCLK              (0x00000000U)

#define LL_RCC_FMC_CLKSOURCE_PLL1Q             (RCC_CDCCIPR_FMCSEL_0)

#define LL_RCC_FMC_CLKSOURCE_PLL2R             (RCC_CDCCIPR_FMCSEL_1)

#define LL_RCC_FMC_CLKSOURCE_CLKP              (RCC_CDCCIPR_FMCSEL_0 | RCC_CDCCIPR_FMCSEL_1)

#endif /* RCC_D1CCIPR_FMCSEL */

#if defined(QUADSPI)

#define LL_RCC_QSPI_CLKSOURCE_HCLK             (0x00000000U)

#define LL_RCC_QSPI_CLKSOURCE_PLL1Q            (RCC_D1CCIPR_QSPISEL_0)

#define LL_RCC_QSPI_CLKSOURCE_PLL2R            (RCC_D1CCIPR_QSPISEL_1)

#define LL_RCC_QSPI_CLKSOURCE_CLKP             (RCC_D1CCIPR_QSPISEL_0 | RCC_D1CCIPR_QSPISEL_1)

#endif /* QUADSPI */


#if defined(OCTOSPI1) || defined(OCTOSPI2)

#if defined(RCC_D1CCIPR_OCTOSPISEL)

#define LL_RCC_OSPI_CLKSOURCE_HCLK             (0x00000000U)

#define LL_RCC_OSPI_CLKSOURCE_PLL1Q            (RCC_D1CCIPR_OCTOSPISEL_0)

#define LL_RCC_OSPI_CLKSOURCE_PLL2R            (RCC_D1CCIPR_OCTOSPISEL_1)

#define LL_RCC_OSPI_CLKSOURCE_CLKP             (RCC_D1CCIPR_OCTOSPISEL_0 | RCC_D1CCIPR_OCTOSPISEL_1)

#else

#define LL_RCC_OSPI_CLKSOURCE_HCLK             (0x00000000U)

#define LL_RCC_OSPI_CLKSOURCE_PLL1Q            (RCC_CDCCIPR_OCTOSPISEL_0)

#define LL_RCC_OSPI_CLKSOURCE_PLL2R            (RCC_CDCCIPR_OCTOSPISEL_1)

#define LL_RCC_OSPI_CLKSOURCE_CLKP             (RCC_CDCCIPR_OCTOSPISEL_0 | RCC_CDCCIPR_OCTOSPISEL_1)

#endif /* RCC_D1CCIPR_OCTOSPISEL */

#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */


#if defined(RCC_D1CCIPR_CKPERSEL)

#define LL_RCC_CLKP_CLKSOURCE_HSI              (0x00000000U)

#define LL_RCC_CLKP_CLKSOURCE_CSI              (RCC_D1CCIPR_CKPERSEL_0)

#define LL_RCC_CLKP_CLKSOURCE_HSE              (RCC_D1CCIPR_CKPERSEL_1)

#else

#define LL_RCC_CLKP_CLKSOURCE_HSI              (0x00000000U)

#define LL_RCC_CLKP_CLKSOURCE_CSI              (RCC_CDCCIPR_CKPERSEL_0)

#define LL_RCC_CLKP_CLKSOURCE_HSE              (RCC_CDCCIPR_CKPERSEL_1)

#endif /* RCC_D1CCIPR_CKPERSEL */

#if defined(RCC_D2CCIP1R_SPI123SEL)

#define LL_RCC_SPI123_CLKSOURCE_PLL1Q          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)

#define LL_RCC_SPI123_CLKSOURCE_PLL2P          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0)

#define LL_RCC_SPI123_CLKSOURCE_PLL3P          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_1)

#define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN       LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)

#define LL_RCC_SPI123_CLKSOURCE_CLKP           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_2)

#else

#define LL_RCC_SPI123_CLKSOURCE_PLL1Q          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)

#define LL_RCC_SPI123_CLKSOURCE_PLL2P          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0)

#define LL_RCC_SPI123_CLKSOURCE_PLL3P          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_1)

#define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN       LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)

#define LL_RCC_SPI123_CLKSOURCE_CLKP           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_2)

#endif /* RCC_D2CCIP1R_SPI123SEL */

#if defined(RCC_D2CCIP1R_SPI45SEL)

#define LL_RCC_SPI45_CLKSOURCE_PCLK2           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  0x00000000U)

#define LL_RCC_SPI45_CLKSOURCE_PLL2Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0)

#define LL_RCC_SPI45_CLKSOURCE_PLL3Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_1)

#define LL_RCC_SPI45_CLKSOURCE_HSI             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)

#define LL_RCC_SPI45_CLKSOURCE_CSI             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_2)

#define LL_RCC_SPI45_CLKSOURCE_HSE             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)

#else

#define LL_RCC_SPI45_CLKSOURCE_PCLK2           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  0x00000000U)

#define LL_RCC_SPI45_CLKSOURCE_PLL2Q           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0)

#define LL_RCC_SPI45_CLKSOURCE_PLL3Q           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_1)

#define LL_RCC_SPI45_CLKSOURCE_HSI             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)

#define LL_RCC_SPI45_CLKSOURCE_CSI             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_2)

#define LL_RCC_SPI45_CLKSOURCE_HSE             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)

#endif /* (RCC_D2CCIP1R_SPI45SEL */

#if defined(RCC_D3CCIPR_SPI6SEL)

#define LL_RCC_SPI6_CLKSOURCE_PCLK4            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    0x00000000U)

#define LL_RCC_SPI6_CLKSOURCE_PLL2Q            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0)

#define LL_RCC_SPI6_CLKSOURCE_PLL3Q            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_1)

#define LL_RCC_SPI6_CLKSOURCE_HSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)

#define LL_RCC_SPI6_CLKSOURCE_CSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_2)

#define LL_RCC_SPI6_CLKSOURCE_HSE              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)

#else

#define LL_RCC_SPI6_CLKSOURCE_PCLK4            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    0x00000000U)

#define LL_RCC_SPI6_CLKSOURCE_PLL2Q            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0)

#define LL_RCC_SPI6_CLKSOURCE_PLL3Q            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_1)

#define LL_RCC_SPI6_CLKSOURCE_HSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)

#define LL_RCC_SPI6_CLKSOURCE_CSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_2)

#define LL_RCC_SPI6_CLKSOURCE_HSE              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)

#define LL_RCC_SPI6_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)

#endif /* RCC_D3CCIPR_SPI6SEL */

#if defined(RCC_D2CCIP1R_SPDIFSEL)

#define LL_RCC_SPDIF_CLKSOURCE_PLL1Q           (0x00000000U)

#define LL_RCC_SPDIF_CLKSOURCE_PLL2R           (RCC_D2CCIP1R_SPDIFSEL_0)

#define LL_RCC_SPDIF_CLKSOURCE_PLL3R           (RCC_D2CCIP1R_SPDIFSEL_1)

#define LL_RCC_SPDIF_CLKSOURCE_HSI             (RCC_D2CCIP1R_SPDIFSEL_0 | RCC_D2CCIP1R_SPDIFSEL_1)

#else

#define LL_RCC_SPDIF_CLKSOURCE_PLL1Q           (0x00000000U)

#define LL_RCC_SPDIF_CLKSOURCE_PLL2R           (RCC_CDCCIP1R_SPDIFSEL_0)

#define LL_RCC_SPDIF_CLKSOURCE_PLL3R           (RCC_CDCCIP1R_SPDIFSEL_1)

#define LL_RCC_SPDIF_CLKSOURCE_HSI             (RCC_CDCCIP1R_SPDIFSEL_0 | RCC_CDCCIP1R_SPDIFSEL_1)

#endif /* RCC_D2CCIP1R_SPDIFSEL */

#if defined(FDCAN1) || defined(FDCAN2)

#if defined(RCC_D2CCIP1R_FDCANSEL)

#define LL_RCC_FDCAN_CLKSOURCE_HSE             (0x00000000U)

#define LL_RCC_FDCAN_CLKSOURCE_PLL1Q           (RCC_D2CCIP1R_FDCANSEL_0)

#define LL_RCC_FDCAN_CLKSOURCE_PLL2Q           (RCC_D2CCIP1R_FDCANSEL_1)

#else

#define LL_RCC_FDCAN_CLKSOURCE_HSE             (0x00000000U)

#define LL_RCC_FDCAN_CLKSOURCE_PLL1Q           (RCC_CDCCIP1R_FDCANSEL_0)

#define LL_RCC_FDCAN_CLKSOURCE_PLL2Q           (RCC_CDCCIP1R_FDCANSEL_1)

#endif /* RCC_D2CCIP1R_FDCANSEL */

#endif /*FDCAN1 || FDCAN2*/


#if defined(RCC_D2CCIP1R_SWPSEL)

#define LL_RCC_SWP_CLKSOURCE_PCLK1             (0x00000000U)

#define LL_RCC_SWP_CLKSOURCE_HSI               (RCC_D2CCIP1R_SWPSEL)

#else

#define LL_RCC_SWP_CLKSOURCE_PCLK1             (0x00000000U)

#define LL_RCC_SWP_CLKSOURCE_HSI               (RCC_CDCCIP1R_SWPSEL)

#endif /* RCC_D2CCIP1R_SWPSEL */

#if defined(RCC_D3CCIPR_ADCSEL)

#define LL_RCC_ADC_CLKSOURCE_PLL2P             (0x00000000U)

#define LL_RCC_ADC_CLKSOURCE_PLL3R             (RCC_D3CCIPR_ADCSEL_0)

#define LL_RCC_ADC_CLKSOURCE_CLKP              (RCC_D3CCIPR_ADCSEL_1)

#else

#define LL_RCC_ADC_CLKSOURCE_PLL2P             (0x00000000U)

#define LL_RCC_ADC_CLKSOURCE_PLL3R             (RCC_SRDCCIPR_ADCSEL_0)

#define LL_RCC_ADC_CLKSOURCE_CLKP              (RCC_SRDCCIPR_ADCSEL_1)

#endif /* RCC_D3CCIPR_ADCSEL */

#if defined (RCC_D2CCIP2R_USART16SEL)

#define LL_RCC_USART16_CLKSOURCE         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)

#elif defined (RCC_D2CCIP2R_USART16910SEL)

#define LL_RCC_USART16_CLKSOURCE         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U)

/* alias*/

#define LL_RCC_USART16910_CLKSOURCE      LL_RCC_USART16_CLKSOURCE

#else

#define LL_RCC_USART16_CLKSOURCE         LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)

/* alias*/

#define LL_RCC_USART16910_CLKSOURCE      LL_RCC_USART16_CLKSOURCE

#endif /* RCC_D2CCIP2R_USART16SEL */

#if defined (RCC_D2CCIP2R_USART28SEL)

#define LL_RCC_USART234578_CLKSOURCE     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)

#else

#define LL_RCC_USART234578_CLKSOURCE     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)

#endif /* RCC_D2CCIP2R_USART28SEL */

#if defined(RCC_D3CCIPR_LPUART1SEL)

#define LL_RCC_LPUART1_CLKSOURCE         RCC_D3CCIPR_LPUART1SEL

#else

#define LL_RCC_LPUART1_CLKSOURCE         RCC_SRDCCIPR_LPUART1SEL

#endif /* RCC_D3CCIPR_LPUART1SEL */

#if defined(RCC_D2CCIP2R_I2C123SEL)

#define LL_RCC_I2C123_CLKSOURCE          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)

/* alias */

#define LL_RCC_I2C1235_CLKSOURCE         LL_RCC_I2C123_CLKSOURCE

#elif defined(RCC_D2CCIP2R_I2C1235SEL)

#define LL_RCC_I2C1235_CLKSOURCE         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U)

/* alias */

#define LL_RCC_I2C123_CLKSOURCE          LL_RCC_I2C1235_CLKSOURCE

#else

#define LL_RCC_I2C123_CLKSOURCE          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)

/* alias */

#define LL_RCC_I2C1235_CLKSOURCE         LL_RCC_I2C123_CLKSOURCE

#endif /* RCC_D2CCIP2R_I2C123SEL */

#if defined(RCC_D3CCIPR_I2C4SEL)

#define LL_RCC_I2C4_CLKSOURCE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    0x00000000U)

#else

#define LL_RCC_I2C4_CLKSOURCE            LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL,   RCC_SRDCCIPR_I2C4SEL_Pos,   0x00000000U)

#endif /* RCC_D3CCIPR_I2C4SEL */

#if defined(RCC_D2CCIP2R_LPTIM1SEL)

#define LL_RCC_LPTIM1_CLKSOURCE          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,      0x00000000U)

#else

#define LL_RCC_LPTIM1_CLKSOURCE          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,      0x00000000U)

#endif /* RCC_D2CCIP2R_LPTIM1SEL) */

#if defined(RCC_D3CCIPR_LPTIM2SEL)

#define LL_RCC_LPTIM2_CLKSOURCE          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,       0x00000000U)

#else

#define LL_RCC_LPTIM2_CLKSOURCE          LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL,  RCC_SRDCCIPR_LPTIM2SEL_Pos,      0x00000000U)

#endif /* RCC_D3CCIPR_LPTIM2SEL */

#if defined(RCC_D3CCIPR_LPTIM345SEL)

#define LL_RCC_LPTIM345_CLKSOURCE        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos,     0x00000000U)

#else

#define LL_RCC_LPTIM345_CLKSOURCE        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos,      0x00000000U)

#define LL_RCC_LPTIM3_CLKSOURCE          LL_RCC_LPTIM345_CLKSOURCE  /* alias */

#endif /* RCC_D3CCIPR_LPTIM345SEL */

#if defined(RCC_D2CCIP1R_SAI1SEL)

#define LL_RCC_SAI1_CLKSOURCE            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  0x00000000U)

#else

#define LL_RCC_SAI1_CLKSOURCE            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  0x00000000U)

#endif /* RCC_D2CCIP1R_SAI1SEL */

#if defined(RCC_D2CCIP1R_SAI23SEL)

#define LL_RCC_SAI23_CLKSOURCE           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)

#endif /* RCC_D2CCIP1R_SAI23SEL */

#if defined(RCC_CDCCIP1R_SAI2ASEL)

#define LL_RCC_SAI2A_CLKSOURCE           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  0x00000000U)

#endif /* RCC_CDCCIP1R_SAI2ASEL */

#if defined(RCC_CDCCIP1R_SAI2BSEL)

#define LL_RCC_SAI2B_CLKSOURCE           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  0x00000000U)

#endif /*  RCC_CDCCIP1R_SAI2BSEL */

#if defined(RCC_D3CCIPR_SAI4ASEL)

#define LL_RCC_SAI4A_CLKSOURCE           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  0x00000000U)

#endif /* RCC_D3CCIPR_SAI4ASEL */

#if defined(RCC_D3CCIPR_SAI4BSEL)

#define LL_RCC_SAI4B_CLKSOURCE           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  0x00000000U)

#endif /*  RCC_D3CCIPR_SAI4BSEL */

#if defined(RCC_D1CCIPR_SDMMCSEL)

#define LL_RCC_SDMMC_CLKSOURCE           RCC_D1CCIPR_SDMMCSEL

#else

#define LL_RCC_SDMMC_CLKSOURCE           RCC_CDCCIPR_SDMMCSEL

#endif /* RCC_D1CCIPR_SDMMCSEL */

#if (RCC_D2CCIP2R_RNGSEL)

#define LL_RCC_RNG_CLKSOURCE             RCC_D2CCIP2R_RNGSEL

#else

#define LL_RCC_RNG_CLKSOURCE             RCC_CDCCIP2R_RNGSEL

#endif /* RCC_D2CCIP2R_RNGSEL */

#if (RCC_D2CCIP2R_USBSEL)

#define LL_RCC_USB_CLKSOURCE             RCC_D2CCIP2R_USBSEL

#else

#define LL_RCC_USB_CLKSOURCE             RCC_CDCCIP2R_USBSEL

#endif  /* RCC_D2CCIP2R_USBSEL */

#if (RCC_D2CCIP2R_CECSEL)

#define LL_RCC_CEC_CLKSOURCE             RCC_D2CCIP2R_CECSEL

#else

#define LL_RCC_CEC_CLKSOURCE             RCC_CDCCIP2R_CECSEL

#endif /* RCC_D2CCIP2R_CECSEL */

#if defined(DSI)

#define LL_RCC_DSI_CLKSOURCE             RCC_D1CCIPR_DSISEL

#endif /* DSI */


#if defined(RCC_D2CCIP1R_DFSDM1SEL)

#define LL_RCC_DFSDM1_CLKSOURCE          RCC_D2CCIP1R_DFSDM1SEL

#else

#define LL_RCC_DFSDM1_CLKSOURCE          RCC_CDCCIP1R_DFSDM1SEL

#endif /* RCC_D2CCIP1R_DFSDM1SEL */

#if defined(DFSDM2_BASE)

#define LL_RCC_DFSDM2_CLKSOURCE          RCC_SRDCCIPR_DFSDM2SEL

#endif /* DFSDM2_BASE */


#if defined(RCC_D1CCIPR_FMCSEL)

#define LL_RCC_FMC_CLKSOURCE             RCC_D1CCIPR_FMCSEL

#else

#define LL_RCC_FMC_CLKSOURCE             RCC_CDCCIPR_FMCSEL

#endif

#if defined(QUADSPI)

#define LL_RCC_QSPI_CLKSOURCE            RCC_D1CCIPR_QSPISEL

#endif /* QUADSPI */


#if defined(OCTOSPI1) || defined(OCTOSPI2)

#if defined(RCC_CDCCIPR_OCTOSPISEL)

#define LL_RCC_OSPI_CLKSOURCE            RCC_CDCCIPR_OCTOSPISEL

#else

#define LL_RCC_OSPI_CLKSOURCE            RCC_D1CCIPR_OCTOSPISEL

#endif /* RCC_CDCCIPR_OCTOSPISEL */

#endif /* OCTOSPI1 || OCTOSPI2 */


#if defined(RCC_D1CCIPR_CKPERSEL)

#define LL_RCC_CLKP_CLKSOURCE            RCC_D1CCIPR_CKPERSEL

#else

#define LL_RCC_CLKP_CLKSOURCE            RCC_CDCCIPR_CKPERSEL

#endif /* RCC_D1CCIPR_CKPERSEL */

#if defined(RCC_D2CCIP1R_SPI123SEL)

#define LL_RCC_SPI123_CLKSOURCE          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)

#else

#define LL_RCC_SPI123_CLKSOURCE          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)

#endif /* RCC_D2CCIP1R_SPI123SEL */

#if defined(RCC_D2CCIP1R_SPI45SEL)

#define LL_RCC_SPI45_CLKSOURCE           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  0x00000000U)

#else

#define LL_RCC_SPI45_CLKSOURCE           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  0x00000000U)

#endif /* RCC_D2CCIP1R_SPI45SEL */

#if defined(RCC_D3CCIPR_SPI6SEL)

#define LL_RCC_SPI6_CLKSOURCE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    0x00000000U)

#else

#define LL_RCC_SPI6_CLKSOURCE            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,   RCC_SRDCCIPR_SPI6SEL_Pos,  0x00000000U)

#endif /* RCC_D3CCIPR_SPI6SEL */

#if defined(RCC_D2CCIP1R_SPDIFSEL)

#define LL_RCC_SPDIF_CLKSOURCE           RCC_D2CCIP1R_SPDIFSEL

#else

#define LL_RCC_SPDIF_CLKSOURCE           RCC_CDCCIP1R_SPDIFSEL

#endif /* RCC_D2CCIP1R_SPDIFSEL */

#if defined(FDCAN1) || defined(FDCAN2)

#if defined(RCC_D2CCIP1R_FDCANSEL)

#define LL_RCC_FDCAN_CLKSOURCE           RCC_D2CCIP1R_FDCANSEL

#else

#define LL_RCC_FDCAN_CLKSOURCE           RCC_CDCCIP1R_FDCANSEL

#endif

#endif /*FDCAN1 || FDCAN2*/


#if defined(RCC_D2CCIP1R_SWPSEL)

#define LL_RCC_SWP_CLKSOURCE             RCC_D2CCIP1R_SWPSEL

#else

#define LL_RCC_SWP_CLKSOURCE             RCC_CDCCIP1R_SWPSEL

#endif /* RCC_D2CCIP1R_SWPSEL */

#if defined(RCC_D3CCIPR_ADCSEL)

#define LL_RCC_ADC_CLKSOURCE             RCC_D3CCIPR_ADCSEL

#else

#define LL_RCC_ADC_CLKSOURCE             RCC_SRDCCIPR_ADCSEL

#endif /* RCC_D3CCIPR_ADCSEL */

#define LL_RCC_RTC_CLKSOURCE_NONE          (uint32_t)(0x00000000U)

#define LL_RCC_RTC_CLKSOURCE_LSE           (uint32_t)(RCC_BDCR_RTCSEL_0)

#define LL_RCC_RTC_CLKSOURCE_LSI           (uint32_t)(RCC_BDCR_RTCSEL_1)

#define LL_RCC_RTC_CLKSOURCE_HSE           (uint32_t)(RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1)

#define LL_RCC_TIM_PRESCALER_TWICE          (uint32_t)(0x00000000U)

#define LL_RCC_TIM_PRESCALER_FOUR_TIMES     (uint32_t)(RCC_CFGR_TIMPRE)

#if defined(HRTIM1)

#define LL_RCC_HRTIM_CLKSOURCE_TIM          (uint32_t)(0x00000000U)           /* HRTIM Clock source is same as other timers */

#define LL_RCC_HRTIM_CLKSOURCE_CPU          (uint32_t)(RCC_CFGR_HRTIMSEL)     /* HRTIM Clock source is the CPU clock */

#endif /* HRTIM1 */


#define LL_RCC_PLLSOURCE_HSI               RCC_PLLCKSELR_PLLSRC_HSI

#define LL_RCC_PLLSOURCE_CSI               RCC_PLLCKSELR_PLLSRC_CSI

#define LL_RCC_PLLSOURCE_HSE               RCC_PLLCKSELR_PLLSRC_HSE

#define LL_RCC_PLLSOURCE_NONE              RCC_PLLCKSELR_PLLSRC_NONE

#define LL_RCC_PLLINPUTRANGE_1_2           (uint32_t)(0x00000000U)

#define LL_RCC_PLLINPUTRANGE_2_4           (uint32_t)(0x00000001)

#define LL_RCC_PLLINPUTRANGE_4_8           (uint32_t)(0x00000002)

#define LL_RCC_PLLINPUTRANGE_8_16          (uint32_t)(0x00000003)

#define LL_RCC_PLLVCORANGE_WIDE            (uint32_t)(0x00000000U)      /* VCO output range: 192 to 836 MHz   OR  128 to 544 MHz (*) */

#define LL_RCC_PLLVCORANGE_MEDIUM          (uint32_t)(0x00000001)       /* VCO output range: 150 to 420 MHz */

/* Exported macro ------------------------------------------------------------*/

#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))


#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)

#if defined(RCC_D1CFGR_D1CPRE)

#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >>  RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU))

#else

#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU))

#endif /* RCC_D1CFGR_D1CPRE */


#if defined(RCC_D1CFGR_HPRE)

#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >>  RCC_D1CFGR_HPRE_Pos]) & 0x1FU))

#else

#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >>  RCC_CDCFGR1_HPRE_Pos]) & 0x1FU))

#endif  /* RCC_D1CFGR_HPRE */


#if defined(RCC_D2CFGR_D2PPRE1)

#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >>  RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU))

#else

#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >>  RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU))

#endif /* RCC_D2CFGR_D2PPRE1 */


#if defined(RCC_D2CFGR_D2PPRE2)

#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >>  RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU))

#else

#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU))

#endif /* RCC_D2CFGR_D2PPRE2 */


#if defined(RCC_D1CFGR_D1PPRE)

#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >>  RCC_D1CFGR_D1PPRE_Pos]) & 0x1FU))

#else

#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos]) & 0x1FU))

#endif /* RCC_D1CFGR_D1PPRE */


#if defined(RCC_D3CFGR_D3PPRE)

#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >>  RCC_D3CFGR_D3PPRE_Pos]) & 0x1FU))

#else

#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >>  RCC_SRDCFGR_SRDPPRE_Pos]) & 0x1FU))

#endif /* RCC_D3CFGR_D3PPRE */


#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)

#define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U

#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU

#endif /* USE_FULL_LL_DRIVER */


/* Exported functions --------------------------------------------------------*/

__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)

{

  SET_BIT(RCC->CR, RCC_CR_CSSHSEON);

}


__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)

{

  SET_BIT(RCC->CR, RCC_CR_HSEBYP);

}


__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)

{

  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);

}


#if defined(RCC_CR_HSEEXT)

__STATIC_INLINE void LL_RCC_HSE_SelectAnalogClock(void)

{

  CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);

}


__STATIC_INLINE void LL_RCC_HSE_SelectDigitalClock(void)

{

  SET_BIT(RCC->CR, RCC_CR_HSEEXT);

}

#endif /* RCC_CR_HSEEXT */


__STATIC_INLINE void LL_RCC_HSE_Enable(void)

{

  SET_BIT(RCC->CR, RCC_CR_HSEON);

}


__STATIC_INLINE void LL_RCC_HSE_Disable(void)

{

  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);

}


__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)

{

  return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);

}


__STATIC_INLINE void LL_RCC_HSI_Enable(void)

{

  SET_BIT(RCC->CR, RCC_CR_HSION);

}


__STATIC_INLINE void LL_RCC_HSI_Disable(void)

{

  CLEAR_BIT(RCC->CR, RCC_CR_HSION);

}


__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)

{

  return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void)

{

  return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF)) ? 1UL : 0UL);

}


__STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider)

{

  MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider);

}


__STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void)

{

  return (READ_BIT(RCC->CR, RCC_CR_HSIDIV));

}


__STATIC_INLINE void LL_RCC_HSI_EnableStopMode(void)

{

  SET_BIT(RCC->CR, RCC_CR_HSIKERON);

}


__STATIC_INLINE void LL_RCC_HSI_DisableStopMode(void)

{

  CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);

}


__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)

{

  return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos);

}


__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)

{

#if defined(RCC_VER_X)

  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)

  {

    /* STM32H7 Rev.Y */

    MODIFY_REG(RCC->HSICFGR, 0x3F000U, Value << 12U);

  }

  else

  {

    /* STM32H7 Rev.V */

    MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);

  }

#else

  MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);

#endif /* RCC_VER_X */

}


__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)

{

#if defined(RCC_VER_X)

  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)

  {

    /* STM32H7 Rev.Y */

    return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3F000U) >> 12U);

  }

  else

  {

    /* STM32H7 Rev.V */

    return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);

  }

#else

  return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);

#endif /* RCC_VER_X */

}


__STATIC_INLINE void LL_RCC_CSI_Enable(void)

{

  SET_BIT(RCC->CR, RCC_CR_CSION);

}


__STATIC_INLINE void LL_RCC_CSI_Disable(void)

{

  CLEAR_BIT(RCC->CR, RCC_CR_CSION);

}


__STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void)

{

  return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY)) ? 1UL : 0UL);

}


__STATIC_INLINE void LL_RCC_CSI_EnableStopMode(void)

{

  SET_BIT(RCC->CR, RCC_CR_CSIKERON);

}


__STATIC_INLINE void LL_RCC_CSI_DisableStopMode(void)

{

  CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON);

}


__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void)

{

#if defined(RCC_VER_X)

  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)

  {

    /* STM32H7 Rev.Y */

    return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3FC0000U) >> 18U);

  }

  else

  {

    /* STM32H7 Rev.V */

    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);

  }

#else

  return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);

#endif /* RCC_VER_X */

}


__STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value)

{

#if defined(RCC_VER_X)

  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)

  {

    /* STM32H7 Rev.Y */

    MODIFY_REG(RCC->HSICFGR, 0x7C000000U, Value << 26U);

  }

  else

  {

    /* STM32H7 Rev.V */

    MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);

  }

#else

  MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);

#endif /* RCC_VER_X */

}


__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void)

{

#if defined(RCC_VER_X)

  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)

  {

    /* STM32H7 Rev.Y */

    return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x7C000000U) >> 26U);

  }

  else

  {

    /* STM32H7 Rev.V */

    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);

  }

#else

  return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);

#endif /* RCC_VER_X */

}


__STATIC_INLINE void LL_RCC_HSI48_Enable(void)

{

  SET_BIT(RCC->CR, RCC_CR_HSI48ON);

}


__STATIC_INLINE void LL_RCC_HSI48_Disable(void)

{

  CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);

}


__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)

{

  return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == (RCC_CR_HSI48RDY)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)

{

  return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);

}

#if defined(RCC_CR_D1CKRDY)


__STATIC_INLINE uint32_t LL_RCC_D1CK_IsReady(void)

{

  return ((READ_BIT(RCC->CR, RCC_CR_D1CKRDY) == (RCC_CR_D1CKRDY)) ? 1UL : 0UL);

}


#else


__STATIC_INLINE uint32_t LL_RCC_CPUCK_IsReady(void)

{

  return ((READ_BIT(RCC->CR, RCC_CR_CPUCKRDY) == (RCC_CR_CPUCKRDY)) ? 1UL : 0UL);

}

/* alias */

#define LL_RCC_D1CK_IsReady  LL_RCC_CPUCK_IsReady

#endif /* RCC_CR_D1CKRDY */


#if defined(RCC_CR_D2CKRDY)


__STATIC_INLINE uint32_t LL_RCC_D2CK_IsReady(void)

{

  return ((READ_BIT(RCC->CR, RCC_CR_D2CKRDY) == (RCC_CR_D2CKRDY)) ? 1UL : 0UL);

}

#else


__STATIC_INLINE uint32_t LL_RCC_CDCK_IsReady(void)

{

  return ((READ_BIT(RCC->CR, RCC_CR_CDCKRDY) == (RCC_CR_CDCKRDY)) ? 1UL : 0UL);

}

#define LL_RCC_D2CK_IsReady LL_RCC_CDCK_IsReady

#endif /* RCC_CR_D2CKRDY */


#if defined(RCC_GCR_WW1RSC)


__STATIC_INLINE void LL_RCC_WWDG1_EnableSystemReset(void)

{

  SET_BIT(RCC->GCR, RCC_GCR_WW1RSC);

}


__STATIC_INLINE uint32_t LL_RCC_WWDG1_IsSystemReset(void)

{

  return ((READ_BIT(RCC->GCR, RCC_GCR_WW1RSC) == RCC_GCR_WW1RSC) ? 1UL : 0UL);

}

#endif  /* RCC_GCR_WW1RSC */


#if defined(DUAL_CORE)

__STATIC_INLINE void LL_RCC_WWDG2_EnableSystemReset(void)

{

  SET_BIT(RCC->GCR, RCC_GCR_WW2RSC);

}


__STATIC_INLINE uint32_t LL_RCC_WWDG2_IsSystemReset(void)

{

  return ((READ_BIT(RCC->GCR, RCC_GCR_WW2RSC) == RCC_GCR_WW2RSC) ? 1UL : 0UL);

}

#endif  /*DUAL_CORE*/

#if defined(DUAL_CORE)

__STATIC_INLINE void LL_RCC_ForceCM4Boot(void)

{

  SET_BIT(RCC->GCR, RCC_GCR_BOOT_C2);

}


__STATIC_INLINE uint32_t LL_RCC_IsCM4BootForced(void)

{

  return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C2) == RCC_GCR_BOOT_C2) ? 1UL : 0UL);

}


__STATIC_INLINE void LL_RCC_ForceCM7Boot(void)

{

  SET_BIT(RCC->GCR, RCC_GCR_BOOT_C1);

}


__STATIC_INLINE uint32_t LL_RCC_IsCM7BootForced(void)

{

  return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C1) == RCC_GCR_BOOT_C1) ? 1UL : 0UL);

}


#endif  /*DUAL_CORE*/


__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)

{

  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);

}


__STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void)

{

  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL);

}


__STATIC_INLINE void LL_RCC_LSE_Enable(void)

{

  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);

}


__STATIC_INLINE void LL_RCC_LSE_Disable(void)

{

  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);

}


__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)

{

  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);

}


__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)

{

  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);

}


#if defined(RCC_BDCR_LSEEXT)

__STATIC_INLINE void LL_RCC_LSE_SelectDigitalClock(void)

{

  SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);

}


__STATIC_INLINE void LL_RCC_LSE_SelectAnalogClock(void)

{

  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);

}

#endif /* RCC_BDCR_LSEEXT */


__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)

{

  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);

}


__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)

{

  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));

}


__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)

{

  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);

}


__STATIC_INLINE void LL_RCC_LSI_Enable(void)

{

  SET_BIT(RCC->CSR, RCC_CSR_LSION);

}


__STATIC_INLINE void LL_RCC_LSI_Disable(void)

{

  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);

}


__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)

{

  return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL);

}


__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)

{

  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);

}


__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)

{

  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));

}


__STATIC_INLINE void LL_RCC_SetSysWakeUpClkSource(uint32_t Source)

{

  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Source);

}


__STATIC_INLINE uint32_t LL_RCC_GetSysWakeUpClkSource(void)

{

  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));

}


__STATIC_INLINE void LL_RCC_SetKerWakeUpClkSource(uint32_t Source)

{

  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, Source);

}


__STATIC_INLINE uint32_t LL_RCC_GetKerWakeUpClkSource(void)

{

  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPKERWUCK));

}


__STATIC_INLINE void LL_RCC_SetSysPrescaler(uint32_t Prescaler)

{

#if defined(RCC_D1CFGR_D1CPRE)

  MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, Prescaler);

#else

  MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, Prescaler);

#endif /* RCC_D1CFGR_D1CPRE */

}


__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)

{

#if defined(RCC_D1CFGR_HPRE)

  MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, Prescaler);

#else

  MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, Prescaler);

#endif /* RCC_D1CFGR_HPRE */

}


__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)

{

#if defined(RCC_D2CFGR_D2PPRE1)

  MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, Prescaler);

#else

  MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, Prescaler);

#endif /* RCC_D2CFGR_D2PPRE1 */

}


__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)

{

#if defined(RCC_D2CFGR_D2PPRE2)

  MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, Prescaler);

#else

  MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, Prescaler);

#endif /* RCC_D2CFGR_D2PPRE2 */

}


__STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler)

{

#if defined(RCC_D1CFGR_D1PPRE)

  MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, Prescaler);

#else

  MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, Prescaler);

#endif /* RCC_D1CFGR_D1PPRE */

}


__STATIC_INLINE void LL_RCC_SetAPB4Prescaler(uint32_t Prescaler)

{

#if defined(RCC_D3CFGR_D3PPRE)

  MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, Prescaler);

#else

  MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, Prescaler);

#endif /* RCC_D3CFGR_D3PPRE */

}


__STATIC_INLINE uint32_t LL_RCC_GetSysPrescaler(void)

{

#if defined(RCC_D1CFGR_D1CPRE)

  return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1CPRE));

#else

  return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE));

#endif /* RCC_D1CFGR_D1CPRE */

}


__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)

{

#if defined(RCC_D1CFGR_HPRE)

  return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_HPRE));

#else

  return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_HPRE));

#endif /* RCC_D1CFGR_HPRE */

}


__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)

{

#if defined(RCC_D2CFGR_D2PPRE1)

  return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1));

#else

  return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1));

#endif /* RCC_D2CFGR_D2PPRE1 */

}


__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)

{

#if defined(RCC_D2CFGR_D2PPRE2)

  return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2));

#else

  return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2));

#endif /* RCC_D2CFGR_D2PPRE2 */

}


__STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void)

{

#if defined(RCC_D1CFGR_D1PPRE)

  return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1PPRE));

#else

  return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE));

#endif /* RCC_D1CFGR_D1PPRE */

}


__STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void)

{

#if defined(RCC_D3CFGR_D3PPRE)

  return (uint32_t)(READ_BIT(RCC->D3CFGR, RCC_D3CFGR_D3PPRE));

#else

  return (uint32_t)(READ_BIT(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE));

#endif /* RCC_D3CFGR_D3PPRE */

}


__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)

{

  MODIFY_REG(RCC->CFGR, (MCOxSource << 16U) | (MCOxPrescaler << 16U), (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U));

}


__STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource)

{

#if defined(RCC_D1CCIPR_FMCSEL)

  uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource));

#else

  uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->CDCCIPR + LL_CLKSOURCE_REG(ClkSource));

#endif /*  */

  MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource));

}


__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t ClkSource)

{

  LL_RCC_SetClockSource(ClkSource);

}


__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t ClkSource)

{

#if defined(RCC_D3CCIPR_LPUART1SEL)

  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, ClkSource);

#else

  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, ClkSource);

#endif /* RCC_D3CCIPR_LPUART1SEL */

}


__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t ClkSource)

{

  LL_RCC_SetClockSource(ClkSource);

}


__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource)

{

  LL_RCC_SetClockSource(ClkSource);

}


__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t ClkSource)

{

  LL_RCC_SetClockSource(ClkSource);

}


__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t ClkSource)

{

#if defined(RCC_D1CCIPR_SDMMCSEL)

  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, ClkSource);

#else

  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, ClkSource);

#endif /* RCC_D1CCIPR_SDMMCSEL */

}


__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t ClkSource)

{

#if defined(RCC_D2CCIP2R_RNGSEL)

  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, ClkSource);

#else

  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, ClkSource);

#endif /* RCC_D2CCIP2R_RNGSEL */

}


__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t ClkSource)

{

#if defined(RCC_D2CCIP2R_USBSEL)

  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, ClkSource);

#else

  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, ClkSource);

#endif /* RCC_D2CCIP2R_USBSEL */

}


__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t ClkSource)

{

#if defined(RCC_D2CCIP2R_CECSEL)

  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, ClkSource);

#else

  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, ClkSource);

#endif /* RCC_D2CCIP2R_CECSEL */

}


#if defined(DSI)

__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t ClkSource)

{

  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, ClkSource);

}

#endif /* DSI */


__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t ClkSource)

{

#if defined(RCC_D2CCIP1R_DFSDM1SEL)

  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, ClkSource);

#else

  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, ClkSource);

#endif /* RCC_D2CCIP1R_DFSDM1SEL */

}


#if defined(DFSDM2_BASE)

__STATIC_INLINE void LL_RCC_SetDFSDM2ClockSource(uint32_t ClkSource)

{

  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, ClkSource);

}

#endif /* DFSDM2_BASE */


__STATIC_INLINE void LL_RCC_SetFMCClockSource(uint32_t ClkSource)

{

#if defined(RCC_D1CCIPR_FMCSEL)

  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, ClkSource);

#else

  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, ClkSource);

#endif /* RCC_D1CCIPR_FMCSEL */

}


#if defined(QUADSPI)

__STATIC_INLINE void LL_RCC_SetQSPIClockSource(uint32_t ClkSource)

{

  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, ClkSource);

}

#endif /* QUADSPI */


#if defined(OCTOSPI1) || defined(OCTOSPI2)

__STATIC_INLINE void LL_RCC_SetOSPIClockSource(uint32_t ClkSource)

{

#if defined(RCC_D1CCIPR_OCTOSPISEL)

  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, ClkSource);

#else

  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, ClkSource);

#endif /* RCC_D1CCIPR_OCTOSPISEL */

}

#endif /* OCTOSPI1 || OCTOSPI2 */


__STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource)

{

#if defined(RCC_D1CCIPR_CKPERSEL)

  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, ClkSource);

#else

  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, ClkSource);

#endif /* RCC_D1CCIPR_CKPERSEL */

}


__STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t ClkSource)

{

  LL_RCC_SetClockSource(ClkSource);

}


__STATIC_INLINE void LL_RCC_SetSPDIFClockSource(uint32_t ClkSource)

{

#if defined(RCC_D2CCIP1R_SPDIFSEL)

  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, ClkSource);

#else

  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, ClkSource);

#endif /* RCC_D2CCIP1R_SPDIFSEL */

}


__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t ClkSource)

{

#if defined(RCC_D2CCIP1R_FDCANSEL)

  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, ClkSource);

#else

  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, ClkSource);

#endif /* RCC_D2CCIP1R_FDCANSEL */

}


__STATIC_INLINE void LL_RCC_SetSWPClockSource(uint32_t ClkSource)

{

#if defined(RCC_D2CCIP1R_SWPSEL)

  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, ClkSource);

#else

  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, ClkSource);

#endif /* RCC_D2CCIP1R_SWPSEL */

}


__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ClkSource)

{

#if defined(RCC_D3CCIPR_ADCSEL)

  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, ClkSource);

#else

  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, ClkSource);

#endif /* RCC_D3CCIPR_ADCSEL */

}


__STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph)

{

#if defined(RCC_D1CCIPR_FMCSEL)

  const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->D1CCIPR) + LL_CLKSOURCE_REG(Periph)));

#else

  const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CDCCIPR) + LL_CLKSOURCE_REG(Periph)));

#endif /* RCC_D1CCIPR_FMCSEL */

  return (uint32_t)(Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT));

}


__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t Periph)

{

  return LL_RCC_GetClockSource(Periph);

}


__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t Periph)

{

  UNUSED(Periph);

#if defined(RCC_D3CCIPR_LPUART1SEL)

  return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL));

#else

  return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL));

#endif  /* RCC_D3CCIPR_LPUART1SEL */

}


__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph)

{

  return LL_RCC_GetClockSource(Periph);

}


__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph)

{

  return LL_RCC_GetClockSource(Periph);

}


__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph)

{

  return LL_RCC_GetClockSource(Periph);

}


__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t Periph)

{

  UNUSED(Periph);

#if defined(RCC_D1CCIPR_SDMMCSEL)

  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL));

#else

  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL));

#endif /* RCC_D1CCIPR_SDMMCSEL */

}


__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t Periph)

{

  UNUSED(Periph);

#if defined(RCC_D2CCIP2R_RNGSEL)

  return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL));

#else

  return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL));

#endif /* RCC_D2CCIP2R_RNGSEL */

}


__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t Periph)

{

  UNUSED(Periph);

#if defined(RCC_D2CCIP2R_USBSEL)

  return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL));

#else

  return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL));

#endif /* RCC_D2CCIP2R_USBSEL */

}


__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t Periph)

{

  UNUSED(Periph);

#if defined(RCC_D2CCIP2R_CECSEL)

  return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL));

#else

  return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL));

#endif  /* RCC_D2CCIP2R_CECSEL */

}


#if defined(DSI)

__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t Periph)

{

  UNUSED(Periph);

  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL));

}

#endif /* DSI */


__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t Periph)

{

  UNUSED(Periph);

#if defined(RCC_D2CCIP1R_DFSDM1SEL)

  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL));

#else

  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL));

#endif /* RCC_D2CCIP1R_DFSDM1SEL */

}


#if defined(DFSDM2_BASE)

__STATIC_INLINE uint32_t LL_RCC_GetDFSDM2ClockSource(uint32_t Periph)

{

  UNUSED(Periph);

  return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL));

}

#endif /* DFSDM2_BASE */


__STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource(uint32_t Periph)

{

  UNUSED(Periph);

#if defined(RCC_D1CCIPR_FMCSEL)

  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL));

#else

  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL));

#endif /* RCC_D1CCIPR_FMCSEL */

}


#if defined(QUADSPI)

__STATIC_INLINE uint32_t LL_RCC_GetQSPIClockSource(uint32_t Periph)

{

  UNUSED(Periph);

  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL));

}

#endif /* QUADSPI */


#if defined(OCTOSPI1) || defined(OCTOSPI2)

__STATIC_INLINE uint32_t LL_RCC_GetOSPIClockSource(uint32_t Periph)

{

  UNUSED(Periph);

#if defined(RCC_D1CCIPR_OCTOSPISEL)

  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL));

#else

  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL));

#endif /* RCC_D1CCIPR_OCTOSPISEL */

}

#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */


__STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t Periph)

{

  UNUSED(Periph);

#if defined(RCC_D1CCIPR_CKPERSEL)

  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL));

#else

  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL));

#endif /* RCC_D1CCIPR_CKPERSEL */

}


__STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph)

{

  return LL_RCC_GetClockSource(Periph);

}


__STATIC_INLINE uint32_t LL_RCC_GetSPDIFClockSource(uint32_t Periph)

{

  UNUSED(Periph);

#if defined(RCC_D2CCIP1R_SPDIFSEL)

  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL));

#else

  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL));

#endif /* RCC_D2CCIP1R_SPDIFSEL */

}


__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph)

{

  UNUSED(Periph);

#if defined(RCC_D2CCIP1R_FDCANSEL)

  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL));

#else

  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL));

#endif /* RCC_D2CCIP1R_FDCANSEL */

}


__STATIC_INLINE uint32_t LL_RCC_GetSWPClockSource(uint32_t Periph)

{

  UNUSED(Periph);

#if defined(RCC_D2CCIP1R_SWPSEL)

  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL));

#else

  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL));

#endif /* RCC_D2CCIP1R_SWPSEL */

}


__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t Periph)

{

  UNUSED(Periph);

#if defined (RCC_D3CCIPR_ADCSEL)

  return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL));

#else

  return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL));

#endif /* RCC_D3CCIPR_ADCSEL */

}


__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)

{

  MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);

}


__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)

{

  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));

}


__STATIC_INLINE void LL_RCC_EnableRTC(void)

{

  SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);

}


__STATIC_INLINE void LL_RCC_DisableRTC(void)

{

  CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);

}


__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)

{

  return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL);

}


__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)

{

  SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);

}


__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)

{

#if defined(RCC_BDCR_BDRST)

  CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);

#else

  CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST);

#endif /* RCC_BDCR_BDRST */

}


__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)

{

  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);

}


__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)

{

  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));

}


__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)

{

  MODIFY_REG(RCC->CFGR, RCC_CFGR_TIMPRE, Prescaler);

}


__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)

{

  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_TIMPRE));

}


#if defined(HRTIM1)

__STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t Prescaler)

{

  MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, Prescaler);

}

#endif /* HRTIM1 */


#if defined(HRTIM1)

__STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(void)

{

  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL));

}

#endif /* HRTIM1 */


__STATIC_INLINE void LL_RCC_PLL_SetSource(uint32_t PLLSource)

{

  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, PLLSource);

}


__STATIC_INLINE uint32_t LL_RCC_PLL_GetSource(void)

{

  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC));

}


__STATIC_INLINE void LL_RCC_PLL1_Enable(void)

{

  SET_BIT(RCC->CR, RCC_CR_PLL1ON);

}


__STATIC_INLINE void LL_RCC_PLL1_Disable(void)

{

  CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);

}


__STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)

{

  return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == (RCC_CR_PLL1RDY)) ? 1UL : 0UL);

}


__STATIC_INLINE void LL_RCC_PLL1P_Enable(void)

{

  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);

}


__STATIC_INLINE void LL_RCC_PLL1Q_Enable(void)

{

  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);

}


__STATIC_INLINE void LL_RCC_PLL1R_Enable(void)

{

  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);

}


__STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void)

{

  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);

}


__STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void)

{

  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN) == RCC_PLLCFGR_DIVP1EN) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void)

{

  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN) == RCC_PLLCFGR_DIVQ1EN) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void)

{

  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN) == RCC_PLLCFGR_DIVR1EN) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void)

{

  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) == RCC_PLLCFGR_PLL1FRACEN) ? 1UL : 0UL);

}


__STATIC_INLINE void LL_RCC_PLL1P_Disable(void)

{

  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);

}


__STATIC_INLINE void LL_RCC_PLL1Q_Disable(void)

{

  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);

}


__STATIC_INLINE void LL_RCC_PLL1R_Disable(void)

{

  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);

}


__STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void)

{

  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);

}


__STATIC_INLINE void LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange)

{

  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, VCORange << RCC_PLLCFGR_PLL1VCOSEL_Pos);

}


__STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)

{

  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, InputRange << RCC_PLLCFGR_PLL1RGE_Pos);

}


__STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)

{

  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_N1) >>  RCC_PLL1DIVR_N1_Pos) + 1UL);

}


__STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void)

{

  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1) >>  RCC_PLLCKSELR_DIVM1_Pos);

}


__STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void)

{

  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_P1) >>  RCC_PLL1DIVR_P1_Pos) + 1UL);

}


__STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void)

{

  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1) >>  RCC_PLL1DIVR_Q1_Pos) + 1UL);

}


__STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void)

{

  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_R1) >>  RCC_PLL1DIVR_R1_Pos) + 1UL);

}


__STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)

{

  return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1) >>  RCC_PLL1FRACR_FRACN1_Pos);

}


__STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N)

{

  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1, (N - 1UL) << RCC_PLL1DIVR_N1_Pos);

}


__STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M)

{

  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1, M << RCC_PLLCKSELR_DIVM1_Pos);

}


__STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P)

{

  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P - 1UL) << RCC_PLL1DIVR_P1_Pos);

}


__STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t Q)

{

  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, (Q - 1UL) << RCC_PLL1DIVR_Q1_Pos);

}


__STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t R)

{

  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R - 1UL) << RCC_PLL1DIVR_R1_Pos);

}


__STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN)

{

  MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, FRACN << RCC_PLL1FRACR_FRACN1_Pos);

}


__STATIC_INLINE void LL_RCC_PLL2_Enable(void)

{

  SET_BIT(RCC->CR, RCC_CR_PLL2ON);

}


__STATIC_INLINE void LL_RCC_PLL2_Disable(void)

{

  CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);

}


__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)

{

  return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY)) ? 1UL : 0UL);

}


__STATIC_INLINE void LL_RCC_PLL2P_Enable(void)

{

  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);

}


__STATIC_INLINE void LL_RCC_PLL2Q_Enable(void)

{

  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);

}


__STATIC_INLINE void LL_RCC_PLL2R_Enable(void)

{

  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);

}


__STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void)

{

  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);

}


__STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void)

{

  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN) == RCC_PLLCFGR_DIVP2EN) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void)

{

  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN) == RCC_PLLCFGR_DIVQ2EN) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void)

{

  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN) == RCC_PLLCFGR_DIVR2EN) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void)

{

  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) == RCC_PLLCFGR_PLL2FRACEN) ? 1UL : 0UL);

}


__STATIC_INLINE void LL_RCC_PLL2P_Disable(void)

{

  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);

}


__STATIC_INLINE void LL_RCC_PLL2Q_Disable(void)

{

  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);

}


__STATIC_INLINE void LL_RCC_PLL2R_Disable(void)

{

  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);

}


__STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void)

{

  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);

}


__STATIC_INLINE void LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange)

{

  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, VCORange << RCC_PLLCFGR_PLL2VCOSEL_Pos);

}


__STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange)

{

  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, InputRange << RCC_PLLCFGR_PLL2RGE_Pos);

}


__STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void)

{

  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_N2) >>  RCC_PLL2DIVR_N2_Pos) + 1UL);

}


__STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void)

{

  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2) >>  RCC_PLLCKSELR_DIVM2_Pos);

}


__STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void)

{

  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_P2) >>  RCC_PLL2DIVR_P2_Pos) + 1UL);

}


__STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void)

{

  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2) >>  RCC_PLL2DIVR_Q2_Pos) + 1UL);

}


__STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void)

{

  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_R2) >>  RCC_PLL2DIVR_R2_Pos) + 1UL);

}


__STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void)

{

  return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2) >>  RCC_PLL2FRACR_FRACN2_Pos);

}


__STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N)

{

  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, (N - 1UL) << RCC_PLL2DIVR_N2_Pos);

}


__STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M)

{

  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2, M << RCC_PLLCKSELR_DIVM2_Pos);

}


__STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t P)

{

  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, (P - 1UL) << RCC_PLL2DIVR_P2_Pos);

}


__STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t Q)

{

  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, (Q - 1UL) << RCC_PLL2DIVR_Q2_Pos);

}


__STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t R)

{

  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, (R - 1UL) << RCC_PLL2DIVR_R2_Pos);

}


__STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN)

{

  MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2, FRACN << RCC_PLL2FRACR_FRACN2_Pos);

}


__STATIC_INLINE void LL_RCC_PLL3_Enable(void)

{

  SET_BIT(RCC->CR, RCC_CR_PLL3ON);

}


__STATIC_INLINE void LL_RCC_PLL3_Disable(void)

{

  CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);

}


__STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void)

{

  return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY)) ? 1UL : 0UL);

}


__STATIC_INLINE void LL_RCC_PLL3P_Enable(void)

{

  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);

}


__STATIC_INLINE void LL_RCC_PLL3Q_Enable(void)

{

  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);

}


__STATIC_INLINE void LL_RCC_PLL3R_Enable(void)

{

  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);

}


__STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void)

{

  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);

}


__STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void)

{

  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN) == RCC_PLLCFGR_DIVP3EN) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void)

{

  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN) == RCC_PLLCFGR_DIVQ3EN) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void)

{

  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN) == RCC_PLLCFGR_DIVR3EN) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void)

{

  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) == RCC_PLLCFGR_PLL3FRACEN) ? 1UL : 0UL);

}


__STATIC_INLINE void LL_RCC_PLL3P_Disable(void)

{

  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);

}


__STATIC_INLINE void LL_RCC_PLL3Q_Disable(void)

{

  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);

}


__STATIC_INLINE void LL_RCC_PLL3R_Disable(void)

{

  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);

}


__STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void)

{

  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);

}


__STATIC_INLINE void LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange)

{

  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, VCORange << RCC_PLLCFGR_PLL3VCOSEL_Pos);

}


__STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange)

{

  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, InputRange << RCC_PLLCFGR_PLL3RGE_Pos);

}


__STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void)

{

  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_N3) >>  RCC_PLL3DIVR_N3_Pos) + 1UL);

}


__STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void)

{

  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3) >>  RCC_PLLCKSELR_DIVM3_Pos);

}


__STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void)

{

  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_P3) >>  RCC_PLL3DIVR_P3_Pos) + 1UL);

}


__STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void)

{

  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3) >>  RCC_PLL3DIVR_Q3_Pos) + 1UL);

}


__STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void)

{

  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_R3) >>  RCC_PLL3DIVR_R3_Pos) + 1UL);

}


__STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void)

{

  return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3) >>  RCC_PLL3FRACR_FRACN3_Pos);

}


__STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N)

{

  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, (N - 1UL) << RCC_PLL3DIVR_N3_Pos);

}


__STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M)

{

  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3, M << RCC_PLLCKSELR_DIVM3_Pos);

}


__STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t P)

{

  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, (P - 1UL) << RCC_PLL3DIVR_P3_Pos);

}


__STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t Q)

{

  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, (Q - 1UL) << RCC_PLL3DIVR_Q3_Pos);

}


__STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t R)

{

  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, (R - 1UL) << RCC_PLL3DIVR_R3_Pos);

}


__STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN)

{

  MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, FRACN << RCC_PLL3FRACR_FRACN3_Pos);

}


__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)

{

  SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);

}


__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)

{

  SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);

}


__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)

{

  SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);

}


__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)

{

  SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);

}


__STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY(void)

{

  SET_BIT(RCC->CICR, RCC_CICR_CSIRDYC);

}


__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)

{

  SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);

}


__STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)

{

  SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);

}


__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)

{

  SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC);

}


__STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void)

{

  SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC);

}


__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)

{

  SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);

}


__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)

{

  SET_BIT(RCC->CICR, RCC_CICR_HSECSSC);

}


__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)

{

  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)

{

  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)

{

  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)

{

  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void)

{

  return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == (RCC_CIFR_CSIRDYF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)

{

  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)

{

  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)

{

  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == (RCC_CIFR_PLL2RDYF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void)

{

  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == (RCC_CIFR_PLL3RDYF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)

{

  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)

{

  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == (RCC_CIFR_HSECSSF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)

{

#if defined(DUAL_CORE)

  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL);

#else

  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == (RCC_RSR_LPWRRSTF)) ? 1UL : 0UL);

#endif /*DUAL_CORE*/

}


#if defined(DUAL_CORE)

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWR2RST(void)

{

  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL);

}

#endif  /*DUAL_CORE*/


__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG1RST(void)

{

  return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL);

}


#if defined(DUAL_CORE)

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG2RST(void)

{

  return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL);

}

#endif  /*DUAL_CORE*/


__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG1RST(void)

{

  return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL);

}


#if defined(DUAL_CORE)

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG2RST(void)

{

  return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL);

}

#endif  /*DUAL_CORE*/


__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)

{

#if defined(DUAL_CORE)

  return ((READ_BIT(RCC->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL);

#else

  return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == (RCC_RSR_SFTRSTF)) ? 1UL : 0UL);

#endif  /*DUAL_CORE*/

}


#if defined(DUAL_CORE)

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFT2RST(void)

{

  return ((READ_BIT(RCC->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL);

}

#endif  /*DUAL_CORE*/


__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)

{

  return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)

{

  return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)

{

  return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL);

}


#if defined(RCC_RSR_D1RSTF)

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D1RST(void)

{

  return ((READ_BIT(RCC->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL);

}

#endif /* RCC_RSR_D1RSTF */


#if defined(RCC_RSR_CDRSTF)

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CDRST(void)

{

  return ((READ_BIT(RCC->RSR, RCC_RSR_CDRSTF) == (RCC_RSR_CDRSTF)) ? 1UL : 0UL);

}

#endif /* RCC_RSR_CDRSTF */


#if defined(RCC_RSR_D2RSTF)

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D2RST(void)

{

  return ((READ_BIT(RCC->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL);

}

#endif /* RCC_RSR_D2RSTF */


#if defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF)

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPURST(void)

{

#if defined(DUAL_CORE)

  return ((READ_BIT(RCC->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL);

#else

  return ((READ_BIT(RCC->RSR, RCC_RSR_CPURSTF) == (RCC_RSR_CPURSTF)) ? 1UL : 0UL);

#endif/*DUAL_CORE*/

}

#endif /* defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF) */


#if defined(DUAL_CORE)

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPU2RST(void)

{

  return ((READ_BIT(RCC->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL);

}

#endif  /*DUAL_CORE*/


__STATIC_INLINE void LL_RCC_ClearResetFlags(void)

{

  SET_BIT(RCC->RSR, RCC_RSR_RMVF);

}


#if defined(DUAL_CORE)

__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWRRST(void)

{

  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWR2RST(void)

{

  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG1RST(void)

{

  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG2RST(void)

{

  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG1RST(void)

{

  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG2RST(void)

{

  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFTRST(void)

{

  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFT2RST(void)

{

  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PORRST(void)

{

  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PINRST(void)

{

  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_BORRST(void)

{

  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D1RST(void)

{

  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D2RST(void)

{

  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPURST(void)

{

  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPU2RST(void)

{

  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE void LL_C1_RCC_ClearResetFlags(void)

{

  SET_BIT(RCC_C1->RSR, RCC_RSR_RMVF);

}


__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWRRST(void)

{

  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWR2RST(void)

{

  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG1RST(void)

{

  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG2RST(void)

{

  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG1RST(void)

{

  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG2RST(void)

{

  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFTRST(void)

{

  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFT2RST(void)

{

  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PORRST(void)

{

  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PINRST(void)

{

  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_BORRST(void)

{

  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D1RST(void)

{

  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D2RST(void)

{

  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPURST(void)

{

  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPU2RST(void)

{

  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL);

}


__STATIC_INLINE void LL_C2_RCC_ClearResetFlags(void)

{

  SET_BIT(RCC_C2->RSR, RCC_RSR_RMVF);

}

#endif /*DUAL_CORE*/


__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)

{

  SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);

}


__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)

{

  SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);

}


__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)

{

  SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);

}


__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)

{

  SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);

}


__STATIC_INLINE void LL_RCC_EnableIT_CSIRDY(void)

{

  SET_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);

}


__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)

{

  SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);

}


__STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)

{

  SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);

}


__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)

{

  SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);

}


__STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void)

{

  SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);

}


__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)

{

  SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);

}


__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)

{

  CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);

}


__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)

{

  CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);

}


__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)

{

  CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);

}


__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)

{

  CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);

}


__STATIC_INLINE void LL_RCC_DisableIT_CSIRDY(void)

{

  CLEAR_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);

}


__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)

{

  CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);

}


__STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)

{

  CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);

}


__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)

{

  CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);

}


__STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void)

{

  CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);

}


__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)

{

  CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);

}


__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY(void)

{

  return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY(void)

{

  return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY(void)

{

  return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY(void)

{

  return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY(void)

{

  return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY(void)

{

  return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY(void)

{

  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY(void)

{

  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY(void)

{

  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE) ? 1UL : 0UL);

}


__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSECSS(void)

{

  return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL);

}

#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)

void LL_RCC_DeInit(void);

uint32_t    LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR);


void        LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);

void        LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);

void        LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);

void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);


uint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);

uint32_t    LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);

uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);

uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);

uint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);

uint32_t    LL_RCC_GetADCClockFreq(uint32_t ADCxSource);

uint32_t    LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);

uint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);

uint32_t    LL_RCC_GetCECClockFreq(uint32_t CECxSource);

uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);

uint32_t    LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);

#if defined(DFSDM2_BASE)

uint32_t    LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource);

#endif /* DFSDM2_BASE */

#if defined(DSI)

uint32_t    LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);

#endif /* DSI */

uint32_t    LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource);

uint32_t    LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);

uint32_t    LL_RCC_GetSWPClockFreq(uint32_t SWPxSource);

uint32_t    LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);

uint32_t    LL_RCC_GetFMCClockFreq(uint32_t FMCxSource);

#if defined(QUADSPI)

uint32_t    LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource);

#endif /* QUADSPI */

#if defined(OCTOSPI1) || defined(OCTOSPI2)

uint32_t    LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource);

#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */

uint32_t    LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource);


#endif /* USE_FULL_LL_DRIVER */


#endif /* defined(RCC) */


#ifdef __cplusplus

}

#endif


#endif /* STM32H7xx_LL_RCC_H */


RCC_CR_CPUCKRDY
#define RCC_CR_CPUCKRDY
Definition: stm32h7a3xx.h:12539

RCC_CR_CSIRDY
#define RCC_CR_CSIRDY
Definition: stm32h723xx.h:14377

RCC_CDCFGR1_CDPPRE
#define RCC_CDCFGR1_CDPPRE
Definition: stm32h7a3xx.h:12784

RCC_D1CFGR_D1PPRE
#define RCC_D1CFGR_D1PPRE
Definition: stm32h723xx.h:14633

RCC_CDCFGR2_CDPPRE1
#define RCC_CDCFGR2_CDPPRE1
Definition: stm32h7a3xx.h:12841

RCC_CR_HSIDIV
#define RCC_CR_HSIDIV
Definition: stm32h723xx.h:14363

RCC_CR_PLL2RDY
#define RCC_CR_PLL2RDY
Definition: stm32h723xx.h:14420

RCC_CR_PLL2ON
#define RCC_CR_PLL2ON
Definition: stm32h723xx.h:14417

RCC_D1CFGR_D1CPRE
#define RCC_D1CFGR_D1CPRE
Definition: stm32h723xx.h:14654

RCC_CR_PLL1RDY
#define RCC_CR_PLL1RDY
Definition: stm32h723xx.h:14414

RCC_CFGR_HRTIMSEL
#define RCC_CFGR_HRTIMSEL
Definition: stm32h742xx.h:13892

RCC_CR_PLL3RDY
#define RCC_CR_PLL3RDY
Definition: stm32h723xx.h:14426

RCC_HSICFGR_HSITRIM
#define RCC_HSICFGR_HSITRIM
Definition: stm32h723xx.h:14457

RCC_CDCFGR2_CDPPRE2
#define RCC_CDCFGR2_CDPPRE2
Definition: stm32h7a3xx.h:12863

RCC_CR_PLL1ON
#define RCC_CR_PLL1ON
Definition: stm32h723xx.h:14411

RCC_CR_CDCKRDY
#define RCC_CR_CDCKRDY
Definition: stm32h7a3xx.h:12542

RCC_CSICFGR_CSICAL_Pos
#define RCC_CSICFGR_CSICAL_Pos
Definition: stm32h723xx.h:14487

RCC_CRRCR_HSI48CAL_Pos
#define RCC_CRRCR_HSI48CAL_Pos
Definition: stm32h723xx.h:14470

RCC_CFGR_STOPWUCK
#define RCC_CFGR_STOPWUCK
Definition: stm32h723xx.h:14539

RCC_CR_D1CKRDY
#define RCC_CR_D1CKRDY
Definition: stm32h723xx.h:14390

RCC_CFGR_TIMPRE
#define RCC_CFGR_TIMPRE
Definition: stm32h723xx.h:14560

RCC_CR_D2CKRDY
#define RCC_CR_D2CKRDY
Definition: stm32h723xx.h:14393

RCC_CDCFGR1_HPRE
#define RCC_CDCFGR1_HPRE
Definition: stm32h7a3xx.h:12749

RCC_CRRCR_HSI48CAL
#define RCC_CRRCR_HSI48CAL
Definition: stm32h723xx.h:14472

RCC_CR_PLL3ON
#define RCC_CR_PLL3ON
Definition: stm32h723xx.h:14423

RCC_CSICFGR_CSITRIM
#define RCC_CSICFGR_CSITRIM
Definition: stm32h723xx.h:14502

RCC_HSICFGR_HSICAL
#define RCC_HSICFGR_HSICAL
Definition: stm32h723xx.h:14440

RCC_HSICFGR_HSICAL_Pos
#define RCC_HSICFGR_HSICAL_Pos
Definition: stm32h723xx.h:14438

RCC_D3CFGR_D3PPRE
#define RCC_D3CFGR_D3PPRE
Definition: stm32h723xx.h:14735

RCC_D1CFGR_HPRE
#define RCC_D1CFGR_HPRE
Definition: stm32h723xx.h:14597

RCC_CR_HSIKERON
#define RCC_CR_HSIKERON
Definition: stm32h723xx.h:14357

RCC_D2CFGR_D2PPRE2
#define RCC_D2CFGR_D2PPRE2
Definition: stm32h723xx.h:14712

RCC_CSICFGR_CSICAL
#define RCC_CSICFGR_CSICAL
Definition: stm32h723xx.h:14489

RCC_CFGR_STOPKERWUCK
#define RCC_CFGR_STOPKERWUCK
Definition: stm32h723xx.h:14543

RCC_SRDCFGR_SRDPPRE
#define RCC_SRDCFGR_SRDPPRE
Definition: stm32h7a3xx.h:12886

RCC_CR_CSSHSEON
#define RCC_CR_CSSHSEON
Definition: stm32h723xx.h:14406

RCC_CR_HSI48ON
#define RCC_CR_HSI48ON
Definition: stm32h723xx.h:14383

RCC_CDCFGR1_CDCPRE
#define RCC_CDCFGR1_CDCPRE
Definition: stm32h7a3xx.h:12805

RCC_CR_HSI48RDY
#define RCC_CR_HSI48RDY
Definition: stm32h723xx.h:14386

RCC_D2CFGR_D2PPRE1
#define RCC_D2CFGR_D2PPRE1
Definition: stm32h723xx.h:14690

RCC_CR_CSION
#define RCC_CR_CSION
Definition: stm32h723xx.h:14374

RCC_CR_HSEEXT
#define RCC_CR_HSEEXT
Definition: stm32h7a3xx.h:12559

RCC_CR_CSIKERON
#define RCC_CR_CSIKERON
Definition: stm32h723xx.h:14380

RCC_CR_HSIDIVF
#define RCC_CR_HSIDIVF
Definition: stm32h723xx.h:14371

stm32h7xx.h
CMSIS STM32H7xx Device Peripheral Access Layer Header File.