RTEMS 6.1-rc6
Loading...
Searching...
No Matches
stm32h7xx_ll_dac.h
Go to the documentation of this file.
1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_LL_DAC_H
21#define STM32H7xx_LL_DAC_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx.h"
29
34#if defined(DAC1) || defined(DAC2)
35
41/* Private types -------------------------------------------------------------*/
42/* Private variables ---------------------------------------------------------*/
43
44/* Private constants ---------------------------------------------------------*/
50/* Internal masks for DAC channels definition */
51/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
52/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
53/* - channel bits position into register SWTRIG */
54/* - channel register offset of data holding register DHRx */
55/* - channel register offset of data output register DORx */
56/* - channel register offset of sample-and-hold sample time register SHSRx */
57#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
58 CR, MCR, CCR, SHHR, SHRR of channel 1 */
59#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
60 CR, MCR, CCR, SHHR, SHRR of channel 2 */
61#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
62
63#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
64#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
65#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
66
67#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
68#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
69 DHR12Rx channel 1 (shifted left of 20 bits) */
70#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
71 DHR12Rx channel 1 (shifted left of 24 bits) */
72
73#define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus
74 DHR12Rx channel 1 (shifted left of 28 bits) */
75#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
76 DHR12Rx channel 1 (shifted left of 20 bits) */
77#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
78 DHR12Rx channel 1 (shifted left of 24 bits) */
79
80#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
81#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
82#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
83#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
84 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
85
86#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
87
88#define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus
89 DORx channel 2 (shifted left of 5 bits) */
90#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
91
92#define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
93#define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus
94 SHSRx channel 2 (shifted left of 6 bits) */
95#define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
96
97
98#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
99 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
100#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
101 to position 0 */
102#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
103 to position 0 */
104
105#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx
106 channel 1 or 2 versus DHR12Rx channel 1
107 (shifted left of 28 bits) */
108#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
109 channel 1 or 2 versus DHR12Rx channel 1
110 (shifted left of 20 bits) */
111#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
112 channel 1 or 2 versus DHR12Rx channel 1
113 (shifted left of 24 bits) */
114#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx
115 channel 1 or 2 versus DORx channel 1
116 (shifted left of 5 bits) */
117#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx
118 channel 1 or 2 versus SHSRx channel 1
119 (shifted left of 6 bits) */
120
121/* DAC registers bits positions */
122#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
123#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
124#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
125
126/* Miscellaneous data */
127#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
128 bits (voltage range determined by analog voltage
129 references Vref+ and Vref-, refer to reference manual) */
130
136/* Private macros ------------------------------------------------------------*/
150#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
151 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
152
158/* Exported types ------------------------------------------------------------*/
159#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
168typedef struct
169{
170 uint32_t TriggerSource;
178 uint32_t WaveAutoGeneration;
184 uint32_t WaveAutoGenerationConfig;
197 uint32_t OutputBuffer;
203 uint32_t OutputConnection;
209 uint32_t OutputMode;
214} LL_DAC_InitTypeDef;
215
219#endif /* USE_FULL_LL_DRIVER */
220
221/* Exported constants --------------------------------------------------------*/
232/* DAC channel 1 flags */
233#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
234#define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1)
235#define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1)
237/* DAC channel 2 flags */
238#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
239#define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2)
240#define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2)
251#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1)
253#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2)
263#define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1)
264#define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2)
273#define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL
274#define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1)
283#define LL_DAC_TRIG_SOFTWARE 0x00000000U
284#define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0)
285#define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 )
286#define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
287#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 )
288#define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)
289#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )
290#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
291#define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 )
292#if defined (HRTIM1)
293#define LL_DAC_TRIG_EXT_HRTIM_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0)
294#define LL_DAC_TRIG_EXT_HRTIM_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 )
295#endif /* HRTIM1 */
296#define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
297#define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 )
298#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)
299#if defined(TIM23)
300#define LL_DAC_TRIG_EXT_TIM23_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )
301#endif /* TIM23 */
302#if defined(TIM24)
303#define LL_DAC_TRIG_EXT_TIM24_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
304#endif /* TIM24 */
305#if defined (DAC2)
306#define LL_DAC_TRIG_EXT_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )
307#endif /* DAC2 */
316#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL
317#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0)
318#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 )
327#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL
328#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0)
329#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )
330#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
331#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )
332#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
333#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
334#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
335#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 )
336#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
337#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
338#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
347#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL
348#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0)
349#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 )
350#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
351#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 )
352#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
353#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
354#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
355#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 )
356#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
357#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
358#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
367#define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL
368#define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)
377#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL
378#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1)
387#define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL
388#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0)
397#define LL_DAC_TRIGGER_SOFTWARE (LL_DAC_TRIG_SOFTWARE)
398#define LL_DAC_TRIGGER_TIM2_TRGO (LL_DAC_TRIG_EXT_TIM2_TRGO)
399#define LL_DAC_TRIGGER_TIM4_TRGO (LL_DAC_TRIG_EXT_TIM4_TRGO)
400#define LL_DAC_TRIGGER_TIM6_TRGO (LL_DAC_TRIG_EXT_TIM6_TRGO)
401#define LL_DAC_TRIGGER_TIM7_TRGO (LL_DAC_TRIG_EXT_TIM7_TRGO)
402#define LL_DAC_TRIGGER_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM8_TRGO)
403#define LL_DAC_TRIGGER_EXT_IT9 (LL_DAC_TRIG_EXT_EXTI_LINE9)
404
405#define LL_DAC_WAVEGENERATION_NONE (LL_DAC_WAVE_AUTO_GENERATION_NONE)
406#define LL_DAC_WAVEGENERATION_NOISE (LL_DAC_WAVE_AUTO_GENERATION_NOISE)
407#define LL_DAC_WAVEGENERATION_TRIANGLE (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)
408
409#define LL_DAC_CONNECT_GPIO (LL_DAC_OUTPUT_CONNECT_GPIO)
410#define LL_DAC_CONNECT_INTERNAL (LL_DAC_OUTPUT_CONNECT_INTERNAL)
418#define LL_DAC_RESOLUTION_12B 0x00000000UL
419#define LL_DAC_RESOLUTION_8B 0x00000002UL
428/* List of DAC registers intended to be used (most commonly) with */
429/* DMA transfer. */
430/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
431#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS
432#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS
433#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS
447/* Delay for DAC channel voltage settling time from DAC channel startup */
448/* (transition from disable to enable). */
449/* Note: DAC channel startup time depends on board application environment: */
450/* impedance connected to DAC channel output. */
451/* The delay below is specified under conditions: */
452/* - voltage maximum transition (lowest to highest value) */
453/* - until voltage reaches final value +-1LSB */
454/* - DAC channel output buffer enabled */
455/* - load impedance of 5kOhm (min), 50pF (max) */
456/* Literal set to maximum value (refer to device datasheet, */
457/* parameter "tWAKEUP"). */
458/* Unit: us */
459#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL
461/* Delay for DAC channel voltage settling time. */
462/* Note: DAC channel startup time depends on board application environment: */
463/* impedance connected to DAC channel output. */
464/* The delay below is specified under conditions: */
465/* - voltage maximum transition (lowest to highest value) */
466/* - until voltage reaches final value +-1LSB */
467/* - DAC channel output buffer enabled */
468/* - load impedance of 5kOhm min, 50pF max */
469/* Literal set to maximum value (refer to device datasheet, */
470/* parameter "tSETTLING"). */
471/* Unit: us */
472#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL
482/* Exported macro ------------------------------------------------------------*/
500#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
501
508#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
509
532#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
533 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
534
548#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
549 (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
550
562#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
563 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
564
583#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \
584 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
585 / (__VREFANALOG_VOLTAGE__) \
586 )
587
597/* Exported functions --------------------------------------------------------*/
622__STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
623{
624 MODIFY_REG(DACx->CR,
625 DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
626 ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
627}
628
642__STATIC_INLINE uint32_t LL_DAC_GetMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
643{
644 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
645 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
646 );
647}
648
662__STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
663{
664 MODIFY_REG(DACx->CCR,
665 DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
666 TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
667}
668
681__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
682{
683 return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
684 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
685 );
686}
687
730__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
731{
732 MODIFY_REG(DACx->CR,
733 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
734 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
735}
736
776__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
777{
778 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
779 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
780 );
781}
782
798__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
799{
800 MODIFY_REG(DACx->CR,
801 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
802 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
803}
804
819__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
820{
821 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
822 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
823 );
824}
825
855__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
856{
857 MODIFY_REG(DACx->CR,
858 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
859 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
860}
861
885__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
886{
887 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
888 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
889 );
890}
891
921__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
922 uint32_t TriangleAmplitude)
923{
924 MODIFY_REG(DACx->CR,
925 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
926 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
927}
928
952__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
953{
954 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
955 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
956 );
957}
958
1003__STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
1004 uint32_t OutputBuffer, uint32_t OutputConnection)
1005{
1006 MODIFY_REG(DACx->MCR,
1007 (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1008 (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1009}
1010
1031__STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
1032{
1033 MODIFY_REG(DACx->MCR,
1034 (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1035 OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1036}
1037
1050__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1051{
1052 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1053 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1054 );
1055}
1056
1074__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
1075{
1076 MODIFY_REG(DACx->MCR,
1077 (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1078 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1079}
1080
1093__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1094{
1095 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1096 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1097 );
1098}
1099
1123__STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
1124{
1125 MODIFY_REG(DACx->MCR,
1126 (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1127 OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1128}
1129
1152__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1153{
1154 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1155 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1156 );
1157}
1158
1175__STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
1176{
1177 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1178 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1179
1180 MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime);
1181}
1182
1194__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1195{
1196 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1197 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1198
1199 return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
1200}
1201
1214__STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
1215{
1216 MODIFY_REG(DACx->SHHR,
1217 DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1218 HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1219}
1220
1232__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1233{
1234 return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1235 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1236 );
1237}
1238
1251__STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
1252{
1253 MODIFY_REG(DACx->SHRR,
1254 DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1255 RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1256}
1257
1269__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1270{
1271 return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1272 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1273 );
1274}
1275
1297__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1298{
1299 SET_BIT(DACx->CR,
1300 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1301}
1302
1315__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1316{
1317 CLEAR_BIT(DACx->CR,
1318 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1319}
1320
1332__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1333{
1334 return ((READ_BIT(DACx->CR,
1335 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1336 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1337}
1338
1371__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
1372{
1373 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
1374 /* DAC channel selected. */
1375 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
1376 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
1377}
1400__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1401{
1402 SET_BIT(DACx->CR,
1403 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1404}
1405
1416__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1417{
1418 CLEAR_BIT(DACx->CR,
1419 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1420}
1421
1433__STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1434{
1435 return ((READ_BIT(DACx->CR,
1436 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1437 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1438}
1439
1458__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1459{
1460 SET_BIT(DACx->CR,
1461 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1462}
1463
1474__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1475{
1476 CLEAR_BIT(DACx->CR,
1477 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1478}
1479
1491__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1492{
1493 return ((READ_BIT(DACx->CR,
1494 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1495 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1496}
1497
1519__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1520{
1521 SET_BIT(DACx->SWTRIGR,
1522 (DAC_Channel & DAC_SWTR_CHX_MASK));
1523}
1524
1538__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1539{
1540 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
1541 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1542
1543 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
1544}
1545
1559__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1560{
1561 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
1562 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1563
1564 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
1565}
1566
1580__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1581{
1582 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
1583 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1584
1585 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
1586}
1587
1588
1600__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1601 uint32_t DataChannel2)
1602{
1603 MODIFY_REG(DACx->DHR12RD,
1604 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1605 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1606}
1607
1619__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1620 uint32_t DataChannel2)
1621{
1622 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1623 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1624 /* the 4 LSB must be taken into account for the shift value. */
1625 MODIFY_REG(DACx->DHR12LD,
1626 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1627 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1628}
1629
1641__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1642 uint32_t DataChannel2)
1643{
1644 MODIFY_REG(DACx->DHR8RD,
1645 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1646 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1647}
1648
1649
1664__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1665{
1666 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
1667 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
1668
1669 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1670}
1671
1687__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef *DACx)
1688{
1689 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
1690}
1691
1692
1699__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef *DACx)
1700{
1701 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
1702}
1703
1704
1711__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef *DACx)
1712{
1713 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
1714}
1715
1722__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef *DACx)
1723{
1724 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
1725}
1726
1727
1734__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx)
1735{
1736 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
1737}
1738
1739
1746__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx)
1747{
1748 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
1749}
1750
1751
1758__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1759{
1760 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1761}
1762
1763
1770__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1771{
1772 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1773}
1774
1775
1791__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1792{
1793 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1794}
1795
1796
1803__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1804{
1805 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1806}
1807
1808
1815__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1816{
1817 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1818}
1819
1820
1827__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1828{
1829 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1830}
1831
1832
1839__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx)
1840{
1841 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
1842}
1843
1844
1851__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx)
1852{
1853 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
1854}
1855
1856
1861#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
1867ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx);
1868ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct);
1869void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
1870
1874#endif /* USE_FULL_LL_DRIVER */
1875
1884#endif /* DAC1 || DAC2 */
1885
1890#ifdef __cplusplus
1891}
1892#endif
1893
1894#endif /* STM32H7xx_LL_DAC_H */
__IO
#define __IO
Definition: core_cm4.h:239
DAC_SHRR_TREFRESH1
#define DAC_SHRR_TREFRESH1
Definition: stm32h723xx.h:6125
DAC_MCR_MODE1_1
#define DAC_MCR_MODE1_1
Definition: stm32h723xx.h:6094
DAC_DHR12L1_DACC1DHR
#define DAC_DHR12L1_DACC1DHR
Definition: stm32h723xx.h:6004
DAC_DHR12LD_DACC1DHR
#define DAC_DHR12LD_DACC1DHR
Definition: stm32h723xx.h:6037
DAC_CCR_OTRIM1
#define DAC_CCR_OTRIM1
Definition: stm32h723xx.h:6084
DAC_CR_MAMP1
#define DAC_CR_MAMP1
Definition: stm32h723xx.h:5932
DAC_DHR12RD_DACC2DHR
#define DAC_DHR12RD_DACC2DHR
Definition: stm32h723xx.h:6032
DAC_CR_CEN1
#define DAC_CR_CEN1
Definition: stm32h723xx.h:5946
DAC_SHHR_THOLD1
#define DAC_SHHR_THOLD1
Definition: stm32h723xx.h:6117
DAC_DHR12R1_DACC1DHR
#define DAC_DHR12R1_DACC1DHR
Definition: stm32h723xx.h:5999
DAC_DOR1_DACC1DOR
#define DAC_DOR1_DACC1DOR
Definition: stm32h723xx.h:6053
DAC_DHR12LD_DACC2DHR
#define DAC_DHR12LD_DACC2DHR
Definition: stm32h723xx.h:6040
DAC_CR_WAVE1
#define DAC_CR_WAVE1
Definition: stm32h723xx.h:5926
DAC_CR_DMAEN1
#define DAC_CR_DMAEN1
Definition: stm32h723xx.h:5940
DAC_CR_TEN1
#define DAC_CR_TEN1
Definition: stm32h723xx.h:5913
DAC_DHR8RD_DACC1DHR
#define DAC_DHR8RD_DACC1DHR
Definition: stm32h723xx.h:6045
DAC_SHSR1_TSAMPLE1
#define DAC_SHSR1_TSAMPLE1
Definition: stm32h723xx.h:6107
DAC_MCR_MODE1_2
#define DAC_MCR_MODE1_2
Definition: stm32h723xx.h:6095
DAC_CR_EN1
#define DAC_CR_EN1
Definition: stm32h723xx.h:5910
DAC_DHR12RD_DACC1DHR
#define DAC_DHR12RD_DACC1DHR
Definition: stm32h723xx.h:6029
DAC_DHR8R1_DACC1DHR
#define DAC_DHR8R1_DACC1DHR
Definition: stm32h723xx.h:6009
DAC_DHR8RD_DACC2DHR
#define DAC_DHR8RD_DACC2DHR
Definition: stm32h723xx.h:6048
DAC_MCR_MODE1_0
#define DAC_MCR_MODE1_0
Definition: stm32h723xx.h:6093
DAC_CR_TSEL1
#define DAC_CR_TSEL1
Definition: stm32h723xx.h:5917
stm32h7xx.h
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32h723xx.h:469
DAC_TypeDef::DHR8RD
__IO uint32_t DHR8RD
Definition: stm32h723xx.h:480
DAC_TypeDef::SR
__IO uint32_t SR
Definition: stm32h723xx.h:483
DAC_TypeDef::CR
__IO uint32_t CR
Definition: stm32h723xx.h:470
DAC_TypeDef::MCR
__IO uint32_t MCR
Definition: stm32h723xx.h:485
DAC_TypeDef::SWTRIGR
__IO uint32_t SWTRIGR
Definition: stm32h723xx.h:471
DAC_TypeDef::DOR1
__IO uint32_t DOR1
Definition: stm32h723xx.h:481
DAC_TypeDef::SHHR
__IO uint32_t SHHR
Definition: stm32h723xx.h:488
DAC_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32h723xx.h:484
DAC_TypeDef::SHSR1
__IO uint32_t SHSR1
Definition: stm32h723xx.h:486
DAC_TypeDef::SHRR
__IO uint32_t SHRR
Definition: stm32h723xx.h:489
DAC_TypeDef::DHR12LD
__IO uint32_t DHR12LD
Definition: stm32h723xx.h:479
DAC_TypeDef::DHR12R1
__IO uint32_t DHR12R1
Definition: stm32h723xx.h:472
DAC_TypeDef::DHR12RD
__IO uint32_t DHR12RD
Definition: stm32h723xx.h:478
Generated by doxygen 1.9.6