RTEMS 6.1-rc6
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reg_crc.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/* The header file is generated by make_header.py from CRC.json */
12/* Current script's version can be found at: */
13/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
14
15/*
16 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
17 *
18 * Czech Technical University in Prague
19 * Zikova 1903/4
20 * 166 36 Praha 6
21 * Czech Republic
22 *
23 * All rights reserved.
24 *
25 * Redistribution and use in source and binary forms, with or without
26 * modification, are permitted provided that the following conditions are met:
27 *
28 * 1. Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following disclaimer.
30 * 2. Redistributions in binary form must reproduce the above copyright notice,
31 * this list of conditions and the following disclaimer in the documentation
32 * and/or other materials provided with the distribution.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
35 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
36 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
37 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
38 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
39 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
40 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
41 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
43 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 *
45 * The views and conclusions contained in the software and documentation are those
46 * of the authors and should not be interpreted as representing official policies,
47 * either expressed or implied, of the FreeBSD Project.
48*/
49#ifndef LIBBSP_ARM_TMS570_CRC
50#define LIBBSP_ARM_TMS570_CRC
51
52#include <bsp/utility.h>
53
54typedef struct{
55 uint32_t CTRL0; /*CRC Global Control Register*/
56 uint8_t reserved1 [4];
57 uint32_t CTRL1; /*CRC Global Control Register 1*/
58 uint8_t reserved2 [4];
59 uint32_t CTRL2; /*CRC Global Control Register 2*/
60 uint8_t reserved3 [4];
61 uint32_t INTS; /*CRC Interrupt Enable Set Register*/
62 uint8_t reserved4 [4];
63 uint32_t INTR; /*CRC Interrupt Enable Reset Register*/
64 uint8_t reserved5 [4];
65 uint32_t STATUS; /*CRC Interrupt Status Register*/
66 uint8_t reserved6 [4];
67 uint32_t INT_OFFS_REG; /*CRC Interrupt Offset Register*/
68 uint8_t reserved7 [4];
69 uint32_t BUSY; /*CRC Busy Register*/
70 uint8_t reserved8 [4];
71 uint32_t PCOUNT_REG1; /*CRC Channel 1 Pattern Counter Preload Register*/
72 uint32_t SCOUNT_REG1; /*CRC Channel 1 Sector Counter Preload Register*/
73 uint32_t CURSEC_REG1; /*CRC Channel 1 Current Sector Register*/
74 uint32_t WDTOPLD1; /*CRC Channel 1 Watchdog Timeout Preload Register*/
75 uint32_t BCTOPLD1; /*CRC Channel 1 Block Complete Timeout Preload Register*/
76 uint8_t reserved9 [12];
77 uint32_t PSA_SIGREGL1; /*Channel 1 PSA Signature Low Register*/
78 uint32_t PSA_SIGREGH1; /*Channel 1 PSA Signature High Register*/
79 uint32_t REGL1; /*Channel 1 CRC Value Low Register*/
80 uint32_t REGH1; /*Channel 1 CRC Value High Register*/
81 uint32_t PSA_SECSIGREGL1; /*Channel 1 PSA Sector Signature Low Register*/
82 uint32_t PSA_SECSIGREGH1; /*Channel 1 PSA Sector Signature High Register*/
83 uint32_t RAW_DATAREGL1; /*Channel 1 Raw Data Low Register*/
84 uint32_t RAW_DATAREGH1; /*Channel 1 Raw Data High Register*/
85 uint32_t PCOUNT_REG2; /*CRC Channel 2 Pattern Counter Preload Register*/
86 uint32_t SCOUNT_REG2; /*CRC Channel 2 Sector Counter Preload Register*/
87 uint32_t CURSEC_REG2; /*CRC Current Sector Register 2*/
88 uint32_t WDTOPLD2; /*CRC Channel 2 Watchdog Timeout Preload Register A*/
89 uint32_t BCTOPLD2; /*CRC Channel 2 Block Complete Timeout Preload Register B*/
90 uint8_t reserved10 [12];
91 uint32_t PSA_SIGREGL2; /*Channel 2 PSA Signature Low Register*/
92 uint32_t PSA_SIGREGH2; /*Channel 2 PSA Signature High Register*/
93 uint32_t REGL2; /*Channel 2 CRC Value Low Register*/
94 uint32_t REGH2; /*Channel 2 CRC Value High Register*/
95 uint32_t PSA_SECSIGREGL2; /*Channel 2 PSA Sector Signature Low Register*/
96 uint32_t PSA_SECSIGREGH2; /*Channel 2 PSA Sector Signature High Register*/
97 uint32_t RAW_DATAREGL2; /*Channel 2 Raw Data Low Register*/
98 uint32_t RAW_DATAREGH2; /*Channel 2 Raw Data High Register*/
99 uint8_t reserved11 [128];
100 uint32_t BUS_SEL; /*Data Bus Selection Register*/
101} tms570_crc_t;
102
103
104/*----------------------TMS570_CRC_CTRL0----------------------*/
105/* field: CH2_PSA_SWREST - Channel 2 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */
106#define TMS570_CRC_CTRL0_CH2_PSA_SWREST BSP_BIT32(8)
107
108/* field: CH1_PSA_SWREST - Channel 1 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */
109#define TMS570_CRC_CTRL0_CH1_PSA_SWREST BSP_BIT32(0)
110
111
112/*----------------------TMS570_CRC_CTRL1----------------------*/
113/* field: PWDN - Power Down. */
114#define TMS570_CRC_CTRL1_PWDN BSP_BIT32(0)
115
116
117/*----------------------TMS570_CRC_CTRL2----------------------*/
118/* field: CH2_MODE - Channel 2 Mode Selection */
119#define TMS570_CRC_CTRL2_CH2_MODE(val) BSP_FLD32(val,8, 9)
120#define TMS570_CRC_CTRL2_CH2_MODE_GET(reg) BSP_FLD32GET(reg,8, 9)
121#define TMS570_CRC_CTRL2_CH2_MODE_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
122
123/* field: CH1_TRACEEN - Channel 1 Data Trace Enable. When set, the channel is put into data trace mode. */
124#define TMS570_CRC_CTRL2_CH1_TRACEEN BSP_BIT32(4)
125
126/* field: CH1_MODE - Channel 1 Mode Selection */
127#define TMS570_CRC_CTRL2_CH1_MODE(val) BSP_FLD32(val,0, 1)
128#define TMS570_CRC_CTRL2_CH1_MODE_GET(reg) BSP_FLD32GET(reg,0, 1)
129#define TMS570_CRC_CTRL2_CH1_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
130
131
132/*----------------------TMS570_CRC_INTS----------------------*/
133/* field: CH2_TIMEOUTENS - Channel 2 Timeout Interrupt Enable Bit. */
134#define TMS570_CRC_INTS_CH2_TIMEOUTENS BSP_BIT32(12)
135
136/* field: CH2_UNDERENS - Channel 2 Underrun Interrupt Enable Bit. */
137#define TMS570_CRC_INTS_CH2_UNDERENS BSP_BIT32(11)
138
139/* field: CH2_OVERENS - Channel 2 Overrun Interrupt Enable Bit. */
140#define TMS570_CRC_INTS_CH2_OVERENS BSP_BIT32(10)
141
142/* field: CH2_CRCFAILENS - Channel 2 CRC Fail Interrupt Enable Bit. */
143#define TMS570_CRC_INTS_CH2_CRCFAILENS BSP_BIT32(9)
144
145/* field: CH2_CCITENS - Channel 2 Compression Complete Interrupt Enable Bit. */
146#define TMS570_CRC_INTS_CH2_CCITENS BSP_BIT32(8)
147
148/* field: CH1_TIMEOUTENS - Channel 1 Timeout Interrupt Enable Bit. */
149#define TMS570_CRC_INTS_CH1_TIMEOUTENS BSP_BIT32(4)
150
151/* field: CH1_UNDERENS - Channel 1 Underrun Interrupt Enable Bit. */
152#define TMS570_CRC_INTS_CH1_UNDERENS BSP_BIT32(3)
153
154/* field: CH1_OVERENS - CH1_OVERENS Channel 1 Overrun Interrupt Enable Bit. */
155#define TMS570_CRC_INTS_CH1_OVERENS BSP_BIT32(2)
156
157/* field: CH1_CRCFAILENS - Channel 1 CRC Fail Interrupt Enable Bit. */
158#define TMS570_CRC_INTS_CH1_CRCFAILENS BSP_BIT32(1)
159
160/* field: CH1_CCITENS - Channel 1 Compression Complete Interrupt Enable Bit. */
161#define TMS570_CRC_INTS_CH1_CCITENS BSP_BIT32(0)
162
163
164/*----------------------TMS570_CRC_INTR----------------------*/
165/* field: CH2_TIMEOUTENR - Channel 2 Timeout Interrupt Enable Bit. */
166#define TMS570_CRC_INTR_CH2_TIMEOUTENR BSP_BIT32(12)
167
168/* field: CH2_UNDERENR - Channel 2 Underrun Interrupt Enable Bit. */
169#define TMS570_CRC_INTR_CH2_UNDERENR BSP_BIT32(11)
170
171/* field: CH2_OVERENR - Channel 2 Overrun Interrupt Enable Bit. */
172#define TMS570_CRC_INTR_CH2_OVERENR BSP_BIT32(10)
173
174/* field: CH2_CRCFAILENR - Channel 2 CRC Fail Interrupt Enable Bit. */
175#define TMS570_CRC_INTR_CH2_CRCFAILENR BSP_BIT32(9)
176
177/* field: CH2_CCITENR - Channel 2 Compression Complete Interrupt Enable Bit. */
178#define TMS570_CRC_INTR_CH2_CCITENR BSP_BIT32(8)
179
180/* field: CH1_TIMEOUTENR - Channel 1 Timeout Interrupt Enable Bit. */
181#define TMS570_CRC_INTR_CH1_TIMEOUTENR BSP_BIT32(4)
182
183/* field: CH1_UNDERENR - interrupt. Writing a zero has no effect. */
184#define TMS570_CRC_INTR_CH1_UNDERENR BSP_BIT32(3)
185
186/* field: CH1_OVERENR - CH1_OVERENR */
187#define TMS570_CRC_INTR_CH1_OVERENR BSP_BIT32(2)
188
189/* field: CH1_CRCFAILENR - Channel 1 CRC Fail Interrupt Enable Bit. */
190#define TMS570_CRC_INTR_CH1_CRCFAILENR BSP_BIT32(1)
191
192/* field: CH1_CCITENR - Channel 1 Compression Complete Interrupt Enable Bit. */
193#define TMS570_CRC_INTR_CH1_CCITENR BSP_BIT32(0)
194
195
196/*---------------------TMS570_CRC_STATUS---------------------*/
197/* field: CH2_TIMEOUT - Channel 2 CRC Timeout Status Flag. This bit is cleared by writing a '1' to it only. */
198#define TMS570_CRC_STATUS_CH2_TIMEOUT BSP_BIT32(12)
199
200/* field: CH2_UNDER - Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a '1' to it only. */
201#define TMS570_CRC_STATUS_CH2_UNDER BSP_BIT32(11)
202
203/* field: CH2_OVER - Channel 2 CRC Overrun Status Flag. This bit is cleared by writing a '1' to it only. */
204#define TMS570_CRC_STATUS_CH2_OVER BSP_BIT32(10)
205
206/* field: CH2_CRCFAIL - Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a '1' to it only. */
207#define TMS570_CRC_STATUS_CH2_CRCFAIL BSP_BIT32(9)
208
209/* field: CH2_CCIT - Channel 2 CRC Pattern Compression Complete Status Flag. */
210#define TMS570_CRC_STATUS_CH2_CCIT BSP_BIT32(8)
211
212/* field: CH1_TIMEOUT - Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). */
213#define TMS570_CRC_STATUS_CH1_TIMEOUT BSP_BIT32(4)
214
215/* field: CH1_UNDER - Channel 1 Underrun Interrupt Enable Bit. */
216#define TMS570_CRC_STATUS_CH1_UNDER BSP_BIT32(3)
217
218/* field: CH1_OVER - Channel 1 Overrun Interrupt Enable Bit. Writing a one to this bit disable the overrun interrupt. */
219#define TMS570_CRC_STATUS_CH1_OVER BSP_BIT32(2)
220
221/* field: CH1_CRCFAIL - Channel 1 CRC Fail Interrupt Enable Bit. */
222#define TMS570_CRC_STATUS_CH1_CRCFAIL BSP_BIT32(1)
223
224/* field: CH1_CCIT - Channel 1 CRC Pattern Compression Complete Status Flag. */
225#define TMS570_CRC_STATUS_CH1_CCIT BSP_BIT32(0)
226
227
228/*------------------TMS570_CRC_INT_OFFS_REG------------------*/
229/* field: OFSTREG - CRC Interrupt Offset. This register indicates the highest priority pending interrupt vector address. */
230#define TMS570_CRC_INT_OFFS_REG_OFSTREG(val) BSP_FLD32(val,0, 7)
231#define TMS570_CRC_INT_OFFS_REG_OFSTREG_GET(reg) BSP_FLD32GET(reg,0, 7)
232#define TMS570_CRC_INT_OFFS_REG_OFSTREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
233
234
235/*----------------------TMS570_CRC_BUSY----------------------*/
236/* field: CH2_BUSY - CH2_BUSY. */
237#define TMS570_CRC_BUSY_CH2_BUSY BSP_BIT32(8)
238
239/* field: CH1_BUSY - CH1_BUSY. */
240#define TMS570_CRC_BUSY_CH1_BUSY BSP_BIT32(0)
241
242
243/*-------------------TMS570_CRC_PCOUNT_REG1-------------------*/
244/* field: CRC_PAT_COUNT1 - Channel 1 Pattern Counter Preload Register. */
245#define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1(val) BSP_FLD32(val,0, 19)
246#define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 19)
247#define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
248
249
250/*-------------------TMS570_CRC_SCOUNT_REG1-------------------*/
251/* field: CRC_SEC_COUNT1 - Channel 1 Sector Counter Preload Register. */
252#define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1(val) BSP_FLD32(val,0, 15)
253#define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 15)
254#define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
255
256
257/*-------------------TMS570_CRC_CURSEC_REG1-------------------*/
258/* field: CRC_CURSEC1 - Channel 1 Current Sector ID Register. */
259#define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1(val) BSP_FLD32(val,0, 15)
260#define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1_GET(reg) BSP_FLD32GET(reg,0, 15)
261#define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
262
263
264/*--------------------TMS570_CRC_WDTOPLD1--------------------*/
265/* field: CRC_WDTOPLD1 - CRC_WDTOPLD1 */
266#define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1(val) BSP_FLD32(val,0, 23)
267#define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1_GET(reg) BSP_FLD32GET(reg,0, 23)
268#define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
269
270
271/*--------------------TMS570_CRC_BCTOPLD1--------------------*/
272/* field: CRC_BCTOPLD1 - Channel 1 Block Complete Timeout Counter Preload Register. */
273#define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1(val) BSP_FLD32(val,0, 23)
274#define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1_GET(reg) BSP_FLD32GET(reg,0, 23)
275#define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
276
277
278/*------------------TMS570_CRC_PSA_SIGREGL1------------------*/
279/* field: PSASIG1 - Channel 1 PSA Signature Low Register. */
280/* Whole 32 bits */
281
282/*------------------TMS570_CRC_PSA_SIGREGH1------------------*/
283/* field: PSASIG1 - register. */
284/* Whole 32 bits */
285
286/*----------------------TMS570_CRC_REGL1----------------------*/
287/* field: CRC1 - Channel 1 CRC Value Low Register. */
288/* Whole 32 bits */
289
290/*----------------------TMS570_CRC_REGH1----------------------*/
291/* field: CRC1 - Channel 1 CRC Value Low Register. */
292/* Whole 32 bits */
293
294/*-----------------TMS570_CRC_PSA_SECSIGREGL1-----------------*/
295/* field: PSASECSIG1 - Channel 1 PSA Sector Signature Low Register. */
296/* Whole 32 bits */
297
298/*-----------------TMS570_CRC_PSA_SECSIGREGH1-----------------*/
299/* field: PSASECSIG1 - Channel 1 PSA Sector Signature High Register. */
300/* Whole 32 bits */
301
302/*------------------TMS570_CRC_RAW_DATAREGL1------------------*/
303/* field: RAW_DATA1 - hannel 1 Raw Data Low Register.This register contains bits 31:0 of the uncompressed raw data. */
304/* Whole 32 bits */
305
306/*------------------TMS570_CRC_RAW_DATAREGH1------------------*/
307/* field: RAW_DATA1 - Channel 1 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data. */
308/* Whole 32 bits */
309
310/*-------------------TMS570_CRC_PCOUNT_REG2-------------------*/
311/* field: CRC_PAT_COUNT2 - Channel 2 Pattern Counter Preload Register. */
312#define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2(val) BSP_FLD32(val,0, 19)
313#define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2_GET(reg) BSP_FLD32GET(reg,0, 19)
314#define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
315
316
317/*-------------------TMS570_CRC_SCOUNT_REG2-------------------*/
318/* field: CRC_SEC_COUNT2 - Channel 2 Sector Counter Preload Register. */
319#define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2(val) BSP_FLD32(val,0, 15)
320#define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2_GET(reg) BSP_FLD32GET(reg,0, 15)
321#define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
322
323
324/*-------------------TMS570_CRC_CURSEC_REG2-------------------*/
325/* field: CRC_CURSEC2 - Channel 2 Current Sector ID Register. */
326#define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2(val) BSP_FLD32(val,0, 15)
327#define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2_GET(reg) BSP_FLD32GET(reg,0, 15)
328#define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
329
330
331/*--------------------TMS570_CRC_WDTOPLD2--------------------*/
332/* field: CRC_WDTOPLD2 - Channel 2 Watchdog Timeout Counter Preload Register. */
333#define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2(val) BSP_FLD32(val,0, 23)
334#define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2_GET(reg) BSP_FLD32GET(reg,0, 23)
335#define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
336
337
338/*--------------------TMS570_CRC_BCTOPLD2--------------------*/
339/* field: CRC_BCTOPLD2 - Channel 2 Block Complete Timeout Counter Preload Register. */
340#define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2(val) BSP_FLD32(val,0, 23)
341#define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2_GET(reg) BSP_FLD32GET(reg,0, 23)
342#define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
343
344
345/*------------------TMS570_CRC_PSA_SIGREGL2------------------*/
346/* field: PSASIG2 - Channel 2 PSA Signature Low Register. */
347/* Whole 32 bits */
348
349/*------------------TMS570_CRC_PSA_SIGREGH2------------------*/
350/* field: PSASIG2 - Channel 2 PSA Signature High Register. */
351/* Whole 32 bits */
352
353/*----------------------TMS570_CRC_REGL2----------------------*/
354/* field: CRC2 - stored at CRC2[31:0] register. */
355/* Whole 32 bits */
356
357/*----------------------TMS570_CRC_REGH2----------------------*/
358/* field: CRC2 - Channel 2 CRC Value High Register. */
359/* Whole 32 bits */
360
361/*-----------------TMS570_CRC_PSA_SECSIGREGL2-----------------*/
362/* field: PSASECSIG2 - Channel 2 PSA Sector Signature Low Register. */
363/* Whole 32 bits */
364
365/*-----------------TMS570_CRC_PSA_SECSIGREGH2-----------------*/
366/* field: PSASECSIG2 - Channel 2 PSA Sector Signature High Register. */
367/* Whole 32 bits */
368
369/*------------------TMS570_CRC_RAW_DATAREGL2------------------*/
370/* field: RAW_DATA2 - Channel 2 Raw Data Low Register. This register contains bits 31:0 of the uncompressed raw data.. */
371/* Whole 32 bits */
372
373/*------------------TMS570_CRC_RAW_DATAREGH2------------------*/
374/* field: RAW_DATA2 - Channel 2 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data.. */
375/* Whole 32 bits */
376
377/*---------------------TMS570_CRC_BUS_SEL---------------------*/
378/* field: MEn - Enable/disables the tracing of Peripheral Bus Master */
379#define TMS570_CRC_BUS_SEL_MEn BSP_BIT32(2)
380
381/* field: DTCMEn - Enable/disables the tracing of data TCM */
382#define TMS570_CRC_BUS_SEL_DTCMEn BSP_BIT32(1)
383
384/* field: ITCMEn - Enable/disables the tracing of instruction TCM */
385#define TMS570_CRC_BUS_SEL_ITCMEn BSP_BIT32(0)
386
387
388
389#endif /* LIBBSP_ARM_TMS570_CRC */
utility.h
This header file provides utility macros for BSPs.
tms570_crc_t
Definition: reg_crc.h:54
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