RTEMS 6.1-rc6
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reg-defs.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2008, 2014 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#ifndef LIBCPU_POWERPC_MPC55XX_REG_DEFS_H
37#define LIBCPU_POWERPC_MPC55XX_REG_DEFS_H
38
39#include <bspopts.h>
40
41#if MPC55XX_CHIP_FAMILY == 551
42 #define FLASH_BIUCR 0xFFFF801C
43#else
44 #define FLASH_BIUCR 0xC3F8801C
45#endif
46
47/*
48 * Definitions for FLASH_BIUCR (Flash BIU Control Register)
49 */
50
51/* Fields for Flash Bus Interface Control */
52/* Fields for Prefetch Control (MnPFE Master n Prefetch Enable) */
53
54/* Fields for M3PFE (Master 3 (EBI) prefetch enable bit [12]) */
55#define FLASH_BUICR_EBI_PREFTCH 0x00080000
56
57/* Fields for M2PFE (Master 2 (eDMA) prefetch enable bit [13]) */
58#define FLASH_BUICR_EDMA_PREFTCH 0x00040000
59
60/* Fields for M1PFE (Master 1 (Nexus) prefetch enable bit [14]) */
61#define FLASH_BUICR_NEX_PREFTCH 0x00020000
62
63/* Fields for M0PFE (Master 0 (e200z core) prefetch enable bit [15]) */
64#define FLASH_BUICR_CPU_PREFTCH 0x00010000
65
66/* Fields for APC (access pipelining control bits [16:18]) */
67#define FLASH_BUICR_APC_0 0x00000000
68#define FLASH_BUICR_APC_1 0x00002000
69#define FLASH_BUICR_APC_2 0x00004000
70#define FLASH_BUICR_APC_3 0x00006000
71#define FLASH_BUICR_APC_4 0x00008000
72#define FLASH_BUICR_APC_5 0x0000A000
73#define FLASH_BUICR_APC_6 0x0000C000
74#define FLASH_BUICR_APC_NO 0x0000E000
75
76/* Fields for WWSC (write wait state control bits [19:20]) */
77#define FLASH_BUICR_WWSC_1 0x00000800
78#define FLASH_BUICR_WWSC_2 0x00001000
79#define FLASH_BUICR_WWSC_3 0x00001800
80
81/* Fields for RWSC (read wait state control bits [21:23]) */
82#define FLASH_BUICR_RWSC_0 0x00000000
83#define FLASH_BUICR_RWSC_1 0x00000100
84#define FLASH_BUICR_RWSC_2 0x00000200
85#define FLASH_BUICR_RWSC_3 0x00000300
86#define FLASH_BUICR_RWSC_4 0x00000400
87#define FLASH_BUICR_RWSC_5 0x00000500
88#define FLASH_BUICR_RWSC_6 0x00000600
89#define FLASH_BUICR_RWSC_7 0x00000700
90
91/* Fields for DPFEN (data prefetch enable bits [24:25]) */
92#define FLASH_BUICR_DPFEN_0 0x00000000
93#define FLASH_BUICR_DPFEN_1 0x00000040
94#define FLASH_BUICR_DPFEN_3 0x000000C0
95
96/* Fields for IPFEN (instruction prefetch enable bits [26:27]) */
97#define FLASH_BUICR_IPFEN_0 0x00000000
98#define FLASH_BUICR_IPFEN_1 0x00000010
99#define FLASH_BUICR_IPFEN_3 0x00000030
100
101/* Fields for PFLIM (additional line prefetch (limit) bits [28:30]) */
102#define FLASH_BUICR_PFLIM_0 0x00000000
103#define FLASH_BUICR_PFLIM_1 0x00000002
104#define FLASH_BUICR_PFLIM_2 0x00000004
105#define FLASH_BUICR_PFLIM_3 0x00000006
106#define FLASH_BUICR_PFLIM_4 0x00000008
107#define FLASH_BUICR_PFLIM_5 0x0000000A
108#define FLASH_BUICR_PFLIM_6 0x0000000C
109
110/* Fields for BFEN (enable line read buffer hits bit [31]) */
111#define FLASH_BUICR_BFEN 0x00000001
112
113#endif /* LIBCPU_POWERPC_MPC55XX_REG_DEFS_H */