RTEMS 6.1-rc6
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qspi.h
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1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30
38#ifndef _QSPI_
39#define _QSPI_
40/*----------------------------------------------------------------------------
41 * Macros
42 *----------------------------------------------------------------------------*/
43
57#define QSPI_SCBR(baudrate, masterClock) \
58 ((uint32_t) (masterClock / baudrate) << 8)
59
61#define QSPI_DLYBS(delay, masterClock) \
62 ((uint32_t) (((masterClock / 1000000) * delay) / 1000) << 16)
63
65#define QSPI_DLYBCT(delay, masterClock) \
66 ((uint32_t) (((masterClock / 1000000) * delay) / 32000) << 24)
67
68/*--------------------------------------------------------------------------- */
69
70#ifdef __cplusplus
71extern "C" {
72#endif
73
74/*----------------------------------------------------------------------------
75 * Exported functions
76 *----------------------------------------------------------------------------*/
77
80typedef enum {
81 CmdAccess = 0,
82 ReadAccess,
83 WriteAccess
84} Access_t;
85
88typedef enum {
89 SpiMode = QSPI_MR_SMM_SPI,
90 QspiMemMode = QSPI_MR_SMM_MEMORY
92
93
96typedef enum {
97 ClockMode_00 = 0,
98 ClockMode_10,
99 ClockMode_01,
100 ClockMode_11
102
103
106typedef enum {
107 QSPI_SUCCESS = 0,
108 QSPI_BUSY,
109 QSPI_BUSY_SENDING,
110 QSPI_READ_ERROR,
111 QSPI_WRITE_ERROR,
112 QSPI_UNKNOWN_ERROR,
113 QSPI_INIT_ERROR,
114 QSPI_INPUT_ERROR,
115 QSPI_TOTAL_ERROR
117
118
121typedef enum {
122 IsReceived = QSPI_SR_RDRF,
123 IsTxSent = QSPI_SR_TDRE,
124 IsTxEmpty = QSPI_SR_TXEMPTY,
125 IsOverrun = QSPI_SR_OVRES,
126 IsCsRise = QSPI_SR_CSR,
127 IsCsAsserted = QSPI_SR_CSS,
128 IsEofInst = QSPI_SR_INSTRE,
129 IsEnabled = QSPI_SR_QSPIENS
131
134typedef struct {
135 uint8_t Instruction;
136 uint8_t Option;
138
141typedef struct {
142 uint32_t TxDataSize; /* Tx buffer size */
143 uint32_t RxDataSize; /* Rx buffer size */
144 const void *pDataTx; /* Tx buffer */
145 void *pDataRx; /* Rx buffer */
147
148
151typedef struct {
153 uint32_t val;
155 uint32_t bwidth: 3,
168 reserved3: 11;
169 } bm;
170 } InstFrame;
171 uint32_t Addr;
173
176typedef struct {
177 uint8_t qspiId; /* QSPI ID */
178 Qspi *pQspiHw; /* QSPI Hw instance */
179 QspiMode_t qspiMode; /* Qspi mode: SPI or QSPI */
180 QspiMemCmd_t qspiCommand; /* Qspi command structure*/
181 QspiBuffer_t qspiBuffer; /* Qspi buffer*/
182 QspiInstFrame_t *pQspiFrame; /* Qspi QSPI mode Fram register informations*/
183} Qspid_t;
184
185
186void QSPI_SwReset(Qspi *pQspi);
187
188void QSPI_Disable(Qspi *pQspi);
189
190void QSPI_Enable(Qspi *pQspi);
191
193
194uint32_t QSPI_GetStatus(Qspi *pQspi, const QspiStatus_t rStatus);
195
196void QSPI_ConfigureClock(Qspi *pQspi, QspiClockMode_t ClockMode,
197 uint32_t dwClockCfg);
198
199QspidStatus_t QSPI_SingleReadSPI(Qspid_t *pQspid, uint16_t *const pData);
200
201QspidStatus_t QSPI_MultiReadSPI(Qspid_t *pQspid, uint16_t *
202 const pData, uint32_t NumOfBytes);
203
204QspidStatus_t QSPI_SingleWriteSPI(Qspid_t *pQspid, uint16_t const *pData);
205
206QspidStatus_t QSPI_MultiWriteSPI(Qspid_t *pQspid, uint16_t const *pData ,
207 uint32_t NumOfBytes);
208
209QspidStatus_t QSPI_EnableIt(Qspi *pQspi, uint32_t dwSources);
210
211QspidStatus_t QSPI_DisableIt(Qspi *pQspi, uint32_t dwSources);
212
213uint32_t QSPI_GetItMask(Qspi *pQspi);
214
215uint32_t QSPI_GetEnabledItStatus(Qspi *pQspi);
216
218 uint32_t dwConfiguration);
219
220QspidStatus_t QSPI_SendCommand(Qspid_t *pQspi, uint8_t const KeepCfg);
221
222QspidStatus_t QSPI_SendCommandWithData(Qspid_t *pQspi, uint8_t const KeepCfg);
223
224QspidStatus_t QSPI_ReadCommand(Qspid_t *pQspi, uint8_t const KeepCfg);
225
226QspidStatus_t QSPI_EnableMemAccess(Qspid_t *pQspi, uint8_t const KeepCfg,
227 uint8_t ScrambleFlag);
228
229QspidStatus_t QSPI_ReadWriteMem(Qspid_t *pQspid, Access_t const ReadWrite);
230
231#ifdef __cplusplus
232}
233#endif
234
235#endif /* #ifndef _QSPI_ */
236
QspidStatus_t QSPI_EndTransfer(Qspi *pQspi)
Ends ongoing transfer by releasing CS of QSPI peripheral.
Definition: qspi.c:360
void QSPI_Disable(Qspi *pQspi)
Disables a QSPI peripheral.
Definition: qspi.c:237
QspidStatus_t QSPI_DisableIt(Qspi *pQspi, uint32_t dwSources)
Disables one or more interrupt sources of a QSPI peripheral.
Definition: qspi.c:275
QspidStatus_t QSPI_SingleWriteSPI(Qspid_t *pQspid, uint16_t const *pData)
Sends a single data through a SPI peripheral.
Definition: qspi.c:473
QspidStatus_t QSPI_EnableMemAccess(Qspid_t *pQspi, uint8_t const KeepCfg, uint8_t ScrambleFlag)
Sends an instruction over QSPI and configures other related address like Addr , Frame and synchronise...
Definition: qspi.c:695
void QSPI_Enable(Qspi *pQspi)
Enables a QSPI peripheral.
Definition: qspi.c:224
QspidStatus_t QSPI_ReadWriteMem(Qspid_t *pQspid, Access_t const ReadWrite)
Writes or reads the QSPI memory (0x80000000) to transmit or receive data from Flash memory.
Definition: qspi.c:730
QspidStatus_t QSPI_SendCommandWithData(Qspid_t *pQspi, uint8_t const KeepCfg)
Send instruction over QSPI with data.
Definition: qspi.c:610
uint32_t QSPI_GetEnabledItStatus(Qspi *pQspi)
Returns enabled interrupt status.
Definition: qspi.c:298
uint32_t QSPI_GetStatus(Qspi *pQspi, const QspiStatus_t rStatus)
Get the current status register of the given QSPI peripheral.
Definition: qspi.c:312
QspiClockMode_t
qspi clock modes , regarding clock phase and clock polarity
Definition: qspi.h:96
QspidStatus_t QSPI_ReadCommand(Qspid_t *pQspi, uint8_t const KeepCfg)
Send instruction over QSPI to read data.
Definition: qspi.c:652
void QSPI_ConfigureClock(Qspi *pQspi, QspiClockMode_t ClockMode, uint32_t dwClockCfg)
Configures peripheral clock of a QSPI/SPI peripheral.
Definition: qspi.c:324
QspidStatus_t
qspi status codes
Definition: qspi.h:106
QspidStatus_t QSPI_SendCommand(Qspid_t *pQspi, uint8_t const KeepCfg)
Send an instruction over QSPI (oly a flash command no data)
Definition: qspi.c:560
QspidStatus_t QSPI_MultiReadSPI(Qspid_t *pQspid, uint16_t *const pData, uint32_t NumOfBytes)
Reads multiple data received by a SPI peripheral. This method must be called after a successful SPI_W...
Definition: qspi.c:422
QspidStatus_t QSPI_SingleReadSPI(Qspid_t *pQspid, uint16_t *const pData)
Reads the data received by a SPI peripheral. This method must be called after a successful SPI_Write ...
Definition: qspi.c:383
QspidStatus_t QSPI_EnableIt(Qspi *pQspi, uint32_t dwSources)
Enables one or more interrupt sources of a QSPI peripheral.
Definition: qspi.c:262
QspidStatus_t QSPI_ConfigureInterface(Qspid_t *pQspid, QspiMode_t Mode, uint32_t dwConfiguration)
Configures QSPI/SPI.
Definition: qspi.c:339
QspiMode_t
qspi modes SPI or QSPI
Definition: qspi.h:88
void QSPI_SwReset(Qspi *pQspi)
Resets a QSPI peripheral.
Definition: qspi.c:250
QspidStatus_t QSPI_MultiWriteSPI(Qspid_t *pQspid, uint16_t const *pData, uint32_t NumOfBytes)
Sends multiple data through a SPI peripheral.
Definition: qspi.c:508
Access_t
qspi access modes
Definition: qspi.h:80
QspiStatus_t
qspi status regiter bits
Definition: qspi.h:121
uint32_t QSPI_GetItMask(Qspi *pQspi)
Return the interrupt mask register.
Definition: qspi.c:287
qspi buffer structure
Definition: qspi.h:141
uint32_t reserved2
Definition: qspi.h:166
uint32_t reserved1
Definition: qspi.h:163
uint32_t bDummyCycles
Definition: qspi.h:167
uint32_t reserved0
Definition: qspi.h:156
uint32_t bContinuesRead
Definition: qspi.h:165
qspi frame structure for QSPI mode
Definition: qspi.h:151
qspi command structure
Definition: qspi.h:134
Qspi hardware registers.
Definition: component_qspi.h:41
qspi driver structure
Definition: qspi.h:176
Definition: qspi.h:152