RTEMS 6.1-rc6
Loading...
Searching...
No Matches
mpc5200.h
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/*
4 * RTEMS generic MPC5200 BSP.
5 *
6 * This file contains definitions for the mpc5200 hw registers.
7 */
8
9/*
10 * Copyright (c) 2005 embedded brains GmbH & Co. KG
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#ifndef __MPC5200_h__
35#define __MPC5200_h__
36
37/* Additional Harpo Core SPR definitions (603le only) */
38#define CSRR0 58 /* Critical Interrupt SRR0 */
39#define CSRR1 59 /* Critical Interrupt SRR1 */
40#define DABR2 1000 /* Data Address Breakpoint #2 */
41#define DBCR 1001 /* Data Address Breakpoint Control */
42#define IBCR 1002 /* Instruction Breakpoint Control */
43#define IABR2 1018 /* Instruction Breakpoint #2 */
44
45/*
46 * Initial post-reset location of MGT5100 module base address register (MBAR)
47 */
48#define MBAR_RESET 0x80000000
49
50/*
51 * Location and size of onchip SRAM (relative to MBAR)
52 */
53#define ONCHIP_SRAM_OFFSET 0x8000
54#define ONCHIP_SRAM_SIZE 0x4000
55
56#ifndef ASM
57#include <rtems.h>
58
59#include <bsp/utility.h>
60
61#ifdef __cplusplus
62extern "C" {
63#endif
64
65#define MPC5200_CAN_NO 2
66#define MPC5200_PSC_NO 6
67 /* XXX: there are only 6 PSCs, but PSC6 has an extra register gap
68 * from PSC5, therefore we instantiate seven(!) PSC register sets
69 */
70#define MPC5200_PSC_REG_SETS 7
71
72#define MPC5200_GPT_NO 8
73#define MPC5200_SLT_NO 2
74
75/*
76 * Bit fields for FEC interrupts, ievent and imask above.
77 */
78#define FEC_INTR_HBERR 0x80000000 /* heartbeat error */
79#define FEC_INTR_BABR 0x40000000 /* babbling receive error */
80#define FEC_INTR_BABT 0x20000000 /* babbling transmit error */
81#define FEC_INTR_GRA 0x10000000 /* graceful stop complete */
82#define FEC_INTR_TFINT 0x08000000 /* transmit frame interrupt */
83/* 0x04000000 reserved */
84/* 0x02000000 reserved */
85/* 0x01000000 reserved */
86#define FEC_INTR_MII 0x00800000 /* MII interrupt */
87/* 0x00400000 reserved */
88#define FEC_INTR_LATE_COL 0x00200000 /* late collision */
89#define FEC_INTR_COL_RETRY 0x00100000 /* collision retry limit */
90#define FEC_INTR_XFIFO_UN 0x00080000 /* transmit FIFO error */
91#define FEC_INTR_XFIFO_ERR 0x00040000 /* transmit FIFO error */
92#define FEC_INTR_RFIFO_ERR 0x00020000 /* receive FIFO error */
93/* 0x00010000 reserved */
94/* 0x0000ffff reserved */
95#define FEC_INTR_HBEEN FEC_INTR_HBERR
96#define FEC_INTR_BREN FEC_INTR_BABR
97#define FEC_INTR_BTEN FEC_INTR_BABT
98#define FEC_INTR_GRAEN FEC_INTR_GRA
99#define FEC_INTR_TFINTEN FEC_INTR_TFINT
100#define FEC_INTR_MIIEN FEC_INTR_MII
101#define FEC_INTR_LCEN FEC_INTR_LATE_COL
102#define FEC_INTR_CRLEN FEC_INTR_COL_RETRY
103#define FEC_INTR_XFUNEN FEC_INTR_XFIFO_UN
104#define FEC_INTR_XFERREN FEC_INTR_XFIFO_ERR
105#define FEC_INTR_RFERREN FEC_INTR_RFIFO_ERR
106#define FEC_INTR_CLEAR_ALL 0xffffffff /* clear all interrupt events */
107#define FEC_INTR_MASK_ALL 0x00000000 /* mask all interrupt events */
108
109/*
110 * Bit fields for FEC ethernet control, ecntrl above.
111 */
112#define FEC_ECNTRL_TAG 0xf0000000 /* TBUS tag bits */
113/* 0x08000000 reserved */
114#define FEC_ECNTRL_TESTMD 0x04000000 /* test mode */
115/* 0x03fffff8 reserved */
116#define FEC_ECNTRL_OE 0x00000004 /* FEC output enable */
117#define FEC_ECNTRL_EN 0x00000002 /* ethernet enable */
118#define FEC_ECNTRL_RESET 0x00000001 /* ethernet controller reset */
119
120/*
121 * Bit fields for FEC receive control, r_cntrl above.
122 */
123/* 0xf1000000 reserved */
124#define FEC_RCNTRL_MAX_FL 0x07ff0000 /* maximum frame length */
125#define FEC_RCNTRL_MAX_FL_SHIFT 16
126/* 0x0000ffc0 reserved */
127#define FEC_RCNTRL_FCE 0x00000020 /* flow control enable */
128#define FEC_RCNTRL_BC_REJ 0x00000010 /* broadcast frame reject */
129#define FEC_RCNTRL_PROM 0x00000008 /* promiscuous mode */
130#define FEC_RCNTRL_MII_MODE 0x00000004 /* select 18-wire (MII) mode */
131#define FEC_RCNTRL_DRT 0x00000002 /* disable receive on transmit */
132#define FEC_RCNTRL_LOOP 0x00000001 /* internal loopback */
133
134/*
135 * Bit fields for FEC transmit control, x_cntrl above.
136 */
137/* 0xffffffe0 reserved */
138#define FEC_XCNTRL_RFC_PAUS 0x00000010 /* FDX flow control pause rx */
139#define FEC_XCNTRL_TFC_PAUS 0x00000008 /* assert a PAUSE frame */
140#define FEC_XCNTRL_FDEN 0x00000004 /* full duplex enable */
141#define FEC_XCNTRL_HBC 0x00000002 /* heartbeat control */
142#define FEC_XCNTRL_GTS 0x00000001 /* graceful transmit stop */
143
144/*
145 * Bit fields for FEC transmit status, x_status above.
146 */
147/* 0xfc000000 reserved */
148#define FEC_XSTAT_DEF 0x02000000 /* defer */
149#define FEC_XSTAT_HB 0x01000000 /* heartbeat error */
150#define FEC_XSTAT_LC 0x00800000 /* late collision */
151#define FEC_XSTAT_RL 0x00400000 /* retry limit */
152#define FEC_XSTAT_RC 0x003c0000 /* retry count */
153#define FEC_XSTAT_UN 0x00020000 /* underrun */
154#define FEX_XSTAT_CSL 0x00010000 /* carrier sense lost */
155/* 0x0000ffff reserved */
156
157/*
158 * Bit fields for FEC transmit FIFO watermark, x_wmrk above.
159 */
160#define FEC_XWMRK_64 0x00000000 /* 64 bytes written to TxFIFO */
161#define FEC_XWMRK_128 0x00000001 /* 128 bytes written to TxFIFO */
162#define FEC_XWMRK_192 0x00000002 /* 192 bytes written to TxFIFO */
163#define FEC_XWMRK_256 0x00000003 /* 256 bytes written to TxFIFO */
164#define FEC_XWMRK_320 0x00000004 /* 320 bytes written to TxFIFO */
165#define FEC_XWMRK_384 0x00000005 /* 384 bytes written to TxFIFO */
166#define FEC_XWMRK_448 0x00000006 /* 448 bytes written to TxFIFO */
167#define FEC_XWMRK_512 0x00000007 /* 512 bytes written to TxFIFO */
168#define FEC_XWMRK_576 0x00000008 /* 576 bytes written to TxFIFO */
169#define FEC_XWMRK_640 0x00000009 /* 640 bytes written to TxFIFO */
170#define FEC_XWMRK_704 0x0000000a /* 704 bytes written to TxFIFO */
171#define FEC_XWMRK_768 0x0000000b /* 768 bytes written to TxFIFO */
172#define FEC_XWMRK_832 0x0000000c /* 832 bytes written to TxFIFO */
173#define FEC_XWMRK_896 0x0000000d /* 896 bytes written to TxFIFO */
174#define FEC_XWMRK_960 0x0000000e /* 960 bytes written to TxFIFO */
175#define FEC_XWMRK_1024 0x0000000f /* 1024 bytes written to TxFIFO */
176
177/*
178 * Bit fields for FEC transmit finite state machine.
179 */
180/* 0xfc000000 reserved */
181#define FEC_FSM_CRC 0x02000000 /* append CRC (typical use) */
182#define FEC_FSM_ENFSM 0x01000000 /* enable CRC FSM (typical use) */
183/* 0x00ffffff reserved */
184
185/*
186 * Bit fields for FEC FIFOs, rfifo_status, rfifo_cntrl, tfifo_status
187 * and tfifo_cntrl.
188 */
189#define FEC_FIFO_STAT_IP 0x80000000 /* illegal pointer, sticky */
190/* 0x70000000 reserved */
191#define FEC_FIFO_STAT_FRAME 0x0f000000 /* frame indicator */
192#define FEC_FIFO_STAT_FAE 0x00800000 /* frame accept error */
193#define FEC_FIFO_STAT_RXW 0x00400000 /* receive wait condition */
194#define FEC_FIFO_STAT_UF 0x00200000 /* underflow */
195#define FEC_FIFO_STAT_OF 0x00100000 /* overflow */
196#define FEC_FIFO_STAT_FR 0x00080000 /* frame ready, read-only */
197#define FEC_FIFO_STAT_FULL 0x00040000 /* full alarm, read-only */
198#define FEC_FIFO_STAT_ALARM 0x00020000 /* fifo alarm */
199#define FEC_FIFO_STAT_EMPTY 0x00010000 /* empty, read-only */
200/* 0x0000ffff reserved */
201#define FEC_FIFO_STAT_ERROR ( FEC_FIFO_STAT_IP \
202 | FEC_FIFO_STAT_FAE \
203 | FEC_FIFO_STAT_RXW \
204 | FEC_FIFO_STAT_UF \
205 | FEC_FIFO_STAT_OF \
206 )
207
208/* 0x80000000 reserved */
209#define FEC_FIFO_CNTRL_WCTL 0x40000000 /* write control */
210#define FEC_FIFO_CNTRL_WFR 0x20000000 /* write frame */
211/* 0x10000000 reserved */
212#define FEC_FIFO_CNTRL_FRAME 0x08000000 /* frame mode enable */
213#define FEC_FIFO_CNTRL_GR 0x07000000 /* last transfer granularity */
214#define FEC_FIFO_CNTRL_GR_SHIFT 24
215#define FEC_FIFO_CNTRL_IP_MASK 0x00800000 /* illegal pointer mask */
216#define FEC_FIFO_CNTRL_FAE_MASK 0x00400000 /* frame accept mask */
217#define FEC_FIFO_CNTRL_RXW_MASK 0x00200000 /* receive wait mask */
218#define FEC_FIFO_CNTRL_UF_MASK 0x00100000 /* underflow mask */
219#define FEC_FIFO_CNTRL_OF_MASK 0x00080000 /* overflow mask */
220/* 0x0007ffff reserved */
221
222#define SDMA_TCR_EN BSP_BBIT16(0)
223#define SDMA_TCR_VAL BSP_BBIT16(1)
224#define SDMA_TCR_ALW_INIT BSP_BBIT16(2)
225#define SDMA_TCR_IN(val) BSP_BFLD16(val, 3, 7)
226#define SDMA_TCR_AUTO_START BSP_BBIT16(8)
227#define SDMA_TCR_HIGH_EN BSP_BBIT16(9)
228#define SDMA_TCR_HOLD BSP_BBIT16(10)
229#define SDMA_TCR_AS(val) BSP_BFLD16(val, 12, 15)
230
231#define SDMA_IPR_HOLD BSP_BBIT8(0)
232#define SDMA_IPR_PRIOR(val) BSP_BFLD8(val, 5, 7)
233
234#define SDMA_REQMUX_SET_31(reg, val) BSP_BFLD32SET(reg, val, 0, 1)
235#define SDMA_REQMUX_SET_30(reg, val) BSP_BFLD32SET(reg, val, 2, 3)
236#define SDMA_REQMUX_SET_29(reg, val) BSP_BFLD32SET(reg, val, 4, 5)
237#define SDMA_REQMUX_SET_28(reg, val) BSP_BFLD32SET(reg, val, 6, 7)
238#define SDMA_REQMUX_SET_27(reg, val) BSP_BFLD32SET(reg, val, 8, 9)
239#define SDMA_REQMUX_SET_26(reg, val) BSP_BFLD32SET(reg, val, 10, 11)
240#define SDMA_REQMUX_SET_25(reg, val) BSP_BFLD32SET(reg, val, 12, 13)
241#define SDMA_REQMUX_SET_24(reg, val) BSP_BFLD32SET(reg, val, 14, 15)
242#define SDMA_REQMUX_SET_23(reg, val) BSP_BFLD32SET(reg, val, 16, 17)
243#define SDMA_REQMUX_SET_22(reg, val) BSP_BFLD32SET(reg, val, 18, 19)
244#define SDMA_REQMUX_SET_21(reg, val) BSP_BFLD32SET(reg, val, 20, 21)
245#define SDMA_REQMUX_SET_20(reg, val) BSP_BFLD32SET(reg, val, 22, 23)
246#define SDMA_REQMUX_SET_19(reg, val) BSP_BFLD32SET(reg, val, 24, 25)
247#define SDMA_REQMUX_SET_18(reg, val) BSP_BFLD32SET(reg, val, 26, 27)
248#define SDMA_REQMUX_SET_17(reg, val) BSP_BFLD32SET(reg, val, 28, 29)
249#define SDMA_REQMUX_SET_16(reg, val) BSP_BFLD32SET(reg, val, 30, 31)
250
251/* SDMA / BestComm */
252typedef struct {
253 uint32_t taskBar;
254 uint32_t currentPointer;
255 uint32_t endPointer;
256 uint32_t variablePointer;
257 uint8_t IntVect1;
258 uint8_t IntVect2;
259 uint16_t PtdCntrl;
260 uint32_t IntPend;
261 uint32_t IntMask;
262 uint16_t tcr [16];
263 uint8_t ipr [32];
264 uint32_t cReqSelect;
265 uint32_t task_size0;
266 uint32_t task_size1;
267 uint32_t reserved_0;
268 uint32_t reserved_1;
269 uint32_t Value1;
270 uint32_t Value2;
271 uint32_t Control;
272 uint32_t Status;
273} mpc5200_sdma;
274
275typedef struct {
276#define CSC_CFG_WAITP(val) BSP_BFLD32(val, 0, 7)
277#define CSC_CFG_WAITX(val) BSP_BFLD32(val, 8, 15)
278#define CSC_CFG_MX BSP_BBIT32(16)
279#define CSC_CFG_AA BSP_BBIT32(18)
280#define CSC_CFG_CE BSP_BBIT32(19)
281#define CSC_CFG_AS(val) BSP_BFLD32(val, 20, 21)
282#define CSC_CFG_DS(val) BSP_BFLD32(val, 22, 23)
283#define CSC_CFG_BANK(val) BSP_BFLD32(val, 24, 25)
284#define CSC_CFG_WTYP(val) BSP_BFLD32(val, 26, 27)
285#define CSC_CFG_WS BSP_BBIT32(28)
286#define CSC_CFG_RS BSP_BBIT32(29)
287#define CSC_CFG_WO BSP_BBIT32(30)
288#define CSC_CFG_RO BSP_BBIT32(31)
289 uint32_t config_0;
290 uint32_t config_1;
291 uint32_t config_2;
292 uint32_t config_3;
293 uint32_t config_4;
294 uint32_t config_5;
295
296#define CSC_CTRL_ME BSP_BBIT32(7)
297 uint32_t control;
298
299#define CSC_STAT_WOERR BSP_BBIT32(2)
300#define CSC_STAT_ROERR BSP_BBIT32(3)
301#define CSC_STAT_GET_CSXERR(reg) BSP_BFLD32GET(reg, 5, 7)
302 uint32_t status;
303
304 uint32_t config_6;
305 uint32_t config_7;
306
307#define CSC_BST_CTRL_CW7 BSP_BBIT32(0)
308#define CSC_BST_CTRL_SLB7 BSP_BBIT32(1)
309#define CSC_BST_CTRL_BRE7 BSP_BBIT32(3)
310#define CSC_BST_CTRL_CW6 BSP_BBIT32(4)
311#define CSC_BST_CTRL_SLB6 BSP_BBIT32(5)
312#define CSC_BST_CTRL_BRE6 BSP_BBIT32(7)
313#define CSC_BST_CTRL_CW5 BSP_BBIT32(8)
314#define CSC_BST_CTRL_SLB5 BSP_BBIT32(9)
315#define CSC_BST_CTRL_BRE5 BSP_BBIT32(11)
316#define CSC_BST_CTRL_CW4 BSP_BBIT32(12)
317#define CSC_BST_CTRL_SLB4 BSP_BBIT32(13)
318#define CSC_BST_CTRL_BRE4 BSP_BBIT32(15)
319#define CSC_BST_CTRL_CW3 BSP_BBIT32(16)
320#define CSC_BST_CTRL_SLB3 BSP_BBIT32(17)
321#define CSC_BST_CTRL_BRE3 BSP_BBIT32(19)
322#define CSC_BST_CTRL_CW2 BSP_BBIT32(20)
323#define CSC_BST_CTRL_SLB2 BSP_BBIT32(21)
324#define CSC_BST_CTRL_BRE2 BSP_BBIT32(23)
325#define CSC_BST_CTRL_CW1 BSP_BBIT32(24)
326#define CSC_BST_CTRL_SLB1 BSP_BBIT32(25)
327#define CSC_BST_CTRL_BRE1 BSP_BBIT32(27)
328#define CSC_BST_CTRL_CW0 BSP_BBIT32(28)
329#define CSC_BST_CTRL_SLB0 BSP_BBIT32(29)
330#define CSC_BST_CTRL_BRE0 BSP_BBIT32(31)
331 uint32_t burst_control;
332
333#define CSC_DCYC_CTRL_DC7(val) BSP_BFLD32(val, 2, 3)
334#define CSC_DCYC_CTRL_SET_DC7(reg, val) BSP_BFLD32SET(reg, val, 2, 3)
335#define CSC_DCYC_CTRL_DC6(val) BSP_BFLD32(val, 6, 7)
336#define CSC_DCYC_CTRL_SET_DC6(reg, val) BSP_BFLD32SET(reg, val, 6, 7)
337#define CSC_DCYC_CTRL_DC5(val) BSP_BFLD32(val, 10, 11)
338#define CSC_DCYC_CTRL_SET_DC5(reg, val) BSP_BFLD32SET(reg, val, 10, 11)
339#define CSC_DCYC_CTRL_DC4(val) BSP_BFLD32(val, 14, 15)
340#define CSC_DCYC_CTRL_SET_DC4(reg, val) BSP_BFLD32SET(reg, val, 14, 15)
341#define CSC_DCYC_CTRL_DC3(val) BSP_BFLD32(val, 18, 19)
342#define CSC_DCYC_CTRL_SET_DC3(reg, val) BSP_BFLD32SET(reg, val, 18, 19)
343#define CSC_DCYC_CTRL_DC2(val) BSP_BFLD32(val, 22, 23)
344#define CSC_DCYC_CTRL_SET_DC2(reg, val) BSP_BFLD32SET(reg, val, 22, 23)
345#define CSC_DCYC_CTRL_DC1(val) BSP_BFLD32(val, 26, 27)
346#define CSC_DCYC_CTRL_SET_DC1(reg, val) BSP_BFLD32SET(reg, val, 26, 27)
347#define CSC_DCYC_CTRL_DC0(val) BSP_BFLD32(val, 30, 31)
348#define CSC_DCYC_CTRL_SET_DC0(reg, val) BSP_BFLD32SET(reg, val, 30, 31)
349 uint32_t deadcycle_control;
350
351 uint8_t reserved [208];
352} mpc5200_csc;
353
354typedef struct {
355 uint32_t memory_address_base;
356 uint32_t cs0_start_address;
357 uint32_t cs0_stop_address;
358 uint32_t cs1_start_address;
359 uint32_t cs1_stop_address;
360 uint32_t cs2_start_address;
361 uint32_t cs2_stop_address;
362 uint32_t cs3_start_address;
363 uint32_t cs3_stop_address;
364 uint32_t cs4_start_address;
365 uint32_t cs4_stop_address;
366 uint32_t cs5_start_address;
367 uint32_t cs5_stop_address;
368 uint32_t sdram_chip_select_0;
369 uint32_t sdram_chip_select_1;
370 uint8_t reserved_0 [16];
371 uint32_t boot_start_address;
372 uint32_t boot_stop_address;
373
374#define MM_IPBI_CTRL_CS7ENA BSP_BBIT16(4)
375#define MM_IPBI_CTRL_CS6ENA BSP_BBIT16(5)
376#define MM_IPBI_CTRL_BOOTENA BSP_BBIT16(6)
377#define MM_IPBI_CTRL_CS5ENA BSP_BBIT16(10)
378#define MM_IPBI_CTRL_CS4ENA BSP_BBIT16(11)
379#define MM_IPBI_CTRL_CS3ENA BSP_BBIT16(12)
380#define MM_IPBI_CTRL_CS2ENA BSP_BBIT16(13)
381#define MM_IPBI_CTRL_CS1ENA BSP_BBIT16(14)
382#define MM_IPBI_CTRL_CS0ENA BSP_BBIT16(15)
383 uint16_t ipbi_control;
384
385 uint16_t wait_state_enable;
386 uint32_t cs6_start_address;
387 uint32_t cs6_stop_address;
388 uint32_t cs7_start_address;
389 uint32_t cs7_stop_address;
390 uint8_t reserved_1 [152];
391} mpc5200_mm;
392
393/*
394*************************************************************************
395* MPC5x00 internal register memory map *
396*************************************************************************
397*/
398typedef struct mpc5200_ {
399 /*
400 * memory map registers (MBAR + 0)
401 */
402 volatile mpc5200_mm mm;
403
404 /*
405 * SDRAM memory controller registers (MBAR + 0x100)
406 */
407 volatile uint8_t mc[0x100];
408
409 /*
410 * clock distribution module registers (MBAR + 0x200)
411 */
412 volatile uint8_t cdm[0x100];
413
414 /*
415 * chip selct controller registers(MBAR + 0x300)
416 */
417 volatile mpc5200_csc csc;
418
419 /*
420 * SmartComm timer registers (MBAR + 0x400)
421 */
422 volatile uint8_t sct[0x100];
423
424 /*
425 * interrupt controller registers (MBAR + 0x500)
426 */
427 volatile uint32_t per_mask; /* + 0x00 */
428 volatile uint32_t per_pri_1; /* + 0x04 */
429 volatile uint32_t per_pri_2; /* + 0x08 */
430 volatile uint32_t per_pri_3; /* + 0x0C */
431
432#define ICTL_EET_ECLR0 BSP_BBIT32(4)
433#define ICTL_EET_ECLR1 BSP_BBIT32(5)
434#define ICTL_EET_ECLR2 BSP_BBIT32(6)
435#define ICTL_EET_ECLR3 BSP_BBIT32(7)
436#define ICTL_EET_ETYPE0(val) BSP_BFLD32(val, 8, 9)
437#define ICTL_EET_ETYPE1(val) BSP_BFLD32(val, 10, 11)
438#define ICTL_EET_ETYPE2(val) BSP_BFLD32(val, 12, 13)
439#define ICTL_EET_ETYPE3(val) BSP_BFLD32(val, 14, 15)
440#define ICTL_EET_SET_ETYPE0(reg, val) BSP_BFLD32SET(reg, val, 8, 9)
441#define ICTL_EET_SET_ETYPE1(reg, val) BSP_BFLD32SET(reg, val, 10, 11)
442#define ICTL_EET_SET_ETYPE2(reg, val) BSP_BFLD32SET(reg, val, 12, 13)
443#define ICTL_EET_SET_ETYPE3(reg, val) BSP_BFLD32SET(reg, val, 14, 15)
444#define ICTL_EET_MEE BSP_BBIT32(19)
445#define ICTL_EET_EENA0 BSP_BBIT32(20)
446#define ICTL_EET_EENA1 BSP_BBIT32(21)
447#define ICTL_EET_EENA2 BSP_BBIT32(22)
448#define ICTL_EET_EENA3 BSP_BBIT32(23)
449#define ICTL_EET_CEB BSP_BBIT32(31)
450
451 volatile uint32_t ext_en_type; /* + 0x10 */
452 volatile uint32_t crit_pri_main_mask;/* + 0x14 */
453 volatile uint32_t main_pri_1; /* + 0x18 */
454 volatile uint32_t main_pri_2; /* + 0x1C */
455 volatile uint32_t res1; /* + 0x20 */
456 volatile uint32_t pmce; /* + 0x24 */
457 volatile uint32_t csa; /* + 0x28 */
458 volatile uint32_t msa; /* + 0x2C */
459 volatile uint32_t psa; /* + 0x30 */
460 volatile uint32_t res2; /* + 0x34 */
461 volatile uint32_t psa_be; /* + 0x38 */
462 volatile uint8_t res3[0xC4]; /* + 0x3C */
463
464 /*
465 * general pupose timer registers (MBAR + 0x600/+ 0x610/+ 0x620/+ 0x630/+ 0x640/+ 0x650/+ 0x660/+ 0x670)
466 */
467 struct mpc5200_gpt {
468 volatile uint32_t emsel; /* + 0x00 */
469 volatile uint32_t count_in; /* + 0x04 */
470 volatile uint32_t pwm_conf; /* + 0x08 */
471 volatile uint32_t status; /* + 0x0C */
472 } gpt[MPC5200_GPT_NO];
473
474#define GPT_STATUS_RESET 0x0000000F
475#define GPT_STATUS_TEXP (1 << 3)
476#define GPT_STATUS_PIN (1 << 8)
477#define GPT_EMSEL_GPIO_DIR (2 << 4)
478#define GPT_EMSEL_GPIO_OUT (1 << 4)
479#define GPT_EMSEL_GPIO_OUT_HIGH (3 << 4)
480#define GPT_EMSEL_TIMER_MS_GPIO (4 << 0)
481#define GPT_EMSEL_GPIO_IN (0 << 0)
482#define GPT_EMSEL_CE (1 << 12)
483#define GPT_EMSEL_ST_CONT (1 << 10)
484#define GPT_EMSEL_INTEN (1 << 8)
485#define GPT_EMSEL_WDEN (1 << 15)
486
487#define GPT0 0
488#define GPT1 1
489#define GPT2 2
490#define GPT3 3
491#define GPT4 4
492#define GPT5 5
493#define GPT6 6
494#define GPT7 7
495
496 volatile uint8_t gpt_res[0x80];
497
498 /*
499 * slice time registers (MBAR + 0x700/+ 0x710)
500 */
501 struct mpc5200_slt {
502 volatile uint32_t tcr; /* + 0x00 */
503 volatile uint32_t cntrl; /* + 0x04 */
504 volatile uint32_t cvr; /* + 0x08 */
505 volatile uint32_t tsr; /* + 0x0C */
506 } slt[MPC5200_SLT_NO];
507
508 volatile uint8_t slt_res[0xE0];
509
510 /*
511 * real time clock registers (MBAR + 0x800)
512 */
513 volatile uint8_t rtc[0x100];
514
515
516 /*
517 * MSCAN registers (MBAR + 0x900 /+ 0x980)
518 */
519 struct mpc5200_mscan {
520 volatile uint8_t ctl0; /* + 0x0 */
521 volatile uint8_t ctl1; /* + 0x1 */
522 volatile uint8_t res1; /* + 0x2 */
523 volatile uint8_t res2; /* + 0x3 */
524 volatile uint8_t btr0; /* + 0x4 */
525 volatile uint8_t btr1; /* + 0x5 */
526 volatile uint8_t res3; /* + 0x6 */
527 volatile uint8_t res4; /* + 0x7 */
528 volatile uint8_t rflg; /* + 0x8 */
529 volatile uint8_t rier; /* + 0x9 */
530 volatile uint8_t res5; /* + 0xA */
531 volatile uint8_t res6; /* + 0xB */
532 volatile uint8_t tflg; /* + 0xC */
533 volatile uint8_t tier; /* + 0xD */
534 volatile uint8_t res7; /* + 0xE */
535 volatile uint8_t res8; /* + 0xF */
536 volatile uint8_t tarq; /* + 0x10 */
537 volatile uint8_t taak; /* + 0x11 */
538 volatile uint8_t res9; /* + 0x12 */
539 volatile uint8_t res10; /* + 0x13 */
540 volatile uint8_t bsel; /* + 0x14 */
541 volatile uint8_t idac; /* + 0x15 */
542 volatile uint8_t res11; /* + 0x16 */
543 volatile uint8_t res12; /* + 0x17 */
544 volatile uint8_t res13; /* + 0x18 */
545 volatile uint8_t res14; /* + 0x19 */
546 volatile uint8_t res15; /* + 0x1A */
547 volatile uint8_t res16; /* + 0x1B */
548 volatile uint8_t rxerr; /* + 0x1C */
549 volatile uint8_t txerr; /* + 0x1D */
550 volatile uint8_t res17; /* + 0x1E */
551 volatile uint8_t res18; /* + 0x1F */
552 volatile uint8_t idar0; /* + 0x20 */
553 volatile uint8_t idar1; /* + 0x21 */
554 volatile uint8_t res19; /* + 0x22 */
555 volatile uint8_t res20; /* + 0x23 */
556 volatile uint8_t idar2; /* + 0x24 */
557 volatile uint8_t idar3; /* + 0x25 */
558 volatile uint8_t res21; /* + 0x26 */
559 volatile uint8_t res22; /* + 0x27 */
560 volatile uint8_t idmr0; /* + 0x28 */
561 volatile uint8_t idmr1; /* + 0x29 */
562 volatile uint8_t res23; /* + 0x2A */
563 volatile uint8_t res24; /* + 0x2B */
564 volatile uint8_t idmr2; /* + 0x2C */
565 volatile uint8_t idmr3; /* + 0x2D */
566 volatile uint8_t res25; /* + 0x2E */
567 volatile uint8_t res26; /* + 0x2F */
568 volatile uint8_t idar4; /* + 0x30 */
569 volatile uint8_t idar5; /* + 0x31 */
570 volatile uint8_t res27; /* + 0x32 */
571 volatile uint8_t res28; /* + 0x33 */
572 volatile uint8_t idar6; /* + 0x34 */
573 volatile uint8_t idar7; /* + 0x35 */
574 volatile uint8_t res29; /* + 0x36 */
575 volatile uint8_t res30; /* + 0x37 */
576 volatile uint8_t idmr4; /* + 0x38 */
577 volatile uint8_t idmr5; /* + 0x39 */
578 volatile uint8_t res31; /* + 0x3A */
579 volatile uint8_t res32; /* + 0x3B */
580 volatile uint8_t idmr6; /* + 0x3C */
581 volatile uint8_t idmr7; /* + 0x3D */
582 volatile uint8_t res33; /* + 0x3E */
583 volatile uint8_t res34; /* + 0x3F */
584 volatile uint8_t rxidr0; /* + 0x40 */
585 volatile uint8_t rxidr1; /* + 0x41 */
586 volatile uint8_t res35; /* + 0x42 */
587 volatile uint8_t res36; /* + 0x43 */
588 volatile uint8_t rxidr2; /* + 0x44 */
589 volatile uint8_t rxidr3; /* + 0x45 */
590 volatile uint8_t res37; /* + 0x46 */
591 volatile uint8_t res38; /* + 0x47 */
592 volatile uint8_t rxdsr0; /* + 0x48 */
593 volatile uint8_t rxdsr1; /* + 0x49 */
594 volatile uint8_t res39; /* + 0x4A */
595 volatile uint8_t res40; /* + 0x4B */
596 volatile uint8_t rxdsr2; /* + 0x4C */
597 volatile uint8_t rxdsr3; /* + 0x4D */
598 volatile uint8_t res41; /* + 0x4E */
599 volatile uint8_t res42; /* + 0x4F */
600 volatile uint8_t rxdsr4; /* + 0x50 */
601 volatile uint8_t rxdsr5; /* + 0x51 */
602 volatile uint8_t res43; /* + 0x52 */
603 volatile uint8_t res44; /* + 0x53 */
604 volatile uint8_t rxdsr6; /* + 0x54 */
605 volatile uint8_t rxdsr7; /* + 0x55 */
606 volatile uint8_t res45; /* + 0x56 */
607 volatile uint8_t res46; /* + 0x57 */
608 volatile uint8_t rxdlr; /* + 0x58 */
609 volatile uint8_t res47; /* + 0x59 */
610 volatile uint8_t res48; /* + 0x5A */
611 volatile uint8_t res49; /* + 0x5B */
612 volatile uint8_t rxtimh; /* + 0x5C */
613 volatile uint8_t rxtiml; /* + 0x5D */
614 volatile uint8_t res50; /* + 0x5E */
615 volatile uint8_t res51; /* + 0x5F */
616 volatile uint8_t txidr0; /* + 0x60 */
617 volatile uint8_t txidr1; /* + 0x61 */
618 volatile uint8_t res52; /* + 0x62 */
619 volatile uint8_t res53; /* + 0x63 */
620 volatile uint8_t txidr2; /* + 0x64 */
621 volatile uint8_t txidr3; /* + 0x65 */
622 volatile uint8_t res54; /* + 0x66 */
623 volatile uint8_t res55; /* + 0x67 */
624 volatile uint8_t txdsr0; /* + 0x68 */
625 volatile uint8_t txdsr1; /* + 0x69 */
626 volatile uint8_t res56; /* + 0x6A */
627 volatile uint8_t res57; /* + 0x6B */
628 volatile uint8_t txdsr2; /* + 0x6C */
629 volatile uint8_t txdsr3; /* + 0x6D */
630 volatile uint8_t res58; /* + 0x6E */
631 volatile uint8_t res59; /* + 0x6F */
632 volatile uint8_t txdsr4; /* + 0x70 */
633 volatile uint8_t txdsr5; /* + 0x71 */
634 volatile uint8_t res60; /* + 0x72 */
635 volatile uint8_t res61; /* + 0x73 */
636 volatile uint8_t txdsr6; /* + 0x74 */
637 volatile uint8_t txdsr7; /* + 0x75 */
638 volatile uint8_t res62; /* + 0x76 */
639 volatile uint8_t res63; /* + 0x77 */
640 volatile uint8_t txdlr; /* + 0x78 */
641 volatile uint8_t txtbpr; /* + 0x79 */
642 volatile uint8_t res64; /* + 0x7A */
643 volatile uint8_t res65; /* + 0x7B */
644 volatile uint8_t txtimh; /* + 0x7C */
645 volatile uint8_t txtiml; /* + 0x7D */
646 volatile uint8_t res66; /* + 0x7E */
647 volatile uint8_t res67; /* + 0x7F */
648 } mscan[MPC5200_CAN_NO];
649
650 volatile uint8_t res[0x100];
651
652 /*
653 * GPIO standard registers (MBAR + 0xB00)
654 */
655 volatile uint32_t gpiopcr; /* + 0x00 */
656 #define GPIO_PCR_CHIP_SELECT_1 0x80000000
657 #define GPIO_PCR_CHIP_ALTS 0x30000000
658 #define GPIO_PCR_CHIP_ALTS_NONE 0x00000000
659 #define GPIO_PCR_CHIP_ALTS_CAN 0x10000000
660 #define GPIO_PCR_CHIP_ALTS_SPI 0x20000000
661 #define GPIO_PCR_CHIP_ALTS_BOTH 0x30000000
662 #define GPIO_PCR_CHIP_SELECT_7 0x08000000
663 #define GPIO_PCR_CHIP_SELECT_6 0x04000000
664 #define GPIO_PCR_CHIP_SELECT_ATA 0x03000000
665 #define GPIO_PCR_CHIP_SELECT_IR_USB_CLK 0x00800000
666 #define GPIO_PCR_IRDA 0x00700000
667 #define GPIO_PCR_ETHERNET 0x000F0000
668 #define GPIO_PCR_PCI_DIS 0x00008000
669 #define GPIO_PCR_USB_SE 0x00004000
670 #define GPIO_PCR_USB_GPIO 0x00003000
671 #define GPIO_PCR_PSC3 0x00000F00
672 #define GPIO_PCR_PSC2 0x00000070
673 #define GPIO_PCR_PSC1 0x00000007
674
675 #define GPIO_S_PIN_IR_USB_CLK BSP_BBIT32(2)
676 #define GPIO_S_PIN_IRDA_TX BSP_BBIT32(3)
677 #define GPIO_S_PIN_ETH_11 BSP_BBIT32(4)
678 #define GPIO_S_PIN_ETH_10 BSP_BBIT32(5)
679 #define GPIO_S_PIN_ETH_9 BSP_BBIT32(6)
680 #define GPIO_S_PIN_ETH_8 BSP_BBIT32(7)
681 #define GPIO_S_PIN_USB1_8 BSP_BBIT32(12)
682 #define GPIO_S_PIN_USB1_7 BSP_BBIT32(13)
683 #define GPIO_S_PIN_USB1_6 BSP_BBIT32(14)
684 #define GPIO_S_PIN_USB1_0 BSP_BBIT32(15)
685 #define GPIO_S_PIN_PSC3_7 BSP_BBIT32(18)
686 #define GPIO_S_PIN_PSC3_6 BSP_BBIT32(19)
687 #define GPIO_S_PIN_PSC3_3 BSP_BBIT32(20)
688 #define GPIO_S_PIN_PSC3_2 BSP_BBIT32(21)
689 #define GPIO_S_PIN_PSC3_1 BSP_BBIT32(22)
690 #define GPIO_S_PIN_PSC3_0 BSP_BBIT32(23)
691 #define GPIO_S_PIN_PSC2_3 BSP_BBIT32(24)
692 #define GPIO_S_PIN_PSC2_2 BSP_BBIT32(25)
693 #define GPIO_S_PIN_PSC2_1 BSP_BBIT32(26)
694 #define GPIO_S_PIN_PSC2_0 BSP_BBIT32(27)
695 #define GPIO_S_PIN_PSC1_3 BSP_BBIT32(28)
696 #define GPIO_S_PIN_PSC1_2 BSP_BBIT32(29)
697 #define GPIO_S_PIN_PSC1_1 BSP_BBIT32(30)
698 #define GPIO_S_PIN_PSC1_0 BSP_BBIT32(31)
699
700 volatile uint32_t gpiosen; /* + 0x04 */
701 volatile uint32_t gpiosod; /* + 0x08 */
702 volatile uint32_t gpiosdd; /* + 0x0C */
703 volatile uint32_t gpiosdo; /* + 0x10 */
704 volatile uint32_t gpiosdi; /* + 0x14 */
705
706 #define GPIO_O_PIN_ETH_7 BSP_BBIT32(0)
707 #define GPIO_O_PIN_ETH_6 BSP_BBIT32(1)
708 #define GPIO_O_PIN_ETH_5 BSP_BBIT32(2)
709 #define GPIO_O_PIN_ETH_4 BSP_BBIT32(3)
710 #define GPIO_O_PIN_ETH_3 BSP_BBIT32(4)
711 #define GPIO_O_PIN_ETH_2 BSP_BBIT32(5)
712 #define GPIO_O_PIN_ETH_1 BSP_BBIT32(6)
713 #define GPIO_O_PIN_ETH_0 BSP_BBIT32(7)
714 #define GPIO_O_PIN_I2C_3 BSP_BBIT32(13)
715 #define GPIO_O_PIN_I2C_0 BSP_BBIT32(14)
716 #define GPIO_O_PIN_I2C_1 BSP_BBIT32(15)
717
718 volatile uint32_t gpiooe; /* + 0x18 */
719 volatile uint32_t gpioodo; /* + 0x1C */
720
721 #define GPIO_I_PIN_ETH_16 BSP_BBIT32(0)
722 #define GPIO_I_PIN_ETH_15 BSP_BBIT32(1)
723 #define GPIO_I_PIN_ETH_14 BSP_BBIT32(2)
724 #define GPIO_I_PIN_ETH_13 BSP_BBIT32(3)
725 #define GPIO_I_PIN_USB1_9 BSP_BBIT32(4)
726 #define GPIO_I_PIN_PSC3_8 BSP_BBIT32(5)
727 #define GPIO_I_PIN_PSC3_5 BSP_BBIT32(6)
728 #define GPIO_I_PIN_PSC3_4 BSP_BBIT32(7)
729
730 volatile uint32_t gpiosie; /* + 0x20 */
731 #define GPIO_SIE_SINT_7_ETH_16_PIN 0x80000000
732 #define GPIO_SIE_SINT_6_ETH_15_PIN 0x40000000
733 #define GPIO_SIE_SINT_5_ETH_14_PIN 0x20000000
734 #define GPIO_SIE_SINT_4_ETH_13_PIN 0x10000000
735 #define GPIO_SIE_SINT_3_USB1_9_PIN 0x08000000
736 #define GPIO_SIE_SINT_2_PSC3_8_PIN 0x04000000
737 #define GPIO_SIE_SINT_1_PSC3_5_PIN 0x02000000
738 #define GPIO_SIE_SINT_0_PSC3_4_PIN 0x01000000
739
740 volatile uint32_t gpiosiod; /* + 0x24 */
741
742 volatile uint32_t gpiosidd; /* + 0x28 */
743 #define GPIO_SIDD_SINT_7_ETH_16_PIN 0x80000000
744 #define GPIO_SIDD_SINT_6_ETH_15_PIN 0x40000000
745 #define GPIO_SIDD_SINT_5_ETH_14_PIN 0x20000000
746 #define GPIO_SIDD_SINT_4_ETH_13_PIN 0x10000000
747 #define GPIO_SIDD_SINT_3_USB1_9_PIN 0x08000000
748 #define GPIO_SIDD_SINT_2_PSC3_8_PIN 0x04000000
749 #define GPIO_SIDD_SINT_1_PSC3_5_PIN 0x02000000
750 #define GPIO_SIDD_SINT_0_PSC3_4_PIN 0x01000000
751
752 volatile uint32_t gpiosido; /* + 0x2C */
753
754 volatile uint32_t gpiosiie; /* + 0x30 */
755 #define GPIO_SIIE_SINT_7_ETH_16_PIN 0x80000000
756 #define GPIO_SIIE_SINT_6_ETH_15_PIN 0x40000000
757 #define GPIO_SIIE_SINT_5_ETH_14_PIN 0x20000000
758 #define GPIO_SIIE_SINT_4_ETH_13_PIN 0x10000000
759 #define GPIO_SIIE_SINT_3_USB1_9_PIN 0x08000000
760 #define GPIO_SIIE_SINT_2_PSC3_8_PIN 0x04000000
761 #define GPIO_SIIE_SINT_1_PSC3_5_PIN 0x02000000
762 #define GPIO_SIIE_SINT_0_PSC3_4_PIN 0x01000000
763
764 volatile uint32_t gpiosiit; /* + 0x34 */
765 #define GPIO_SIIT_SET_ETH_16_PIN(reg, val) BSP_BFLD32SET(reg, val, 0, 1)
766 #define GPIO_SIIT_SET_ETH_15_PIN(reg, val) BSP_BFLD32SET(reg, val, 2, 3)
767 #define GPIO_SIIT_SET_ETH_14_PIN(reg, val) BSP_BFLD32SET(reg, val, 4, 5)
768 #define GPIO_SIIT_SET_ETH_13_PIN(reg, val) BSP_BFLD32SET(reg, val, 6, 7)
769 #define GPIO_SIIT_SET_USB1_9_PIN(reg, val) BSP_BFLD32SET(reg, val, 8, 9)
770 #define GPIO_SIIT_SET_PSC3_8_PIN(reg, val) BSP_BFLD32SET(reg, val, 10, 11)
771 #define GPIO_SIIT_SET_PSC3_5_PIN(reg, val) BSP_BFLD32SET(reg, val, 12, 13)
772 #define GPIO_SIIT_SET_PSC3_4_PIN(reg, val) BSP_BFLD32SET(reg, val, 14, 15)
773
774 #define GPIO_SIIT_SINT_7_ETH_16_PIN_MASK 0xc0000000
775 #define GPIO_SIIT_SINT_6_ETH_15_PIN_MASK 0x30000000
776 #define GPIO_SIIT_SINT_5_ETH_14_PIN_MASK 0x0c000000
777 #define GPIO_SIIT_SINT_4_ETH_13_PIN_MASK 0x03000000
778 #define GPIO_SIIT_SINT_3_USB1_9_PIN_MASK 0x00c00000
779 #define GPIO_SIIT_SINT_2_PSC3_8_PIN_MASK 0x00300000
780 #define GPIO_SIIT_SINT_1_PSC3_5_PIN_MASK 0x000c0000
781 #define GPIO_SIIT_SINT_0_PSC3_4_PIN_MASK 0x00030000
782
783 #define GPIO_SIIT_ON_ANY_TRANSITION 0x00000000
784 #define GPIO_SIIT_ON_RISING_EDGE 0x00000001
785 #define GPIO_SIIT_ON_FALLING_EDGE 0x00000002
786 #define GPIO_SIIT_ON_PULSE 0x00000003
787
788 #define GPIO_SIIT_SINT_7_ETH_16_PIN_SHIFT 16
789 #define GPIO_SIIT_SINT_6_ETH_15_PIN_SHIFT 18
790 #define GPIO_SIIT_SINT_5_ETH_14_PIN_SHIFT 20
791 #define GPIO_SIIT_SINT_4_ETH_13_PIN_SHIFT 22
792 #define GPIO_SIIT_SINT_3_USB1_9_PIN_SHIFT 24
793 #define GPIO_SIIT_SINT_2_PSC3_8_PIN_SHIFT 26
794 #define GPIO_SIIT_SINT_1_PSC3_5_PIN_SHIFT 28
795 #define GPIO_SIIT_SINT_0_PSC3_4_PIN_SHIFT 30
796
797 volatile uint32_t gpiosime; /* + 0x38 */
798 #define GPIO_SIME_MASTER_ENABLE 0x10000000
799
800 volatile uint32_t gpiosist; /* + 0x3C */
801 #define GPIO_SIST_SINT_7_ETH_16_PIN_STATUS 0x80000000
802 #define GPIO_SIST_SINT_6_ETH_15_PIN_STATUS 0x40000000
803 #define GPIO_SIST_SINT_5_ETH_14_PIN_STATUS 0x20000000
804 #define GPIO_SIST_SINT_4_ETH_13_PIN_STATUS 0x10000000
805 #define GPIO_SIST_SINT_3_USB1_9_PIN_STATUS 0x08000000
806 #define GPIO_SIST_SINT_2_PSC3_8_PIN_STATUS 0x04000000
807 #define GPIO_SIST_SINT_1_PSC3_5_PIN_STATUS 0x02000000
808 #define GPIO_SIST_SINT_0_PSC3_4_PIN_STATUS 0x01000000
809 #define GPIO_SIST_SINT_7_ETH_16_PIN_VALUE 0x00800000
810 #define GPIO_SIST_SINT_6_ETH_15_PIN_VALUE 0x00400000
811 #define GPIO_SIST_SINT_5_ETH_14_PIN_VALUE 0x00200000
812 #define GPIO_SIST_SINT_4_ETH_13_PIN_VALUE 0x00100000
813 #define GPIO_SIST_SINT_3_USB1_9_PIN_VALUE 0x00080000
814 #define GPIO_SIST_SINT_2_PSC3_8_PIN_VALUE 0x00040000
815 #define GPIO_SIST_SINT_1_PSC3_5_PIN_VALUE 0x00020000
816 #define GPIO_SIST_SINT_0_PSC3_4_PIN_VALUE 0x00010000
817
818 #define GPIO_SIST_SINT_CLEAR_ALL 0xff000000
819
820 volatile uint8_t res4[0xC0];
821
822 /*
823 * GPIO wakeup registers (MBAR + 0xC00)
824 */
825
826 #define GPIO_W_PIN_GPIO_WKUP_7 BSP_BBIT32(0)
827 #define GPIO_W_PIN_GPIO_WKUP_6 BSP_BBIT32(1)
828 #define GPIO_W_PIN_PSC6_1 BSP_BBIT32(2)
829 #define GPIO_W_PIN_PSC6_0 BSP_BBIT32(3)
830 #define GPIO_W_PIN_ETH_17 BSP_BBIT32(4)
831 #define GPIO_W_PIN_PSC3_9 BSP_BBIT32(5)
832 #define GPIO_W_PIN_PSC2_4 BSP_BBIT32(6)
833 #define GPIO_W_PIN_PSC1_4 BSP_BBIT32(7)
834
835 volatile uint32_t gpiowe; /* + 0x00 */
836 volatile uint32_t gpiowod; /* + 0x04 */
837 volatile uint32_t gpiowdd; /* + 0x08 */
838 volatile uint32_t gpiowdo; /* + 0x0C */
839 volatile uint32_t gpiowue; /* + 0x10 */
840 volatile uint32_t gpiowsie; /* + 0x14 */
841 volatile uint32_t gpiowt; /* + 0x18 */
842 volatile uint32_t gpiowme; /* + 0x1C */
843 volatile uint32_t gpiowi; /* + 0x20 */
844 volatile uint32_t gpiows; /* + 0x24 */
845 volatile uint8_t gpiow_res[0xD8];
846
847 /*
848 * PPC PCI registers (MBAR + 0xD00)
849 */
850 volatile uint8_t ppci[0x100];
851
852 /*
853 * consumer infrared registers (MBAR + 0xE00)
854 */
855 volatile uint8_t ir[0x100];
856
857 /*
858 * serial peripheral interface registers (MBAR + 0xF00)
859 */
860 volatile uint8_t spi[0x100];
861
862 /*
863 * universal serial bus registers (MBAR + 0x1000)
864 */
865 volatile uint8_t usb[0x200];
866
867 /*
868 * SmartComm DMA registers (MBAR + 0x1200)
869 */
870 volatile mpc5200_sdma sdma;
871
872 volatile uint32_t EU00; /* + 0x80 sdMac macer reg */
873 volatile uint32_t EU01; /* + 0x84 sdMac macemr reg */
874 volatile uint32_t EU02; /* + 0x88 unused */
875 volatile uint32_t EU03; /* + 0x8c unused */
876 volatile uint32_t EU04; /* + 0x90 unused */
877 volatile uint32_t EU05; /* + 0x94 unused */
878 volatile uint32_t EU06; /* + 0x98 unused */
879 volatile uint32_t EU07; /* + 0x9c unused */
880 volatile uint32_t EU10; /* + 0xa0 unused */
881 volatile uint32_t EU11; /* + 0xa4 unused */
882 volatile uint32_t EU12; /* + 0xa8 unused */
883 volatile uint32_t EU13; /* + 0xac unused */
884 volatile uint32_t EU14; /* + 0xb0 unused */
885 volatile uint32_t EU15; /* + 0xb4 unused */
886 volatile uint32_t EU16; /* + 0xb8 unused */
887 volatile uint32_t EU17; /* + 0xbc unused */
888 volatile uint32_t EU20; /* + 0xc0 unused */
889 volatile uint32_t EU21; /* + 0xc4 unused */
890 volatile uint32_t EU22; /* + 0xc8 unused */
891 volatile uint32_t EU23; /* + 0xcc unused */
892 volatile uint32_t EU24; /* + 0xd0 unused */
893 volatile uint32_t EU25; /* + 0xd4 unused */
894 volatile uint32_t EU26; /* + 0xd8 unused */
895 volatile uint32_t EU27; /* + 0xdc unused */
896 volatile uint32_t EU30; /* + 0xe0 unused */
897 volatile uint32_t EU31; /* + 0xe4 unused */
898 volatile uint32_t EU32; /* + 0xe8 unused */
899 volatile uint32_t EU33; /* + 0xec unused */
900 volatile uint32_t EU34; /* + 0xf0 unused */
901 volatile uint32_t EU35; /* + 0xf4 unused */
902 volatile uint32_t EU36; /* + 0xf8 unused */
903 volatile uint32_t EU37; /* + 0xfc unused */
904#if 0
905 volatile uint32_t res8[0x340];
906#else
907 volatile uint8_t res_1300[0xc00];
908
909 volatile uint32_t reserved0; /* MBAR_XLB_ARB + 0x0000 reserved */
910 volatile uint32_t reserved1; /* MBAR_XLB_ARB + 0x0004 reserved */
911 volatile uint32_t reserved2; /* MBAR_XLB_ARB + 0x0008 reserved */
912 volatile uint32_t reserved3; /* MBAR_XLB_ARB + 0x000c reserved */
913 volatile uint32_t reserved4; /* MBAR_XLB_ARB + 0x0010 reserved */
914 volatile uint32_t reserved5; /* MBAR_XLB_ARB + 0x0014 reserved */
915 volatile uint32_t reserved6; /* MBAR_XLB_ARB + 0x0018 reserved */
916 volatile uint32_t reserved7; /* MBAR_XLB_ARB + 0x001c reserved */
917 volatile uint32_t reserved8; /* MBAR_XLB_ARB + 0x0020 reserved */
918 volatile uint32_t reserved9; /* MBAR_XLB_ARB + 0x0024 reserved */
919 volatile uint32_t reserved10; /* MBAR_XLB_ARB + 0x0028 reserved */
920 volatile uint32_t reserved11; /* MBAR_XLB_ARB + 0x002c reserved */
921 volatile uint32_t reserved12; /* MBAR_XLB_ARB + 0x0030 reserved */
922 volatile uint32_t reserved13; /* MBAR_XLB_ARB + 0x0034 reserved */
923 volatile uint32_t reserved14; /* MBAR_XLB_ARB + 0x0038 reserved */
924 volatile uint32_t reserved15; /* MBAR_XLB_ARB + 0x003c reserved */
925
926#define XLB_CFG_PLDIS BSP_BBIT32(0)
927#define XLB_CFG_BSDIS BSP_BBIT32(15)
928#define XLB_CFG_SE BSP_BBIT32(16)
929#define XLB_CFG_USE_WWF BSP_BBIT32(17)
930#define XLB_CFG_TBEN BSP_BBIT32(18)
931#define XLB_CFG_WS BSP_BBIT32(20)
932#define XLB_CFG_SP(val) BSP_BFLD32(val, 21, 23)
933#define XLB_CFG_SET_SP(reg, val) BSP_BFLD32SET(reg, val, 21, 23)
934#define XLB_CFG_PM(val) BSP_BFLD32(val, 25, 26)
935#define XLB_CFG_SET_PM(reg, val) BSP_BFLD32SET(reg, val, 25, 26)
936#define XLB_CFG_BA BSP_BBIT32(28)
937#define XLB_CFG_DT BSP_BBIT32(29)
938#define XLB_CFG_AT BSP_BBIT32(30)
939
940 volatile uint32_t config; /* MBAR_XLB_ARB + 0x0040 */
941 volatile uint32_t version; /* MBAR_XLB_ARB + 0x0044 */
942
943#define XLB_ST_SEA BSP_BBIT32(23)
944#define XLB_ST_MM BSP_BBIT32(24)
945#define XLB_ST_TTA BSP_BBIT32(25)
946#define XLB_ST_TTR BSP_BBIT32(26)
947#define XLB_ST_ECW BSP_BBIT32(27)
948#define XLB_ST_TTM BSP_BBIT32(28)
949#define XLB_ST_BA BSP_BBIT32(29)
950#define XLB_ST_DT BSP_BBIT32(30)
951#define XLB_ST_AT BSP_BBIT32(31)
952 /* read only = 0x0001 */
953 volatile uint32_t xlb_status; /* MBAR_XLB_ARB + 0x0048 */
954 volatile uint32_t int_enable; /* MBAR_XLB_ARB + 0x004c */
955 volatile uint32_t add_capture; /* MBAR_XLB_ARB + 0x0050 read only */
956 volatile uint32_t bus_sig_capture; /* MBAR_XLB_ARB + 0x0054 read only */
957 volatile uint32_t add_time_out; /* MBAR_XLB_ARB + 0x0058 */
958 volatile uint32_t data_time_out; /* MBAR_XLB_ARB + 0x005c */
959 volatile uint32_t bus_time_out; /* MBAR_XLB_ARB + 0x0060 */
960 volatile uint32_t priority_enable; /* MBAR_XLB_ARB + 0x0064 */
961 volatile uint32_t priority; /* MBAR_XLB_ARB + 0x0068 */
962 volatile uint32_t arb_base_addr2; /* MBAR_XLB_ARB + 0x006c */
963 volatile uint32_t snoop_window; /* MBAR_XLB_ARB + 0x0070 */
964
965 volatile uint32_t reserved16; /* MBAR_XLB_ARB + 0x0074 reserved */
966 volatile uint32_t reserved17; /* MBAR_XLB_ARB + 0x0078 reserved */
967 volatile uint32_t reserved18; /* MBAR_XLB_ARB + 0x007c reserved */
968
969 volatile uint32_t control; /* MBAR_XLB_ARB + 0x0080 */
970 volatile uint32_t init_total_count; /* MBAR_XLB_ARB + 0x0084 */
971 volatile uint32_t int_total_count; /* MBAR_XLB_ARB + 0x0088 */
972
973 volatile uint32_t reserved19; /* MBAR_XLB_ARB + 0x008c reserved */
974
975 volatile uint32_t lower_address; /* MBAR_XLB_ARB + 0x0090 */
976 volatile uint32_t higher_address; /* MBAR_XLB_ARB + 0x0094 */
977 volatile uint32_t int_window_count; /* MBAR_XLB_ARB + 0x0098 */
978 volatile uint32_t window_ter_count; /* MBAR_XLB_ARB + 0x009c */
979 volatile uint8_t res_0x1fa0[0x60];
980
981
982#endif
983 /*
984 * programmable serial controller 1 (MBAR + 0x2000)
985 */
986
987 struct mpc5200_psc {
988 volatile uint8_t mr; /* + 0x00 */
989 volatile uint8_t res1[3];
990 volatile uint16_t sr_csr; /* + 0x04 */
991 volatile uint16_t res2[1];
992 volatile uint16_t cr; /* + 0x08 */
993 volatile uint16_t res3[1];
994 volatile uint32_t rb_tb; /* + 0x0c */
995 volatile uint16_t ipcr_acr; /* + 0x10 */
996 volatile uint16_t res4[1];
997 volatile uint16_t isr_imr; /* + 0x14 */
998#define ISR_TX_RDY (1 << 8)
999#define ISR_RX_RDY_FULL (1 << 9)
1000#define ISR_RB (1 << 15)
1001#define ISR_FE (1 << 14)
1002#define ISR_PE (1 << 13)
1003#define ISR_OE (1 << 12)
1004#define ISR_ERROR (ISR_FE | ISR_PE | ISR_OE)
1005
1006#define IMR_TX_RDY (1 << 8)
1007#define IMR_RX_RDY_FULL (1 << 9)
1008 volatile uint16_t res5[1];
1009 volatile uint8_t ctur; /* + 0x18 */
1010 volatile uint8_t res6[3];
1011 volatile uint8_t ctlr; /* + 0x1C */
1012 volatile uint8_t res7[0x13];
1013 volatile uint8_t ivr; /* + 0x30 */
1014 volatile uint8_t res8[3];
1015 volatile uint8_t ip; /* + 0x34 */
1016 volatile uint8_t res9[3];
1017 volatile uint8_t op1; /* + 0x38 */
1018 volatile uint8_t res10[3];
1019 volatile uint8_t op0; /* + 0x3C */
1020 volatile uint8_t res11[3];
1021 volatile uint8_t sicr; /* + 0x40 */
1022 volatile uint8_t res12[0x17];
1023 volatile uint16_t rfnum; /* + 0x58 */
1024 volatile uint16_t res13[1];
1025 volatile uint16_t tfnum; /* + 0x5C */
1026 volatile uint16_t res14[1];
1027 volatile uint16_t rfdata; /* + 0x60 */
1028 volatile uint16_t res15[1];
1029 volatile uint16_t rfstat; /* + 0x64 */
1030 volatile uint16_t res16[1];
1031 volatile uint8_t rfcntl; /* + 0x68 */
1032 volatile uint8_t res17[5];
1033 volatile uint16_t rfalarm; /* + 0x6E */
1034 volatile uint8_t res18[2];
1035 volatile uint16_t rfrptr; /* + 0x72 */
1036 volatile uint16_t res19[1];
1037 volatile uint16_t rfwptr; /* + 0x76 */
1038 volatile uint16_t res20[1];
1039 volatile uint16_t rflrfptr; /* + 0x7A */
1040 volatile uint16_t rflwfptr; /* + 0x7C */
1041 volatile uint16_t res21[1];
1042 volatile uint16_t tfdata; /* + 0x80 */
1043 volatile uint16_t res22[1];
1044 volatile uint16_t tfstat; /* + 0x84 */
1045 volatile uint16_t res23[1];
1046 volatile uint8_t tfcntl; /* + 0x88 */
1047 volatile uint8_t res24[5];
1048 volatile uint16_t tfalarm; /* + 0x8E */
1049 volatile uint8_t res25[2];
1050 volatile uint16_t tfrptr; /* + 0x92 */
1051 volatile uint16_t res26[1];
1052 volatile uint16_t tfwptr; /* + 0x96 */
1053 volatile uint16_t res27[1];
1054 volatile uint16_t tflrfptr; /* + 0x96 */
1055 volatile uint16_t tflwfptr; /* + 0x9C */
1056 volatile uint16_t res28[1]; /* end at offset 0x9F */
1057 volatile uint8_t res29[0x160];
1058 } psc[MPC5200_PSC_REG_SETS];
1059 /* XXX: there are only 6 PSCs, but PSC6 has an extra register gap
1060 * from PSC5, therefore we instantiate seven(!) PSC register sets
1061 */
1062
1063#define TX_FIFO_SIZE 256
1064#define RX_FIFO_SIZE 512
1065
1066
1067 volatile uint8_t irda[0x200];
1068
1069 /*
1070 * ethernet registers (MBAR + 0x3000)
1071 */
1072
1073 /* Control and status Registers (offset 000-1FF) */
1074
1075 volatile uint32_t fec_id; /* + 0x000 */
1076 volatile uint32_t ievent; /* + 0x004 */
1077 volatile uint32_t imask; /* + 0x008 */
1078
1079 volatile uint32_t res9[1]; /* + 0x00C */
1080 volatile uint32_t r_des_active; /* + 0x010 */
1081 volatile uint32_t x_des_active; /* + 0x014 */
1082 volatile uint32_t r_des_active_cl; /* + 0x018 */
1083 volatile uint32_t x_des_active_cl; /* + 0x01C */
1084 volatile uint32_t ivent_set; /* + 0x020 */
1085 volatile uint32_t ecntrl; /* + 0x024 */
1086
1087 volatile uint32_t res10[6]; /* + 0x028-03C */
1088 volatile uint32_t mii_data; /* + 0x040 */
1089 volatile uint32_t mii_speed; /* + 0x044 */
1090 volatile uint32_t mii_status; /* + 0x048 */
1091
1092 volatile uint32_t res11[5]; /* + 0x04C-05C */
1093 volatile uint32_t mib_data; /* + 0x060 */
1094 volatile uint32_t mib_control; /* + 0x064 */
1095
1096 volatile uint32_t res12[6]; /* + 0x068-7C */
1097 volatile uint32_t r_activate; /* + 0x080 */
1098 volatile uint32_t r_cntrl; /* + 0x084 */
1099 volatile uint32_t r_hash; /* + 0x088 */
1100 volatile uint32_t r_data; /* + 0x08C */
1101 volatile uint32_t ar_done; /* + 0x090 */
1102 volatile uint32_t r_test; /* + 0x094 */
1103 volatile uint32_t r_mib; /* + 0x098 */
1104 volatile uint32_t r_da_low; /* + 0x09C */
1105 volatile uint32_t r_da_high; /* + 0x0A0 */
1106
1107 volatile uint32_t res13[7]; /* + 0x0A4-0BC */
1108 volatile uint32_t x_activate; /* + 0x0C0 */
1109 volatile uint32_t x_cntrl; /* + 0x0C4 */
1110 volatile uint32_t backoff; /* + 0x0C8 */
1111 volatile uint32_t x_data; /* + 0x0CC */
1112 volatile uint32_t x_status; /* + 0x0D0 */
1113 volatile uint32_t x_mib; /* + 0x0D4 */
1114 volatile uint32_t x_test; /* + 0x0D8 */
1115 volatile uint32_t fdxfc_da1; /* + 0x0DC */
1116 volatile uint32_t fdxfc_da2; /* + 0x0E0 */
1117 volatile uint32_t paddr1; /* + 0x0E4 */
1118 volatile uint32_t paddr2; /* + 0x0E8 */
1119 volatile uint32_t op_pause; /* + 0x0EC */
1120
1121 volatile uint32_t res14[4]; /* + 0x0F0-0FC */
1122 volatile uint32_t instr_reg; /* + 0x100 */
1123 volatile uint32_t context_reg; /* + 0x104 */
1124 volatile uint32_t test_cntrl; /* + 0x108 */
1125 volatile uint32_t acc_reg; /* + 0x10C */
1126 volatile uint32_t ones; /* + 0x110 */
1127 volatile uint32_t zeros; /* + 0x114 */
1128 volatile uint32_t iaddr1; /* + 0x118 */
1129 volatile uint32_t iaddr2; /* + 0x11C */
1130 volatile uint32_t gaddr1; /* + 0x120 */
1131 volatile uint32_t gaddr2; /* + 0x124 */
1132 volatile uint32_t random; /* + 0x128 */
1133 volatile uint32_t rand1; /* + 0x12C */
1134 volatile uint32_t tmp; /* + 0x130 */
1135
1136 volatile uint32_t res15[3]; /* + 0x134-13C */
1137 volatile uint32_t fifo_id; /* + 0x140 */
1138 volatile uint32_t x_wmrk; /* + 0x144 */
1139 volatile uint32_t fcntrl; /* + 0x148 */
1140 volatile uint32_t r_bound; /* + 0x14C */
1141 volatile uint32_t r_fstart; /* + 0x150 */
1142 volatile uint32_t r_count; /* + 0x154 */
1143 volatile uint32_t r_lag; /* + 0x158 */
1144 volatile uint32_t r_read; /* + 0x15C */
1145 volatile uint32_t r_write; /* + 0x160 */
1146 volatile uint32_t x_count; /* + 0x164 */
1147 volatile uint32_t x_lag; /* + 0x168 */
1148 volatile uint32_t x_retry; /* + 0x16C */
1149 volatile uint32_t x_write; /* + 0x170 */
1150 volatile uint32_t x_read; /* + 0x174 */
1151
1152 volatile uint32_t res16[2]; /* + 0x178-17C */
1153 volatile uint32_t fm_cntrl; /* + 0x180 */
1154 volatile uint32_t rfifo_data; /* + 0x184 */
1155 volatile uint32_t rfifo_status; /* + 0x188 */
1156 volatile uint32_t rfifo_cntrl; /* + 0x18C */
1157 volatile uint32_t rfifo_lrf_ptr; /* + 0x190 */
1158 volatile uint32_t rfifo_lwf_ptr; /* + 0x194 */
1159 volatile uint32_t rfifo_alarm; /* + 0x198 */
1160 volatile uint32_t rfifo_rdptr; /* + 0x19C */
1161 volatile uint32_t rfifo_wrptr; /* + 0x1A0 */
1162 volatile uint32_t tfifo_data; /* + 0x1A4 */
1163 volatile uint32_t tfifo_status; /* + 0x1A8 */
1164 volatile uint32_t tfifo_cntrl; /* + 0x1AC */
1165 volatile uint32_t tfifo_lrf_ptr; /* + 0x1B0 */
1166 volatile uint32_t tfifo_lwf_ptr; /* + 0x1B4 */
1167 volatile uint32_t tfifo_alarm; /* + 0x1B8 */
1168 volatile uint32_t tfifo_rdptr; /* + 0x1BC */
1169 volatile uint32_t tfifo_wrptr; /* + 0x1C0 */
1170
1171 volatile uint32_t reset_cntrl; /* + 0x1C4 */
1172 volatile uint32_t xmit_fsm; /* + 0x1C8 */
1173
1174 volatile uint32_t res17[3]; /* + 0x1CC-1D4 */
1175 volatile uint32_t rdes_data0; /* + 0x1D8 */
1176 volatile uint32_t rdes_data1; /* + 0x1DC */
1177 volatile uint32_t r_length; /* + 0x1E0 */
1178 volatile uint32_t x_length; /* + 0x1E4 */
1179 volatile uint32_t x_addr; /* + 0x1E8 */
1180 volatile uint32_t cdes_data; /* + 0x1EC */
1181 volatile uint32_t status; /* + 0x1F0 */
1182 volatile uint32_t dma_control; /* + 0x1F4 */
1183 volatile uint32_t des_cmnd; /* + 0x1F8 */
1184 volatile uint32_t data; /* + 0x1FC */
1185
1186 volatile uint8_t RES[0x600];
1187
1188
1189#if 0
1190 /* MIB COUNTERS (Offset 200-2FF) */
1191
1192 volatile uint32_t rmon_t_drop; /* + 0x200 */
1193 volatile uint32_t rmon_t_packets; /* + 0x204 */
1194 volatile uint32_t rmon_t_bc_pkt; /* + 0x208 */
1195 volatile uint32_t rmon_t_mc_pkt; /* + 0x20C */
1196 volatile uint32_t rmon_t_crc_align; /* + 0x210 */
1197 volatile uint32_t rmon_t_undersize; /* + 0x214 */
1198 volatile uint32_t rmon_t_oversize; /* + 0x218 */
1199 volatile uint32_t rmon_t_frag; /* + 0x21C */
1200 volatile uint32_t rmon_t_jab; /* + 0x220 */
1201 volatile uint32_t rmon_t_col; /* + 0x224 */
1202 volatile uint32_t rmon_t_p64; /* + 0x228 */
1203 volatile uint32_t rmon_t_p65to127; /* + 0x22C */
1204 volatile uint32_t rmon_t_p128to255; /* + 0x230 */
1205 volatile uint32_t rmon_t_p256to511; /* + 0x234 */
1206 volatile uint32_t rmon_t_p512to1023; /* + 0x238 */
1207 volatile uint32_t rmon_t_p1024to2047; /* + 0x23C */
1208 volatile uint32_t rmon_t_p_gte2048; /* + 0x240 */
1209 volatile uint32_t rmon_t_octets; /* + 0x244 */
1210 volatile uint32_t ieee_t_drop; /* + 0x248 */
1211 volatile uint32_t ieee_t_frame_ok; /* + 0x24C */
1212 volatile uint32_t ieee_t_1col; /* + 0x250 */
1213 volatile uint32_t ieee_t_mcol; /* + 0x254 */
1214 volatile uint32_t ieee_t_def; /* + 0x258 */
1215 volatile uint32_t ieee_t_lcol; /* + 0x25C */
1216 volatile uint32_t ieee_t_excol; /* + 0x260 */
1217 volatile uint32_t ieee_t_macerr; /* + 0x264 */
1218 volatile uint32_t ieee_t_cserr; /* + 0x268 */
1219 volatile uint32_t ieee_t_sqe; /* + 0x26C */
1220 volatile uint32_t t_fdxfc; /* + 0x270 */
1221 volatile uint32_t ieee_t_octets_ok; /* + 0x274 */
1222
1223 volatile uint32_t res18[2]; /* + 0x278-27C */
1224 volatile uint32_t rmon_r_drop; /* + 0x280 */
1225 volatile uint32_t rmon_r_packets; /* + 0x284 */
1226 volatile uint32_t rmon_r_bc_pkt; /* + 0x288 */
1227 volatile uint32_t rmon_r_mc_pkt; /* + 0x28C */
1228 volatile uint32_t rmon_r_crc_align; /* + 0x290 */
1229 volatile uint32_t rmon_r_undersize; /* + 0x294 */
1230 volatile uint32_t rmon_r_oversize; /* + 0x298 */
1231 volatile uint32_t rmon_r_frag; /* + 0x29C */
1232 volatile uint32_t rmon_r_jab; /* + 0x2A0 */
1233
1234 volatile uint32_t rmon_r_resvd_0; /* + 0x2A4 */
1235
1236 volatile uint32_t rmon_r_p64; /* + 0x2A8 */
1237 volatile uint32_t rmon_r_p65to127; /* + 0x2AC */
1238 volatile uint32_t rmon_r_p128to255; /* + 0x2B0 */
1239 volatile uint32_t rmon_r_p256to511; /* + 0x2B4 */
1240 volatile uint32_t rmon_r_p512to1023; /* + 0x2B8 */
1241 volatile uint32_t rmon_r_p1024to2047; /* + 0x2BC */
1242 volatile uint32_t rmon_r_p_gte2048; /* + 0x2C0 */
1243 volatile uint32_t rmon_r_octets; /* + 0x2C4 */
1244 volatile uint32_t ieee_r_drop; /* + 0x2C8 */
1245 volatile uint32_t ieee_r_frame_ok; /* + 0x2CC */
1246 volatile uint32_t ieee_r_crc; /* + 0x2D0 */
1247 volatile uint32_t ieee_r_align; /* + 0x2D4 */
1248 volatile uint32_t r_macerr; /* + 0x2D8 */
1249 volatile uint32_t r_fdxfc; /* + 0x2DC */
1250 volatile uint32_t ieee_r_octets_ok; /* + 0x2E0 */
1251
1252 volatile uint32_t res19[6]; /* + 0x2E4-2FC */
1253
1254 volatile uint32_t res20[64]; /* + 0x300-3FF */
1255
1256 volatile uint32_t res21[256]; /* + 0x400-800 */
1257#endif
1258
1259 /*
1260 * SmartComm DMA PCI registers (MBAR + 0x3800)
1261 */
1262 volatile uint8_t pci[0x200];
1263
1264 /*
1265 * advanced technology attachment registers (MBAR + 0x3A00)
1266 */
1267
1268 /* ATA host registers (offset 0x00-0x28) */
1269 volatile uint32_t ata_hcfg; /* + 0x00 */
1270 volatile uint32_t ata_hsr; /* + 0x04 */
1271 volatile uint32_t ata_pio1; /* + 0x08 */
1272 volatile uint32_t ata_pio2; /* + 0x0C */
1273 volatile uint32_t ata_dma1; /* + 0x10 */
1274 volatile uint32_t ata_dma2; /* + 0x14 */
1275 volatile uint32_t ata_udma1; /* + 0x18 */
1276 volatile uint32_t ata_udma2; /* + 0x1C */
1277 volatile uint32_t ata_udma3; /* + 0x20 */
1278 volatile uint32_t ata_udma4; /* + 0x24 */
1279 volatile uint32_t ata_udma5; /* + 0x28 */
1280 volatile uint32_t ata_res1[4]; /* + 0x2C-0x3C */
1281
1282 /* ATA FIFO registers (offset 0x3C-0x50) */
1283 volatile uint32_t ata_rtfdwr; /* + 0x3C */
1284
1285#define ATA_RTFSR_ERR BSP_BBIT32(9)
1286#define ATA_RTFSR_UF BSP_BBIT32(10)
1287#define ATA_RTFSR_OF BSP_BBIT32(11)
1288#define ATA_RTFSR_FULL BSP_BBIT32(12)
1289#define ATA_RTFSR_HI BSP_BBIT32(13)
1290#define ATA_RTFSR_LO BSP_BBIT32(14)
1291#define ATA_RTFSR_EMPTY BSP_BBIT32(15)
1292
1293 volatile uint32_t ata_rtfsr; /* + 0x40 */
1294
1295#define ATA_RTFCR_WFR BSP_BBIT32(2)
1296#define ATA_RTFCR_GR(val) BSP_BFLD32(val, 5, 7)
1297
1298 volatile uint32_t ata_rtfcr; /* + 0x44 */
1299 volatile uint32_t ata_rtfar; /* + 0x48 */
1300 volatile uint32_t ata_rtfrpr; /* + 0x4C */
1301 volatile uint32_t ata_rtfwpr; /* + 0x50 */
1302 volatile uint32_t ata_res2[2]; /* + 0x54-0x5C */
1303
1304 /* ATA drive registers (offset 0x5C-0x80) */
1305 volatile uint32_t ata_dctr_dasr; /* + 0x5C */
1306 volatile uint32_t ata_ddr; /* + 0x60 */
1307 volatile uint32_t ata_dfr_der; /* + 0x64 */
1308 volatile uint32_t ata_dscr; /* + 0x68 */
1309 volatile uint32_t ata_dsnr; /* + 0x6C */
1310 volatile uint32_t ata_dclr; /* + 0x70 */
1311 volatile uint32_t ata_dchr; /* + 0x74 */
1312 volatile uint32_t ata_ddhr; /* + 0x78 */
1313 volatile uint32_t ata_dcr_dsr; /* + 0x7C */
1314 volatile uint32_t ata_res3[0xA0]; /* + 0x80-0x200 */
1315
1316 /*
1317 * inter-integrated circuit registers (MBAR + 0x3D00)
1318 */
1319 struct mpc5200_i2c_regs_s {
1320 volatile uint8_t madr; /* i2c address reg. + 0x00 */
1321 volatile uint8_t res_1[3];
1322 volatile uint8_t mfdr; /* i2c freq. divider reg. + 0x04 */
1323 volatile uint8_t res_5[3];
1324 volatile uint8_t mcr; /* i2c control reg. + 0x08 */
1325 volatile uint8_t res_9[3];
1326
1327#define MPC5200_I2C_MCR_MEN (1 << (7-0))
1328#define MPC5200_I2C_MCR_MIEN (1 << (7-1))
1329#define MPC5200_I2C_MCR_MSTA (1 << (7-2))
1330#define MPC5200_I2C_MCR_MTX (1 << (7-3))
1331#define MPC5200_I2C_MCR_TXAK (1 << (7-4))
1332#define MPC5200_I2C_MCR_RSTA (1 << (7-5))
1333
1334 volatile uint8_t msr; /* i2c status reg. + 0x0C */
1335 volatile uint8_t res_d[3];
1336#define MPC5200_I2C_MSR_CF (1 << (7-0))
1337#define MPC5200_I2C_MSR_MAAS (1 << (7-1))
1338#define MPC5200_I2C_MSR_BB (1 << (7-2))
1339#define MPC5200_I2C_MSR_MAL (1 << (7-3))
1340#define MPC5200_I2C_MSR_SRW (1 << (7-5))
1341#define MPC5200_I2C_MSR_MIF (1 << (7-6))
1342#define MPC5200_I2C_MSR_RXAK (1 << (7-7))
1343 volatile uint8_t mdr; /* i2c data I/O reg. + 0x10 */
1344 volatile uint8_t res_11[3];
1345 volatile uint8_t res_14[12]; /* reserved + 0x14 */
1346 volatile uint8_t icr; /* i2c irq ctrl reg. + 0x20 */
1347#define MPC5200_I2C_ICR_BNBE2 (1 << (7-0))
1348#define MPC5200_I2C_ICR_TE2 (1 << (7-1))
1349#define MPC5200_I2C_ICR_RE2 (1 << (7-2))
1350#define MPC5200_I2C_ICR_IE2 (1 << (7-3))
1351#define MPC5200_I2C_ICR_MASK2 (MPC5200_I2C_ICR_BNBE2|MPC5200_I2C_ICR_TE2\
1352 |MPC5200_I2C_ICR_RE2|MPC5200_I2C_ICR_IE2)
1353#define MPC5200_I2C_ICR_BNBE1 (1 << (7-4))
1354#define MPC5200_I2C_ICR_TE1 (1 << (7-5))
1355#define MPC5200_I2C_ICR_RE1 (1 << (7-6))
1356#define MPC5200_I2C_ICR_IE1 (1 << (7-7))
1357#define MPC5200_I2C_ICR_MASK1 (MPC5200_I2C_ICR_BNBE1|MPC5200_I2C_ICR_TE1\
1358 |MPC5200_I2C_ICR_RE1|MPC5200_I2C_ICR_IE1)
1359 volatile uint8_t res_21[3];
1360 volatile uint32_t res_24[7]; /* reserved + 0x24 */
1361 } i2c_regs[2];
1362 volatile uint8_t res_3d80[0x280];
1363
1364 /*
1365 * on-chip static RAM memory locations (MBAR + 0x4000)
1366 */
1367 volatile uint8_t sram_res0x4000[0x4000];
1368 volatile uint8_t sram[0x4000];
1369
1370} mpc5200_t;
1371
1372extern volatile mpc5200_t mpc5200;
1373
1374#ifdef __cplusplus
1375}
1376#endif
1377
1378#endif /*ASM*/
1379
1380#endif /* __MPC5200_h__ */
mscan
struct mpc5200_mscan mscan
MSCAN registers.
Definition: mscan-base.h:255
utility.h
This header file provides utility macros for BSPs.
rtems.h
This header file defines the RTEMS Classic API.
config_s
Definition: deflate.c:114
control
Definition: intercom.c:87
i2c_regs
Definition: i2c.h:49
mpc5200_::mpc5200_gpt
Definition: mpc5200.h:467
mpc5200_::mpc5200_i2c_regs_s
Definition: mpc5200.h:1319
mpc5200_::mpc5200_mscan
Definition: mpc5200.h:519
mpc5200_::mpc5200_psc
Definition: mpc5200.h:987
mpc5200_::mpc5200_slt
Definition: mpc5200.h:501
mpc5200_
Definition: mpc5200.h:398
mpc5200_csc
Definition: mpc5200.h:275
mpc5200_mm
Definition: mpc5200.h:354
mpc5200_sdma
Definition: mpc5200.h:252
Generated by doxygen 1.9.6