RTEMS 6.1-rc6
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l2cache-regs.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2021 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36/*
37 * This file is part of the RTEMS quality process and was automatically
38 * generated. If you find something that needs to be fixed or
39 * worded better please post a report or patch to an RTEMS mailing list
40 * or raise a bug report:
41 *
42 * https://www.rtems.org/bugs.html
43 *
44 * For information on updating and regenerating please refer to the How-To
45 * section in the Software Requirements Engineering chapter of the
46 * RTEMS Software Engineering manual. The manual is provided as a part of
47 * a release. For development sources please refer to the online
48 * documentation at:
49 *
50 * https://docs.rtems.org
51 */
52
53/* Generated from spec:/dev/grlib/if/l2cache-header */
54
55#ifndef _GRLIB_L2CACHE_REGS_H
56#define _GRLIB_L2CACHE_REGS_H
57
58#include <stdint.h>
59
60#ifdef __cplusplus
61extern "C" {
62#endif
63
64/* Generated from spec:/dev/grlib/if/l2cache */
65
84#define L2CACHE_L2CC_EN 0x80000000U
85
86#define L2CACHE_L2CC_EDAC 0x40000000U
87
88#define L2CACHE_L2CC_REPL_SHIFT 28
89#define L2CACHE_L2CC_REPL_MASK 0x30000000U
90#define L2CACHE_L2CC_REPL_GET( _reg ) \
91 ( ( ( _reg ) & L2CACHE_L2CC_REPL_MASK ) >> \
92 L2CACHE_L2CC_REPL_SHIFT )
93#define L2CACHE_L2CC_REPL_SET( _reg, _val ) \
94 ( ( ( _reg ) & ~L2CACHE_L2CC_REPL_MASK ) | \
95 ( ( ( _val ) << L2CACHE_L2CC_REPL_SHIFT ) & \
96 L2CACHE_L2CC_REPL_MASK ) )
97#define L2CACHE_L2CC_REPL( _val ) \
98 ( ( ( _val ) << L2CACHE_L2CC_REPL_SHIFT ) & \
99 L2CACHE_L2CC_REPL_MASK )
100
101#define L2CACHE_L2CC_BBS_SHIFT 16
102#define L2CACHE_L2CC_BBS_MASK 0x70000U
103#define L2CACHE_L2CC_BBS_GET( _reg ) \
104 ( ( ( _reg ) & L2CACHE_L2CC_BBS_MASK ) >> \
105 L2CACHE_L2CC_BBS_SHIFT )
106#define L2CACHE_L2CC_BBS_SET( _reg, _val ) \
107 ( ( ( _reg ) & ~L2CACHE_L2CC_BBS_MASK ) | \
108 ( ( ( _val ) << L2CACHE_L2CC_BBS_SHIFT ) & \
109 L2CACHE_L2CC_BBS_MASK ) )
110#define L2CACHE_L2CC_BBS( _val ) \
111 ( ( ( _val ) << L2CACHE_L2CC_BBS_SHIFT ) & \
112 L2CACHE_L2CC_BBS_MASK )
113
114#define L2CACHE_L2CC_INDEX_WAY_SHIFT 12
115#define L2CACHE_L2CC_INDEX_WAY_MASK 0xf000U
116#define L2CACHE_L2CC_INDEX_WAY_GET( _reg ) \
117 ( ( ( _reg ) & L2CACHE_L2CC_INDEX_WAY_MASK ) >> \
118 L2CACHE_L2CC_INDEX_WAY_SHIFT )
119#define L2CACHE_L2CC_INDEX_WAY_SET( _reg, _val ) \
120 ( ( ( _reg ) & ~L2CACHE_L2CC_INDEX_WAY_MASK ) | \
121 ( ( ( _val ) << L2CACHE_L2CC_INDEX_WAY_SHIFT ) & \
122 L2CACHE_L2CC_INDEX_WAY_MASK ) )
123#define L2CACHE_L2CC_INDEX_WAY( _val ) \
124 ( ( ( _val ) << L2CACHE_L2CC_INDEX_WAY_SHIFT ) & \
125 L2CACHE_L2CC_INDEX_WAY_MASK )
126
127#define L2CACHE_L2CC_LOCK_SHIFT 8
128#define L2CACHE_L2CC_LOCK_MASK 0xf00U
129#define L2CACHE_L2CC_LOCK_GET( _reg ) \
130 ( ( ( _reg ) & L2CACHE_L2CC_LOCK_MASK ) >> \
131 L2CACHE_L2CC_LOCK_SHIFT )
132#define L2CACHE_L2CC_LOCK_SET( _reg, _val ) \
133 ( ( ( _reg ) & ~L2CACHE_L2CC_LOCK_MASK ) | \
134 ( ( ( _val ) << L2CACHE_L2CC_LOCK_SHIFT ) & \
135 L2CACHE_L2CC_LOCK_MASK ) )
136#define L2CACHE_L2CC_LOCK( _val ) \
137 ( ( ( _val ) << L2CACHE_L2CC_LOCK_SHIFT ) & \
138 L2CACHE_L2CC_LOCK_MASK )
139
140#define L2CACHE_L2CC_HPRHB 0x20U
141
142#define L2CACHE_L2CC_HPB 0x10U
143
144#define L2CACHE_L2CC_UC 0x8U
145
146#define L2CACHE_L2CC_HC 0x4U
147
148#define L2CACHE_L2CC_WP 0x2U
149
150#define L2CACHE_L2CC_HP 0x1U
151
162#define L2CACHE_L2CS_LS 0x1000000U
163
164#define L2CACHE_L2CS_AT 0x800000U
165
166#define L2CACHE_L2CS_MP 0x400000U
167
168#define L2CACHE_L2CS_MTRR_SHIFT 16
169#define L2CACHE_L2CS_MTRR_MASK 0x3f0000U
170#define L2CACHE_L2CS_MTRR_GET( _reg ) \
171 ( ( ( _reg ) & L2CACHE_L2CS_MTRR_MASK ) >> \
172 L2CACHE_L2CS_MTRR_SHIFT )
173#define L2CACHE_L2CS_MTRR_SET( _reg, _val ) \
174 ( ( ( _reg ) & ~L2CACHE_L2CS_MTRR_MASK ) | \
175 ( ( ( _val ) << L2CACHE_L2CS_MTRR_SHIFT ) & \
176 L2CACHE_L2CS_MTRR_MASK ) )
177#define L2CACHE_L2CS_MTRR( _val ) \
178 ( ( ( _val ) << L2CACHE_L2CS_MTRR_SHIFT ) & \
179 L2CACHE_L2CS_MTRR_MASK )
180
181#define L2CACHE_L2CS_BBUS_W_SHIFT 13
182#define L2CACHE_L2CS_BBUS_W_MASK 0xe000U
183#define L2CACHE_L2CS_BBUS_W_GET( _reg ) \
184 ( ( ( _reg ) & L2CACHE_L2CS_BBUS_W_MASK ) >> \
185 L2CACHE_L2CS_BBUS_W_SHIFT )
186#define L2CACHE_L2CS_BBUS_W_SET( _reg, _val ) \
187 ( ( ( _reg ) & ~L2CACHE_L2CS_BBUS_W_MASK ) | \
188 ( ( ( _val ) << L2CACHE_L2CS_BBUS_W_SHIFT ) & \
189 L2CACHE_L2CS_BBUS_W_MASK ) )
190#define L2CACHE_L2CS_BBUS_W( _val ) \
191 ( ( ( _val ) << L2CACHE_L2CS_BBUS_W_SHIFT ) & \
192 L2CACHE_L2CS_BBUS_W_MASK )
193
194#define L2CACHE_L2CS_WAY_SIZE_SHIFT 2
195#define L2CACHE_L2CS_WAY_SIZE_MASK 0x1ffcU
196#define L2CACHE_L2CS_WAY_SIZE_GET( _reg ) \
197 ( ( ( _reg ) & L2CACHE_L2CS_WAY_SIZE_MASK ) >> \
198 L2CACHE_L2CS_WAY_SIZE_SHIFT )
199#define L2CACHE_L2CS_WAY_SIZE_SET( _reg, _val ) \
200 ( ( ( _reg ) & ~L2CACHE_L2CS_WAY_SIZE_MASK ) | \
201 ( ( ( _val ) << L2CACHE_L2CS_WAY_SIZE_SHIFT ) & \
202 L2CACHE_L2CS_WAY_SIZE_MASK ) )
203#define L2CACHE_L2CS_WAY_SIZE( _val ) \
204 ( ( ( _val ) << L2CACHE_L2CS_WAY_SIZE_SHIFT ) & \
205 L2CACHE_L2CS_WAY_SIZE_MASK )
206
207#define L2CACHE_L2CS_WAY_SHIFT 0
208#define L2CACHE_L2CS_WAY_MASK 0x3U
209#define L2CACHE_L2CS_WAY_GET( _reg ) \
210 ( ( ( _reg ) & L2CACHE_L2CS_WAY_MASK ) >> \
211 L2CACHE_L2CS_WAY_SHIFT )
212#define L2CACHE_L2CS_WAY_SET( _reg, _val ) \
213 ( ( ( _reg ) & ~L2CACHE_L2CS_WAY_MASK ) | \
214 ( ( ( _val ) << L2CACHE_L2CS_WAY_SHIFT ) & \
215 L2CACHE_L2CS_WAY_MASK ) )
216#define L2CACHE_L2CS_WAY( _val ) \
217 ( ( ( _val ) << L2CACHE_L2CS_WAY_SHIFT ) & \
218 L2CACHE_L2CS_WAY_MASK )
219
231#define L2CACHE_L2CFMA_ADDR_SHIFT 5
232#define L2CACHE_L2CFMA_ADDR_MASK 0xffffffe0U
233#define L2CACHE_L2CFMA_ADDR_GET( _reg ) \
234 ( ( ( _reg ) & L2CACHE_L2CFMA_ADDR_MASK ) >> \
235 L2CACHE_L2CFMA_ADDR_SHIFT )
236#define L2CACHE_L2CFMA_ADDR_SET( _reg, _val ) \
237 ( ( ( _reg ) & ~L2CACHE_L2CFMA_ADDR_MASK ) | \
238 ( ( ( _val ) << L2CACHE_L2CFMA_ADDR_SHIFT ) & \
239 L2CACHE_L2CFMA_ADDR_MASK ) )
240#define L2CACHE_L2CFMA_ADDR( _val ) \
241 ( ( ( _val ) << L2CACHE_L2CFMA_ADDR_SHIFT ) & \
242 L2CACHE_L2CFMA_ADDR_MASK )
243
244#define L2CACHE_L2CFMA_DI 0x8U
245
246#define L2CACHE_L2CFMA_FMODE_SHIFT 0
247#define L2CACHE_L2CFMA_FMODE_MASK 0x7U
248#define L2CACHE_L2CFMA_FMODE_GET( _reg ) \
249 ( ( ( _reg ) & L2CACHE_L2CFMA_FMODE_MASK ) >> \
250 L2CACHE_L2CFMA_FMODE_SHIFT )
251#define L2CACHE_L2CFMA_FMODE_SET( _reg, _val ) \
252 ( ( ( _reg ) & ~L2CACHE_L2CFMA_FMODE_MASK ) | \
253 ( ( ( _val ) << L2CACHE_L2CFMA_FMODE_SHIFT ) & \
254 L2CACHE_L2CFMA_FMODE_MASK ) )
255#define L2CACHE_L2CFMA_FMODE( _val ) \
256 ( ( ( _val ) << L2CACHE_L2CFMA_FMODE_SHIFT ) & \
257 L2CACHE_L2CFMA_FMODE_MASK )
258
270#define L2CACHE_L2CFSI_INDEX_SHIFT 16
271#define L2CACHE_L2CFSI_INDEX_MASK 0xffff0000U
272#define L2CACHE_L2CFSI_INDEX_GET( _reg ) \
273 ( ( ( _reg ) & L2CACHE_L2CFSI_INDEX_MASK ) >> \
274 L2CACHE_L2CFSI_INDEX_SHIFT )
275#define L2CACHE_L2CFSI_INDEX_SET( _reg, _val ) \
276 ( ( ( _reg ) & ~L2CACHE_L2CFSI_INDEX_MASK ) | \
277 ( ( ( _val ) << L2CACHE_L2CFSI_INDEX_SHIFT ) & \
278 L2CACHE_L2CFSI_INDEX_MASK ) )
279#define L2CACHE_L2CFSI_INDEX( _val ) \
280 ( ( ( _val ) << L2CACHE_L2CFSI_INDEX_SHIFT ) & \
281 L2CACHE_L2CFSI_INDEX_MASK )
282
283#define L2CACHE_L2CFSI_TAG_SHIFT 10
284#define L2CACHE_L2CFSI_TAG_MASK 0xfffffc00U
285#define L2CACHE_L2CFSI_TAG_GET( _reg ) \
286 ( ( ( _reg ) & L2CACHE_L2CFSI_TAG_MASK ) >> \
287 L2CACHE_L2CFSI_TAG_SHIFT )
288#define L2CACHE_L2CFSI_TAG_SET( _reg, _val ) \
289 ( ( ( _reg ) & ~L2CACHE_L2CFSI_TAG_MASK ) | \
290 ( ( ( _val ) << L2CACHE_L2CFSI_TAG_SHIFT ) & \
291 L2CACHE_L2CFSI_TAG_MASK ) )
292#define L2CACHE_L2CFSI_TAG( _val ) \
293 ( ( ( _val ) << L2CACHE_L2CFSI_TAG_SHIFT ) & \
294 L2CACHE_L2CFSI_TAG_MASK )
295
296#define L2CACHE_L2CFSI_FL 0x200U
297
298#define L2CACHE_L2CFSI_VB 0x100U
299
300#define L2CACHE_L2CFSI_DB 0x80U
301
302#define L2CACHE_L2CFSI_WAY_SHIFT 4
303#define L2CACHE_L2CFSI_WAY_MASK 0x30U
304#define L2CACHE_L2CFSI_WAY_GET( _reg ) \
305 ( ( ( _reg ) & L2CACHE_L2CFSI_WAY_MASK ) >> \
306 L2CACHE_L2CFSI_WAY_SHIFT )
307#define L2CACHE_L2CFSI_WAY_SET( _reg, _val ) \
308 ( ( ( _reg ) & ~L2CACHE_L2CFSI_WAY_MASK ) | \
309 ( ( ( _val ) << L2CACHE_L2CFSI_WAY_SHIFT ) & \
310 L2CACHE_L2CFSI_WAY_MASK ) )
311#define L2CACHE_L2CFSI_WAY( _val ) \
312 ( ( ( _val ) << L2CACHE_L2CFSI_WAY_SHIFT ) & \
313 L2CACHE_L2CFSI_WAY_MASK )
314
315#define L2CACHE_L2CFSI_DI 0x8U
316
317#define L2CACHE_L2CFSI_WF 0x4U
318
319#define L2CACHE_L2CFSI_FMODE_SHIFT 0
320#define L2CACHE_L2CFSI_FMODE_MASK 0x3U
321#define L2CACHE_L2CFSI_FMODE_GET( _reg ) \
322 ( ( ( _reg ) & L2CACHE_L2CFSI_FMODE_MASK ) >> \
323 L2CACHE_L2CFSI_FMODE_SHIFT )
324#define L2CACHE_L2CFSI_FMODE_SET( _reg, _val ) \
325 ( ( ( _reg ) & ~L2CACHE_L2CFSI_FMODE_MASK ) | \
326 ( ( ( _val ) << L2CACHE_L2CFSI_FMODE_SHIFT ) & \
327 L2CACHE_L2CFSI_FMODE_MASK ) )
328#define L2CACHE_L2CFSI_FMODE( _val ) \
329 ( ( ( _val ) << L2CACHE_L2CFSI_FMODE_SHIFT ) & \
330 L2CACHE_L2CFSI_FMODE_MASK )
331
343#define L2CACHE_L2CERR_AHB_MASTER_INDEX_SHIFT 28
344#define L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK 0xf0000000U
345#define L2CACHE_L2CERR_AHB_MASTER_INDEX_GET( _reg ) \
346 ( ( ( _reg ) & L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK ) >> \
347 L2CACHE_L2CERR_AHB_MASTER_INDEX_SHIFT )
348#define L2CACHE_L2CERR_AHB_MASTER_INDEX_SET( _reg, _val ) \
349 ( ( ( _reg ) & ~L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK ) | \
350 ( ( ( _val ) << L2CACHE_L2CERR_AHB_MASTER_INDEX_SHIFT ) & \
351 L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK ) )
352#define L2CACHE_L2CERR_AHB_MASTER_INDEX( _val ) \
353 ( ( ( _val ) << L2CACHE_L2CERR_AHB_MASTER_INDEX_SHIFT ) & \
354 L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK )
355
356#define L2CACHE_L2CERR_SCRUB 0x8000000U
357
358#define L2CACHE_L2CERR_TYPE_SHIFT 24
359#define L2CACHE_L2CERR_TYPE_MASK 0x7000000U
360#define L2CACHE_L2CERR_TYPE_GET( _reg ) \
361 ( ( ( _reg ) & L2CACHE_L2CERR_TYPE_MASK ) >> \
362 L2CACHE_L2CERR_TYPE_SHIFT )
363#define L2CACHE_L2CERR_TYPE_SET( _reg, _val ) \
364 ( ( ( _reg ) & ~L2CACHE_L2CERR_TYPE_MASK ) | \
365 ( ( ( _val ) << L2CACHE_L2CERR_TYPE_SHIFT ) & \
366 L2CACHE_L2CERR_TYPE_MASK ) )
367#define L2CACHE_L2CERR_TYPE( _val ) \
368 ( ( ( _val ) << L2CACHE_L2CERR_TYPE_SHIFT ) & \
369 L2CACHE_L2CERR_TYPE_MASK )
370
371#define L2CACHE_L2CERR_TAG_DATA 0x800000U
372
373#define L2CACHE_L2CERR_COR_UCOR 0x400000U
374
375#define L2CACHE_L2CERR_MULTI 0x200000U
376
377#define L2CACHE_L2CERR_VALID 0x100000U
378
379#define L2CACHE_L2CERR_DISERESP 0x80000U
380
381#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SHIFT 16
382#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK 0x70000U
383#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_GET( _reg ) \
384 ( ( ( _reg ) & L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK ) >> \
385 L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SHIFT )
386#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SET( _reg, _val ) \
387 ( ( ( _reg ) & ~L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK ) | \
388 ( ( ( _val ) << L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SHIFT ) & \
389 L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK ) )
390#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER( _val ) \
391 ( ( ( _val ) << L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SHIFT ) & \
392 L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK )
393
394#define L2CACHE_L2CERR_IRQ_PENDING_SHIFT 12
395#define L2CACHE_L2CERR_IRQ_PENDING_MASK 0xf000U
396#define L2CACHE_L2CERR_IRQ_PENDING_GET( _reg ) \
397 ( ( ( _reg ) & L2CACHE_L2CERR_IRQ_PENDING_MASK ) >> \
398 L2CACHE_L2CERR_IRQ_PENDING_SHIFT )
399#define L2CACHE_L2CERR_IRQ_PENDING_SET( _reg, _val ) \
400 ( ( ( _reg ) & ~L2CACHE_L2CERR_IRQ_PENDING_MASK ) | \
401 ( ( ( _val ) << L2CACHE_L2CERR_IRQ_PENDING_SHIFT ) & \
402 L2CACHE_L2CERR_IRQ_PENDING_MASK ) )
403#define L2CACHE_L2CERR_IRQ_PENDING( _val ) \
404 ( ( ( _val ) << L2CACHE_L2CERR_IRQ_PENDING_SHIFT ) & \
405 L2CACHE_L2CERR_IRQ_PENDING_MASK )
406
407#define L2CACHE_L2CERR_IRQ_MASK_SHIFT 8
408#define L2CACHE_L2CERR_IRQ_MASK_MASK 0xf00U
409#define L2CACHE_L2CERR_IRQ_MASK_GET( _reg ) \
410 ( ( ( _reg ) & L2CACHE_L2CERR_IRQ_MASK_MASK ) >> \
411 L2CACHE_L2CERR_IRQ_MASK_SHIFT )
412#define L2CACHE_L2CERR_IRQ_MASK_SET( _reg, _val ) \
413 ( ( ( _reg ) & ~L2CACHE_L2CERR_IRQ_MASK_MASK ) | \
414 ( ( ( _val ) << L2CACHE_L2CERR_IRQ_MASK_SHIFT ) & \
415 L2CACHE_L2CERR_IRQ_MASK_MASK ) )
416#define L2CACHE_L2CERR_IRQ_MASK( _val ) \
417 ( ( ( _val ) << L2CACHE_L2CERR_IRQ_MASK_SHIFT ) & \
418 L2CACHE_L2CERR_IRQ_MASK_MASK )
419
420#define L2CACHE_L2CERR_SELECT_CB_SHIFT 6
421#define L2CACHE_L2CERR_SELECT_CB_MASK 0xc0U
422#define L2CACHE_L2CERR_SELECT_CB_GET( _reg ) \
423 ( ( ( _reg ) & L2CACHE_L2CERR_SELECT_CB_MASK ) >> \
424 L2CACHE_L2CERR_SELECT_CB_SHIFT )
425#define L2CACHE_L2CERR_SELECT_CB_SET( _reg, _val ) \
426 ( ( ( _reg ) & ~L2CACHE_L2CERR_SELECT_CB_MASK ) | \
427 ( ( ( _val ) << L2CACHE_L2CERR_SELECT_CB_SHIFT ) & \
428 L2CACHE_L2CERR_SELECT_CB_MASK ) )
429#define L2CACHE_L2CERR_SELECT_CB( _val ) \
430 ( ( ( _val ) << L2CACHE_L2CERR_SELECT_CB_SHIFT ) & \
431 L2CACHE_L2CERR_SELECT_CB_MASK )
432
433#define L2CACHE_L2CERR_SELECT_TCB_SHIFT 4
434#define L2CACHE_L2CERR_SELECT_TCB_MASK 0x30U
435#define L2CACHE_L2CERR_SELECT_TCB_GET( _reg ) \
436 ( ( ( _reg ) & L2CACHE_L2CERR_SELECT_TCB_MASK ) >> \
437 L2CACHE_L2CERR_SELECT_TCB_SHIFT )
438#define L2CACHE_L2CERR_SELECT_TCB_SET( _reg, _val ) \
439 ( ( ( _reg ) & ~L2CACHE_L2CERR_SELECT_TCB_MASK ) | \
440 ( ( ( _val ) << L2CACHE_L2CERR_SELECT_TCB_SHIFT ) & \
441 L2CACHE_L2CERR_SELECT_TCB_MASK ) )
442#define L2CACHE_L2CERR_SELECT_TCB( _val ) \
443 ( ( ( _val ) << L2CACHE_L2CERR_SELECT_TCB_SHIFT ) & \
444 L2CACHE_L2CERR_SELECT_TCB_MASK )
445
446#define L2CACHE_L2CERR_XCB 0x8U
447
448#define L2CACHE_L2CERR_RCB 0x4U
449
450#define L2CACHE_L2CERR_COMP 0x2U
451
452#define L2CACHE_L2CERR_RST 0x1U
453
465#define L2CACHE_L2CERRA_EADDR_SHIFT 0
466#define L2CACHE_L2CERRA_EADDR_MASK 0xffffffffU
467#define L2CACHE_L2CERRA_EADDR_GET( _reg ) \
468 ( ( ( _reg ) & L2CACHE_L2CERRA_EADDR_MASK ) >> \
469 L2CACHE_L2CERRA_EADDR_SHIFT )
470#define L2CACHE_L2CERRA_EADDR_SET( _reg, _val ) \
471 ( ( ( _reg ) & ~L2CACHE_L2CERRA_EADDR_MASK ) | \
472 ( ( ( _val ) << L2CACHE_L2CERRA_EADDR_SHIFT ) & \
473 L2CACHE_L2CERRA_EADDR_MASK ) )
474#define L2CACHE_L2CERRA_EADDR( _val ) \
475 ( ( ( _val ) << L2CACHE_L2CERRA_EADDR_SHIFT ) & \
476 L2CACHE_L2CERRA_EADDR_MASK )
477
488#define L2CACHE_L2CTCB_TCB_SHIFT 0
489#define L2CACHE_L2CTCB_TCB_MASK 0x7fU
490#define L2CACHE_L2CTCB_TCB_GET( _reg ) \
491 ( ( ( _reg ) & L2CACHE_L2CTCB_TCB_MASK ) >> \
492 L2CACHE_L2CTCB_TCB_SHIFT )
493#define L2CACHE_L2CTCB_TCB_SET( _reg, _val ) \
494 ( ( ( _reg ) & ~L2CACHE_L2CTCB_TCB_MASK ) | \
495 ( ( ( _val ) << L2CACHE_L2CTCB_TCB_SHIFT ) & \
496 L2CACHE_L2CTCB_TCB_MASK ) )
497#define L2CACHE_L2CTCB_TCB( _val ) \
498 ( ( ( _val ) << L2CACHE_L2CTCB_TCB_SHIFT ) & \
499 L2CACHE_L2CTCB_TCB_MASK )
500
511#define L2CACHE_L2CCB_CB_SHIFT 0
512#define L2CACHE_L2CCB_CB_MASK 0xfffffffU
513#define L2CACHE_L2CCB_CB_GET( _reg ) \
514 ( ( ( _reg ) & L2CACHE_L2CCB_CB_MASK ) >> \
515 L2CACHE_L2CCB_CB_SHIFT )
516#define L2CACHE_L2CCB_CB_SET( _reg, _val ) \
517 ( ( ( _reg ) & ~L2CACHE_L2CCB_CB_MASK ) | \
518 ( ( ( _val ) << L2CACHE_L2CCB_CB_SHIFT ) & \
519 L2CACHE_L2CCB_CB_MASK ) )
520#define L2CACHE_L2CCB_CB( _val ) \
521 ( ( ( _val ) << L2CACHE_L2CCB_CB_SHIFT ) & \
522 L2CACHE_L2CCB_CB_MASK )
523
535#define L2CACHE_L2CSCRUB_INDEX_SHIFT 16
536#define L2CACHE_L2CSCRUB_INDEX_MASK 0xffff0000U
537#define L2CACHE_L2CSCRUB_INDEX_GET( _reg ) \
538 ( ( ( _reg ) & L2CACHE_L2CSCRUB_INDEX_MASK ) >> \
539 L2CACHE_L2CSCRUB_INDEX_SHIFT )
540#define L2CACHE_L2CSCRUB_INDEX_SET( _reg, _val ) \
541 ( ( ( _reg ) & ~L2CACHE_L2CSCRUB_INDEX_MASK ) | \
542 ( ( ( _val ) << L2CACHE_L2CSCRUB_INDEX_SHIFT ) & \
543 L2CACHE_L2CSCRUB_INDEX_MASK ) )
544#define L2CACHE_L2CSCRUB_INDEX( _val ) \
545 ( ( ( _val ) << L2CACHE_L2CSCRUB_INDEX_SHIFT ) & \
546 L2CACHE_L2CSCRUB_INDEX_MASK )
547
548#define L2CACHE_L2CSCRUB_WAY_SHIFT 2
549#define L2CACHE_L2CSCRUB_WAY_MASK 0xcU
550#define L2CACHE_L2CSCRUB_WAY_GET( _reg ) \
551 ( ( ( _reg ) & L2CACHE_L2CSCRUB_WAY_MASK ) >> \
552 L2CACHE_L2CSCRUB_WAY_SHIFT )
553#define L2CACHE_L2CSCRUB_WAY_SET( _reg, _val ) \
554 ( ( ( _reg ) & ~L2CACHE_L2CSCRUB_WAY_MASK ) | \
555 ( ( ( _val ) << L2CACHE_L2CSCRUB_WAY_SHIFT ) & \
556 L2CACHE_L2CSCRUB_WAY_MASK ) )
557#define L2CACHE_L2CSCRUB_WAY( _val ) \
558 ( ( ( _val ) << L2CACHE_L2CSCRUB_WAY_SHIFT ) & \
559 L2CACHE_L2CSCRUB_WAY_MASK )
560
561#define L2CACHE_L2CSCRUB_PEN 0x2U
562
563#define L2CACHE_L2CSCRUB_EN 0x1U
564
575#define L2CACHE_L2CSDEL_DEL_SHIFT 0
576#define L2CACHE_L2CSDEL_DEL_MASK 0xffffU
577#define L2CACHE_L2CSDEL_DEL_GET( _reg ) \
578 ( ( ( _reg ) & L2CACHE_L2CSDEL_DEL_MASK ) >> \
579 L2CACHE_L2CSDEL_DEL_SHIFT )
580#define L2CACHE_L2CSDEL_DEL_SET( _reg, _val ) \
581 ( ( ( _reg ) & ~L2CACHE_L2CSDEL_DEL_MASK ) | \
582 ( ( ( _val ) << L2CACHE_L2CSDEL_DEL_SHIFT ) & \
583 L2CACHE_L2CSDEL_DEL_MASK ) )
584#define L2CACHE_L2CSDEL_DEL( _val ) \
585 ( ( ( _val ) << L2CACHE_L2CSDEL_DEL_SHIFT ) & \
586 L2CACHE_L2CSDEL_DEL_MASK )
587
599#define L2CACHE_L2CEINJ_ADDR_SHIFT 2
600#define L2CACHE_L2CEINJ_ADDR_MASK 0xfffffffcU
601#define L2CACHE_L2CEINJ_ADDR_GET( _reg ) \
602 ( ( ( _reg ) & L2CACHE_L2CEINJ_ADDR_MASK ) >> \
603 L2CACHE_L2CEINJ_ADDR_SHIFT )
604#define L2CACHE_L2CEINJ_ADDR_SET( _reg, _val ) \
605 ( ( ( _reg ) & ~L2CACHE_L2CEINJ_ADDR_MASK ) | \
606 ( ( ( _val ) << L2CACHE_L2CEINJ_ADDR_SHIFT ) & \
607 L2CACHE_L2CEINJ_ADDR_MASK ) )
608#define L2CACHE_L2CEINJ_ADDR( _val ) \
609 ( ( ( _val ) << L2CACHE_L2CEINJ_ADDR_SHIFT ) & \
610 L2CACHE_L2CEINJ_ADDR_MASK )
611
612#define L2CACHE_L2CEINJ_INJ 0x1U
613
625#define L2CACHE_L2CACCC_DSC 0x4000U
626
627#define L2CACHE_L2CACCC_SH 0x2000U
628
629#define L2CACHE_L2CACCC_SPLITQ 0x400U
630
631#define L2CACHE_L2CACCC_NHM 0x200U
632
633#define L2CACHE_L2CACCC_BERR 0x100U
634
635#define L2CACHE_L2CACCC_OAPM 0x80U
636
637#define L2CACHE_L2CACCC_FLINE 0x40U
638
639#define L2CACHE_L2CACCC_DBPF 0x20U
640
641#define L2CACHE_L2CACCC_128WF 0x10U
642
643#define L2CACHE_L2CACCC_DBPWS 0x4U
644
645#define L2CACHE_L2CACCC_SPLIT 0x2U
646
658#define L2CACHE_L2CEINJCFG_EDI 0x400U
659
660#define L2CACHE_L2CEINJCFG_TER 0x200U
661
662#define L2CACHE_L2CEINJCFG_IMD 0x100U
663
675#define L2CACHE_L2CMTRR_ADDR_SHIFT 18
676#define L2CACHE_L2CMTRR_ADDR_MASK 0xfffc0000U
677#define L2CACHE_L2CMTRR_ADDR_GET( _reg ) \
678 ( ( ( _reg ) & L2CACHE_L2CMTRR_ADDR_MASK ) >> \
679 L2CACHE_L2CMTRR_ADDR_SHIFT )
680#define L2CACHE_L2CMTRR_ADDR_SET( _reg, _val ) \
681 ( ( ( _reg ) & ~L2CACHE_L2CMTRR_ADDR_MASK ) | \
682 ( ( ( _val ) << L2CACHE_L2CMTRR_ADDR_SHIFT ) & \
683 L2CACHE_L2CMTRR_ADDR_MASK ) )
684#define L2CACHE_L2CMTRR_ADDR( _val ) \
685 ( ( ( _val ) << L2CACHE_L2CMTRR_ADDR_SHIFT ) & \
686 L2CACHE_L2CMTRR_ADDR_MASK )
687
688#define L2CACHE_L2CMTRR_ACC_SHIFT 16
689#define L2CACHE_L2CMTRR_ACC_MASK 0x30000U
690#define L2CACHE_L2CMTRR_ACC_GET( _reg ) \
691 ( ( ( _reg ) & L2CACHE_L2CMTRR_ACC_MASK ) >> \
692 L2CACHE_L2CMTRR_ACC_SHIFT )
693#define L2CACHE_L2CMTRR_ACC_SET( _reg, _val ) \
694 ( ( ( _reg ) & ~L2CACHE_L2CMTRR_ACC_MASK ) | \
695 ( ( ( _val ) << L2CACHE_L2CMTRR_ACC_SHIFT ) & \
696 L2CACHE_L2CMTRR_ACC_MASK ) )
697#define L2CACHE_L2CMTRR_ACC( _val ) \
698 ( ( ( _val ) << L2CACHE_L2CMTRR_ACC_SHIFT ) & \
699 L2CACHE_L2CMTRR_ACC_MASK )
700
701#define L2CACHE_L2CMTRR_MASK_SHIFT 2
702#define L2CACHE_L2CMTRR_MASK_MASK 0xfffcU
703#define L2CACHE_L2CMTRR_MASK_GET( _reg ) \
704 ( ( ( _reg ) & L2CACHE_L2CMTRR_MASK_MASK ) >> \
705 L2CACHE_L2CMTRR_MASK_SHIFT )
706#define L2CACHE_L2CMTRR_MASK_SET( _reg, _val ) \
707 ( ( ( _reg ) & ~L2CACHE_L2CMTRR_MASK_MASK ) | \
708 ( ( ( _val ) << L2CACHE_L2CMTRR_MASK_SHIFT ) & \
709 L2CACHE_L2CMTRR_MASK_MASK ) )
710#define L2CACHE_L2CMTRR_MASK( _val ) \
711 ( ( ( _val ) << L2CACHE_L2CMTRR_MASK_SHIFT ) & \
712 L2CACHE_L2CMTRR_MASK_MASK )
713
714#define L2CACHE_L2CMTRR_WP 0x2U
715
716#define L2CACHE_L2CMTRR_AC 0x1U
717
723typedef struct l2cache {
727 uint32_t l2cc;
728
732 uint32_t l2cs;
733
737 uint32_t l2cfma;
738
742 uint32_t l2cfsi;
743
744 uint32_t reserved_10_20[ 4 ];
745
749 uint32_t l2cerr;
750
754 uint32_t l2cerra;
755
759 uint32_t l2ctcb;
760
764 uint32_t l2ccb;
765
769 uint32_t l2cscrub;
770
774 uint32_t l2csdel;
775
779 uint32_t l2ceinj;
780
784 uint32_t l2caccc;
785
786 uint32_t reserved_40_4c[ 3 ];
787
791 uint32_t l2ceinjcfg;
792
793 uint32_t reserved_50_80[ 12 ];
794
798 uint32_t l2cmtrr;
799} l2cache;
800
803#ifdef __cplusplus
804}
805#endif
806
807#endif /* _GRLIB_L2CACHE_REGS_H */
l2cache
This structure defines the L2CACHE register block memory map.
Definition: l2cache-regs.h:723
l2cache::l2cfma
uint32_t l2cfma
See L2C Flush (Memory address) register (L2CFMA).
Definition: l2cache-regs.h:737
l2cache::l2csdel
uint32_t l2csdel
See L2C Scrub delay register (L2CSDEL).
Definition: l2cache-regs.h:774
l2cache::l2ceinjcfg
uint32_t l2ceinjcfg
See L2C injection configuration register (L2CEINJCFG).
Definition: l2cache-regs.h:791
l2cache::l2cmtrr
uint32_t l2cmtrr
See L2C Memory type range register (L2CMTRR).
Definition: l2cache-regs.h:798
l2cache::l2cfsi
uint32_t l2cfsi
See L2C Flush (Set, Index) register (L2CFSI).
Definition: l2cache-regs.h:742
l2cache::l2cc
uint32_t l2cc
See L2C Control register (L2CC).
Definition: l2cache-regs.h:727
l2cache::l2cscrub
uint32_t l2cscrub
See L2C Scrub control/status register (L2CSCRUB).
Definition: l2cache-regs.h:769
l2cache::l2cerr
uint32_t l2cerr
See L2CError status/control register (L2CERR).
Definition: l2cache-regs.h:749
l2cache::l2ctcb
uint32_t l2ctcb
See L2C TAG-Check-Bits register (L2CTCB).
Definition: l2cache-regs.h:759
l2cache::l2ceinj
uint32_t l2ceinj
See L2C Error injection register (L2CEINJ).
Definition: l2cache-regs.h:779
l2cache::l2caccc
uint32_t l2caccc
See L2C Access control register (L2CACCC).
Definition: l2cache-regs.h:784
l2cache::l2ccb
uint32_t l2ccb
See L2C Data-Check-Bits register (L2CCB).
Definition: l2cache-regs.h:764
l2cache::l2cs
uint32_t l2cs
See L2C Status register (L2CS).
Definition: l2cache-regs.h:732
l2cache::l2cerra
uint32_t l2cerra
See L2C Error address register (L2CERRA).
Definition: l2cache-regs.h:754
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