RTEMS 6.1-rc6
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intc.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#ifndef LIBBSP_MICROBLAZE_FPGA_INTC_H
37#define LIBBSP_MICROBLAZE_FPGA_INTC_H
38
39#include <bspopts.h>
40
41#include <bsp/utility.h>
42
43#ifdef __cplusplus
44extern "C" {
45#endif /* __cplusplus */
46
47typedef struct {
48 /* Interrupt Status Register */
49 uint32_t isr;
50 uint32_t ipr;
51 /* Interrupt Enable Register */
52 uint32_t ier;
53 /* Interrupt Acknowledge Register */
54 uint32_t iar;
55 uint32_t sie;
56 uint32_t cie;
57 uint32_t ivr;
58#define MICROBLAZE_INTC_MER_HIE BSP_BIT32(1)
59#define MICROBLAZE_INTC_MER_ME BSP_BIT32(0)
60 /* Master Enable Register */
61 uint32_t mer;
62 /* Interrupt Mode Register, this is present only for Fast Interrupt */
63 uint32_t imr;
64 /* Interrupt Level Register */
65 uint32_t ilr;
67
68#ifdef __cplusplus
69}
70#endif /* __cplusplus */
71
72#endif /* LIBBSP_MICROBLAZE_FPGA_INTC_H */
This header file provides utility macros for BSPs.
Definition: intc.h:47