36#ifndef __GRPCI2DMA_H__
37#define __GRPCI2DMA_H__
47#define GRPCI2DMA_ERR_OK 0
48#define GRPCI2DMA_ERR_WRONGPTR -1
49#define GRPCI2DMA_ERR_NOINIT -2
50#define GRPCI2DMA_ERR_TOOMANY -3
51#define GRPCI2DMA_ERR_ERROR -4
52#define GRPCI2DMA_ERR_STOPDMA -5
53#define GRPCI2DMA_ERR_NOTFOUND -6
56#define GRPCI2DMA_BD_CHAN_SIZE 0x10
57#define GRPCI2DMA_BD_DATA_SIZE 0x10
60#define GRPCI2DMA_BD_CHAN_ALIGN 0x10
61#define GRPCI2DMA_BD_DATA_ALIGN 0x10
66extern void * grpci2dma_channel_new(
int number);
67extern void grpci2dma_channel_delete(
void * chanbd);
68extern void * grpci2dma_data_new(
int number);
69extern void grpci2dma_data_delete(
void * databd);
94#define GRPCI2DMA_AHBTOPCI 1
95#define GRPCI2DMA_PCITOAHB 0
96#define GRPCI2DMA_LITTLEENDIAN 1
97#define GRPCI2DMA_BIGENDIAN 0
98extern int grpci2dma_prepare(
99 uint32_t pci_start, uint32_t ahb_start,
int dir,
int endianness,
100 int size,
void * databd,
int bdindex,
int bdmax,
int block_size);
119#define GRPCI2DMA_BD_STATUS_DISABLED 0
120#define GRPCI2DMA_BD_STATUS_ENABLED 1
121#define GRPCI2DMA_BD_STATUS_ERR 2
122extern int grpci2dma_status(
void *databd,
int bdindex,
int bdsize);
129typedef void (*grpci2dma_isr_t)(
void *arg,
int cid,
unsigned int status);
144extern int grpci2dma_isr_register(
145 int chan_no, grpci2dma_isr_t dmaisr,
void *arg);
158extern int grpci2dma_isr_unregister(
int chan_no);
174extern int grpci2dma_open(
void * chan);
190extern int grpci2dma_close(
int chan_no);
206extern int grpci2dma_start(
int chan_no,
int options);
220extern int grpci2dma_stop(
int chan_no);
237extern int grpci2dma_push(
int chan_no,
void *databd,
int bdindex,
int bdsize);
248extern int grpci2dma_active(
void);
268#define GRPCI2DMA_OPTIONS_ALL 1
269#define GRPCI2DMA_OPTIONS_ONE 0
270extern int grpci2dma_interrupt_enable(
271 void *databd,
int bdindex,
int bdmax,
int options);
275extern int grpci2dma_print(
int chan_no);
276extern int grpci2dma_print_bd(
void * data);