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RTEMS 6.1-rc6
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RTEMS 6.1-rc6
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Macros | |
| #define | FSL_COMPONENT_ID "platform.drivers.nic301" |
| #define | FSL_COMPONENT_ID "platform.drivers.nic301" |
Driver version | |
| enum | _nic_reg { kNIC_REG_READ_QOS_LCD = NIC_LCD_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_USBO2 = NIC_USBO2_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_TestPort = NIC_TestPort_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_CM7 = NIC_CM7_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_DMA = NIC_DMA_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_WRITE_QOS_LCD = NIC_LCD_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_CSI = NIC_CSI_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_PXP = NIC_PXP_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_DCP = NIC_DCP_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_ENET = NIC_ENET_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_USBO2 = NIC_USBO2_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_TestPort = NIC_TestPort_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_CM7 = NIC_CM7_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_DMA = NIC_DMA_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_FN_MOD_LCD = NIC_LCD_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_CSI = NIC_CSI_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_PXP = NIC_PXP_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_DCP = NIC_DCP_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_ENET = NIC_ENET_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_USBO2 = NIC_USBO2_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_USDHC2 = NIC_USDHC2_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_TestPort = NIC_TestPort_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_CM7 = NIC_CM7_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_DMA = NIC_DMA_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD2_DCP = NIC_ENET_BASE + NIC_FN_MOD2_OFFSET , kNIC_REG_FN_MOD_AHB_ENET = NIC_ENET_BASE + NIC_FN_MOD_AHB_OFFSET , kNIC_REG_FN_MOD_AHB_TestPort = NIC_TestPort_BASE + NIC_FN_MOD_AHB_OFFSET , kNIC_REG_FN_MOD_AHB_DMA = NIC_DMA_BASE + NIC_FN_MOD_AHB_OFFSET , kNIC_REG_WR_TIDEMARK_CM7 = NIC_CM7_BASE + NIC_WR_TIDEMARK_OFFSET , kNIC_REG_READ_QOS_GC355 = NIC_GC355_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_LCDIF = NIC_LCDIF_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_LCDIFV2 = NIC_LCDIFV2_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_CAAM = NIC_CAAM_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_ENET1G_TX = NIC_ENET1G_TX_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_USBO2 = NIC_USBO2_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_ENET_QOS = NIC_ENET_QOS_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_CM7 = NIC_CM7_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_DMA = NIC_DMA_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_IEE = NIC_IEE_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_WRITE_QOS_GC355 = NIC_GC355_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_PXP = NIC_PXP_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_LCDIF = NIC_LCDIF_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_LCDIFV2 = NIC_LCDIFV2_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_CSI = NIC_CSI_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_CAAM = NIC_CAAM_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_ENET1G_TX = NIC_ENET1G_TX_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_ENET = NIC_ENET_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_USBO2 = NIC_USBO2_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_ENET_QOS = NIC_ENET_QOS_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_CM7 = NIC_CM7_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_DMA = NIC_DMA_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_IEE = NIC_IEE_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_FN_MOD_GC355 = NIC_GC355_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_PXP = NIC_PXP_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_LCDIF = NIC_LCDIF_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_LCDIFV2 = NIC_LCDIFV2_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_CSI = NIC_CSI_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_CAAM = NIC_CAAM_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_ENET1G_TX = NIC_ENET1G_TX_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_ENET = NIC_ENET_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_USBO2 = NIC_USBO2_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_USDHC2 = NIC_USDHC2_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_ENET_QOS = NIC_ENET_QOS_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_CM7 = NIC_CM7_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_DMA = NIC_DMA_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_IEE = NIC_IEE_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_AHB_ENET = NIC_ENET_BASE + NIC_FN_MOD_AHB_OFFSET , kNIC_REG_FN_MOD_AHB_DMA = NIC_DMA_BASE + NIC_FN_MOD_AHB_OFFSET , kNIC_REG_WR_TIDEMARK_LPSRMIX_M = NIC_LPSRMIX_M_BASE + NIC_WR_TIDEMARK_OFFSET } |
| enum | _nic_fn_mod2 { kNIC_FN_MOD2_ENABLE = 0 , kNIC_FN_MOD2_BYPASS } |
| enum | _nic_fn_mod_ahb { kNIC_FN_MOD_AHB_RD_INCR_OVERRIDE = 0 , kNIC_FN_MOD_AHB_WR_INCR_OVERRIDE , kNIC_FN_MOD_AHB_LOCK_OVERRIDE , kNIC_FN_MOD_AHB_RD_INCR_OVERRIDE = 0 , kNIC_FN_MOD_AHB_WR_INCR_OVERRIDE , kNIC_FN_MOD_AHB_LOCK_OVERRIDE } |
| enum | _nic_fn_mod { kNIC_FN_MOD_ReadIssue = 0 , kNIC_FN_MOD_WriteIssue , kNIC_FN_MOD_ReadIssue = 0 , kNIC_FN_MOD_WriteIssue } |
| enum | _nic_qos { kNIC_QOS_0 = 0 , kNIC_QOS_1 , kNIC_QOS_2 , kNIC_QOS_3 , kNIC_QOS_4 , kNIC_QOS_5 , kNIC_QOS_6 , kNIC_QOS_7 , kNIC_QOS_8 , kNIC_QOS_9 , kNIC_QOS_10 , kNIC_QOS_11 , kNIC_QOS_12 , kNIC_QOS_13 , kNIC_QOS_14 , kNIC_QOS_15 , kNIC_QOS_0 = 0 , kNIC_QOS_1 , kNIC_QOS_2 , kNIC_QOS_3 , kNIC_QOS_4 , kNIC_QOS_5 , kNIC_QOS_6 , kNIC_QOS_7 , kNIC_QOS_8 , kNIC_QOS_9 , kNIC_QOS_10 , kNIC_QOS_11 , kNIC_QOS_12 , kNIC_QOS_13 , kNIC_QOS_14 , kNIC_QOS_15 } |
| typedef enum _nic_reg | nic_reg_t |
| typedef enum _nic_fn_mod2 | nic_fn_mod2_t |
| typedef enum _nic_fn_mod_ahb | nic_fn_mod_ahb_t |
| typedef enum _nic_fn_mod | nic_fn_mod_t |
| typedef enum _nic_qos | nic_qos_t |
| #define | FSL_NIC301_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U)) |
| NIC301 driver version 2.0.1. | |
| #define | GPV0_BASE (0x41000000UL) |
| #define | GPV1_BASE (0x41100000UL) |
| #define | GPV4_BASE (0x41400000UL) |
| #define | NIC_FN_MOD2_OFFSET (0x024UL) |
| #define | NIC_FN_MOD_AHB_OFFSET (0x028UL) |
| #define | NIC_WR_TIDEMARK_OFFSET (0x040UL) |
| #define | NIC_READ_QOS_OFFSET (0x100UL) |
| #define | NIC_WRITE_QOS_OFFSET (0x104UL) |
| #define | NIC_FN_MOD_OFFSET (0x108UL) |
| #define | NIC_LCD_BASE (GPV0_BASE + 0x44000) |
| #define | NIC_CSI_BASE (GPV0_BASE + 0x45000) |
| #define | NIC_PXP_BASE (GPV0_BASE + 0x46000) |
| #define | NIC_DCP_BASE (GPV1_BASE + 0x42000) |
| #define | NIC_ENET_BASE (GPV1_BASE + 0x43000) |
| #define | NIC_USBO2_BASE (GPV1_BASE + 0x44000) |
| #define | NIC_USDHC1_BASE (GPV1_BASE + 0x45000) |
| #define | NIC_USDHC2_BASE (GPV1_BASE + 0x46000) |
| #define | NIC_TestPort_BASE (GPV1_BASE + 0x47000) |
| #define | NIC_CM7_BASE (GPV4_BASE + 0x42000) |
| #define | NIC_DMA_BASE (GPV4_BASE + 0x43000) |
| #define | NIC_QOS_MASK (0xF) |
| #define | NIC_WR_TIDEMARK_MASK (0x7) |
| #define | NIC_FN_MOD_AHB_MASK (0x7) |
| #define | NIC_FN_MOD_MASK (0x1) |
| #define | NIC_FN_MOD2_MASK (0x1) |
Driver version | |
| enum | _nic_reg { kNIC_REG_READ_QOS_LCD = NIC_LCD_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_USBO2 = NIC_USBO2_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_TestPort = NIC_TestPort_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_CM7 = NIC_CM7_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_DMA = NIC_DMA_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_WRITE_QOS_LCD = NIC_LCD_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_CSI = NIC_CSI_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_PXP = NIC_PXP_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_DCP = NIC_DCP_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_ENET = NIC_ENET_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_USBO2 = NIC_USBO2_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_TestPort = NIC_TestPort_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_CM7 = NIC_CM7_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_DMA = NIC_DMA_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_FN_MOD_LCD = NIC_LCD_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_CSI = NIC_CSI_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_PXP = NIC_PXP_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_DCP = NIC_DCP_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_ENET = NIC_ENET_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_USBO2 = NIC_USBO2_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_USDHC2 = NIC_USDHC2_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_TestPort = NIC_TestPort_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_CM7 = NIC_CM7_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_DMA = NIC_DMA_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD2_DCP = NIC_ENET_BASE + NIC_FN_MOD2_OFFSET , kNIC_REG_FN_MOD_AHB_ENET = NIC_ENET_BASE + NIC_FN_MOD_AHB_OFFSET , kNIC_REG_FN_MOD_AHB_TestPort = NIC_TestPort_BASE + NIC_FN_MOD_AHB_OFFSET , kNIC_REG_FN_MOD_AHB_DMA = NIC_DMA_BASE + NIC_FN_MOD_AHB_OFFSET , kNIC_REG_WR_TIDEMARK_CM7 = NIC_CM7_BASE + NIC_WR_TIDEMARK_OFFSET , kNIC_REG_READ_QOS_GC355 = NIC_GC355_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_LCDIF = NIC_LCDIF_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_LCDIFV2 = NIC_LCDIFV2_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_CAAM = NIC_CAAM_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_ENET1G_TX = NIC_ENET1G_TX_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_USBO2 = NIC_USBO2_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_ENET_QOS = NIC_ENET_QOS_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_CM7 = NIC_CM7_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_DMA = NIC_DMA_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_READ_QOS_IEE = NIC_IEE_BASE + NIC_READ_QOS_OFFSET , kNIC_REG_WRITE_QOS_GC355 = NIC_GC355_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_PXP = NIC_PXP_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_LCDIF = NIC_LCDIF_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_LCDIFV2 = NIC_LCDIFV2_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_CSI = NIC_CSI_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_CAAM = NIC_CAAM_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_ENET1G_TX = NIC_ENET1G_TX_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_ENET = NIC_ENET_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_USBO2 = NIC_USBO2_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_ENET_QOS = NIC_ENET_QOS_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_CM7 = NIC_CM7_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_DMA = NIC_DMA_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_WRITE_QOS_IEE = NIC_IEE_BASE + NIC_WRITE_QOS_OFFSET , kNIC_REG_FN_MOD_GC355 = NIC_GC355_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_PXP = NIC_PXP_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_LCDIF = NIC_LCDIF_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_LCDIFV2 = NIC_LCDIFV2_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_CSI = NIC_CSI_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_CAAM = NIC_CAAM_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_ENET1G_TX = NIC_ENET1G_TX_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_ENET = NIC_ENET_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_USBO2 = NIC_USBO2_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_USDHC2 = NIC_USDHC2_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_ENET_QOS = NIC_ENET_QOS_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_CM7 = NIC_CM7_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_DMA = NIC_DMA_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_IEE = NIC_IEE_BASE + NIC_FN_MOD_OFFSET , kNIC_REG_FN_MOD_AHB_ENET = NIC_ENET_BASE + NIC_FN_MOD_AHB_OFFSET , kNIC_REG_FN_MOD_AHB_DMA = NIC_DMA_BASE + NIC_FN_MOD_AHB_OFFSET , kNIC_REG_WR_TIDEMARK_LPSRMIX_M = NIC_LPSRMIX_M_BASE + NIC_WR_TIDEMARK_OFFSET } |
| enum | _nic_fn_mod_ahb { kNIC_FN_MOD_AHB_RD_INCR_OVERRIDE = 0 , kNIC_FN_MOD_AHB_WR_INCR_OVERRIDE , kNIC_FN_MOD_AHB_LOCK_OVERRIDE , kNIC_FN_MOD_AHB_RD_INCR_OVERRIDE = 0 , kNIC_FN_MOD_AHB_WR_INCR_OVERRIDE , kNIC_FN_MOD_AHB_LOCK_OVERRIDE } |
| enum | _nic_fn_mod { kNIC_FN_MOD_ReadIssue = 0 , kNIC_FN_MOD_WriteIssue , kNIC_FN_MOD_ReadIssue = 0 , kNIC_FN_MOD_WriteIssue } |
| enum | _nic_qos { kNIC_QOS_0 = 0 , kNIC_QOS_1 , kNIC_QOS_2 , kNIC_QOS_3 , kNIC_QOS_4 , kNIC_QOS_5 , kNIC_QOS_6 , kNIC_QOS_7 , kNIC_QOS_8 , kNIC_QOS_9 , kNIC_QOS_10 , kNIC_QOS_11 , kNIC_QOS_12 , kNIC_QOS_13 , kNIC_QOS_14 , kNIC_QOS_15 , kNIC_QOS_0 = 0 , kNIC_QOS_1 , kNIC_QOS_2 , kNIC_QOS_3 , kNIC_QOS_4 , kNIC_QOS_5 , kNIC_QOS_6 , kNIC_QOS_7 , kNIC_QOS_8 , kNIC_QOS_9 , kNIC_QOS_10 , kNIC_QOS_11 , kNIC_QOS_12 , kNIC_QOS_13 , kNIC_QOS_14 , kNIC_QOS_15 } |
| typedef enum _nic_reg | nic_reg_t |
| typedef enum _nic_fn_mod_ahb | nic_fn_mod_ahb_t |
| typedef enum _nic_fn_mod | nic_fn_mod_t |
| typedef enum _nic_qos | nic_qos_t |
| #define | FSL_NIC301_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U)) |
| NIC301 driver version 2.0.1. | |
| #define | GPV0_BASE (0x41000000UL) |
| #define | GPV1_BASE (0x41100000UL) |
| #define | GPV4_BASE (0x41400000UL) |
| #define | NIC_FN_MOD_AHB_OFFSET (0x028UL) |
| #define | NIC_WR_TIDEMARK_OFFSET (0x040UL) |
| #define | NIC_READ_QOS_OFFSET (0x100UL) |
| #define | NIC_WRITE_QOS_OFFSET (0x104UL) |
| #define | NIC_FN_MOD_OFFSET (0x108UL) |
| #define | NIC_GC355_BASE (GPV0_BASE + 0x42000) |
| #define | NIC_PXP_BASE (GPV0_BASE + 0x43000) |
| #define | NIC_LCDIF_BASE (GPV0_BASE + 0x44000) |
| #define | NIC_LCDIFV2_BASE (GPV0_BASE + 0x45000) |
| #define | NIC_CSI_BASE (GPV0_BASE + 0x46000) |
| #define | NIC_CAAM_BASE (GPV1_BASE + 0x42000) |
| #define | NIC_ENET1G_RX_BASE (GPV1_BASE + 0x43000) |
| #define | NIC_ENET1G_TX_BASE (GPV1_BASE + 0x44000) |
| #define | NIC_ENET_BASE (GPV1_BASE + 0x45000) |
| #define | NIC_USBO2_BASE (GPV1_BASE + 0x46000) |
| #define | NIC_USDHC1_BASE (GPV1_BASE + 0x47000) |
| #define | NIC_USDHC2_BASE (GPV1_BASE + 0x48000) |
| #define | NIC_ENET_QOS_BASE (GPV1_BASE + 0x4A000) |
| #define | NIC_CM7_BASE (GPV4_BASE + 0x42000) |
| #define | NIC_LPSRMIX_M_BASE (GPV4_BASE + 0x46000) |
| #define | NIC_DMA_BASE (GPV4_BASE + 0x47000) |
| #define | NIC_IEE_BASE (GPV4_BASE + 0x48000) |
| #define | NIC_QOS_MASK (0xF) |
| #define | NIC_WR_TIDEMARK_MASK (0xF) |
| #define | NIC_FN_MOD_AHB_MASK (0x7) |
| #define | NIC_FN_MOD_MASK (0x1) |
1.9.6