RTEMS 6.1-rc6
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fsl_flexspi.h
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2022 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef __FSL_FLEXSPI_H_
10#define __FSL_FLEXSPI_H_
11
12#include <stddef.h>
13#include "fsl_device_registers.h"
14#include "fsl_common.h"
15
21/*******************************************************************************
22 * Definitions
23 ******************************************************************************/
24
28#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 5, 0))
31#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0)
32
34#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
35 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
36 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
37
39enum
40{
48};
49
51enum
52{
84};
85
87typedef enum _flexspi_pad
88{
89 kFLEXSPI_1PAD = 0x00U,
90 kFLEXSPI_2PAD = 0x01U,
91 kFLEXSPI_4PAD = 0x02U,
92 kFLEXSPI_8PAD = 0x03U,
94
96typedef enum _flexspi_flags
97{
98 kFLEXSPI_SequenceExecutionTimeoutFlag = FLEXSPI_INTEN_SEQTIMEOUTEN_MASK,
99#if defined(FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN) && FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN
100 kFLEXSPI_AhbBusErrorFlag = FLEXSPI_INTEN_AHBBUSERROREN_MASK,
101#else
102 kFLEXSPI_AhbBusTimeoutFlag = FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK,
103#endif
105 FLEXSPI_INTEN_SCKSTOPBYWREN_MASK,
108 FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK,
110#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN))
111 kFLEXSPI_DataLearningFailedFlag = FLEXSPI_INTEN_DATALEARNFAILEN_MASK,
112#endif
113 kFLEXSPI_IpTxFifoWatermarkEmptyFlag = FLEXSPI_INTEN_IPTXWEEN_MASK,
114 kFLEXSPI_IpRxFifoWatermarkAvailableFlag = FLEXSPI_INTEN_IPRXWAEN_MASK,
116 FLEXSPI_INTEN_AHBCMDERREN_MASK,
117 kFLEXSPI_IpCommandSequenceErrorFlag = FLEXSPI_INTEN_IPCMDERREN_MASK,
119 FLEXSPI_INTEN_AHBCMDGEEN_MASK,
121 FLEXSPI_INTEN_IPCMDGEEN_MASK,
123 FLEXSPI_INTEN_IPCMDDONEEN_MASK,
126
129{
137
140{
144
147{
157
160{
173
176{
187
189typedef enum _flexspi_port
190{
193#if !((defined(FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB)) && (FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB))
196#endif
197 kFLEXSPI_PortCount
199
202{
203 kFLEXSPI_AhbReadCommand = 0x0U,
204 kFLEXSPI_AhbWriteCommand = 0x1U,
205 kFLEXSPI_IpCommand = 0x2U,
206 kFLEXSPI_SuspendedCommand = 0x3U,
208
211{
214 kFLEXSPI_Read, /* /!< FlexSPI operation: Read, only Rx Buffer is effective. */
215 kFLEXSPI_Write, /* /!< FlexSPI operation: Read, only Tx Buffer is effective. */
217
219{
220 uint8_t priority;
221 uint8_t masterIndex;
222 uint16_t bufferSize;
226
228typedef struct _flexspi_config
229{
232#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN)
235#endif
239#if defined(FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB) && FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB
240 flexspi_read_sample_clock_t rxSampleClockPortB;
241#endif
242#if defined(FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF) && FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF
243 bool rxSampleClockDiff;
244#endif
245#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT)
248#endif
255 uint8_t txWatermark;
256 uint8_t rxWatermark;
257 struct
258 {
259#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN)
261#endif
262#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN)
264#endif
271 flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT];
281 } ahbConfig;
283
286{
287 uint32_t flexspiRootClk;
289 uint32_t flashSize;
290#if defined(FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT) && (FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT)
291 bool addressShift;
292#endif /* FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT */
294 uint16_t CSInterval;
296 uint8_t CSHoldTime;
297 uint8_t CSSetupTime;
299 uint8_t columnspace;
301 uint8_t AWRSeqIndex;
302 uint8_t AWRSeqNumber;
303 uint8_t ARDSeqIndex;
304 uint8_t ARDSeqNumber;
310#if defined(FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426) && (FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426)
311 bool isFroClockSource;
312#endif
314
316typedef struct _flexspi_transfer
317{
318 uint32_t deviceAddress;
321 uint8_t seqIndex;
322 uint8_t SeqNumber;
323 uint32_t *data;
324 size_t dataSize;
326
327/* Forward declaration of the handle typedef. */
328typedef struct _flexspi_handle flexspi_handle_t;
329
332 flexspi_handle_t *handle,
333 status_t status,
334 void *userData);
335
338{
339 uint32_t state;
340 uint8_t *data;
341 size_t dataSize;
344 void *userData;
345};
346
347/*******************************************************************************
348 * API
349 ******************************************************************************/
350
351#if defined(__cplusplus)
352extern "C" {
353#endif /*_cplusplus. */
354
365uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base);
366
373status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status);
374
385
392
399void FLEXSPI_Deinit(FLEXSPI_Type *base);
400
409
422
431static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
432{
433 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
434 while (0U != (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK))
435 {
436 }
437}
438
445static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)
446{
447 if (enable)
448 {
449 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
450 }
451 else
452 {
453 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
454 }
455}
456
457/* @} */
458
469static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask)
470{
471 base->INTEN |= mask;
472}
473
480static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask)
481{
482 base->INTEN &= ~mask;
483}
484
485/* @} */
486
489
496static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable)
497{
498 if (enable)
499 {
500 base->IPTXFCR |= FLEXSPI_IPTXFCR_TXDMAEN_MASK;
501 }
502 else
503 {
504 base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXDMAEN_MASK;
505 }
506}
507
514static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable)
515{
516 if (enable)
517 {
518 base->IPRXFCR |= FLEXSPI_IPRXFCR_RXDMAEN_MASK;
519 }
520 else
521 {
522 base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXDMAEN_MASK;
523 }
524}
525
532static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base)
533{
534 return (uint32_t)&base->TFDR[0];
535}
536
543static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base)
544{
545 return (uint32_t)&base->RFDR[0];
546}
547
552
559static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo)
560{
561 if (txFifo)
562 {
563 base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK;
564 }
565 if (rxFifo)
566 {
567 base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK;
568 }
569}
570
580static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount)
581{
582 if (NULL != txCount)
583 {
584 *txCount = (((base->IPTXFSTS) & FLEXSPI_IPTXFSTS_FILL_MASK) >> FLEXSPI_IPTXFSTS_FILL_SHIFT) * 8U;
585 }
586 if (NULL != rxCount)
587 {
588 *rxCount = (((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * 8U;
589 }
590}
591
604static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)
605{
606 return base->INTR;
607}
608
615static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask)
616{
617 base->INTR |= mask;
618}
619
620#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN))
627static inline void FLEXSPI_GetDataLearningPhase(FLEXSPI_Type *base, uint8_t *portAPhase, uint8_t *portBPhase)
628{
629 if (portAPhase != NULL)
630 {
631 *portAPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEA_MASK) >> FLEXSPI_STS0_DATALEARNPHASEA_SHIFT);
632 }
633
634#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB))
635 if (portBPhase != NULL)
636 {
637 *portBPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEB_MASK) >> FLEXSPI_STS0_DATALEARNPHASEB_SHIFT);
638 }
639#endif
640}
641#endif
642
648static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base)
649{
651 (uint32_t)((base->STS0 & FLEXSPI_STS0_ARBCMDSRC_MASK) >> FLEXSPI_STS0_ARBCMDSRC_SHIFT));
652}
653
660static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
661{
662 *index = (uint8_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRID_MASK) >> FLEXSPI_STS1_IPCMDERRID_SHIFT);
664 (uint32_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRCODE_MASK) >> FLEXSPI_STS1_IPCMDERRCODE_SHIFT));
665}
666
673static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
674{
675 *index = (uint8_t)(base->STS1 & FLEXSPI_STS1_AHBCMDERRID_MASK) >> FLEXSPI_STS1_AHBCMDERRID_SHIFT;
677 (uint32_t)((base->STS1 & FLEXSPI_STS1_AHBCMDERRCODE_MASK) >> FLEXSPI_STS1_AHBCMDERRCODE_SHIFT));
678}
679
686static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
687{
688 return (0U != (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK)) && (0U != (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK));
689}
703
704#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE) && FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE)
710static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable)
711{
712 if (enable)
713 {
714 base->IPCR1 |= FLEXSPI_IPCR1_IPAREN_MASK;
715 }
716 else
717 {
718 base->IPCR1 &= ~FLEXSPI_IPCR1_IPAREN_MASK;
719 }
720}
721#endif
722
723#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE) && FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE)
729static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable)
730{
731 if (enable)
732 {
733 base->AHBCR |= FLEXSPI_AHBCR_APAREN_MASK;
734 }
735 else
736 {
737 base->AHBCR &= ~FLEXSPI_AHBCR_APAREN_MASK;
738 }
739}
740#endif
741
751void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count);
752
760static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex)
761{
762 base->TFDR[fifoIndex] = data;
763}
764
772static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex)
773{
774 return base->RFDR[fifoIndex];
775}
776
788status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size);
789
801status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size);
802
829 flexspi_handle_t *handle,
831 void *userData);
832
849
860
871
881#if defined(__cplusplus)
882}
883#endif /*_cplusplus. */
886#endif /* __FSL_FLEXSPI_H_ */
uint8_t priority
Definition: fsl_flexspi.h:220
size_t dataSize
Definition: fsl_flexspi.h:324
void FLEXSPI_UpdateDllValue(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)
Update FLEXSPI DLL value depending on currently flexspi root clock.
Definition: fsl_flexspi.c:433
_flexspi_pad
pad definition of FLEXSPI, use to form LUT instruction.
Definition: fsl_flexspi.h:88
_flexspi_command_type
Command type.
Definition: fsl_flexspi.h:211
flexspi_transfer_callback_t completionCallback
Definition: fsl_flexspi.h:343
status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count)
Gets the master transfer status during a interrupt non-blocking transfer.
Definition: fsl_flexspi.c:1022
uint8_t AWRSeqNumber
Definition: fsl_flexspi.h:302
uint8_t txWatermark
Definition: fsl_flexspi.h:255
uint8_t CSHoldTime
Definition: fsl_flexspi.h:296
_flexspi_ahb_write_wait_unit
FLEXSPI AHB wait interval unit for writing.
Definition: fsl_flexspi.h:147
enum _flexspi_ahb_error_code flexspi_ahb_error_code_t
Error Code when AHB command Error detected.
flexspi_command_type_t cmdType
Definition: fsl_flexspi.h:320
void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count)
Updates the LUT table.
Definition: fsl_flexspi.c:588
uint16_t seqTimeoutCycle
Definition: fsl_flexspi.h:251
uint8_t SeqNumber
Definition: fsl_flexspi.h:322
uint16_t AHBWriteWaitInterval
Definition: fsl_flexspi.h:306
uint32_t deviceAddress
Definition: fsl_flexspi.h:318
bool enableDoze
Definition: fsl_flexspi.h:236
uint8_t masterIndex
Definition: fsl_flexspi.h:221
uint32_t * data
Definition: fsl_flexspi.h:323
enum _flexspi_flags flexspi_flags_t
FLEXSPI interrupt status flags.
uint8_t ahbGrantTimeoutCycle
Definition: fsl_flexspi.h:265
size_t dataSize
Definition: fsl_flexspi.h:341
status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)
Check and clear IP command execution errors.
Definition: fsl_flexspi.c:210
enum _flexspi_pad flexspi_pad_t
pad definition of FLEXSPI, use to form LUT instruction.
flexspi_port_t port
Definition: fsl_flexspi.h:319
uint16_t ahbBusTimeoutCycle
Definition: fsl_flexspi.h:267
bool enableSckBDiffOpt
Definition: fsl_flexspi.h:246
uint8_t ARDSeqNumber
Definition: fsl_flexspi.h:304
bool enableAHBCachable
Definition: fsl_flexspi.h:280
flexspi_cs_interval_cycle_unit_t CSIntervalUnit
Definition: fsl_flexspi.h:293
bool enableClearAHBBufferOpt
Definition: fsl_flexspi.h:272
_flexspi_arb_command_source
Trigger source of current command sequence granted by arbitrator.
Definition: fsl_flexspi.h:202
void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)
Configures the connected device parameter.
Definition: fsl_flexspi.c:495
_flexspi_cs_interval_cycle_unit
FLEXSPI interval unit for flash device select.
Definition: fsl_flexspi.h:140
bool enableWordAddress
Definition: fsl_flexspi.h:300
void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource)
Update read sample clock source.
Definition: fsl_flexspi.c:624
bool enableAHBPrefetch
Definition: fsl_flexspi.h:276
enum _flexspi_read_sample_clock flexspi_read_sample_clock_t
FLEXSPI sample clock source selection for Flash Reading.
flexspi_ahb_write_wait_unit_t AHBWriteWaitUnit
Definition: fsl_flexspi.h:305
struct _flexspi_transfer flexspi_transfer_t
Transfer structure for FLEXSPI.
bool enableAHBWriteIpRxFifo
Definition: fsl_flexspi.h:263
bool enableHalfSpeedAccess
Definition: fsl_flexspi.h:237
status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size)
Receives a buffer of data bytes using a blocking method.
Definition: fsl_flexspi.c:732
void * userData
Definition: fsl_flexspi.h:344
uint32_t state
Definition: fsl_flexspi.h:339
struct _flexspi_config flexspi_config_t
FLEXSPI configuration structure.
enum _flexspi_ahb_write_wait_unit flexspi_ahb_write_wait_unit_t
FLEXSPI AHB wait interval unit for writing.
void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_callback_t callback, void *userData)
Initializes the FLEXSPI handle which is used in transactional functions.
Definition: fsl_flexspi.c:904
void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle)
Aborts an interrupt non-blocking transfer early.
Definition: fsl_flexspi.c:1049
enum _flexspi_port flexspi_port_t
FLEXSPI operation port select.
bool enablePrefetch
Definition: fsl_flexspi.h:223
enum _flexspi_cs_interval_cycle_unit flexspi_cs_interval_cycle_unit_t
FLEXSPI interval unit for flash device select.
status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
Execute command to transfer a buffer data bytes using a blocking method.
Definition: fsl_flexspi.c:837
uint8_t ipGrantTimeoutCycle
Definition: fsl_flexspi.h:253
bool enableAHBWriteIpTxFifo
Definition: fsl_flexspi.h:260
uint16_t CSInterval
Definition: fsl_flexspi.h:294
struct _flexspi_device_config flexspi_device_config_t
External device configuration items.
uint8_t resumeWaitCycle
Definition: fsl_flexspi.h:269
flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT]
Definition: fsl_flexspi.h:271
void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
Gets default settings for FLEXSPI.
Definition: fsl_flexspi.c:362
bool enableWriteMask
Definition: fsl_flexspi.h:308
void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
Initializes the FLEXSPI module and internal state.
Definition: fsl_flexspi.c:256
uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base)
Get the instance number for FLEXSPI.
Definition: fsl_flexspi.c:130
enum _flexspi_ip_error_code flexspi_ip_error_code_t
Error Code when IP command Error detected.
uint8_t seqIndex
Definition: fsl_flexspi.h:321
status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size)
Sends a buffer of data bytes using blocking method.
Definition: fsl_flexspi.c:653
status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer)
Performs a interrupt non-blocking transfer on the FLEXSPI bus.
Definition: fsl_flexspi.c:945
_flexspi_read_sample_clock
FLEXSPI sample clock source selection for Flash Reading.
Definition: fsl_flexspi.h:129
void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
Master interrupt handler.
Definition: fsl_flexspi.c:1063
bool enableAHBBufferable
Definition: fsl_flexspi.h:278
enum _flexspi_arb_command_source flexspi_arb_command_source_t
Trigger source of current command sequence granted by arbitrator.
bool enableSckFreeRunning
Definition: fsl_flexspi.h:231
void FLEXSPI_Deinit(FLEXSPI_Type *base)
Deinitializes the FLEXSPI module.
Definition: fsl_flexspi.c:420
uint16_t bufferSize
Definition: fsl_flexspi.h:222
uint8_t CSSetupTime
Definition: fsl_flexspi.h:297
_flexspi_ip_error_code
Error Code when IP command Error detected.
Definition: fsl_flexspi.h:160
bool isSck2Enabled
Definition: fsl_flexspi.h:288
flexspi_read_sample_clock_t rxSampleClock
Definition: fsl_flexspi.h:230
uint8_t dataValidTime
Definition: fsl_flexspi.h:298
_flexspi_port
FLEXSPI operation port select.
Definition: fsl_flexspi.h:190
uint32_t flashSize
Definition: fsl_flexspi.h:289
uint8_t AWRSeqIndex
Definition: fsl_flexspi.h:301
uint8_t columnspace
Definition: fsl_flexspi.h:299
uint8_t * data
Definition: fsl_flexspi.h:340
_flexspi_flags
FLEXSPI interrupt status flags.
Definition: fsl_flexspi.h:97
bool enableCombination
Definition: fsl_flexspi.h:233
uint32_t flexspiRootClk
Definition: fsl_flexspi.h:287
bool enableReadAddressOpt
Definition: fsl_flexspi.h:274
uint8_t ARDSeqIndex
Definition: fsl_flexspi.h:303
uint8_t rxWatermark
Definition: fsl_flexspi.h:256
bool enableSameConfigForAll
Definition: fsl_flexspi.h:249
enum _flexspi_command_type flexspi_command_type_t
Command type.
void(* flexspi_transfer_callback_t)(FLEXSPI_Type *base, flexspi_handle_t *handle, status_t status, void *userData)
FLEXSPI transfer callback function.
Definition: fsl_flexspi.h:331
_flexspi_ahb_error_code
Error Code when AHB command Error detected.
Definition: fsl_flexspi.h:176
size_t transferTotalSize
Definition: fsl_flexspi.h:342
@ kFLEXSPI_2PAD
Definition: fsl_flexspi.h:90
@ kFLEXSPI_1PAD
Definition: fsl_flexspi.h:89
@ kFLEXSPI_8PAD
Definition: fsl_flexspi.h:92
@ kFLEXSPI_4PAD
Definition: fsl_flexspi.h:91
@ kFLEXSPI_Config
Definition: fsl_flexspi.h:213
@ kFLEXSPI_Command
Definition: fsl_flexspi.h:212
@ kFLEXSPI_AhbWriteWaitUnit32AhbCycle
Definition: fsl_flexspi.h:150
@ kFLEXSPI_AhbWriteWaitUnit8AhbCycle
Definition: fsl_flexspi.h:149
@ kFLEXSPI_AhbWriteWaitUnit2AhbCycle
Definition: fsl_flexspi.h:148
@ kFLEXSPI_AhbWriteWaitUnit2048AhbCycle
Definition: fsl_flexspi.h:153
@ kFLEXSPI_AhbWriteWaitUnit8192AhbCycle
Definition: fsl_flexspi.h:154
@ kFLEXSPI_AhbWriteWaitUnit512AhbCycle
Definition: fsl_flexspi.h:152
@ kFLEXSPI_AhbWriteWaitUnit128AhbCycle
Definition: fsl_flexspi.h:151
@ kFLEXSPI_AhbWriteWaitUnit32768AhbCycle
Definition: fsl_flexspi.h:155
@ kFLEXSPI_Command_DUMMY_RWDS_DDR
Definition: fsl_flexspi.h:80
@ kFLEXSPI_Command_DUMMY_RWDS_SDR
Definition: fsl_flexspi.h:66
@ kFLEXSPI_Command_CADDR_SDR
Definition: fsl_flexspi.h:56
@ kFLEXSPI_Command_LEARN_DDR
Definition: fsl_flexspi.h:77
@ kFLEXSPI_Command_SDR
Definition: fsl_flexspi.h:54
@ kFLEXSPI_Command_DDR
Definition: fsl_flexspi.h:68
@ kFLEXSPI_Command_MODE1_SDR
Definition: fsl_flexspi.h:57
@ kFLEXSPI_Command_DATSZ_SDR
Definition: fsl_flexspi.h:64
@ kFLEXSPI_Command_DATSZ_DDR
Definition: fsl_flexspi.h:78
@ kFLEXSPI_Command_RADDR_SDR
Definition: fsl_flexspi.h:55
@ kFLEXSPI_Command_DUMMY_DDR
Definition: fsl_flexspi.h:79
@ kFLEXSPI_Command_MODE4_DDR
Definition: fsl_flexspi.h:73
@ kFLEXSPI_Command_LEARN_SDR
Definition: fsl_flexspi.h:63
@ kFLEXSPI_Command_RADDR_DDR
Definition: fsl_flexspi.h:69
@ kFLEXSPI_Command_MODE4_SDR
Definition: fsl_flexspi.h:59
@ kFLEXSPI_Command_MODE8_SDR
Definition: fsl_flexspi.h:60
@ kFLEXSPI_Command_READ_DDR
Definition: fsl_flexspi.h:76
@ kFLEXSPI_Command_WRITE_SDR
Definition: fsl_flexspi.h:61
@ kFLEXSPI_Command_MODE2_DDR
Definition: fsl_flexspi.h:72
@ kFLEXSPI_Command_JUMP_ON_CS
Definition: fsl_flexspi.h:82
@ kFLEXSPI_Command_DUMMY_SDR
Definition: fsl_flexspi.h:65
@ kFLEXSPI_Command_STOP
Definition: fsl_flexspi.h:53
@ kFLEXSPI_Command_MODE2_SDR
Definition: fsl_flexspi.h:58
@ kFLEXSPI_Command_READ_SDR
Definition: fsl_flexspi.h:62
@ kFLEXSPI_Command_WRITE_DDR
Definition: fsl_flexspi.h:75
@ kFLEXSPI_Command_CADDR_DDR
Definition: fsl_flexspi.h:70
@ kFLEXSPI_Command_MODE8_DDR
Definition: fsl_flexspi.h:74
@ kFLEXSPI_Command_MODE1_DDR
Definition: fsl_flexspi.h:71
@ kFLEXSPI_CsIntervalUnit1SckCycle
Definition: fsl_flexspi.h:141
@ kFLEXSPI_CsIntervalUnit256SckCycle
Definition: fsl_flexspi.h:142
@ kStatus_FLEXSPI_Busy
Definition: fsl_flexspi.h:41
@ kStatus_FLEXSPI_IpCommandSequenceError
Definition: fsl_flexspi.h:44
@ kStatus_FLEXSPI_IpCommandGrantTimeout
Definition: fsl_flexspi.h:46
@ kStatus_FLEXSPI_SequenceExecutionTimeout
Definition: fsl_flexspi.h:42
@ kFLEXSPI_ReadSampleClkExternalInputFromDqsPad
Definition: fsl_flexspi.h:135
@ kFLEXSPI_ReadSampleClkLoopbackFromDqsPad
Definition: fsl_flexspi.h:132
@ kFLEXSPI_ReadSampleClkLoopbackFromSckPad
Definition: fsl_flexspi.h:134
@ kFLEXSPI_ReadSampleClkLoopbackInternally
Definition: fsl_flexspi.h:130
@ kFLEXSPI_IpCmdErrorJumpOnCsInIpCmd
Definition: fsl_flexspi.h:162
@ kFLEXSPI_IpCmdErrorUnknownOpCode
Definition: fsl_flexspi.h:163
@ kFLEXSPI_IpCmdErrorDdrDummyInSdrSequence
Definition: fsl_flexspi.h:166
@ kFLEXSPI_IpCmdErrorFlashBoundaryAcrosss
Definition: fsl_flexspi.h:171
@ kFLEXSPI_IpCmdErrorSdrDummyInDdrSequence
Definition: fsl_flexspi.h:164
@ kFLEXSPI_IpCmdErrorInvalidAddress
Definition: fsl_flexspi.h:168
@ kFLEXSPI_IpCmdErrorNoError
Definition: fsl_flexspi.h:161
@ kFLEXSPI_IpCmdErrorSequenceExecutionTimeout
Definition: fsl_flexspi.h:170
@ kFLEXSPI_PortA1
Definition: fsl_flexspi.h:191
@ kFLEXSPI_PortB2
Definition: fsl_flexspi.h:195
@ kFLEXSPI_PortB1
Definition: fsl_flexspi.h:194
@ kFLEXSPI_PortA2
Definition: fsl_flexspi.h:192
@ kFLEXSPI_AllInterruptFlags
Definition: fsl_flexspi.h:124
@ kFLEXSPI_DataLearningFailedFlag
Definition: fsl_flexspi.h:111
@ kFLEXSPI_IpCommandExecutionDoneFlag
Definition: fsl_flexspi.h:122
@ kFLEXSPI_IpCommandSequenceErrorFlag
Definition: fsl_flexspi.h:117
@ kFLEXSPI_IpRxFifoWatermarkAvailableFlag
Definition: fsl_flexspi.h:114
@ kFLEXSPI_SckStoppedBecauseRxFullFlag
Definition: fsl_flexspi.h:107
@ kFLEXSPI_SequenceExecutionTimeoutFlag
Definition: fsl_flexspi.h:98
@ kFLEXSPI_IpCommandGrantTimeoutFlag
Definition: fsl_flexspi.h:120
@ kFLEXSPI_AhbBusTimeoutFlag
Definition: fsl_flexspi.h:102
@ kFLEXSPI_SckStoppedBecauseTxEmptyFlag
Definition: fsl_flexspi.h:104
@ kFLEXSPI_AhbCommandGrantTimeoutFlag
Definition: fsl_flexspi.h:118
@ kFLEXSPI_AhbCommandSequenceErrorFlag
Definition: fsl_flexspi.h:115
@ kFLEXSPI_IpTxFifoWatermarkEmptyFlag
Definition: fsl_flexspi.h:113
@ kFLEXSPI_AhbCmdErrorUnknownOpCode
Definition: fsl_flexspi.h:180
@ kFLEXSPI_AhbCmdErrorDdrDummyInSdrSequence
Definition: fsl_flexspi.h:183
@ kFLEXSPI_AhbCmdErrorNoError
Definition: fsl_flexspi.h:177
@ kFLEXSPI_AhbCmdErrorSdrDummyInDdrSequence
Definition: fsl_flexspi.h:181
@ kFLEXSPI_AhbCmdSequenceExecutionTimeout
Definition: fsl_flexspi.h:185
@ kFLEXSPI_AhbCmdErrorJumpOnCsInWriteCmd
Definition: fsl_flexspi.h:178
int32_t status_t
Type used for all status and error return values.
Definition: fsl_common.h:225
#define MAKE_STATUS(group, code)
Construct a status code value from a group and code number.
Definition: fsl_common.h:47
@ kStatusGroup_FLEXSPI
Definition: fsl_common.h:142
Definition: MIMXRT1052.h:21299
Definition: fsl_flexspi.h:219
FLEXSPI configuration structure.
Definition: fsl_flexspi.h:229
External device configuration items.
Definition: fsl_flexspi.h:286
Transfer handle structure for FLEXSPI.
Definition: fsl_flexspi.h:338
Transfer structure for FLEXSPI.
Definition: fsl_flexspi.h:317
Definition: deflate.c:114